Barrier configuration for metal wiring using manganese and graphene

Abstract

A method for forming a semiconductor device comprises the steps of: providing a substrate having a patterned film containing manganese; depositing a graphene layer on an exposed surface of the patterned film; depositing a dielectric layer containing silicon and oxygen on the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 229,925 filed on August 5, 2021, and accordingly, that application is incorporated herein by reference.

[0003] The present invention generally relates to the manufacture of semiconductor devices, and more specifically, to a barrier scheme for metallization using manganese and graphene. Background Technology

[0004] For reliability, a barrier layer is required between the copper interconnect leads and the surrounding dielectric layer. Copper diffusion and electromigration degrade the dielectric, causing a reduced breakdown voltage and, in some cases, an electrical short circuit between adjacent interconnect leads.

[0005] Reducing resistance by minimizing the barrier thickness surrounding proportionally reduced copper (Cu) interconnects is important for future microelectronic devices. Conventional barrier materials, such as titanium nitride and tantalum nitride, do not thin proportionally as copper interconnect wires are proportionally reduced. Since the resistance of conventional barrier materials is greater than that of copper, the Cu barrier layer causes increasing resistance to the copper interconnect wires as the wires are proportionally reduced. Designing ultrathin barriers is difficult because any defect within the barrier provides a pathway for copper diffusion into the dielectric, which can lead to device failure. Large Cu grain size is important for reducing copper interconnect resistivity and achieving improved electrical conductivity.

[0006] A method for forming a semiconductor device comprises the steps of: providing a substrate having a patterned film containing manganese; depositing a graphene layer on an exposed surface of the patterned film; depositing a dielectric layer containing silicon and oxygen on the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

[0007] A method for forming a semiconductor device comprises the steps of: providing a substrate comprising a first dielectric layer comprising silicon and oxygen and a metal wiring layer; depositing a barrier layer on the metal wiring layer and on the first dielectric layer; depositing a conductive film comprising manganese on the barrier layer; heat-treating the substrate for a first time to form a first manganese-containing diffusion barrier region between the barrier layer and the first dielectric layer; patterning and etching a conductive film to form a patterned conductive film on the first manganese-containing diffusion barrier region; depositing a graphene layer on the upper surface of the conductive film and on the sidewall surface; depositing a second dielectric layer comprising silicon and oxygen on the graphene layer; and heat-treating the substrate for a second time to form a second manganese-containing diffusion barrier region.

[0008] A semiconductor device comprises: a substrate comprising a patterned copper film containing manganese; a graphene layer disposed on an exposed surface of the patterned copper film; a first manganese-containing diffusion barrier layer disposed on a portion of the graphene layer; and a first dielectric layer comprising silicon and oxygen disposed on the first manganese-containing diffusion barrier layer and on the graphene layer. Brief explanation of the drawing

[0009] Now, for a more complete understanding of the present invention and its advantages, refer to the following description in conjunction with the accompanying drawings, and as the accompanying drawings: FIG. 1a is a flowchart illustrating the formation of a selective copper barrier configuration on a plasma-etched copper interconnect using manganese and graphene according to an embodiment, and the fabrication of a semiconductor device; FIGS. 1b to 1j are cross-sectional views of a semiconductor device during various manufacturing steps in various embodiments, representing the steps of the flowchart in FIG. 1a; FIG. 2a is a flowchart illustrating the formation of a selective copper barrier configuration on a damascene copper wire using manganese and graphene according to an embodiment and the fabrication of a semiconductor device; FIGS. 2b to 2e are cross-sectional views of a semiconductor during various manufacturing steps in various embodiments, representing the steps of the flowchart in FIG. 2a; FIG. 3a is a flowchart illustrating the formation of a selective copper barrier configuration on a damascene copper wire using manganese and graphene according to an embodiment and the fabrication of a semiconductor device; FIGS. 3b to 3g are cross-sectional views of a semiconductor device during various manufacturing steps in various embodiments, representing the steps of the flowchart in FIG. 3a; FIG. 4a is a flowchart illustrating the formation of a selective copper barrier configuration on a damascene copper wire using manganese and graphene according to an embodiment and the fabrication of a semiconductor device; and FIGS. 4b to 4j are cross-sectional views of a semiconductor device during various manufacturing steps in various embodiments, representing the steps of the flowchart in FIG. 4a. Specific details for implementing the invention

[0010] Although the present invention has been described with reference to exemplary embodiments, such description is not intended to be interpreted in a limiting sense. By referring to the description, various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art. Accordingly, the appended claims are intended to include any such modifications or embodiments.

[0011] Copper interconnect wires are surrounded by a copper diffusion barrier to prevent copper atoms from diffusing into the interlayer dielectric between the interconnect wires. For example, copper diffusion can be increased by the electric field during IC operation, for instance, due to electron migration. Copper diffusion into the interlayer dielectric can reduce the breakdown voltage between wires and, in extreme cases, cause an electrical short circuit between adjacent wires.

[0012] Barrier layers made of materials such as titanium nitride (TiN) and tantalum nitride (TaN) have been used for several generations of copper interconnects. To prevent copper electron migration, a minimum thickness of these barrier materials is required. As copper interconnect wires shrink proportionally, the barrier material occupies a larger cross-sectional area of ​​the wire, thereby increasing the wire's resistance. The resistivity of TiN and TaN (~200 μΩcm) is approximately 100 times higher than that of copper (~1.7 μΩcm).

[0013] Embodiments of the present application replace a deposited TiN or TaN barrier with an optional Cu barrier configuration using manganese (Mn) and graphene. An ultrathin graphene layer is an excellent barrier against Cu diffusion. Additionally, graphene is highly conductive, and the interface between Cu and graphene causes lower carrier scattering than the interface between Cu and TiN or TaN, thus providing low resistance. A graphene barrier layer that effectively blocks Cu diffusion can be optionally grown to a thickness of nearly a monolayer on an exposed Cu metal surface. However, defects (e.g., grain boundaries) may form within the thin graphene barrier layer through which copper can diffuse. When Mn-doped copper interconnects clad with a graphene barrier are annealed, Mn may diffuse from the interconnect wires through defects and grain boundaries within the graphene barrier layer to the Cu interconnect / interlayer dielectric interface. Mn can react with silicon and oxygen in the interlayer dielectric to self-form a MnSiO barrier layer that blocks Cu diffusion through defects. The MnSiO barrier layer is formed before Cu has a chance to diffuse into the surrounding dielectric through defects.

[0014] The interface between the graphene barrier and the copper interconnect wires is much smoother than the interface between conventional barrier configurations, such as Ta / TaN, and the copper interconnect wires. The atomically smooth graphene interface reduces carrier scattering, thereby improving carrier mobility and consequently further reducing interconnect wire resistance.

[0015] FIG. 1a is a flowchart illustrating the formation of a copper barrier on plasma-etched copper using Mn and graphene according to an embodiment and the fabrication of a semiconductor device.

[0016] FIGS. 1b to 1j schematically illustrate a method for forming an element according to an embodiment of the present invention through cross-sectional views.

[0017] Referring to the block (101) of FIG. 1a and the cross-sectional view of FIG. 1b, a partially processed semiconductor device is provided. The partially processed semiconductor device includes a semiconductor substrate (100) comprising a first dielectric layer (ILD1) (102), and a metal-filled feature (106) extends through the first dielectric layer (ILD1) (102) and is stopped on the substrate (100).

[0018] The membrane structure of FIG. 1b may be flattened to form a first dielectric layer (ILD1) (102) and a metal-filled feature (106) within the same horizontal plane. In one or more embodiments, the metal-filled feature (106) is a via. In one embodiment, the metal-filled feature (106) may comprise copper metal. In another embodiment, the metal-filled feature (106) may comprise tungsten metal. In another embodiment, the metal-filled via may at least partially comprise cobalt (Co) metal, Ru, Mo, Ir, Mn, Ta, Ni, or a silicide such as cobalt, titanium, or nickel silicide.

[0019] The barrier layer (104) separates the metal-filled shape portion (106) from the first dielectric layer (ILD1) (102). The semiconductor substrate (100) may be a single-crystal material such as single-crystal silicon, silicon-on-insulator, single-crystal germanium, single-crystal silicon carbide, or single-crystal gallium arsenide, as well as other compound semiconductor substrates. Additionally, the substrate (100) may include one or more epitaxial layers, including a hetero-epitaxial layer such as gallium nitride on silicon, for example. The substrate (100) below the first dielectric layer (ILD1) (102) may include electrical components such as CMOS and bipolar transistors, capacitors, resistors, inductors, and memory cells. The first dielectric layer (ILD1) (102) may be a silicon and oxygen-containing dielectric, such as silicon dioxide (SiO2) or silicon oxynitride (SiON), as well as other low-k dielectrics. In various embodiments, the first dielectric layer (ILD1) (102) may include dielectric materials such as oxides and oxynitrides, and other low-k materials such as fluorine-doped silicon dioxide, organic silicate glass including carbon-doped oxides, porous silicon dioxide, porous organic silicate glass, and other spin-on dielectrics. The first dielectric layer (ILD1) (102) may also include an air gap in some embodiments. The first dielectric layer (ILD1) (102) can be deposited in various embodiments using a thermal process, a chemical vapor deposition (CVD) process, e.g., CVD, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), negative pressure CVD (SACVD), plasma enhanced CVD (PECVD), and a spin-on process.

[0020] The barrier (104) may be a barrier material such as titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten nitride, and combinations thereof. The metal-filled shape (106) may be filled with a metal such as copper, tungsten, ruthenium, iridium, or cobalt. The barrier (104) may be deposited using a vapor deposition process such as sputtering, ion metal plasma (IMP) deposition, CVD, ALD, PECVD, etc.

[0021] In the block (103) of FIG. 1a and the cross-sectional view of FIG. 1c, a barrier layer (108) is deposited on the first dielectric layer (ILD1) (102) and on the metal-filled shape portion (106). In one embodiment, the barrier layer (108) is deposited as a blanket layer. In one embodiment, the barrier layer (108) may comprise Ta, TaN, Ti, or TiN. In one embodiment, the barrier layer (108) further comprises a nitride such as manganese (Mn), MnN, and an oxide such as MnO. In one embodiment, the barrier layer (108) comprises manganese (Mn) metal. The barrier layer (108) may be deposited using a physical vapor deposition (PVD) method including sputtering, a chemical vapor deposition (CVD) method including plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0022] In the block (105) of FIG. 1a and the cross-sectional view of FIG. 1d, a copper (Cu) film (110) containing Mn is deposited on a barrier layer (108). In various embodiments, the Cu film (110) may be deposited by chemical vapor deposition (CVD), ALD, physical vapor deposition (PVD), or electrochemical deposition. In various embodiments, the Cu film (110) comprises a copper alloy. In one or more embodiments, the Cu film (110) may contain 1% to 5% atomic percent Mn. Additionally, the Cu film (110) may contain other elements such as aluminum and silicon.

[0023] Block (107) of FIG. 1e and FIG. 1a illustrates a film structure after a first heat treatment. The first heat treatment includes the step of annealing the substrate (100) in a batch furnace or in a single wafer annealing tool. In various embodiments, the annealing may be furnace annealing, rapid thermal annealing, flash annealing, etc. During the first heat treatment, the substrate (100) is loaded into an annealing chamber and heated to a temperature of 200°C to 500°C. In one embodiment, the annealing may be performed at 300°C to 400°C. In various embodiments, the substrate (100) may be annealed for a duration of 60 seconds to 3600 seconds.

[0024] Although not limited to any specific theory, the inventors of the present application determine that during annealing, Mn is thermally diffused from the Cu film (110) and / or the barrier layer (108) to the surface of the first dielectric layer (ILD1) (102). Due to the heat treatment, a self-forming MnSiO barrier layer (112) is formed between the Cu film (110) and the first dielectric layer (ILD1) (102), or on any surface containing silicon and oxygen that is in direct contact with the barrier layer (108).

[0025] According to one embodiment, the heat treatment during the first time melts, for example, the barrier layer (112) between the metal wiring layer within the metal-filled shape (106) and the copper film (110) providing a low electrical resistance contact. In one embodiment, the barrier layer (112) is completely melted during the heat treatment. According to one embodiment, the heat treatment is optimized to grow the crystals within the Cu film (110) as large as possible to reduce the overall electrical resistivity.

[0026] Referring to the cross-sectional view and block (109) of FIG. 1f, an interconnected wire photoresist pattern (114) is formed on a Cu film (110). In some embodiments, the interconnected wire photoresist pattern (114) may be formed using conventional lithography. In other embodiments, other techniques including direct printing may be used to form the interconnected wire photoresist pattern (114). In one or more embodiments, the interconnected wire photoresist pattern (114) may comprise a laminate of layers including a hard mask layer and an anti-reflective layer, such as silicon nitride, titanium nitride, tungsten silicide, tungsten carbide, or ruthenium.

[0027] An additional process includes the step of patterning a Cu film (110) to form a patterned conductive film comprising copper interconnect wires (116), as described in the cross-sectional view of FIG. 1g and block (109) of FIG. 1a. The Cu film (110) can be patterned by performing a plasma etching process using an interconnect wire photoresist pattern (114) as an etching mask. The plasma etching process can be performed using, for example, chlorine and / or HCl containing Cl2 / Ar, a chlorine-based chemical having plasma hydrogen, HBr, or an etching chemical containing hydrogen.

[0028] The plasma etching process may remove the barrier layer (112) from the first dielectric layer (ILD1) (102) within the opening in the patterned Cu film (110). In some embodiments, the plasma etching process may be designed to stop at the barrier layer (112), and when the barrier layer (112) is exposed, the gas chemical is modified to etch the exposed barrier layer (112).

[0029] In the cross-sectional view of block (111) and FIG. 1h, an additional process includes the step of selectively depositing a single graphene monolayer on almost all exposed surfaces of the Cu interconnect wire (116). In this embodiment, a graphene barrier layer (118) is deposited on the sidewalls and the top surface of the Cu interconnect wire (116). One embodiment includes catalytic CVD decomposition of hydrocarbon gas, which selectively deposits graphene on the exposed Cu surfaces but does not deposit graphene on the first dielectric layer (ILD1) (102). To facilitate the deposition of the graphene barrier layer (118), the copper surface must be free of oxidation. A precleaning process step, such as isopropyl alcohol wet cleaning, citric acid wet cleaning, or hydrogen plasma treatment, may be performed immediately before the graphene deposition. In some embodiments, the precleaning process may be performed within the same chamber where the selective deposition of graphene is performed.

[0030] An exposed copper surface heated to a temperature of 250°C to 450°C can act as a catalyst for the thermal decomposition of hydrocarbon gases such as ethylene and acetylene. An ultrathin sheet of graphene, a nearly monolayer, is formed on the surface of the copper crystal. The thickness of the graphene barrier layer (118) may be in the range of about 3 angstroms to 2 nm. Defects and grain boundaries (119) between individual graphene sheets may be formed within the thin graphene barrier layer (118) through which Cu can diffuse. During subsequent annealing, Mn atoms diffuse from the Mn-doped copper to form a MnSiO barrier layer that blocks Cu diffusion through these defects (119).

[0031] The hydrocarbon gas may be diluted in an inert carrier gas such as nitrogen, helium, or argon. The graphene layer (118) may be deposited in an LPCVD furnace or in a single-wafer CVD deposition tool. The flow rate of the hydrocarbon gas may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 10 sccm to 10,000 sccm or more in various embodiments. Additionally, the deposition time may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 5 minutes to 1 hour or more. In some embodiments, plasma-enhanced CVD (PECVD) may be used to reduce the deposition temperature. The hydrocarbon gas may include ethylene or acetylene.

[0032] Block (113) and the cross-sectional view of FIG. 1i illustrate a film structure after deposition of a second dielectric layer (ILD2) (120) covering a graphene barrier layer (118) on a Cu interconnect wire (116). The second dielectric layer (ILD2) (120) may include dielectric materials such as oxides and oxynitrides, and other low-k materials such as fluorine-doped silicon dioxide, organic silicate glass including carbon-doped oxides, porous silicon dioxide, porous organic silicate glass, and other spin-on dielectrics. The second dielectric layer (ILD2) (120) may also include an air gap in some embodiments. The second dielectric layer (ILD2) (120) may be deposited using a thermal process, a vapor deposition process, e.g., CVD, PECVD, and a spin-on process, in various embodiments.

[0033] Block (115) and the cross-sectional view of FIG. 1J illustrate a film structure after a second heat treatment in which Mn is thermally diffused from the Cu film (110) to the surface of the second dielectric layer (ILD2) (120) through a defect (119) in the graphene barrier layer (118). Mn reacts with Si and O in the second dielectric layer (ILD2) (120) to self-form a Mn-containing diffusion barrier layer (MnSiO barrier layer (122)). The self-formed MnSiO barrier layer (122) may be formed as a plurality of discontinuous regions around the graphene barrier layer (118) at locations around the defect (119). The self-formed MnSiO barrier layer (122) blocks Cu diffusion through the defect (119) in a manner similar to plugging holes in the graphene barrier layer (118) for copper to diffuse. The formation of the Mn-containing diffusion barrier layer (122) is self-limiting when the second dielectric layer (ILD2) comes into contact with Mn. The heat treatment step may include heating the substrate (100) to a temperature of 200°C to 500°C with an inert gas such as nitrogen.

[0034] The optionally deposited graphene barrier layer (118) and the self-formed MnSiO barrier layer (122) (optional graphene and Mn barrier configuration) together provide a reliable barrier against copper electron movement into the interlayer dielectric. Preferably, since the self-formed MnSiO barrier layer (122) provides a stop plug, the defect level of the graphene barrier layer (118) does not need to be strictly controlled. Thus, the optional graphene and Mn barrier configuration described in various embodiments has the advantage of being very thin compared to the previous barrier configuration and consequently having lower resistance than the previous barrier. Additionally, the optional graphene and Mn barrier configuration provides an atomically smooth surface between the graphene layer (118) and the copper interconnect wire (116), thereby reducing carrier scattering (higher carrier mobility) and causing reduced copper interconnect wire (116) resistance.

[0035] The film structure may be further processed by the steps of etching a new via within the second dielectric layer (ILD2) (120), filling the new via with metal, flattening the new via filled with metal to form the second dielectric layer (ILD2) (120) and the new via filled with metal within the same horizontal plane, and then repeating blocks (103 to 117) of FIG. 1a to add additional interconnection levels. Additional interconnection levels may be added by repeating the processes of the embodiment. Thus, each metal wiring level may include optional graphene and Mn barrier configurations.

[0036] FIG. 2a is a flowchart illustrating the formation of a copper barrier on damascene copper using Mn and graphene according to an embodiment and the manufacture of a semiconductor device.

[0037] FIGS. 2b to 2e schematically illustrate a method for forming an element according to an embodiment of the present invention through cross-sectional views.

[0038] Now, referring to block (201) in FIG. 2a and the cross-sectional view in FIG. 2b, a substrate having Mn-doped copper interconnect wires (130) formed using a damascene process within a silicon and oxygen-containing first dielectric layer (ILD1) (128) is provided. In the damascene process, trenches are etched into the first dielectric layer (ILD1) (128), filled with metal, and then flattened using chemical mechanical polishing (CMP). The damascene process may be single damascene or double damascene. In a single damascene process, metal-filled vias (132) are formed using the first damascene process, and metal-filled interconnect trenches are formed using the second damascene process. In the more commonly used double damascene process, via trenches and interconnect trenches are first formed within the first dielectric layer (ILD1) (128). The double vias and interconnected trenches are filled simultaneously using a single damascene process.

[0039] In FIG. 2b, Mn-doped copper interconnect wires (130) and metal-filled vias (132) are formed within the first dielectric layer (ILD1) (128). In various embodiments, the first dielectric layer (ILD1) (128) may comprise a dielectric material comprising silicon and oxygen, such as silicon dioxide, silicon oxynitride, and other low-k materials, such as fluorine-doped silicon dioxide, an organicsilicate glass comprising carbon-doped oxide, porous silicon dioxide, a porous organicsilicate glass, and other spin-on dielectrics. ILD1 (128) may also include an air gap in some embodiments. The first dielectric layer (ILD1) (128) can be deposited in various embodiments using a thermal process, a chemical vapor deposition (CVD) process, e.g., CVD, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), negative pressure CVD (SACVD), plasma enhanced CVD (PECVD), and a spin-on process.

[0040] A first dielectric layer (ILD1) (128) is deposited on a substrate layer (100), such as a semiconductor substrate. The semiconductor substrate may be a substrate (100) such as single-crystal silicon, silicon-on-insulator, single-crystal germanium, single-crystal silicon carbide, or single-crystal gallium arsenide, as well as other compound semiconductor substrates. Additionally, the substrate (100) may include one or more epitaxial layers, such as a hetero-epitaxial layer, such as gallium nitride on silicon. The substrate (100) under the first dielectric layer (ILD1) (128) may include electronic components such as transistors, resistors, capacitors, inductors, etc. A barrier layer (134) between the Mn-doped copper interconnect wire (130) and the first dielectric layer (ILD1) (128) prevents copper from electron-transferring into the first dielectric layer (ILD1) (128) and degrading the first dielectric layer (ILD1) (128). In one embodiment, the barrier layer (134) may comprise Ta, TaN, Ti, TiN, TiW, or WN. In one embodiment, the barrier layer (134) further comprises a nitride such as manganese (Mn), MnN, and an oxide such as MnO. In one embodiment, the barrier layer (134) comprises manganese (Mn) metal. The barrier layer (134) may be deposited using a physical vapor deposition (PVD) method including sputtering, a chemical vapor deposition (CVD) method including plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), ion metal plasma (IMP) deposition, etc.

[0041] In the cross-sectional view of block (203) and FIG. 2c, an additional process includes the step of selectively depositing nearly one monolayer of graphene barrier layer (136) on the exposed surface of the damascene Mn-doped Cu interconnect (130). In this embodiment, the graphene barrier layer (136) is selectively deposited on the upper surface of the Mn-doped Cu interconnect wire (130).

[0042] An exposed copper surface heated to a temperature of 250°C to 450°C can act as a catalyst for the thermal decomposition of hydrocarbon gases such as ethylene and acetylene. An ultrathin sheet of graphene, a nearly monolayer, can be formed on the surface of the copper crystal. The thickness of the graphene barrier layer (136) can be in the range of about 3 angstroms to 2 nm. Defects (119), such as grain boundaries and line defects between individual graphene sheets, can be formed within the thin graphene barrier layer (136) through which Cu can diffuse. During subsequent annealing, Mn atoms diffuse from the Mn-doped copper to form a MnSiO barrier layer (140) that blocks Cu diffusion through these defects (119).

[0043] In various embodiments, the hydrocarbon gas may be diluted in an inert carrier gas such as nitrogen, helium, or argon. The graphene layer (136) may be deposited in a batch LPCVD furnace or in a single-wafer CVD deposition tool. The flow rate of the hydrocarbon gas may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 10 sccm to 10,000 sccm or more in various embodiments. Additionally, the deposition time may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 5 minutes to 1 hour or more. In some embodiments, plasma-enhanced CVD (PECVD) may be used to reduce the deposition temperature.

[0044] In the block (205) of FIG. 2a and the cross-sectional view of FIG. 2d, a silicon and oxygen-containing second dielectric layer (ILD2) (138) is deposited on the graphene barrier layer (136) and on the first dielectric layer (128). In various embodiments, the second dielectric layer (ILD2) (138) may include dielectric materials such as silicon dioxide, silicon oxynitride, and other low-k silicon and oxygen-containing materials such as fluorine-doped silicon dioxide, organic silicate glass including carbon-doped silicon oxide, porous silicon dioxide, porous organic silicate glass, and other spin-on dielectrics. The second dielectric layer (ILD2) (138) may also include an air gap in some embodiments. The second dielectric layer (ILD2) (138) can be deposited in various embodiments using a thermal process, a chemical vapor deposition (CVD) process, e.g., CVD, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), negative pressure CVD (SACVD), plasma enhanced CVD (PECVD), and a spin-on process.

[0045] In the block (207) of FIG. 2a and the cross-sectional view of FIG. 2e, by performing annealing, Mn diffuses from the Mn-doped Cu interconnect wire (130) and through the defect (119) in the graphene barrier layer (136) to the interface between the Mn-doped Cu interconnect wire (130) and the second dielectric layer (ILD2) (138). The Mn reacts with Si and O in the ILD2 layer (138) to self-form a MnSiO barrier layer (140). The self-formed MnSiO barrier layer (140) may be formed as a number of discontinuous regions around the graphene barrier layer (136) at locations around the defect (119). The self-formed MnSiO barrier layer (140) blocks Cu from diffusing or electron transferring into the second dielectric layer (ILD2) (138) through defects (119) within the graphene barrier layer (136). Annealing can be performed in a batch annealing tool, such as a furnace, or in a single wafer annealing tool, such as a rapid thermal annealing chamber. In various embodiments, annealing can be furnace annealing, rapid thermal annealing, flash annealing, etc. During annealing, the substrate (100) is loaded into the annealing chamber and heated to a temperature of 200°C to 500°C in an inert atmosphere, such as argon or nitrogen. In one embodiment, annealing can be performed at 300°C to 400°C. In various embodiments, the substrate (100) can be annealed for a duration of 60 seconds to 3600 seconds.

[0046] The selective graphene as well as the Mn barrier provides a reliable barrier that blocks copper electron movement into the surrounding interlayer dielectric. The selective graphene as well as the self-formed MnSiO barrier configuration provides an ultrathin copper diffusion barrier with low electrical resistance. Additionally, the selective graphene as well as the self-formed MnSiO barrier improves carrier mobility and reduces resistance by providing an atomically smooth surface between the graphene barrier layer (136) and the Mn-doped copper interconnect wire (130).

[0047] According to the procedure of the same embodiment, another Mn-doped copper interconnect layer may be formed within the second dielectric layer (ILD2) (138). Additional interconnect levels may be added by repeating the processes of the embodiment. Thus, each metal wiring level may include optional graphene and Mn barrier configurations.

[0048] FIG. 3a is a flowchart illustrating a different process for forming a selective copper barrier on damascene copper using Mn and graphene according to an embodiment and illustrating the fabrication of a semiconductor device. This process can be implemented using a single damascene or a double damascene.

[0049] FIGS. 3b to 3g schematically illustrate the steps of the flowchart of FIG. 3a for forming an element according to one embodiment of the present invention through cross-sectional views.

[0050] Now refer to block (301) in FIG. 3a and cross-sectional view in FIG. 3b. FIG. 3b is a cross-sectional view of an Mn-doped copper interconnect wire (130) formed by a silicon and oxygen damascene process including a first dielectric layer (ILD1) (128). In the damascene process, interconnect trenches are etched into the first dielectric layer (ILD1) (128), filled with Mn containing copper, and then flattened using chemical mechanical polishing (CMP).

[0051] In the cross-sectional view and block (303) of FIG. 3c, an additional process includes the step of etching a portion of the first dielectric layer (ILD1) (128) adjacent to the Mn-doped copper interconnect wire (130) so as to further expose the sidewalls of the Mn-doped copper interconnect wire (130). A barrier layer (134) (if present) covering the sidewalls of the Mn-doped copper interconnect wire (130) is also exposed. The first dielectric layer (ILD1) (128) may be plasma etched using oxygen diluted in a carrier gas such as argon or helium, as well as fluorocarbon gases such as CF4 and CHF3, where silicon and oxygen, or silicon, oxygen, and nitrogen are included.

[0052] In the block (305) of FIG. 3a and the cross-sectional view of FIG. 3d, the barrier layer (134) (if present) is etched to expose the sidewall surface of the Mn-doped Cu interconnect wire (130). The barrier layer (134), such as TiN and TaN, can be plasma-etched in an inductively coupled plasma (ICP) reactor using Cl2 or HBr diluted in a carrier gas such as argon or helium. To ensure that there is no oxidation on the copper surface, a pre-cleaning process step, such as isopropyl alcohol wet cleaning, citric acid wet cleaning, or hydrogen plasma treatment, can be performed immediately before the deposition of the graphene barrier layer (150). In some embodiments, the pre-cleaning process can be performed in the same chamber as the selective deposition of graphene.

[0053] In the block (307) of FIG. 3a and the cross-sectional view of FIG. 3e, nearly a single monolayer of graphene is deposited on the exposed top and sidewall surfaces of the Mn-doped Cu interconnect wire (130). When the exposed copper surface is heated to a temperature of 250°C to 450°C, it promotes the thermal decomposition of hydrocarbon gases such as ethylene and acetylene, thereby forming an ultrathin sheet, nearly a monolayer of graphene, on the exposed copper surface. The thickness of the graphene barrier layer (150) may be in the range of about 3 Angstroms to 2 nm. Defects and grain boundaries (119) between individual graphene sheets may be formed within the thin graphene barrier layer (150) through which Cu can diffuse. During subsequent annealing, Mn atoms diffuse from the Mn-doped copper to self-form a MnSiO barrier layer (154) that blocks Cu diffusion through the defects (119).

[0054] The hydrocarbon gas may be diluted in an inert carrier gas such as nitrogen, helium, or argon. The graphene barrier layer (150) may be deposited in an LPCVD furnace or in a single-wafer CVD deposition tool. The flow rate of the hydrocarbon gas may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 10 sccm to 10,000 sccm or more in various embodiments. Additionally, the deposition time may vary significantly depending on whether the process is a single-wafer process or a batch process, and may range from 5 minutes to 1 hour or more. In some embodiments, plasma-enhanced CVD (PECVD) may be used to reduce the deposition temperature.

[0055] In block (309) of FIG. 3a and cross-sectional view of FIG. 3f, a second dielectric layer (ILD2) (152) containing silicon and oxygen is deposited on the graphene barrier layer (150) and on the first dielectric layer (ILD1) (128). In various embodiments, the second dielectric layer (ILD2) (152) may include silicon and oxygen-containing dielectric materials such as silicon oxide, silicon oxynitride, and low-k materials such as fluorine-doped silicon dioxide, organic silicate glass including carbon-doped oxide, porous silicon dioxide, porous organic silicate glass, and other silicon and oxygen-containing spin-on dielectrics. The second dielectric layer (ILD2) (152) may also include an air gap in some embodiments. The second dielectric layer (ILD2) (152) can be deposited in various embodiments using a thermal process, a chemical vapor deposition (CVD) process, e.g., CVD, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), negative pressure CVD (SACVD), plasma enhanced CVD (PECVD), and a spin-on process.

[0056] In the block (311) of FIG. 3a and the cross-sectional view of FIG. 3g, by performing annealing, Mn diffuses from the Mn-doped Cu interconnect wire (130) and through the defect (119) in the graphene barrier layer (150) to the interface of the Mn-doped Cu interconnect (130) / second dielectric layer (ILD2) (152). Mn reacts with Si and O in the second dielectric layer (ILD2) (152) to self-form a MnSiO barrier layer (154) that blocks Cu from diffusing into the second dielectric layer (ILD2) (152) or electron transferring to degrade the second dielectric layer (ILD2) (152). The self-formed MnSiO barrier layer (154) may be formed as a plurality of discontinuous regions around the graphene barrier layer (150) at locations around the defect (119). Annealing may be performed in a batch furnace or in a single wafer annealing chamber. During annealing, the substrate (100) may be heated to a temperature of 200°C to 500°C. In one embodiment, annealing may be performed at 300°C to 400°C. In various embodiments, the substrate (100) may be annealed for a duration of 60 seconds to 3600 seconds.

[0057] The advantage of the present embodiment over the embodiments described in FIGS. 2a through 2e is that, in addition to forming a barrier layer on the top surface, an optional graphene barrier layer (150) as well as a self-formed MnSiO barrier layer (154) are formed on the sidewall surface of the Mn-doped copper interconnect wire (130). The formation of barriers on the sidewall further reduces the resistance of the Mn-doped Cu interconnect wire (130). In this embodiment, the optional graphene barrier layer (150) as well as the self-formed MnSiO barrier layer (154) provide reliability by blocking copper electron transfer into the surrounding second dielectric layer (ILD2) (152). Since the optional graphene and the self-formed MnSiO barrier layer (154) are ultrathin films (almost monolayers), they provide exceptionally low electrical resistance. Additionally, the optional graphene barrier layer (150) as well as the self-formed MnSiO barrier layer (154) improve carrier mobility and reduce wire resistance by providing an atomically smooth surface between the graphene barrier layer (150) and the Mn-doped copper interconnect wire (130).

[0058] By repeating the procedure of the embodiment, an additional Mn-doped copper interconnect layer may be formed on the second dielectric layer (ILD2) (152). Thus, each metal wiring level may include optional graphene and Mn barrier configurations.

[0059] FIG. 4a is a flowchart illustrating a process for forming a selective copper barrier layer on damascene copper using Mn and graphene according to an embodiment and for manufacturing a semiconductor device. This process can further reduce the complexity and cost of the damascene embodiment by eliminating the formation of a barrier layer before copper electroplating and by eliminating the removal of a barrier layer before depositing a graphene barrier layer.

[0060] FIGS. 4b to 4i schematically illustrate the steps of the flowchart of FIG. 4a for forming an element according to an embodiment of the present invention through cross-sectional views.

[0061] Now refer to block (401) in FIG. 4a and the cross-sectional view in FIG. 4b. FIG. 4b is a cross-sectional view of a substrate (100) overlaid with a first dielectric layer (128). A metal-filled via (132) (optional) protrudes through the first dielectric layer (128) which is stationary on the substrate (100). The substrate (100) may be a semiconductor substrate comprising electrical elements such as a transistor, a resistor, a capacitor, a diode, and a memory cell. The first dielectric layer (128) may be a dielectric material such as silicon oxide, silicon oxynitride, and a low-k material such as an organicsilicate glass comprising fluorine-doped silicon dioxide, carbon-doped oxide, porous silicon dioxide, porous organicsilicate glass, and other silicon and oxygen-containing spin-on dielectrics. The first dielectric layer (128) may also include an air gap in some embodiments. The first dielectric layer (128) can be deposited in various embodiments using a thermal process, a chemical vapor deposition (CVD) process, e.g., CVD, low-pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), negative pressure CVD (SACVD), plasma-enhanced CVD (PECVD), and a spin-on process. The metal-filled vias (132) can be filled with metals such as tungsten, copper, ruthenium, iridium, cobalt, and nickel.

[0062] In the cross-sectional view of block (403) and FIG. 4c, a disposable second dielectric layer (134) is deposited on the first dielectric layer (128). In one embodiment, the disposable second dielectric layer (134) may be a dielectric layer with the same material as the first dielectric layer (128) and may be deposited in a similar manner. Using conventional lithography techniques, a damascene trench pattern (137) may be formed on the disposable second dielectric layer (134).

[0063] In block (405) and the cross-sectional view of FIG. 4d, a damascene trench is etched into the disposable second dielectric layer (134). The upper surface of the metal-filled via (132) (if present) is exposed.

[0064] In block (407) and the cross-sectional view of FIG. 4e, the damascene trench pattern (137) is removed, and a thin manganese-containing copper seed layer (139) is deposited on the surface of the damascene trench etched into the disposable second dielectric layer (134) and on the surface of the disposable second dielectric layer (134). In a conventional copper damascene process, the copper seed layer (139) is deposited over a copper barrier layer such as Ti, TiN, Ta, or TaN. In this embodiment, the deposition of the copper barrier layer may be omitted. The copper seed layer (139) assists in conducting electricity during the initial stage of copper electroplating. The seed layer (139) may be deposited using various physical vapor deposition methods such as sputtering, evaporation, and ion metal plasma deposition. In this embodiment, since the disposable second dielectric layer (134) will be removed, there is no concern about performance degradation of the disposable second dielectric layer (134) due to copper electron migration. By omitting the deposition of conventional barrier layers such as Ti, TiN, Ta, and TaN, the deposition tools and deposition materials are eliminated, and the cycle time is reduced, thereby reducing costs.

[0065] Now, referring to block (409) in FIG. 4a and the cross-sectional view in FIG. 4f, in the damascene process, the damascene trench is filled with electroplated manganese containing copper and then flattened using chemical mechanical polishing (CMP). During the CMP flattening process, any excess electroplated copper overfill and copper seed layer (139) are polished from the surface of the flattened second dielectric (134).

[0066] In the cross-sectional view and block (411) illustrated in FIG. 4g, an additional process includes the step of etching a first dielectric layer (ILD1) (128) adjacent to the Mn-doped copper interconnect wire (130) to further expose the sidewalls of the Mn-doped copper interconnect wire (130). In this embodiment, since the barrier layer does not cover the sidewalls of the Mn-doped copper interconnect wire (130), the equipment, materials, and process time required to remove conventional barrier layers such as Ti, TiN, Ta, and TaN are eliminated, thereby reducing process costs.

[0067] In the block (413) of FIG. 4a and the cross-sectional view shown in FIG. 4h, as described above, nearly one monolayer of graphene barrier layer (150) is deposited on the exposed top and sidewall surfaces of the Mn-doped Cu interconnect wire (130).

[0068] In the block (415) of FIG. 4a and the cross-sectional view shown in FIG. 4i, as described above, a third dielectric layer (ILD3) (152) containing silicon and oxygen is deposited on the graphene barrier layer (150) and on the first dielectric layer (ILD1) (128).

[0069] In the block (417) of FIG. 4a and the cross-sectional view shown in FIG. 4j, annealing is performed so that Mn diffuses from the Mn-doped Cu interconnect wire (130) and through defects (119) within the graphene barrier layer (150) to the Mn-doped Cu interconnect (130) / third dielectric layer (ILD3) (152) interface. During annealing, Mn diffuses from the Mn-containing copper seed layer (139) and from the Mn-containing copper wire (130) to form a MnSiO barrier layer (157) between the bottom of the Mn-containing copper wire (130) and the top surface of the first dielectric layer (128).

[0070] The advantage of the present embodiment over the embodiments described in FIGS. 3a through 3g is that it eliminates the process equipment, process chemicals, and cycle time required to first deposit a copper barrier layer on the interlayer dielectric before copper deposition. It also eliminates the process equipment, process chemicals, and cycle time required to remove the copper barrier layer before depositing the graphene barrier layer. In this embodiment, a copper wire having a thin, low-resistance barrier layer of one embodiment is formed using a low-cost copper damascene process.

[0071] Exemplary embodiments of the present invention are summarized herein. Other embodiments may be understood from the entire specification as well as from the claims submitted herein.

[0072] Example 1. A method for forming a semiconductor device comprises the steps of: providing a substrate having a patterned film containing manganese; depositing a graphene layer on an exposed surface of the patterned film; depositing a dielectric layer containing silicon and oxygen on the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

[0073] Example 2. Method of Example 1, wherein the manganese-containing diffusion barrier region comprises manganese, silicon, and oxygen.

[0074] Example 3. A method in which, in either Example 1 or 2, the heat treatment step comprises heating the substrate to a temperature of 200°C to 500°C.

[0075] Example 4. Any one of Examples 1 to 3, further comprising the step of performing a damascene process to form the patterned film within another dielectric layer below the dielectric layer, wherein the patterned film forms a copper interconnect wire.

[0076] Example 5. A method in any one of Examples 1 to 4, further comprising the step of etching a portion of the other dielectric layer adjacent to the patterned film to expose the sidewalls of the patterned film before depositing the graphene layer.

[0077] Example 6. A method comprising, in any one of Examples 1 to 5, further a step of removing a barrier layer from the sidewall of the patterned film.

[0078] Example 7. A method in any one of Examples 1 to 6, wherein the exposed surface is the upper surface and the sidewall surface of the patterned film.

[0079] Example 8. Any one of Examples 1 to 7, further comprising the step of performing a double damascene process to form the patterned film within another dielectric layer below the dielectric layer, wherein the patterned film forms a copper interconnect wire.

[0080] Example 9. A method in any one of Examples 1 to 8, wherein the patterned film comprises the manganese-doped copper alloy.

[0081] Example 10. A method in any one of Examples 1 to 9, wherein the patterned film further comprises ruthenium, cobalt, tungsten, nickel, or iridium.

[0082] Example 11. A method for forming a semiconductor device comprises the steps of: providing a substrate comprising a first dielectric layer comprising silicon and oxygen and a metal wiring layer; depositing a barrier layer on the metal wiring layer and on the first dielectric layer; depositing a conductive film comprising manganese on the barrier layer; heat-treating the substrate for a first time to form a first manganese-containing diffusion barrier region between the barrier layer and the first dielectric layer; patterning and etching the conductive film to form a patterned conductive film on the first manganese-containing diffusion barrier region; depositing a graphene layer on the upper surface of the conductive film and on the sidewall surface; depositing a second dielectric layer comprising silicon and oxygen on the graphene layer; and heat-treating the substrate for a second time to form a second manganese-containing diffusion barrier region.

[0083] Example 12. The method of Example 11, wherein the first and second manganese-containing diffusion barrier regions comprise manganese, silicon, and oxygen.

[0084] Example 13. A method in which, in either Example 11 or 12, the step of heat treating for the first and second times comprises the step of heating the substrate to a temperature of 200°C to 500°C.

[0085] Example 14. A method in any one of Examples 11 to 13, wherein the step of heat treating for the first time melts the barrier layer between the metal wiring layer and the conductive film.

[0086] Example 15. A method in any one of Examples 11 to 14, wherein the conductive film comprises copper and the barrier layer comprises manganese.

[0087] Example 16. A semiconductor device comprises: a substrate comprising a patterned copper film containing manganese; a graphene layer disposed on an exposed surface of the patterned copper film; a first manganese-containing diffusion barrier layer disposed on a portion of the graphene layer; and a first dielectric layer comprising silicon and oxygen disposed on the first manganese-containing diffusion barrier layer and on the graphene layer.

[0088] Example 17. The semiconductor device of Example 16, further comprising: a second dielectric layer comprising silicon and oxygen; a barrier layer between the patterned copper film and the second dielectric layer; and a second manganese-containing diffusion barrier layer between the second dielectric layer and the barrier layer.

[0089] Example 18. A semiconductor device in which, in either Example 16 or 17, the first and second manganese-containing diffusion barrier layers comprise manganese, silicon, and oxygen.

[0090] Example 19. A semiconductor device in any one of Examples 16 to 18, wherein the barrier layer comprises manganese.

[0091] Example 20. A semiconductor device in any one of Examples 16 to 19, wherein the graphene layer is approximately one monolayer thick.

[0092] Example 21. A method for forming a semiconductor device comprises the steps of: providing a substrate having a manganese-containing copper interconnect wire formed using a damascene process within a first dielectric layer; depositing a graphene layer on an exposed surface of the manganese-containing copper interconnect wire; depositing a second dielectric layer on the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region.

[0093] Example 22. Method of Example 21, wherein the exposed surface is the upper surface of the manganese-containing copper interconnect wire.

[0094] Example 23. A method in which, in either Example 21 or 22, a portion of the first dielectric layer adjacent to the manganese-containing copper interconnect wire is etched to expose the sidewall of the manganese-containing copper interconnect wire before depositing the graphene layer.

[0095] Example 24. A method comprising, in any one of Examples 21 to 23, further a step of removing a barrier layer from the sidewall of the manganese-containing copper interconnect wire.

[0096] Example 25. A method in any one of Examples 21 to 24, wherein the exposed surface is the upper surface and sidewall surface of the manganese-containing copper interconnect wire.

[0097] Example 26. The method of Example 23, further comprising the steps of: forming the manganese-containing copper interconnect wire by depositing a manganese-containing copper seed layer on the first dielectric layer and on the surface of the damascene trench; electroplating manganese-containing copper to fill the damascene trench; flattening the surface of the manganese-containing copper interconnect wire so as to be coplanar with the surface of the first dielectric layer; etching the first dielectric layer to expose the sidewalls of the manganese-containing copper interconnect wire; and depositing a graphene barrier layer.

[0098] Although the present invention has been described with reference to exemplary embodiments, such description is not intended to be interpreted in a limiting sense. By referring to the description, various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art. Accordingly, the appended claims are intended to include any such modifications or embodiments.

Claims

Claim 1 A method for forming a semiconductor device, the method comprising: providing a substrate having a patterned film containing manganese; depositing a graphene layer on an exposed surface of the patterned film, wherein the graphene layer contains a plurality of defects; depositing a dielectric layer containing silicon and oxygen on the graphene layer; and heat-treating the substrate to form a plurality of manganese-containing diffusion barrier regions between the graphene layer and the dielectric layer, wherein each of the plurality of manganese-containing diffusion barrier regions is formed at a respective defect among the plurality of defects, and the plurality of manganese-containing diffusion barrier regions are discontinuous regions. Claim 2 A method according to claim 1, wherein the plurality of manganese-containing diffusion barrier regions comprises manganese, silicon, and oxygen. Claim 3 A method according to claim 1, wherein the heat treatment step comprises heating the substrate to a temperature of 200°C to 500°C. Claim 4 The method of claim 1 further comprises the step of performing a damascene process to form the patterned film within another dielectric layer below the dielectric layer, wherein the patterned film forms a copper interconnect wire. Claim 5 A method according to claim 4, further comprising the step of etching a portion of the other dielectric layer adjacent to the patterned film to expose the sidewalls of the patterned film before depositing the graphene layer. Claim 6 A method according to claim 5, further comprising the step of removing a barrier layer from the sidewall of the patterned film. Claim 7 In paragraph 5, the method wherein the exposed surface is the upper surface and sidewall surface of the patterned film. Claim 8 A method according to claim 1, further comprising the step of performing a double damascene process to form the patterned film within another dielectric layer below the dielectric layer, wherein the patterned film forms a copper interconnect wire. Claim 9 A method according to claim 1, wherein the patterned film comprises a manganese-doped copper alloy. Claim 10 A method according to claim 1, wherein the patterned film further comprises ruthenium, cobalt, tungsten, nickel, or iridium. Claim 11 A method for forming a semiconductor device, the method comprises: providing a substrate comprising a first dielectric layer comprising silicon and oxygen and a metal wiring layer; depositing a barrier layer on the metal wiring layer and on the first dielectric layer; depositing a conductive film comprising manganese on the barrier layer; heat-treating the substrate for a first time to form a first manganese-containing diffusion barrier region between the barrier layer and the first dielectric layer; patterning and etching the conductive film to form a patterned conductive film on the first manganese-containing diffusion barrier region; depositing a graphene layer on the upper surface of the patterned conductive film and on the sidewall surface, wherein the graphene layer comprises a plurality of defects; and depositing a second dielectric layer comprising silicon and oxygen on the graphene layer. A method for forming a semiconductor device, comprising the step of heat-treating the substrate for a second time to form a second manganese-containing diffusion barrier region, wherein the second manganese-containing diffusion barrier region comprises a plurality of manganese-containing diffusion barrier regions, each of the plurality of manganese-containing diffusion barrier regions is formed at a respective defect among the plurality of defects, and the plurality of manganese-containing diffusion barrier regions are discontinuous regions. Claim 12 In claim 11, the method wherein the first and second manganese-containing diffusion barrier regions comprise manganese, silicon, and oxygen. Claim 13 In claim 11, the step of heat treating during the first and second times comprises the step of heating the substrate to a temperature of 200°C to 500°C. Claim 14 In claim 11, the step of heat treating during the first time is a method of dissolving the barrier layer between the metal wiring layer and the conductive film. Claim 15 A method according to claim 11, wherein the conductive film comprises copper and the barrier layer comprises manganese. Claim 16 A semiconductor device comprising: a substrate comprising a patterned copper film containing manganese; a graphene layer disposed on an exposed surface of the patterned copper film, wherein the graphene layer comprises a plurality of defects; a first manganese-containing diffusion barrier layer disposed on a portion of the graphene layer, wherein the first manganese-containing diffusion barrier layer comprises a plurality of manganese-containing diffusion barrier regions; and a first dielectric layer comprising silicon and oxygen disposed on the first manganese-containing diffusion barrier layer and on the graphene layer, wherein each of the plurality of manganese-containing diffusion barrier regions is formed at each of the respective defects among the plurality of defects, and the plurality of manganese-containing diffusion barrier regions are discontinuous regions. Claim 17 A semiconductor device according to claim 16, further comprising: a second dielectric layer comprising silicon and oxygen; a barrier layer between the patterned copper film and the second dielectric layer; and a second manganese-containing diffusion barrier layer between the second dielectric layer and the barrier layer. Claim 18 In claim 17, the semiconductor device wherein the first and second manganese-containing diffusion barrier layers comprise manganese, silicon, and oxygen. Claim 19 In claim 17, the semiconductor device wherein the barrier layer comprises manganese. Claim 20 A semiconductor device according to claim 16, wherein the graphene layer is approximately one monolayer thick.

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