Vertical stacked device architecture and formation of low-temperature and high-temperature in situ doped source and drain epitaxy using selective heating for wrap-around contacts

Abstract

The technology of the present invention provides a heat treatment solution applicable to all existing FinFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistors and gate-on-gate monolithic or heterogeneous CFETs. The technology includes the step of heating or annealing a first target material without affecting or heating the performance of a second material or other materials. The technology includes the step of heating a substrate and a material provided thereon to a first temperature using a first heating process, and then, using a wavelength / frequency variable second heating process, increasing the temperature of the target material without increasing the temperature of the second material or other materials.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] The present disclosure claims the benefit of U.S. Provisional Application No. 63 / 064,876 filed August 12, 2020, and U.S. Regular Application No. 17 / 196,137 filed March 9, 2021, the entire contents of which are incorporated herein by reference.

[0003] The present disclosure relates to a method for manufacturing a semiconductor device. In particular, a device process is performed in which a high-temperature process is completed before the deposition of a predetermined metal. Background Technology

[0004] The background description provided herein is generally intended to provide the background of the present disclosure. The work of the inventors currently designated is not explicitly or implicitly recognized as prior art compared with the present disclosure, to the extent that the work is described in these background sections, as well as in the modes of description that may not otherwise be limited as prior art at the time of filing.

[0005] When manufacturing semiconductor CMOS devices, high-temperature processes such as epitaxy growth and activation annealing are performed before the deposition of metals, such as the work function metal of the HKMG (high-k metal gate), the silicide used to manufacture the contact between the source / drain and the interconnect, and the porous ultra-low k film used as the dielectric of the back end of the line metal layer.

[0006] The present disclosure relates to a method for manufacturing a semiconductor device, comprising the steps of: providing a substrate comprising a first material and a second material disposed on the surface of a substrate; heating the substrate, the first material, and the second material to a first temperature using a first heating process, wherein the first temperature is less than a predetermined threshold temperature; and heating the first material to a second temperature using a second heating process, wherein the second heating process heats the first material more than the second material, and the second temperature is less than a predetermined threshold temperature.

[0007] Additionally, the present disclosure relates to a system for manufacturing a semiconductor device, comprising: a process chamber configured to receive a wafer; a first heating device configured to heat the process chamber and the wafer, wherein the wafer comprises a first material and a second material; and a second heating device configured to direct energy to the wafer at one or more predetermined wavelengths having a predetermined intensity to heat the first material on the wafer.

[0008] It should be noted that this summary does not specify all embodiments and / or progressively new aspects of the present disclosure or the claimed invention. Instead, this summary provides only a preliminary description of different embodiments and their elements of novelty. For further details and / or possible aspects of the invention and embodiments, the reader refers to the detailed description of the present disclosure and the drawings as further described below. Brief explanation of the drawing

[0009] Various embodiments of the present disclosure proposed as examples will be described in detail with reference to the following drawings, in which similar numbers indicate similar elements, and as drawings: FIG. 1 is an example of a heat treatment step for a fin field-effect transistor logic device. FIG. 2 is an example of a CFET type process flow for device-on-device stacking. FIGS. 3a to 3c are schematic cross-sectional views of various source and drain contact structures according to one embodiment of the present disclosure. FIG. 4 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 5 is a schematic block diagram of a system for manufacturing a semiconductor device using selective heating according to one embodiment of the present disclosure. FIG. 6 is a schematic diagram of a computer for controlling components of a system according to one embodiment. Specific details for implementing the invention

[0010] The following disclosure provides a number of different embodiments or examples for implementing different features of the claimed subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various embodiments. Such repetition is for the purpose of brevity and clarity and does not affect the relationship between the various embodiments and / or configurations described. Additionally, spatially relative terms such as "upper," "lower," "below," "lower," "above," and "upper" may be used herein for convenience of explanation to describe the relationship of one element or feature to other element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to include different orientations of the element being used or operated, in addition to the orientations illustrated in the drawings. The device may be oriented differently (it may be rotated 90 degrees or in other directions), and spatially relative terms used herein may likewise be interpreted accordingly.

[0011] For clarity, the order of description of different steps as described herein is provided. In general, these steps may be performed in any suitable order. Additionally, while each different feature, technique, configuration, etc. of this invention may be described in different places within this disclosure, each concept is intended to be performed independently or in combination with one another. Accordingly, the invention may be embodied and considered in a number of different ways.

[0012] FIG. 1 illustrates an example of a heat treatment step for a FIN field-effect transistor (FINFET) logic device. A number of high-temperature processes, such as shallow trench insulation (STI) annealing, silicon pre-cleaning and epitaxial growth, and high-k reliability annealing, are completed before the deposition of work function metal within the HKMG structure and the formation of silicide within the contact / interconnection module. The structure in step (105) illustrates, for example, STI annealing at 1000°C. The structure in step (110) illustrates, for example, Si pre-cleaning at 750°C to 800°C. The structure in step (115) illustrates, for example, the formation of a source / drain for an NMOS device at 600°C to 700°C. The structure in step (120) illustrates, for example, the formation of a source / drain for a PMOS device at 525°C to 650°C. The structure in step (125) illustrates, for example, reliability annealing at 700°C to 780°C. The structure in step (130) illustrates, for example, source / drain activation for NMOS and PMOS devices at 800°C to 1,100°C. The structure in step (135) illustrates the deposition of a work function metal. The structure in step (140) illustrates silicide formation. The structure in step (145) illustrates, for example, post-metallization annealing of interconnect metal wiring at 450°C. The structure in step (150) illustrates metal wiring.

[0013] However, this temperature-based integration trend is difficult to implement with 3D devices (i.e., architectures featuring vertical stacks of field-effect transistors). Two significant changes in CMOS device manufacturing are transforming the thermal management process flow. One change involves the need to use wrap-around contacts (WACs), where silicides are formed over as much of the source and drain contact surface area as possible, as well as the interconnect metal. The purpose is to reduce contact resistance as a mechanism to increase the device's overall Power / Performance / Area (PPA) metric. The second change involves the introduction of 3D logic architectures, such as transistor-on-transistor stacking or gate-on-gate stacking. 3D stacking can be performed, for example, using complementary field-effect transistor (CFET) type devices. The formation of stacked devices can be achieved through monolithic stacking (single wafer) or heterogeneous stacking (wafer-on-wafer).

[0014] FIG. 2 illustrates an example of a CFET-type process flow for device-on-device stacking. In particular, a bottom device interconnect is to be fully formed, and a temperature-sensitive silicide is formed on the bottom interconnect structure before an additional high-temperature process is performed for the subsequent device to be formed on top of the device. The fully formed bottom interconnect may cause process issues, such as maintaining a thermal control level during subsequent processes to prevent damage to the sensitive metal or silicide formed on the completed bottom device. The structure in step (205) illustrates, for example, the formation of a source / drain for an NMOS device at 600°C to 700°C. The structure in step (210) illustrates the formation of an NMOS silicide. The structure in step (215) illustrates, for example, annealing after metal wiring at 450°C to 650°C. The structure in step (220) illustrates, for example, Si pre-cleaning at 750°C to 800°C. The structure in step (225) illustrates, for example, the formation of a source / drain for a PMOS device at 550°C to 650°C. The structure in step (230) illustrates the formation of PMOS silicide. The structure in step (235) illustrates, for example, reliability annealing at 700°C to 780°C. The structure in step (240) illustrates, for example, the activation of a source / drain for NOMS and PMOS devices at 800°C to 1,100°C. The structure in step (245) illustrates work function metal deposition. The structure in step (250) illustrates, for example, post-metal wiring annealing at 450°C.

[0015] In the case of the aforementioned monolithically formed CFET device, since contact formation, silicidation, and subsequent metal wiring of the bottom and top devices are performed prior to the high-k metal gate (HKMG) process, the silicidation on the bottom device will undergo reliability annealing within the HKMG process as well as heat treatment related to the step of forming the top device structure. In the case of a heterogeneous CFET device, the process is similar except that the bottom device likewise has a bottom transistor formed prior to the formation of the top device and transistor. Both integrates of the CFET device will have the same fundamental thermal limit.

[0016] This problem is exacerbated by stacking multiple CFET structures in sequence to form multiple planes of logic devices for future CMOS proportional scaling. As with CFET devices, WACs often require that silicide formations be created around source and drain contacts before any high-temperature process is completed within the HKMG process. However, unlike CFET devices, interconnects for FinFET-based devices using wrap-around contacts will not allow any interconnect metal wiring to be completed. Nevertheless, silicides still pose a problem because they are thermally sensitive materials that can undergo phase changes or aggregation associated with higher-temperature processes.

[0017] Accordingly, the technology of the present invention provides a thermal treatment solution applicable to 3D architectures, such as transistor-on-transistors and gate-on-gate monolithic or heterogeneous CFETs, as well as to existing FinFET applications (including WAC). The technology comprises the step of heating or annealing a first (target) material without affecting or heating the performance of the second material(s). The technology comprises the step of heating a substrate to a first temperature using a first heating mechanism, and then, using a wavelength / frequency tunable second heating mechanism, increasing the temperature of the target material without increasing the temperature of the second material.

[0018] FIGS. 3a through 3c are schematic cross-sectional views of various source and drain contact structures according to one embodiment of the present disclosure. FIG. 3a is a schematic cross-sectional view of an n-type source and drain contact structure prior to metal wiring. FIG. 3b is a schematic cross-sectional view of a wrap-around contact prior to metal wiring. FIG. 3c is a schematic cross-sectional view of a CFET contact in which local interconnects are metal-wired prior to subsequent complementary device formation. In the case of the process used in FIG. 3a, silicides may be formed after local interconnection trenches are used to open the source and drain epitaxial contacts. Typically, a protective liner (e.g., a SiN or SiCN liner) may be used to prevent oxygen diffusion into the contacts or damage caused by the etching process of opening the interconnection trenches. Such a protective liner is easily removed with little to no damage to the surface of the source and drain contacts. In the case of the process used in Fig. 3b, the silicide must cover the surface of as many source and drain contacts as possible. Given the limitations on the size of the interconnect trench width, the silicide is formed after the epitaxial growth of the source and drain contacts, considering that the interconnect trench cannot easily overlap the entire contact structure without causing an area penalty to the standard cell. Thus, the silicide is placed in place before the opening of the contacts through the interconnect trenches, which is typically completed after the HKMG process, where a high-temperature process (e.g., reliability annealing) is completed. In Fig. 3c, the CFET contacts follow a process similar to WAC, except that the interconnect metal electrodes are formed and metal-wired before the HKMG process. Therefore, the silicide is susceptible to arbitrary control of the diffusion of dopant species from the contacts to the high-conductivity interconnect metal, as well as the selection of the interconnect metal and the temperature influence of the reliability annealing process.

[0019] Accordingly, in one embodiment, when silicide is grown on the source and drain contacts, a maximum heat treatment temperature of 500°C may be set. For example, in the case of a CFET device with a bottom element formed, the maximum heat treatment temperature may indicate that the top source and drain epitaxy formation must be completed at 500°C. For current device geometries and stacked FET devices, the source and drain epitaxy may be grown by in-situ doping, where the solubility of the dopant species into the source and drain epitaxy is thermally dependent. For example, in the case of phosphorus in-situ doping of epitaxial silicon, such as used for NMOS devices, the nominal doping level achieved at a nominal process temperature of 700°C is 1E21 atoms / cm³ 3 It can exceed. If this temperature is reduced to 500℃, the maximum doping that can be achieved is 7E20 atoms / cm² 3 The result of reduced doping levels in source and drain epitaxy is a significant reduction in contact resistance, which has a direct adverse effect on the chip's PPA metric.

[0020] The ability to selectively heat a single material or a set of materials selectively relative to other materials in the present invention provides some mechanism for solving the problem highlighted above. The technology of the present invention can selectively target specific materials within a device stack using microwave annealing. Microwave annealing systems utilize variable microwave energy within a given spectral range. Such variable systems can be used to isolate materials for selective heating. It is understood that there are various microwave annealing systems commonly available for selectively heating isolated materials.

[0021] In the case of an embodiment of a CFET device in which the bottom source and drain are grown, silicides are formed, and the bottom interconnects are metal-wired, the top epitaxial growth can be performed at a process chamber temperature of 500°C, along with microwave annealing that primarily targets the material used in the top device. As a specific embodiment that is not limited, where the bottom device is an NMOS in which the source and drain are composed of epitaxial silicon having phosphorus doped in situ with titanium silicide and the interconnect structure is metal-wired with a high conductivity metal such as cobalt or ruthenium, the top PMOS device is composed of boron-doped silicon germanium (typically, the germanium component is in the range of 25 to 50 atomic percent) to provide lattice mismatch-induced strain to the PMOS silicon channel to induce mobility across the channel.

[0022] By tuning the microwave frequency to be selective for silicon germanium due to less absorption by silicon, the top source and drain epitaxy can be heated to temperatures exceeding 500°C to enable increased dopant solubility into the contacts. Meanwhile, the silicon-phosphorus contacts on the bottom device will face only the chamber temperature and any energy resulting from reduced microwave absorption and any thermal diffusion from the top device structure. This method can be used to preserve the thermal limit of the bottom device while allowing the top device to be processed using a temperature that increases dopant solubility to a level where the desired contact resistance can be achieved for the top device. The microwave frequency range of the variable microwave annealing system is 2 GHz to 7 GHz, or 5.5 GHz to 6.5 GHz.

[0023] Silicon and silicon germanium will absorb microwave energy of discrete frequencies. However, when doping species are added to these epitaxial materials, the absorption frequency or wavelength may change. Therefore, the level of selectivity must be identified to adjust the annealing process, for example, by increasing or decreasing a specific wavelength to match the absorption rate and absorbance of the doping species. For example, in the case mentioned above, the top device in situ doping epitaxial growth process may be initially set to a chamber temperature of 500°C to enable an appropriate doping saturation level. Then, microwave annealing targeted to the partially doped silicon germanium is activated to increase dopant saturation by selectively heating the top source and drain to a higher temperature. Accordingly, the system and method of the present invention include the step of changing the wavelength of microwave annealing during the physical annealing process.

[0024] In some embodiments, the actual microwave annealing arrangement may be configured as a remote process within the chemical vapor deposition (CVD) epitaxy chamber itself. Alternatively, a sequential chamber process may be used in which the targeted material is annealed at a high temperature and then transferred to an epitaxy CVD chamber for processing.

[0025] In some embodiments, laser heating may be included. Selective heating may be additionally (or instead) provided by using a specific laser frequency in which different wavelengths are more readily absorbed into the material (e.g., silicon) and provide appropriate absorption selectivity for other species, such as phosphorus-doped silicon, silicon germanium, or germanium. Thus, alternative techniques may perform schematic functions as described herein by using energy supplied by a variable laser. The predetermined wavelength range of a variable laser annealing system may be 700 nm to 2,000 nm, or 800 nm to 1,500 nm, or 900 nm to 1,300 nm. It is understood that there are various laser annealing systems commonly available.

[0026] In one embodiment, the channel is formed as part of a CMOS device. The channel can be formed from various materials such as silicon, silicon germanium, germanium, and doped silicon. A dielectric material, such as a low-k spacer or a gate spacer, forms an opening at one end of one or both lateral ends of the channel of the CMOS device. The spacer may subsequently be removed to form what is commonly known as an air-gap gate spacer. Alternatively, the spacer may remain as a physical dielectric barrier between the metal gate and the metal contact electrode. Initial source and drain epitaxial growth may be initiated from the ends of the channel at a temperature within specification limits set by the current thermally sensitive material within the corresponding integration flow. For example, the initial source and drain epitaxial growth may be limited to the temperature threshold of the fabricated device element or material on the wafer. The initial epitaxial growth may be undoped or doped. The dopant concentration may be limited by the maximum allowable thermal specification (i.e., temperature threshold) set by the integration process.

[0027] The deposition temperature of the initial deposition may range from the minimum required temperature for undoped source / drain epitaxial growth (e.g., as low as 400°C) to the maximum temperature allowed by integration. For example, in the case of a CFET device where TiSi is used as the silicide for the bottom device, the maximum thermal temperature may be 500°C to 700°C. The range may depend on the phase change of the silicide contained within the device and the duration of the annealing process.

[0028] After a portion of the source / drain structure has been formed / grown using a lower chamber temperature, a selective heating mechanism can be activated to increase the dopant saturation into the continuously growing epitaxial film by heating a selective epitaxial material for a wafer material having a lower thermal threshold. For example, the first heating mechanism can heat the entire wafer. The first heating mechanism may be, for example, a chamber bake. Then, a second heating mechanism may be used to heat the source / drain material without heating the heat-sensitive material beyond a predetermined threshold. The second heating mechanism may be, for example, a variable microwave generator having sufficient material selectivity. The selected microwave annealing system may be configured to adjust the microwave energy so that it is readily absorbed by one species or material (e.g., silicon) but not sufficiently absorbed by a second material (e.g., silicon germanium) (and vice versa). This can be achieved by adjusting the emitted microwave wavelength of the microwave annealing system. The wavelength may have a narrow full-width half-max at its peak to increase selectivity for different materials and prevent overlap with other absorbance profiles.

[0029] Alternatively, the second heating mechanism may be a laser-based system in which light of different wavelengths can be used to be absorbed by specific materials that are selective to each other. For example, a wavelength-tunable laser system may be used. In some embodiments, three heating mechanisms may be used, such as a baking chamber, a variable microwave annealing system, and a variable laser annealing system.

[0030] As a specific exemplary embodiment, to form PMOS source and drain contacts having a very low doping profile, epitaxial silicon germanium (boron-doped in situ or not doped) may be grown from a silicon channel at an initial chamber temperature of 400°C to 500°C. After the initial growth of the silicon germanium (boron-doped in situ or not doped), secondary heating, such as selective annealing (e.g., variable microwave and / or laser annealing), may be performed to increase the temperature of the silicon germanium, or silicon germanium with boron in situ, without significant heating of any existing source / drain or channel material, such as silicon, or silicon with phosphorus or arsenic in situ or other doping species. Likewise, secondary heating can heat the target material without heating or damaging the existing silicified material on another formed device (e.g., a monolithic or heterogeneous CFET integrated device).

[0031] Increased temperature of silicon germanium or in situ-doped silicon germanium enables higher in situ doping levels of species such as boron into the film, thereby increasing the overall conductivity of the source and drain contacts. Due to the increased doping, lower contact resistance is produced compared to situations where the in situ dopant is limited to saturation corresponding to lower temperatures. These temperatures at which appropriate dopant saturation can occur may be approximately 600°C to 750°C, which may be outside the thermal stability limits of most silicides for other conventional devices that may exist in CFET-type architectures. Therefore, high-temperature annealing specific to the targeted material can be performed without heating the surrounding material beyond a level that degrades device performance.

[0032] As can be understood, various materials can be targeted without excessive heating of various other materials. For example, selective annealing may be performed, and the intended / target growth material is epitaxial silicon having in situ-doped phosphorus or other n-type doping species. Meanwhile, during selective annealing, materials such as in situ-doped silicon germanium source and drain contacts already present at the time of process or any formed silicon germanium are unaffected or are not significantly affected.

[0033] In addition, the mechanism for the selective heating process will also have in-process variable functions to reflect the changing characteristics of the film being deposited. For example, the initial growth of the target material (e.g., undoped silicon germanium from a silicon channel) can be achieved at the nominal CVD chamber temperature with or without any external heating from a microwave system or a laser system. If secondary heating is performed during the epitaxial deposition process, the frequency or wavelength used is set so that more absorption occurs in the silicon germanium on the in situ-doped silicon germanium and less absorption occurs into the silicon.

[0034] As dopant species are added to silicon germanium growth, microwave and laser absorption peaks may change. That is, for a predetermined wavelength, the absorption spectrum or cross-section of such material may change as the material composition changes. Accordingly, microwave annealing and / or laser annealing may have corresponding changes in frequency or wavelength during the process to maximize the absorbance for the targeted film as the targeted film is doped (and as the concentration changes). In some embodiments, a set of microwave frequencies may be targeted for the maximum selectivity difference in absorption between silicon germanium and silicon. During such processes in which an in situ dopant, such as boron, is introduced, the microwave frequency may be adjusted during the process to provide the maximum selectivity difference between in situ-doped silicon germanium and silicon or between in situ-doped silicon.

[0035] In one embodiment, the secondary heating mechanism can be controlled to be turned on or off, or the intensity of the annealing can be adjusted to control some level of heat separation from the intended targeted material or the overall heat transfer to the material where selectivity is desired. For example, any selective heating of an in situ doped silicide transferred to a bottom contact structure, where heat can be absorbed by the formed silicide structure, can cause crystal reorientation and thus have a negative effect on the device.

[0036] In one embodiment, a predictive or in-situ measurement controller may be configured to determine an appropriate sequence of frequency or wavelength modulation, the temporal timing of the process, etc. Such a heating sequence (changes in energy intensity and wavelength over time) optimizes the targeted absorption of energy into a specific species and maintains appropriate thermal control of the process throughout the entire device. Some heating sequences may include periods without secondary heating to allow the sensitive material to be cooled to a safer temperature.

[0037] In one embodiment, the selective heating process may be performed in a specific flow involving a number of doping paper processes to provide greater variability in selectivity possible within the process. For example, two dopant papers may be introduced into the contact forming, and dopant species A may be introduced into the process earlier to provide some functional coordination of heat absorption between the intended source and drain contacts and the already formed complementary source and drain contacts. Subsequently, as selectivity begins to decrease as dopant A is added into the film, the process may be switched to another dopant species with a corresponding transition to a second energy pattern.

[0038] In one embodiment, the system of the present invention includes a microwave annealing system and / or a laser annealing system physically embedded / integrated as part of a CVD epitaxy chamber. Alternatively, the microwave or laser annealing function is located in a separate chamber, and the process is separated into a sequence of deposition / selective heating / deposition / selective heating by passing the wafer under vacuum between the CVD epitaxy deposition chamber and the annealing chamber. The annealing chamber may be located within the same physical part of the hardware, but does not necessarily need to be located within the same process chamber. In the case of an embodiment comprising a sequential deposition process in a first chamber, selective annealing in a second chamber, and a process repeated multiple times for a given wafer, the transfer of the wafer between the two chambers is preferably performed under vacuum without any air blockage.

[0039] In an embodiment for processing a monolithic or heterogeneous CFET device in which complementary devices are stacked on top of each other, the dielectric film can encapsulate the already formed bottom device. During the growth of the top device in situ-doped epitaxial source and drain contacts, the dielectric can be adjusted to have thermal selectivity for the top source and drain epitaxial growth so that the dielectric blocks the absorption of any energy from microwave or laser annealing. Thus, the interlayer dielectric film functions as a high-temperature shield for wavelength-targeted annealing.

[0040] In another embodiment, the frequency and / or wavelength of the annealing can be adjusted to have selectivity for any dielectric film encapsulating any formed bottom element of the CFET device structure, so that some level of protection for the formed bottom element can be provided during the annealing and processing of the top element.

[0041] The selective heating function of the present invention can be extended to enable selectivity between high-k dielectric films, such as hafnium oxide and hafnium oxide having dipole dopant species such as AlO and LaO. Depending on the selectivity for source and drain contact materials, such as silicon, silicon having doped phosphorus or other n-type dopant species, silicon germanium, silicon germanium having doped boron or other p-type dopant species, germanium, and germanium having doped boron or other p-type dopant species, and formed silicide materials such as TiSi, RuSi, NiSi, NiPtSi, etc., the high-k film can be selectively annealed to an appropriate temperature to induce reliability improvement related to the removal of charge traps, while preventing the formed silicide from being heated to a temperature at which crystal reorientation can occur. As can be understood, the technology of the present invention can be applied to a number of structures and material systems in which one material can be selectively heated without overheating other materials.

[0042] FIG. 4 is a flowchart of a method (400) for manufacturing a semiconductor device using selective heating according to one embodiment of the present disclosure. In step (405), a substrate comprising a first material and a second material disposed on the surface of a substrate is provided. In step (410), the substrate, the first material, and the second material are heated using a first heating process, such as chamber baking. In step (415), the first material is heated using a second heating process. This can be performed so that the second material is heated less or at a slower rate than the first material. In particular, this enables processing of the first material while preventing unwanted effects on the second material occurring at a predetermined temperature threshold. In step (420), the dopant concentration in the first material can be determined. In particular, in step (425), the dopant concentration can be monitored throughout the entire heating process, and the peak wavelength of the second heating process can be adjusted based on the dopant concentration. In step (430), additional deposition may be performed, and a heating process may be performed again to selectively heat the deposited material.

[0043] FIG. 5 is a schematic block diagram of a system for manufacturing a semiconductor device using selective heating according to one embodiment of the present disclosure. In one embodiment, the system may be configured to perform a method (400). The system may include a process chamber (505); a first heating device (510) configured to heat the process chamber (505) and a wafer, wherein the wafer comprises a first material and a second material; and a second heating device (515) configured to direct energy to the wafer at one or more predetermined wavelengths having a predetermined intensity to heat the first material on the wafer. Additionally, the system may include a control device (600) comprising a processing circuit configured to perform the method (400). As previously described, it may be understood that there are various microwave and laser annealing systems commonly available for selectively heating separated materials.

[0044] Next, a hardware description of a control device according to an exemplary embodiment is described with reference to FIG. 6. In FIG. 6, the control device includes a CPU (600) that performs the aforementioned process. Process data and instructions may be stored in memory (602). Additionally, these processes and instructions may be stored on a storage media disk (604), such as a hard drive (HDD) or a portable storage medium, or may be stored remotely. Furthermore, the claimed improvements are not limited to the form of a computer-readable medium in which instructions for the process of the present invention are stored. For example, instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device that communicates with the control device, such as a server or computer.

[0045] Additionally, the claimed improvement may be provided as a utility application, a background daemon, or a component of an operating system, or a combination thereof, running with an operating system and CPU (600), such as Microsoft Windows 7, UNIX, Solaris, LINUX, Apple MAC-OS, and other systems known to those skilled in the art.

[0046] Hardware elements for achieving the control device may be implemented by various circuit elements known to those skilled in the art. For example, the CPU (600) may be a Xenon or Core processor from Intel, USA, an Opteron processor from AMD, USA, or other types of processors recognized by those skilled in the art. Alternatively, the CPU (600) may be implemented via an FPGA, ASIC, PLD, or using discrete logic circuits, as recognized by those skilled in the art. Additionally, the CPU (600) may be implemented as a plurality of processors that work in parallel to perform instructions of the process of the present invention described above.

[0047] Additionally, the control device of FIG. 6 includes a network controller (606), such as an Intel Ethernet PRO network interface card from Intel Corporation, USA, for interfacing with the network (650). As can be understood, the network (650) may be a public network such as the Internet, or a private network such as a LAN or WAN network, or any combination thereof, and may include a PSTN or ISDN sub-network. Additionally, the network (650) may be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network may be WiFi, Bluetooth, or any other known form of wireless communication.

[0048] The control unit further includes a display controller (608), such as an NVIDIA GeForce GTX or Quadro graphics adapter from NVIDIA Corporation, USA, for interfacing with a display (610), such as a Hewlett Packard HPL2445w LCD monitor. The universal I / O interface (612) is not only interfaced with a keyboard and / or mouse (614), but also with a touch screen panel (616) on or separate from the display (610). Additionally, the universal I / O interface (612) is connected to various peripherals (618), including any peripherals suitable for the electron microscope.

[0049] A general-purpose storage device controller (624) connects a storage media disk (604) to a communication bus (626), which may be ISA, EISA, VESA, PCI, or similar, in order to interconnect all components of the control device. A description of the overall features and functions of the display (610), keyboard and / or mouse (614), as well as the display controller (608), storage device controller (624), network controller (606), sound controller (620), and general-purpose I / O interface (612) is omitted herein for brevity as these features are known.

[0050] In the foregoing description, specific details, such as the specific shape of the process system and the description of the various components and processes used within it, have been detailed. However, it should be understood that the technology of the present invention may be implemented in other embodiments that deviate from these specific details, and that these details are for illustrative purposes only and are not limiting. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes and to provide a complete understanding, specific numbers, materials, and configurations have been detailed. Nevertheless, embodiments may be implemented without these specific details. Components having substantially the same functional configuration are indicated by similar reference numerals, so any redundant description may be omitted.

[0051] To aid in understanding various embodiments, various techniques have been described as multiple separate tasks. The order of description should not be interpreted to mean that these tasks must necessarily depend on the order. In practice, these tasks do not need to be performed in the order presented. The described tasks may be performed in a different order than that of the described embodiments. Various additional tasks may or may be performed in additional embodiments, and the described tasks may be omitted in additional embodiments.

[0052] As used herein, “substrate” or “target substrate” generally refers to an object processed according to the present invention. A substrate may comprise any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer placed on or over a base substrate structure such as a thin film. Accordingly, a substrate is not limited to any specific base structure, underlayer, or overlayer, whether patterned or unpatterned, but is considered to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to specific types of substrates, but this is for illustrative purposes only.

[0053] Furthermore, those skilled in the art will understand that many modifications may be made to the work of the technology described above while still achieving the same objective of the present invention. Such modifications are intended to be covered by the scope of this disclosure. Accordingly, the foregoing description of the embodiments of the present invention is not intended to be limiting. Rather, any limitations on the embodiments of the present invention are set forth in the following claims.

Claims

Claim 1 A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first transistor device comprising a first source / drain material; performing a first heating process on the substrate and the first transistor device to form a layer of a first silicide material from the first source / drain material; providing a second transistor device on the substrate comprising a second source / drain material, wherein the first silicide material has a first silicide material absorption wavelength and the second source / drain material has a second source / drain material absorption wavelength, and the first silicide material absorption wavelength is different from the second source / drain material absorption wavelength; and performing a selective heating process on the substrate, the first transistor device having the first silicide material, and the second transistor device using a selective wavelength based on the fact that the first silicide material absorption wavelength is different from the second source / drain material absorption wavelength, wherein the selective heating process is based on the second source / drain material absorption wavelength absorbing the selective wavelength of the selective heating process. A method for manufacturing a semiconductor device comprising: heating the second source / drain material by causing the source / drain material to reach a first temperature and keeping the first silicide material below a second temperature based on the absorption wavelength of the first silicide material absorbing the selective wavelength of the selective heating process to a minimum; performing a deposition process after performing the selective heating process; and repeating the step of performing the selective heating process and the step of performing the deposition process. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the step of heating the second source / drain material further comprises the step of irradiating the second source / drain material with the selective wavelength having a first intensity and a first peak wavelength through the selective heating process. Claim 3 A method for manufacturing a semiconductor device according to claim 2, further comprising the step of adjusting the selective wavelength having the first peak wavelength of the selective heating process while performing the selective heating process on the substrate, the first transistor device having the first silicide material and the second transistor device. Claim 4 A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first transistor device comprising a first source / drain material; performing a first heating process on the substrate and the first transistor device to form a layer of a first silicide material from the first source / drain material; and providing a second transistor device on the substrate comprising a second source / drain material, wherein the first silicide material has a first silicide material absorption wavelength, the second source / drain material has a second source / drain material absorption wavelength, and the first silicide material absorption wavelength is different from the second source / drain material absorption wavelength.The method comprises the step of performing a selective heating process on the substrate, the first transistor device having the first silicide material, and the second transistor device using a selective wavelength based on the fact that the absorption wavelength of the first silicide material is different from the absorption wavelength of the second source / drain material; wherein the selective heating process heats the second source / drain material by causing the second source / drain material to reach a first temperature based on the absorption wavelength of the second source / drain material absorbing the selective wavelength of the selective heating process, and causing the first silicide material to remain below a second temperature based on the absorption wavelength of the first silicide material absorbing the selective wavelength of the selective heating process to a minimum; and the step of heating the second source / drain material further comprises the step of irradiating the second source / drain material with the selective wavelength having a first intensity and a first peak wavelength through the selective heating process, and wherein, while performing the selective heating process on the substrate, the first transistor device having the first silicide material, and the second transistor device, A method for manufacturing a semiconductor device, comprising further comprising the step of adjusting the selective wavelength having the first peak wavelength of the selective heating process, wherein the method further comprises the step of determining the dopant concentration in the second source / drain material, and wherein the selective wavelength having the first peak wavelength of the selective heating process is adjusted based on the dopant concentration in the second source / drain material. Claim 5 delete Claim 6 delete Claim 7 A method for manufacturing a semiconductor device according to paragraph 2, wherein the step of performing the selective heating process follows a heating sequence comprising a set value of the selective wavelength having the first peak wavelength at the corresponding set value of the first intensity over a corresponding first time interval set. Claim 8 A method for manufacturing a semiconductor device according to claim 2, wherein the absorption wavelength of the first silicide material of the first silicide material does not include the selective wavelength having the first peak wavelength. Claim 9 A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first transistor device comprising a first source / drain material; performing a first heating process on the substrate and the first transistor device to form a layer of a first silicide material from the first source / drain material; and providing a second transistor device on the substrate comprising a second source / drain material, wherein the first silicide material has a first silicide material absorption wavelength, the second source / drain material has a second source / drain material absorption wavelength, and the first silicide material absorption wavelength is different from the second source / drain material absorption wavelength. A semiconductor device comprising: a step of performing a selective heating process on the substrate, the first transistor device having the first silicide material and the second transistor device using a selective wavelength based on the fact that the absorption wavelength of the first silicide material is different from the absorption wavelength of the second source / drain material; wherein the selective heating process heats the second source / drain material by causing the second source / drain material to reach a first temperature based on the absorption wavelength of the second source / drain material absorbing the selective wavelength of the selective heating process, and causing the first silicide material to remain below a second temperature based on the absorption wavelength of the first silicide material absorbing the selective wavelength of the selective heating process to a minimum; and wherein the step of heating the second source / drain material further comprises the step of irradiating the second source / drain material with the selective wavelength having a first intensity and a first peak wavelength through the selective heating process, and wherein the selective heating process comprises the step of using a variable microwave annealing system configured to emit at the first peak wavelength and the first intensity. Method of manufacturing. Claim 10 A method for manufacturing a semiconductor device according to claim 9, wherein the range of the first peak wavelength of the emission of the variable microwave annealing system is 42 to 150 millimeters. Claim 11 A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first transistor device comprising a first source / drain material; performing a first heating process on the substrate and the first transistor device to form a layer of a first silicide material from the first source / drain material; and providing a second transistor device on the substrate comprising a second source / drain material, wherein the first silicide material has a first silicide material absorption wavelength, the second source / drain material has a second source / drain material absorption wavelength, and the first silicide material absorption wavelength is different from the second source / drain material absorption wavelength. Based on the fact that the absorption wavelength of the first silicide material is different from the absorption wavelength of the second source / drain material, the method comprises the step of performing a selective heating process on the substrate, the first transistor device having the first silicide material and the second transistor device using a selective wavelength; wherein the selective heating process heats the second source / drain material by causing the second source / drain material to reach a first temperature based on the absorption wavelength of the second source / drain material absorbing the selective wavelength of the selective heating process, and causing the first silicide material to remain below a second temperature based on the absorption wavelength of the first silicide material absorbing the selective wavelength of the selective heating process to a minimum; and the step of heating the second source / drain material further comprises the step of irradiating the second source / drain material with the selective wavelength having a first intensity and a first peak wavelength through the selective heating process, and wherein the selective heating process uses a variable laser annealing system configured to emit the selective wavelength having the first peak wavelength and the first intensity. A method for manufacturing a semiconductor device comprising Claim 12 A method for manufacturing a semiconductor device according to claim 11, wherein the range of the selective wavelength having the first peak wavelength of the variable laser annealing system is 700 nm to 2000 nm. Claim 13 A method for manufacturing a semiconductor device according to paragraph 2, wherein the second source / drain material is silicon or silicon germanium. Claim 14 A method for manufacturing a semiconductor device according to claim 1, wherein the second temperature is 500 ℃. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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