Display device including pixel driving circuit

Abstract

A display device comprises: a substrate in which a plurality of data lines and a plurality of driving lines intersect to form a plurality of subpixel regions; a panel disposed in the light-emitting region of the subpixel; and a pixel driving circuit formed in each of the plurality of subpixel regions. The pixel driving circuit comprises: a PWM generator configured to generate a PWM signal by comparing an M-bit counter value with a data value; a multiplexer that controls the PWM generator to generate the PWM signal by comparing a reference signal that determines the distributed timing between the data value and the pixel; a level shifter configured to change the voltage level of the PWM signal to the level of the LED power supply; and a current driver that controls the current determined by the bias driving voltage to flow through or be blocked through the anode terminal.

Description

Technology Field

[0001] The present invention relates to a display device having a pixel driving circuit. More specifically, it relates to a pixel driving circuit including a PWM distribution function and a display device having the same. Background Technology

[0003] Recently, various display devices are configured to have a plurality of pixels, and each of the plurality of pixels is configured to have a pixel driving circuit. In this regard, FIG. 1 shows a pixel driving circuit related to the present invention.

[0004] Referring to FIG. 1, the pixel driving circuit (200a) may be configured to include a first transistor (TR1), a second transistor (TR2), and a first capacitor (C1). A VLED, which is a 4.5V to 6.0V power supply for driving an LED, may be applied to the first terminal of the first transistor (TR1). A first capacitor (C1) may be connected between the first terminal of the first transistor (TR1) and the input terminal of the first transistor (TR1).

[0005] A reference voltage DRV_BIAS for driving an LED can be applied to the input terminal of the first transistor (TR1). DRV_BIAS is a reference voltage set to allow a current of a specified reference current (e.g., 10uA) to flow. In this regard, DRV_BIAS does not change even if the data value changes.

[0006] The on / off duty is determined by a PWM signal determined by the logic contained within the pixel. The final PWM signal is implemented as a PWM_LS signal through a level transition device (not shown). In this regard, when the data value changes, the PWM_LS signal changes. As the number of data bits increases, the PWM time increases as shown in Fig. 7 described later.

[0007] Meanwhile, the data driving circuit can transmit 8-bit or 16-bit image data to pixels through data lines. In this regard, as the number of bits in the input image data increases, the frame frequency decreases, causing flicker.

[0008] In this regard, flicker can be improved through a PWM distribution function that drives LEDs by dividing a single frame into multiple subframes. However, there is a problem in that the size of the unit pixel circuit increases in order to implement the PWM distribution function. The increase in the area of ​​the unit pixel circuit is disadvantageous to the integration density of high-resolution displays, and the increase in current consumption is disadvantageous to portable devices. The problem to be solved

[0010] The present invention is intended to improve the flicker phenomenon that occurs as the frame frequency decreases as the number of bits of input image data increases.

[0011] The present invention is intended to improve the flicker phenomenon through a PWM distribution function that drives an LED by dividing a single frame into a plurality of subframes.

[0012] The present invention is intended to provide a pixel driving circuit including a PWM distribution function and a display device equipped with the same.

[0013] The present invention aims to solve the problem that the size of the unit pixel circuit increases in order to implement a PWM distribution function.

[0014] The present invention aims to solve the problem that an increase in the circuit area of ​​a unit pixel is disadvantageous to the integration density of high-resolution displays, and an increase in current consumption is disadvantageous to portable devices, etc. means of solving the problem

[0016] A display device having a pixel driving circuit according to the present invention comprises: a substrate in which a plurality of data lines and a plurality of driving lines intersect to form a plurality of subpixel regions; a panel disposed in a light-emitting region of the subpixel; and a pixel driving circuit formed in each of the plurality of subpixel regions. The pixel driving circuit comprises: a PWM generator configured to generate a PWM signal by comparing an M-bit counter value with a data value; a multiplexer that controls the PWM generator to generate the PWM signal by comparing a reference signal that determines dispersion timing between the data value and the pixel; a level shifter configured to change the voltage level of the PWM signal to the level of the LED power supply; and a current driver that controls the current determined by the bias driving voltage to flow through or be blocked through an anode terminal.

[0017] According to an embodiment, the PWM generator may further include: a comparator configured to compare a counter value of M bits among N bits with a data value; a first multiplexer configured to select one of a first PWM signal associated with a pulse clock and the distributed timing; a first flip-flop connected to a first output of the first multiplexer and configured to receive the output of the comparator; a second flip-flop connected to a second output of the first flip-flop and configured to receive the second output; and an OR gate configured to receive a third output of the second flip-flop, the first PWM signal, and the second output of the first flip-flop to generate a fourth output.

[0018] According to an embodiment, the pixel driving circuit may further include a second multiplexer configured to output the PWM signal by selecting one of the second output of the first flip-flop and the fourth output of the OR gate.

[0019] According to an embodiment, the pixel driving circuit may further include: a first latch configured to store the N-bit data value based on a first control signal; a second latch operably coupled to the first latch and generating a first data set of M bits to generate the PWM signal based on a second control signal; and a third latch operably coupled to the first latch and generating a second data set of (NM) bits to generate a PWM distributed signal based on the second control signal.

[0020] According to an embodiment, the multiplexer may include a switch module configured to switch the second data set bit by bit according to a bit selection signal; and a second comparator configured to compare each bit value of the second data set output by the switch module with the reference signal. The multiplexer may control a PWM selection signal generated based on the output of the second comparator to be output through the second multiplexer.

[0021] According to an embodiment, the multiplexer may further include an AND gate configured to receive a bit value associated with the pulse clock and the output of the second comparator; a third flip-flop connected to the output of the AND gate and configured to receive the output of the second comparator; and a fourth flip-flop connected to the output of the third flip-flop and configured to receive the output of the flip-flop as an input and the output as a control signal of the second multiplexer.

[0022] According to an embodiment, the input terminal of the third flip-flop is connected to the output terminal of the second comparator so that the output of the second comparator is applied to the third flip-flop, and the output value of the AND gate is applied to the clock terminal of the third flip-flop, and the input terminal of the fourth flip-flop is connected to the first output terminal of the third flip-flop so that the output of the third flip-flop can be applied to the fourth flip-flop. The second output terminal of the third flip-flop is connected to the input terminal of the AND gate, and a first PWM signal associated with the distributed timing can be applied to the clock terminal of the fourth flip-flop.

[0023] According to an embodiment, the current driver may include a first transistor arranged such that its gate and source are connected to the output and the anode terminal of the level shifter, respectively; a second transistor whose source is connected to the drain of the first transistor; and a capacitor connected between the gate and the drain of the second transistor. The bias driving voltage and the LED power supply may be applied to the gate and the drain of the second transistor, respectively. Effects of the invention

[0025] The technical effects of a display device having a pixel driving circuit according to the present invention can be summarized as follows, but are not limited thereto.

[0026] According to the present invention, the flicker phenomenon caused by the frame frequency decreasing as the number of bits of input image data increases through a PWM generator equipped with a comparator and a multiplexer structure can be improved.

[0027] According to the present invention, the flicker phenomenon can be improved through a PWM distribution function that drives an LED by dividing a single frame into a plurality of subframes through a PWM generator equipped with a comparator and a multiplexer structure.

[0028] According to the present invention, a pixel driving circuit including a PWM distribution function through a PWM generator having a comparator and a multiplexer structure, and a display device having the same can be provided.

[0029] According to the present invention, the problem of the unit pixel circuit size increasing in order to implement a PWM distribution function through a PWM generator equipped with a comparator and a multiplexer structure can be solved.

[0030] According to the present invention, through a PWM generator equipped with a comparator and a multiplexer structure, the problem that an increase in the circuit area of ​​a unit pixel is disadvantageous to the integration density of a high-resolution display and an increase in current consumption is disadvantageous to portable devices, etc. can be solved. Brief explanation of the drawing

[0032] Figure 1 shows a pixel driving circuit related to the present invention. FIG. 2 shows the configuration of a display device having a pixel driving circuit according to the present invention. FIG. 3 shows an example pixel driving circuit in relation to the present invention. FIG. 4 shows another example of a pixel driving circuit in relation to the present invention. Figure 5 shows a timing diagram of the pixel driving circuit of Figure 3. Figure 6 shows a timing diagram of the pixel driving circuit of Figure 3 for 8-bit image data. Figure 7 illustrates the process of calculating frame frequencies for 8-bit and 16-bit data. Figure 8 shows a timing diagram of the pixel driving circuit of Figure 4. Figure 9 shows a timing diagram of the pixel driving circuit of Figure 4 for 8-bit image data. FIG. 10 shows a block diagram of a pixel driving circuit according to the present disclosure. Figure 11 shows a timing diagram of the pixel driving circuit of Figure 10. FIGS. 12 and FIGS. 13 show timing diagrams of the pixel driving circuit of FIG. 10 for 8-bit image data having a value of 0 or 1. Figure 14 shows the detailed circuit of the pixel driving circuit of Figure 10. FIG. 15 shows a timing chart for implementing a PWM distribution function in a pixel according to the present disclosure. Specific details for implementing the invention

[0033] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of the present invention, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical spirit of the present invention; therefore, it should be understood that various equivalents and modifications capable of replacing them may exist at the time of filing this application.

[0034] Hereinafter, a display device having a pixel driving circuit according to the present invention will be described. In this regard, FIG. 2 shows the configuration of a display device having a pixel driving circuit according to the present invention.

[0035] Referring to FIGS. 1 and 2, a data driving circuit (120) can be operably coupled to a pixel driving circuit (200) of a panel (110) through a plurality of data lines (DL1 to DLn). The data driving circuit (120) can transmit image data to a selected pixel through the plurality of data lines (DL1 to DLn). The plurality of data lines (DL1 to DLn) can transmit 8-bit image data such as DATA[7:0].

[0036] The scan driving circuit (130) can be operably coupled to the pixel driving circuit (200) of the panel (110) through a plurality of driving lines (SL1 to SLn). The scan driving circuit (130) can select a pixel by sequentially driving the plurality of driving lines (SL1 to SLn). The plurality of driving lines (SL1 to SLn) can correspond to control signals that are turned on / off on a line-by-line basis, such as PWM_CNT[7:0], PCK, PWM_RSTB, LD, LAT, etc.

[0037] The controller (140) can be operably coupled with the data driving circuit (120) and the scan driving circuit (130). The controller (140) can control the operation timing of the data driving circuit (120) and the scan driving circuit (130). The controller (140) can control the pixel driving circuit (200) through the data driving circuit (120) and the scan driving circuit (130).

[0038] The structures of FIGS. 1 and 2 can be used in display structures such as LCD, OLED, and LED. Here, one signal or multiple signals may be used in SLx and DLx.

[0039] Meanwhile, FIG. 3 illustrates an exemplary pixel driving circuit in relation to the present invention. Referring to FIG. 3, the pixel driving circuit (200b) may be configured to include a PWM generator (210), a level shifter (240), a current driver (250), a first latch (261), and a second latch (262).

[0040] FIG. 4 illustrates a pixel driving circuit of another example in relation to the present invention. Referring to FIG. 4, the pixel driving circuit (200c) may be configured to include a PWM generator (210), PWM distributed logic (220b), a level shifter (240), a current driver (250), a first latch (261), and a second latch (262).

[0041] Referring to FIGS. 3 and 4, DATA[7:0] is an input signal for pixel image data, and the data can be temporarily stored in the first latch (261) by the LAT signal. The LAT signal is a control signal for storing DATA[7:0] in the first latch (261). LD is a control signal used to move the output DI[7:0] of the first latch (261) to the second latch (262). The output D[7:0] of the second latch (262) is used to generate a PWM signal.

[0042] Referring to FIGS. 2 to 4, PWM_RSTB is a signal driven by the scan driving circuit (130) and periodically resets the PWM generator (210) equipped with a comparator and the signal of PWM_CNT[7:0]. The pulse clock (PCK) is the clock signal of the PWM generator (210) equipped with a comparator. Here, VDD is a low voltage power supply for operating the logic circuit, and GND corresponds to ground. VLED is a 4.5V to 6.0V power supply for driving the LED, and DRV_BIAS is a reference voltage for driving the LED.

[0043] Meanwhile, PWM is a signal generated and output by a PWM generator (210) equipped with a comparator. The PWM signal is a low voltage signal generated by the VDD power supply, and PWM_LS is a signal that has transitioned to a medium voltage level generated by the VLED power supply.

[0044] When the current is determined by the bias driving voltage (DRV_BIAS), the current driver (250) can turn the current on or off by the PWM_LS signal to the anode terminal. An LED is connected to the anode terminal (Anode) to GND.

[0045] The pixel driving circuit (200c) of FIG. 4 differs from the pixel driving circuit (200b) of FIG. 3 in that a PWM distribution logic (220b) is added. When the input signal of PWM_CNT[4:0] is applied, the PWM distribution logic (220b) performs a PWM distribution function. The PWM distribution logic (220b) performs a function of distributing the PWM signal. The PWM distribution logic (220b) may be equipped with circuits such as a subframe counter block and a distribution sequence counter.

[0046] FIG. 5 shows a timing diagram of the pixel driving circuit of FIG. 3. Referring to FIG. 3 and FIG. 5, the signal of DATA[7:0] is stored as DI[7:0] in the first latch (261) by the LAT signal. The signal of DI[7:0] is stored as D[7:0] in the second latch (262) by the LD signal. The value of D[7:0] stored in the second latch (262) is used as a signal to generate a PWM signal.

[0047] The 8-bit value of D[7:0] stored in the second latch (262) is transmitted to the PWM generator (210). The PWM generator (210) compares the value of D[7:0] with an 8-bit counter value called PWM_CNT[7:0]. Referring to FIGS. 2, 3 and 5, PWM_CNT[7:0] input to the scan driving circuit (130) is used as a reference signal to determine the temporal width of the PWM signal.

[0048] Meanwhile, when PWM_RSTB=high, PWM_CNT[7:0] starts an up count, and accordingly, a PWM signal with a width proportional to the DATA[7:0] value is output. The PWM output signal is enabled while the data value is greater than or equal to the counter value.

[0049] In relation to LED driving, the voltage level of the PWM signal can be adjusted through a level shifter (240). A current driver (250) can control the brightness of the LED by flowing current to the anode terminal according to the on / off duty of the PWM signal. The PWM_RSTB signal serves to periodically reset the PWM_CNT[7:0] counter.

[0050] Meanwhile, FIG. 6 shows a timing diagram of the pixel driving circuit of FIG. 3 for 8-bit image data. Referring to FIG. 3, FIG. 5 and FIG. 6, the PWM output signal is formed differently depending on the value of DATA[7:0], which is 8-bit data stored in the pixel.

[0051] In this regard, it represents a PWM operation mode in which the time (pulse width) during which the PWM output signal remains HIGH increases linearly as the value of DATA[7:0] increases. All PWM signals are defined as the time from the falling edge of PCK to the falling edge of PCK at which the value of PWM_CNT[7:0] matches the value of DATA[7:0].

[0052] The PWM output is kept in a HIGH / ON state by the PWM generator (210) while the PWM_CNT[7:0] value is smaller than the DATA[7:0] value. When the PWM_CNT[7:0] value becomes equal to or larger than the DATA[7:0] value, the PWM output is changed to a LOW / OFF state.

[0053] PWM_CNT[7:0] is a decimal value of an 8-bit PWM counter, and it can repeat increasing from 0 to 1, 2, 3, … up to 255 in sequence according to the pulse clock (PCK) and returning to 0. It starts simultaneously when PWM_CNT becomes 0 due to the PWM_RSTB signal.

[0054] Meanwhile, FIG. 7 illustrates the process of calculating the frame frequency for 8-bit and 16-bit data. FIG. 7(a) illustrates the process of calculating the frame frequency for 8-bit data. Referring to FIG. 7(a), when the PCK uses a 1 MHz clock, it has a frame frequency of approximately 3.861 kHz.

[0055] Figure 7(b) illustrates the process of calculating the frame frequency for 16-bit data. Referring to Figure 7(b), the PCK uses a 10 MHz clock but has a frame frequency of approximately 152 Hz.

[0056] Referring to Fig. 7, as the number of bits in the input data increases, the frame frequency decreases, causing a flicker phenomenon. It can be observed that the frame frequency decreases significantly when using 16-bit data compared to when using 8-bit data. Due to this low frame frequency, a flicker phenomenon occurs on the display.

[0057] Although 8-bit data can be used, 16-bit data can actually be used to implement the Gamma Curve. As the frame frequency decreases due to the higher bit data, a higher pulse clock frequency is required to increase the frame frequency. This higher pulse clock frequency causes an increase in current consumption.

[0058] Meanwhile, FIG. 8 shows a timing diagram of the pixel driving circuit of FIG. 4. FIG. 9 shows a timing diagram of the pixel driving circuit of FIG. 4 for 8-bit image data.

[0059] Referring to FIGS. 4 and FIGS. 8, when the PWM data is 8 bits, the entire PWM range is High for 256 PCK. However, the upper 5 bits of data can be used to determine the PWM width of the subframe, and the lower 3 bits of data can be used for PWM dispersion. That is, the number of subframes is determined by the lower 3 bits of data.

[0060] Since the LED is driven by dividing one frame into 8 subframes, it has the advantage of shortening the OFF period, which can improve the flicker phenomenon. Since it has a 5-bit PWM period per subframe, it can perform PWM functions by receiving the input signal of PWM_CNT[4:0].

[0061] Referring to FIGS. 4 and 9, in a circuit with a built-in PWM distributed logic (220b), the PWM output signal can be formed differently depending on the value of DATA[7:0], which is 8-bit data stored in a pixel. As the value of DATA[7:0] increases, the time (pulse width) during which the PWM output signal is maintained at HIGH in the 8 divided subframes starts distributed into 8 parts and then linearly lengthens, indicating a PWM operation method.

[0062] In this regard, there is a problem that the size of the unit pixel circuit increases in order to implement the PWM distribution function. The PWM distribution logic (220b) includes a subframe logic counter and a distribution sequence counter, and since a flip-flop counter is used, there is a problem that the area increases and the current consumption increases. The increase in area is disadvantageous to the integration density of high-resolution displays, and the increase in current consumption is disadvantageous to portable devices, etc.

[0063] A display device having a pixel driving circuit according to the present disclosure for overcoming the aforementioned problems is described. In this regard, FIG. 10 shows a block diagram of a pixel driving circuit according to the present disclosure. FIG. 11 shows a timing diagram of the pixel driving circuit of FIG. 10.

[0064] Compared to the pixel driving circuit (200c) of FIG. 4, the pixel driving circuit (200) of FIG. 10 differs in that a multiplexer (220) is added. To implement the same function as PWM distribution, the multiplexer (220) for comparing DATA[(N-1):0] and S_ID can be implemented as a 1-bit MUX Comparator & 2-bit F / F. To implement the comparison simply with a small circuit size, a signal called SEL_BIT[(NM-1):0] is received by the scan driving circuit (130).

[0065] The reference signal (S_ID) is a serial identifier (ID) of (NM) bits for comparison with DATA[(NM-1):0] to operate the distribution function. The S_ID is provided by an external scan driving circuit (130) and provides a reference signal for determining the distribution timing between pixels.

[0066] Meanwhile, SEL_BIT[(NM-1):0] is a signal to select a MUX to compare DATA[(N-1):0] with S_ID. To reduce the circuit size of the pixel, the comparison signal is also received by the scan driving circuit (130).

[0067] ID_RSTB serves to initialize the signal determining the on / off status of the distribution function in the previous subframe. PWM_PS is used to load the on / off result of the PWM signal distribution in the next subframe. In this regard, the distribution result of the (n-1)th subframe can be applied to the nth subframe.

[0068] Compared to the distribution function of Fig. 4, which is entirely inside the pixel, Fig. 10 has the advantage of enabling a high-resolution display without significantly increasing the pixel size, as only the minimum circuitry of the comparator, MUX, and 2-bit flip-flop is inside the pixel.

[0069] Referring to Figures 10 and 11 in comparison with Figures 4 and 8, there are differences in the ID_RSTB, SEL_BIT[(NM-1):0], and SI_D signals. In this regard, the ID_RSTB, SEL_BIT[(NM-1):0], and SI_D signals are signals used in the 1-bit MUX Comparator and 2-bit F / F. Through these signals, it is determined whether to add a distributed PWM 1-bit in the next subframe or not. In this regard, if it is determined to add a distributed PWM 1-bit in the previous subframe, it is formed as a PWM signal in the additional time interval (TDa).

[0070] Meanwhile, FIGS. 12 and 13 show a timing diagram of the pixel driving circuit of FIG. 10 for 8-bit image data having a value of 0 or 1. Referring to FIGS. 10 to 12, a timing diagram for 8 subframes of a pixel circuit including a PWM distribution function is shown. The DATA input is 8-bit, the upper 5 bits are PWM data, and DATA[7:3]=0. When DATA[7:3]=0, the PWM distribution waveform is shown for 8 cases where DATA[2:0] is 0 to 7. Since one frame is divided into 8 subframes to drive the LED, there is an advantage of being able to shorten the OFF period, which can improve the flicker phenomenon.

[0071] Referring to FIGS. 10, 11, and 13, a timing diagram for an 8-subframe of a pixel circuit including a PWM distribution function is shown. The DATA input is 8-bit, the upper 5-bits are PWM data, and DATA[7:3]=1. When DATA[7:3]=1, DATA[2:0] represents a PWM distribution waveform for 8 cases ranging from 0 to 7.

[0072] Meanwhile, FIG. 14 shows the detailed circuit of the pixel driving circuit of FIG. 10. Referring to FIG. 10 and FIG. 14, the PWM generator (210) can be implemented as a Comparator & PWM Generator. The Comparator of the PWM generator (210) compares PWM_CNT[(M-1):0] and M-bit DATA[(N-1):(NM)] and generates a PWM signal from the PWM Generator. The multiplexer (220) can be implemented as a 1-bit MUX Comparator & 2-bit F / F.

[0073] The S_ID signal input in series with the signal of DATA[(NM-1):0] is compared from MSB to LSB through the first multiplexer (212) of the PWM generator (210) by SEL_BIT[(NM-1):0]. The comparator (211) can be composed of simple logic such as A AND ~B. For example, assuming M=8 and M=5, the DATA inputs become D2, D1, and D0, and the S_ID inputs become S2, S1, and S0.

[0074] In this regard, comparisons can be performed sequentially in the order of D2 : S2, D1 : S1, and D0 : S0. Among the sequences 1, 2, and 3, if the corresponding bit (Dx) of the data is greater than the corresponding bit (Sx) of S_ID first (Dx=1, Sx=0), the comparison is stopped. In this regard, the output of the third flip-flop (224) is determined to be in a low state, and the input pulse clock (PCK) of the third flip-flop (224) is stopped by the AND gate (223), thereby stopping the comparison function. Thus, unnecessary comparison operations can be prevented, thereby reducing power consumption. Accordingly, distributed on / off is determined during the next 1-subframe. In this regard, the signal determined in the (n-1)th subframe is stored as the output value (Q) of the third flip-flop (224), and in the nth subframe, it is loaded by PWM_PS and used as the PWM_SEL signal.

[0075] In this regard, a PWM generator (210) implemented with a 1-bit MUX Comparator and a 2-bit F / F is a minimal circuit that replaces the PWM distributed logic (220b) of FIG. 4, and most of the functions of the PWM distributed logic (220b) can be separated into a scan driving circuit (130).

[0076] Meanwhile, FIG. 15 shows a timing chart for implementing a PWM distribution function in a pixel according to the present disclosure. Referring to FIGS. 10 through 15, in order to minimize the circuit size when implementing a PWM distribution function in a pixel, an S_ID must be input externally.

[0077] In the case of 8-bit input data, 8 subframes can be formed using 3 bits of PWM[2:0]. In this regard, 8 levels from 7, 6, 5 to 0 can be represented in binary. Additionally, MSN / LSB can be flipped, and sPWM_ID can be represented again in decimal / hexadecimal. When the upper 5 bits of the data in PWM[7:0] are used as pulses for the sub-PWM and the lower 3 bits are used as subframes for distribution, it can be confirmed that PWM[7:0] = values ​​from 0 to 255.

[0078] Hereinafter, a display device having a pixel driving circuit according to the present disclosure will be described with reference to FIG. 2 and FIG. 10 to FIG. 15.

[0079] The display device (100) may be configured to include a panel (110), a pixel driving circuit (200), and a substrate (300).

[0080] A substrate (300) may be divided into multiple subpixel regions by intersecting multiple data lines (DL1 to DLn) and multiple driving lines (SL1 to SLn). Additionally, a panel (110) may be disposed in the light-emitting regions of the multiple subpixels. A pixel driving circuit (200) may be formed in each of the multiple subpixel regions. In this regard, the pixel driving circuit (200) may correspond to the pixel driving circuit (200a) of FIG. 1.

[0081] The pixel driving circuit (200) may be configured to include a PWM generator (210), a multiplexer (220), a level shifter (240), and a current driver (250).

[0082] The PWM generator (210) can be configured to generate a PWM signal by comparing the counter value of M bits out of N bits with the data value.

[0083] The multiplexer (220) can control the PWM generator (210) to generate a PWM signal by comparing a reference signal that determines the dispersion timing between the data value and the pixel.

[0084] The level shifter (230) can be configured to change the voltage level of the PWM signal to the level of the LED power supply. The current driver (240) can control the current determined by the bias driving voltage to flow through or be blocked through the anode terminal.

[0085] The PWM generator (210) may be configured to further include a comparator (211), a first multiplexer (212), a first flip-flop (213), a second flip-flop (214), and an OR gate (215).

[0086] The comparator (211) may be configured to compare an M-bit counter value and a data value. In this regard, the comparator (211) may compare PWM_CNT[(M-1):0] corresponding to an M-bit counter value and DATA[(N-1):(NM)] corresponding to an M-bit data value.

[0087] The first multiplexer (212) may be configured to select one of the pulse clock (PCK) and the first PWM signal (PWM_PS) associated with the dispersion timing. The first PWM signal (PWM_PS) may be used to load the on / off result of the dispersion of the PWM signal in the next subframe. In this regard, the dispersion result of the (n-1)th subframe may be applied to the nth subframe.

[0088] The first flip-flop (213) can be connected to the first output of the first multiplexer (212). The first flip-flop (213) can be configured to receive the output of the comparator (211). The first output of the first multiplexer (212) can be received at the clock terminal of the first flip-flop (213).

[0089] The second flip-flop (214) can be connected to the second output of the first flip-flop (213). The second flip-flop (214) can be configured to receive the second output of the first flip-flop (213). A pulse clock (PCK) can be received at the clock terminal of the second flip-flop (214).

[0090] The OR gate (215) can be connected to the third output of the second flip-flop (214). The OR gate (215) can be configured to generate a fourth output by applying the third output of the second flip-flop (214), the first PWM signal (PWM_PS), and the second output of the first flip-flop (213).

[0091] The pixel driving circuit (200) may be configured to further include a second multiplexer (230). The second multiplexer (230) may be configured to output a PWM signal by selecting one of the second output of the first flip-flop (213) and the fourth output of the OR gate (215).

[0092] The pixel driving circuit (200) may be configured to further include a plurality of latch circuits. The pixel driving circuit (200) may be configured to further include a first latch (261), a second latch (262), and a third latch (263).

[0093] The first latch (261) may be configured to store an N-bit data value based on a first control signal (LAT). The second latch (262) may be operablely coupled with the first latch (261). The second latch (262) may generate a first data set of M bits to generate a PWM signal based on a second control signal (LD). The third latch (263) may be operablely coupled with the first latch (261). The third latch (263) may generate a second data set of (NM) bits to generate a PWM distributed signal based on the second control signal.

[0094] The multiplexer (220) may be configured to include a switch module (221) and a second comparator (222). The switch module (221) may be configured to switch the second data set bit by bit according to a bit selection signal (SEL_BIT). The second comparator (222) may be configured to compare each bit value of the second data set output by the switch module (221) with a reference signal (S_ID). The multiplexer (220) may control the output of a PWM selection signal generated based on the output of the second comparator (222) to be output through the second multiplexer (230).

[0095] The multiplexer (220) may be configured to further include an AND gate (223), a third flip-flop (224), and a fourth flip-flop (225).

[0096] The AND gate (223) can be configured to receive a bit value associated with the pulse clock (PCK) and the output of the second comparator (222). The AND gate (223) can be configured to receive the pulse clock (PCK) and the inverted value (QB) of the output of the third flip-flop (224).

[0097] The third flip-flop (224) can be connected to the output of the AND gate (223). The output of the AND gate (223) can be applied to the clock terminal of the third flip-flop (224). The third flip-flop (224) can be configured to have the output of the second comparator (222) applied to it.

[0098] The fourth flip-flop (225) can be connected to the output of the third flip-flop (224). The output of the third flip-flop (224) can be applied as the input of the fourth flip-flop (225). The fourth flip-flop (225) can be configured so that its output is applied as a control signal to the second multiplexer (230).

[0099] The input terminal of the third flip-flop (224) is connected to the output terminal of the second comparator (222), so that the output of the second comparator (222) can be applied to the third flip-flop (224). The output value of the AND gate (223) can be applied to the clock terminal of the third flip-flop (224).

[0100] The input terminal of the fourth flip-flop (225) is connected to the first output terminal of the third flip-flop (224), so that the output of the third flip-flop (224) can be applied to the fourth flip-flop (225). The second output terminal of the third flip-flop (224) can be connected to the input terminal of the AND gate (223). A first PWM signal (PWM_PS) associated with distributed timing can be applied to the clock terminal of the fourth flip-flop (225).

[0101] The current driver (250) may be configured to include a plurality of transistors and capacitors. The current driver (250) may be configured to include a first transistor (TR1), a second transistor (TR2), and a capacitor (C).

[0102] The first transistor (TR1) may be positioned so that its gate and source are connected to the output and anode terminal (Anode) of the level shifter (240), respectively. The second transistor (TR2) may be positioned so that its source is connected to the drain of the first transistor (TR1). A capacitor (C) may be connected between the gate and drain of the second transistor (TR2). A bias driving voltage (DRV_BIAS) and an LED power supply (VLED) may be applied to the gate and drain of the second transistor (TR2), respectively.

[0103] The above describes a display device having a pixel driving circuit according to the present invention. The technical effects of the display device having a pixel driving circuit according to the present invention can be summarized as follows, but are not limited thereto.

[0104] The technical effects of a display device having a pixel driving circuit according to the present invention can be summarized as follows, but are not limited thereto.

[0105] According to the present invention, the flicker phenomenon caused by the frame frequency decreasing as the number of bits of input image data increases through a PWM generator equipped with a comparator and a multiplexer structure can be improved.

[0106] According to the present invention, the flicker phenomenon can be improved through a PWM distribution function that drives an LED by dividing a single frame into a plurality of subframes through a PWM generator equipped with a comparator and a multiplexer structure.

[0107] According to the present invention, a pixel driving circuit including a PWM distribution function through a PWM generator having a comparator and a multiplexer structure, and a display device having the same can be provided.

[0108] According to the present invention, the problem of the unit pixel circuit size increasing in order to implement a PWM distribution function through a PWM generator equipped with a comparator and a multiplexer structure can be solved.

[0109] According to the present invention, through a PWM generator equipped with a comparator and a multiplexer structure, the problem that an increase in the circuit area of ​​a unit pixel is disadvantageous to the integration density of a high-resolution display and an increase in current consumption is disadvantageous to portable devices, etc. can be solved.

[0110] Although the present invention has been described above in relation to specific embodiments, this is merely illustrative and the present invention is not limited thereto. A person skilled in the art to which the present invention pertains may change or modify the described embodiments without departing from the scope of the present invention, and various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims set forth below. Explanation of the symbols

[0112] 100: Display device 110: Panel 120: Data driving circuit 130: Scan driving circuit 140: Controller 200: Pixel driving circuit 210: PWM Generator 220: Multiplexer 230: Second multiplexer 240: Level 100 250: Current driver 261, 262, 263: 1st latch, 2nd latch, 3rd latch 300: Substrate

Claims

Claim 1 A display device having a pixel driving circuit comprises: a substrate in which a plurality of data lines and a plurality of driving lines intersect to form a plurality of subpixel regions; a panel disposed in a light-emitting region of the subpixel; and a pixel driving circuit formed in each of the plurality of subpixel regions; wherein the pixel driving circuit comprises: a PWM generator configured to generate a PWM signal by comparing an M-bit counter value and a data value; a multiplexer that controls the PWM generator to generate the PWM signal by comparing a reference signal that determines a dispersion timing between the data value and the pixel; a level shifter configured to change the voltage level of the PWM signal to the level of the LED power supply; and a current driver that controls the current determined by the bias driving voltage to flow through or be blocked through an anode terminal; wherein the PWM generator comprises: a comparator configured to compare the M-bit counter value and the data value among N bits; and a first multiplexer configured to select one of a pulse clock and a first PWM signal associated with the dispersion timing. A first flip-flop connected to the first output of the first multiplexer and configured to receive the output of the comparator; a second flip-flop connected to the second output of the first flip-flop and configured to receive the second output; and an OR gate configured to receive the third output of the second flip-flop, the first PWM signal, and the second output of the first flip-flop to generate a fourth output; the pixel driving circuit further includes a second multiplexer configured to select one of the second output of the first flip-flop and the fourth output of the OR gate to output the PWM signal; and the pixel driving circuit further includes a first latch configured to store the N-bit data value based on a first control signal;A display device further comprising: a second latch operably coupled to the first latch and generating a first data set of M bits to generate the PWM signal based on a second control signal; and a third latch operably coupled to the first latch and generating a second data set of (NM) bits to generate a PWM distributed signal based on the second control signal; wherein the multiplexer comprises: a switch module configured to switch the second data set bit by bit according to a bit selection signal; and a second comparator configured to compare each bit value of the second data set output by the switch module with the reference signal; and wherein the multiplexer controls the output of the second comparator to output a PWM selection signal generated based on the output of the second comparator through the second multiplexer. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 A display device according to claim 1, wherein the multiplexer further comprises: an AND gate configured to receive a bit value associated with the pulse clock and the output of the second comparator; a third flip-flop connected to the output of the AND gate and configured to receive the output of the second comparator; and a fourth flip-flop connected to the output of the third flip-flop and configured to receive the output of the flip-flop as an input and the output as a control signal of the second multiplexer. Claim 7 A display device according to claim 6, wherein the input terminal of the third flip-flop is connected to the output terminal of the second comparator so that the output of the second comparator is applied to the third flip-flop and the output value of the AND gate is applied to the clock terminal of the third flip-flop, the input terminal of the fourth flip-flop is connected to the first output terminal of the third flip-flop so that the output of the third flip-flop is applied to the fourth flip-flop, the second output terminal of the third flip-flop is connected to the input terminal of the AND gate, and a first PWM signal associated with the distributed timing is applied to the clock terminal of the fourth flip-flop. Claim 8 A display device according to claim 1, wherein the current driver comprises: a first transistor arranged such that its gate and source are respectively connected to the output of the level shifter and the anode terminal; a second transistor whose source is connected to the drain of the first transistor; and a capacitor connected between the gate and drain of the second transistor, wherein the bias driving voltage and the LED power supply are respectively applied to the gate and drain of the second transistor.

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