Display panel and electronic device including the same

Abstract

The display panel of the present invention comprises a base layer including a component region, a circuit layer disposed on the base layer, and a light-emitting element layer including a first light-emitting element disposed on the component region. The circuit layer comprises a plurality of first conductive patterns, each extending in a first direction; at least one first intermediate insulating layer disposed on the plurality of first conductive patterns; and a plurality of second conductive patterns disposed on the at least one first intermediate insulating layer, each extending in a second direction intersecting the first direction. In a planar plane, each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps with the first light-emitting element. Accordingly, the reliability of the display panel of the present invention can be improved.

Description

Technology Field

[0001] The present invention relates to a display panel comprising a display area through which an optical signal is transmitted, and an electronic device comprising the same. Background Technology

[0002] The electronic device may include various electronic components, such as a display panel and an electronic module. The electronic module may include a camera, an infrared detection sensor, or a proximity sensor. The electronic module may be placed beneath the display panel. The transmittance of some areas of the display panel may be higher than the transmittance of other areas of the display panel. The electronic module may receive or transmit optical signals through the area with high transmittance.

[0003] For example, electronic modules may include camera modules, sensors that measure the distance between an object and a mobile phone (such as proximity sensors), and sensors that recognize parts of the user's body (e.g., fingerprints, irises, or faces). The operation of electronic modules can be affected by structures within the display panel. Research on the internal structures of display panels is ongoing to improve the reliability of electronic modules. The problem to be solved

[0004] The present invention aims to provide a display panel with reduced distortion of optical signals.

[0005] The present invention aims to provide an electronic device including the above-mentioned display panel. means of solving the problem

[0006] The display panel of the present invention comprises: a base layer including a component area; a circuit layer disposed on the base layer; and a light-emitting element layer including a first light-emitting element disposed on the component area; wherein the circuit layer comprises a plurality of first conductive patterns, each extending in a first direction; at least one first intermediate insulating layer disposed on the plurality of first conductive patterns; and a plurality of second conductive patterns disposed on the at least one first intermediate insulating layer, each extending in a second direction intersecting the first direction; and wherein, on a plane, each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps the first light-emitting element.

[0007] In one embodiment, the circuit layer further comprises at least one second intermediate insulating layer disposed on the plurality of second conductive patterns and a third conductive pattern disposed on the at least one second intermediate insulating layer, and each of the plurality of first conductive patterns and the plurality of second conductive patterns can be superimposed on the third conductive pattern in a planar manner.

[0008] In one embodiment, the first light-emitting element includes a first pixel electrode disposed in the component region, the component region includes a device region that overlaps the first pixel electrode and a transmission region that does not overlap the first pixel electrode, and the plurality of first conductive patterns, the plurality of second conductive patterns, and the third conductive pattern may overlap the first pixel electrode and not overlap the transmission region.

[0009] In one embodiment, the circuit layer further comprises a barrier layer including an inorganic material disposed on the base layer, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed on the second insulating layer, wherein the at least one first intermediate insulating layer is the buffer layer and the first insulating layer, the at least one second intermediate insulating layer is the second insulating layer, the plurality of first conductive patterns are disposed between the barrier layer and the buffer layer, the plurality of second conductive patterns are disposed between the first insulating layer and the second insulating layer, and the third conductive pattern may be disposed between the second insulating layer and the third insulating layer.

[0010] In one embodiment, the barrier layer may include at least one of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and an amorphous silicon layer.

[0011] In one embodiment, the circuit layer further comprises a barrier layer including an inorganic material disposed on the base layer, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer, wherein the at least one first intermediate insulating layer is the second insulating layer, the plurality of first conductive patterns are disposed between the first insulating layer and the second insulating layer, and the plurality of second conductive patterns may be disposed between the second insulating layer and the third insulating layer.

[0012] In one embodiment, the plurality of first conductive patterns are spaced apart from each other by a first interval along the second direction, and the first interval may be from several micrometers to several tens of micrometers.

[0013] In one embodiment, the plurality of second conductive patterns are spaced apart from each other by a second interval along the first direction, and the second interval may be from several micrometers to several tens of micrometers.

[0014] In one embodiment, the base layer further includes an intermediate region adjacent to the component region, the light-emitting element layer further includes a second light-emitting element including a second pixel electrode disposed in the intermediate region, and the circuit layer further includes a first pixel circuit and a second pixel circuit, each disposed in the intermediate region, and the first pixel circuit may be electrically connected to the first pixel electrode and the second pixel circuit may be electrically connected to the second pixel electrode.

[0015] In one embodiment, the base layer further includes a main display area adjacent to the intermediate area, the light-emitting element layer further includes a third light-emitting element including a third pixel electrode disposed in the main display area, and the circuit layer further includes a third pixel circuit each disposed in the main display area, and the third pixel circuit may be electrically connected to the third pixel electrode.

[0016] In one embodiment, the first direction on a plane may be perpendicular to the second direction.

[0017] The display panel of the present invention comprises a base layer, a circuit layer disposed on the base layer, and a light-emitting element layer disposed on the circuit layer, wherein the circuit layer comprises: a plurality of first conductive patterns, each extending in a first direction on the base layer; at least one first intermediate insulating layer covering the plurality of first conductive patterns; a plurality of second conductive patterns disposed on the at least one first intermediate insulating layer, each extending in a second direction intersecting the first direction; at least one second intermediate insulating layer covering the plurality of second conductive patterns; and a third conductive pattern disposed on the at least one second intermediate insulating layer; wherein, in a planar plane, each of the plurality of second conductive patterns intersects the plurality of first conductive patterns, and in a planar plane, each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps the third conductive pattern.

[0018] In one embodiment, the base layer includes a component region comprising a device region and a light-transmitting region, and the light-emitting device layer includes a first light-emitting device superimposed on the device region, and the plurality of first conductive patterns, the plurality of first conductive patterns, and a third conductive pattern may be disposed in the device region.

[0019] In one embodiment, the first light-emitting element comprises a first pixel electrode, a pixel defining pattern exposing at least a portion of the first pixel electrode, a light-emitting layer disposed on the first pixel electrode, and a second pixel electrode disposed on the light-emitting layer, wherein each of the first pixel electrode, the pixel defining pattern, and the light-emitting layer may overlap the element region and not overlap the transmission region.

[0020] In one embodiment, the base layer further includes an intermediate region surrounding at least a portion of the component region, the light-emitting element layer further includes a second light-emitting element disposed in the intermediate region, and the circuit layer may further include a first pixel circuit disposed in the intermediate region and electrically connected to the first light-emitting element, and a second pixel circuit disposed in the intermediate region and electrically connected to the second light-emitting element.

[0021] In one embodiment, the base layer further includes a main display area surrounding at least a portion of the intermediate area, the light-emitting element layer further includes a third light-emitting element disposed in the main display area, and the circuit layer may further include a third pixel circuit disposed in the main display area and electrically connected to the third light-emitting element.

[0022] In one embodiment, the plurality of first conductive patterns are spaced apart from each other by a first interval in the second direction, and the plurality of second conductive patterns are spaced apart from each other by a second interval in the first direction, and the first interval and the second interval may each be independently greater than several micrometers and less than or equal to several tens of micrometers.

[0023] The electronic device of the present invention comprises: a base layer including a component region including a device region and a transmission region; a light-emitting element layer including a first light-emitting element superimposed on the device region in a planar plane; and a circuit layer disposed between the base layer and the light-emitting element layer, comprising a first conductive pattern, a second conductive pattern, and a third conductive pattern that are insulated from each other; wherein, in a planar plane, the second conductive pattern intersects the first conductive pattern, and in a planar plane, the third conductive pattern covers the first conductive pattern and the second conductive pattern, and in a planar plane, the first conductive pattern, the second conductive pattern, and the third conductive pattern superimpose on the device region.

[0024] In one embodiment, an electronic module may be further included that overlaps the component area on a plane.

[0025] In one embodiment, the base layer further includes an intermediate region adjacent to the component region and not overlapping with the electronic module, the light-emitting element layer further includes a second light-emitting element disposed in the intermediate region, and the circuit layer may further include a first pixel circuit disposed in the intermediate region and electrically connected to the first light-emitting element, and a second pixel circuit disposed in the intermediate region and connected to the second light-emitting element. Effects of the invention

[0026] The reliability of the display panel of the present invention can be improved.

[0027] The electronic device of the present invention can improve the reliability of the electronic module. Brief explanation of the drawing

[0028] FIG. 1 is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 2 is an exploded perspective view illustrating some components of an electronic device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 5 is a plan view of a display panel according to one embodiment of the present invention. Figure 6 is a plan view showing an enlarged view of the AA area of ​​Figure 5. FIG. 7 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 8 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 9 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 10 is a plan view of a device region according to one embodiment of the present invention. FIG. 11a is a cross-sectional view along the cutting line B-B' of FIG. 10. FIG. 11b is a cross-sectional view along the cutting line C-C' of FIG. 10. FIG. 12 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 13 is a graph showing the reflectance according to the angle of incidence of the electronic devices of Example 1 and Example 2. Specific details for implementing the invention

[0029] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0030] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0031] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0032] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0033] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0035] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0036] FIG. 1 is a perspective view of an electronic device (1000) according to one embodiment of the present invention.

[0037] Referring to FIG. 1, the electronic device (1000) may include a display device, and in this embodiment, a mobile phone is illustrated as an example. However, it is not limited thereto, and the electronic device (1000) may be a tablet, monitor, television, car navigation system, game console, or wearable device.

[0038] The electronic device (1000) can display an image through a display area (1000A). The display area (1000A) may include a plane defined by a first direction (DR1) and a second direction (DR2). The display area (1000A) may further include curved surfaces bent from at least two sides of the plane. However, the shape of the display area (1000A) is not limited thereto. For example, the display area (1000A) may include only the plane, or the display area (1000A) may further include four curved surfaces bent from at least two, for example, four sides of the plane.

[0039] A portion of the display area (1000A) may be defined as a sensing area (1000SA). In FIG. 1, one sensing area (1000SA) is illustrated as an example, but the number of sensing areas (1000SA) is not limited thereto. The sensing area (1000SA) may be a part of the display area (1000A), but may have a higher light signal transmittance compared to other areas of the display area (1000A). Therefore, an image can be displayed through the sensing area (1000SA), and a light signal can be provided through the sensing area (1000SA).

[0040] The electronic device (1000) may include an electronic module placed in an area overlapping with the sensing area (1000SA). The electronic module may receive a light signal provided from the outside through the sensing area (1000SA) or output a light signal through the sensing area (1000SA). For example, the electronic module may be a camera module, a sensor that measures the distance between an object and a mobile phone such as a proximity sensor, a sensor that recognizes a part of the user's body (e.g., fingerprint, iris, or face), or a small lamp that outputs light, but is not particularly limited thereto.

[0041] The thickness direction of the electronic device (1000) may be a third direction (DR3) which is the normal direction of the display area (1000A). The front (or top) and back (or bottom) surfaces of the components constituting the electronic device (1000) may be defined based on the third direction (DR3).

[0042] FIG. 2 is an exploded perspective view illustrating some components of an electronic device (1000) according to one embodiment of the present invention.

[0043] Referring to FIG. 2, the electronic device (1000) may include a display device (DD) and an electronic module (CM). The display device (DD) can generate an image and detect an external input. The electronic module (CM) is positioned below the display device (DD). When the display device (DD) is defined as a first electronic module constituting the electronic device (1000), the electronic module (CM) may be defined as a second electronic module. In one embodiment, the electronic module (CM) may be a camera module.

[0044] The display device (DD) may include a display area (100A) and a peripheral area (100N). The display area (100A) may correspond to the display area (1000A) shown in FIG. 1. A portion of the display device (DD) may be defined as a sensing area (100SA), and the sensing area (100SA) may have a higher transmittance than another portion of the display area (100A) (hereinafter referred to as the main display area). Thus, the sensing area (100SA) can provide external natural light to the electronic module (CM). Since the sensing area (100SA) is a part of the display area (100A), it can display an image.

[0045] Pixels (PX, see FIG. 5) are placed in the display area (100A). Pixels (PX) are placed in the sensing area (100SA) and the main display area, respectively. However, the configuration of the pixels (PX) placed in the sensing area (100SA) and the main display area may differ. A detailed explanation of this will be provided later.

[0046] FIG. 3 is a cross-sectional view of a display device (DD) according to one embodiment of the present invention.

[0047] Referring to FIG. 3, the display device (DD) may include a display panel (100), a sensor layer (200), and an anti-reflection layer (300).

[0048] The display panel (100) may be a configuration that substantially generates an image. The display panel (100) may be a light-emitting display panel, for example, the display panel (100) may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel. The display panel (100) may also be referred to as a display layer.

[0049] The display panel (100) may include a base layer (110), a circuit layer (120), a light-emitting element layer (130), and an encapsulation layer (140).

[0050] The base layer (110) may be a member that provides a base surface on which the circuit layer (120) is placed. The base layer (110) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. The base layer (110) may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer (110) may be an inorganic layer, an organic layer, or a composite material layer.

[0051] The base layer (110) may have a multilayer structure. For example, the base layer (110) may include a first synthetic resin layer, a multilayer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multilayer or single-layer inorganic layer. Each of the first and second synthetic resin layers may include a polyimide-based resin, and is not particularly limited.

[0052] A circuit layer (120) may be placed on a base layer (110). The circuit layer (120) may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line, etc. An insulating layer, a semiconductor layer, and a conductive layer are formed on the base layer (110) by means of coating, deposition, etc., and subsequently, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through multiple photolithography and etching processes.

[0053] The light-emitting element layer (130) may be disposed on the circuit layer (120). The light-emitting element layer (130) may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0054] The encapsulation layer (140) may be placed on the light-emitting element layer (130). The encapsulation layer (140) may protect the light-emitting element layer (130) from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer (140) may include at least one inorganic layer. The encapsulation layer (140) may include a stacked structure of an inorganic layer / organic layer / inorganic layer.

[0055] The sensor layer (200) can be placed on the display panel (100). The sensor layer (200) can detect external input applied from the outside. The external input may be user input. User input may include various forms of external input such as a part of the user's body, light, heat, a pen, or pressure.

[0056] The sensor layer (200) can be formed on the display panel (100) through a continuous process. In this case, the sensor layer (200) can be placed directly on the display panel (100). Here, "placed directly" may mean that no third component is placed between the sensor layer (200) and the display panel (100). That is, a separate adhesive member may not be placed between the sensor layer (200) and the display panel (100).

[0057] The anti-reflection layer (300) can be placed directly on the sensor layer (200). The anti-reflection layer (300) can reduce the reflectivity of external light incident from outside the display device (DD). The anti-reflection layer (300) can be formed on the sensor layer (200) through a continuous process. The anti-reflection layer (300) may include color filters. The color filters may have a predetermined arrangement. For example, the color filters may be arranged considering the light emission colors of the pixels included in the display panel (100). Additionally, the anti-reflection layer (300) may further include a black matrix adjacent to the color filters. A detailed description of the anti-reflection layer (300) will be provided later.

[0058] In one embodiment of the present invention, the sensor layer (200) may be omitted. In this case, the anti-reflection layer (300) may be placed directly on the display panel (100). In one embodiment of the present invention, the positions of the sensor layer (200) and the anti-reflection layer (300) may be interchanged.

[0059] Although not illustrated, in one embodiment of the present invention, the display device (DD) may further include an optical layer disposed on the anti-reflection layer (300). For example, the optical layer may be formed on the anti-reflection layer (300) through a continuous process. The optical layer may improve the front brightness of the display device (DD) by controlling the direction of light incident from the display panel (100). For example, the optical layer may include an organic insulating layer in which openings are defined corresponding to each light-emitting region of the pixels included in the display panel (100), and a high-refractive index layer covering the organic insulating layer and filling the openings. The high-refractive index layer may have a higher refractive index than the organic insulating layer.

[0060] FIG. 4 is an equivalent circuit diagram of a pixel (PX) according to one embodiment of the present invention.

[0061] Referring to FIG. 4, the pixel (PX) may include a light-emitting element (LD) and a pixel circuit (PC). The light-emitting element (LD) may be a component included in the light-emitting element layer (130) of FIG. 3, and the pixel circuit (PC) may be a component included in the circuit layer (120) of FIG. 3.

[0062] The pixel circuit (PC) may include a plurality of thin-film transistors (T1 to T7) and a storage capacitor (Cst). The plurality of thin-film transistors (T1 to T7) and the storage capacitor (Cst) may be electrically connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2) (or, an anode initialization voltage line), and a driving voltage line (PL).

[0063] A plurality of thin film transistors (T1 to T7) may include a driving thin film transistor (T1, or the first thin film transistor), a switching thin film transistor (T2, or the second thin film transistor), a compensation thin film transistor (T3, or the third thin film transistor), a first initialization thin film transistor (T4, or the fourth thin film transistor), an operation control thin film transistor (T5, or the fifth thin film transistor), a light emission control thin film transistor (T6, or the sixth thin film transistor), and a second initialization thin film transistor (T7, or the seventh thin film transistor).

[0064] The light-emitting element (LD) may include a first electrode (e.g., an anode electrode or a pixel electrode) and a second electrode (e.g., a cathode electrode or a common electrode), and the first electrode of the light-emitting element (LD) is connected to a driving thin-film transistor (T1) via a light-emitting control thin-film transistor (T6) to provide a driving current (I LD ) is provided, and the second electrode may be provided with a low power supply voltage (ELVSS). The light-emitting element (LD) is provided with a driving current (I LD It can generate light of luminance corresponding to ).

[0065] Some of the plurality of thin-film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). For example, among the plurality of thin-film transistors (T1 to T7), the compensation thin-film transistor (T3) and the first initialization thin-film transistor (T4) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs).

[0066] According to one embodiment of the present invention, among a plurality of thin-film transistors (T1 to T7), the compensation thin-film transistor (T3), the first initialization thin-film transistor (T4), and the second initialization thin-film transistor (T7) may be NMOS, and the remainder may be PMOS. According to one embodiment of the present invention, only one of the plurality of thin-film transistors (T1 to T7) may be NMOS, and the remainder may be PMOS. According to one embodiment of the present invention, all of the plurality of thin-film transistors (T1 to T7) may be NMOS, or all may be PMOS.

[0067] The signal line may include a first current scan line (SL1) that transmits a first scan signal (Sn), a second current scan line (SL2) that transmits a second scan signal (Sn'), a prior scan line (SLp) that transmits a previous scan signal (Sn-1) to a first initialization thin film transistor (T4), a light emission control line (EL) that transmits a light emission control signal (En) to an operation control thin film transistor (T5) and a light emission control thin film transistor (T6), a next scan line (SLn) that transmits a subsequent scan signal (Sn+1) to a second initialization thin film transistor (T7), and a data line (DL) that intersects with the first current scan line (SL1) and transmits a data signal (Dm).

[0068] The driving voltage line (PL) transmits a driving voltage (ELVDD) to the driving thin-film transistor (T1), and the first initialization voltage line (VL1) can transmit an initialization voltage (Vint1) that initializes the driving thin-film transistor (T1) and the first electrode of the light-emitting element (LD).

[0069] The gate of the driving thin-film transistor (T1) is connected to the storage capacitor (Cst), the source of the driving thin-film transistor (T1) is connected to the driving voltage line (PL) via the operation control thin-film transistor (T5), and the drain of the driving thin-film transistor (T1) can be electrically connected to the first electrode of the light-emitting element (LD) via the light-emitting control thin-film transistor (T6). The driving thin-film transistor (T1) receives a data signal (Dm) according to the switching operation of the switching thin-film transistor (T2) and transmits a driving current (I) to the light-emitting element (LD). LD Can supply ).

[0070] The gate of the switching thin-film transistor (T2) is connected to the first current scan line (SL1) that transmits the first scan signal (Sn), the source of the switching thin-film transistor (T2) is connected to the data line (DL), and the drain of the switching thin-film transistor (T2) is connected to the source of the driving thin-film transistor (T1) and can be connected to the driving voltage line (PL) via the operation control thin-film transistor (T5). The switching thin-film transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first current scan line (SL1) and transmits the data signal (Dm) transmitted through the data line (DL) to the source of the driving thin-film transistor (T1).

[0071] The gate of the compensation thin film transistor (T3) is connected to the second current scan line (SL2). The drain of the compensation thin film transistor (T3) is connected to the drain of the driving thin film transistor (T1) and can be connected to the first electrode of the light-emitting element (LD) via the light-emitting control thin film transistor (T6). The source of the compensation thin film transistor (T3) can be connected to the first capacitor electrode (CE10) of the storage capacitor (Cst) and the gate of the driving thin film transistor (T1). Additionally, the source of the compensation thin film transistor (T3) can be connected to the drain of the first initialization thin film transistor (T4).

[0072] The compensation thin film transistor (T3) is turned on according to the second scan signal (Sn') received through the second current scan line (SL2) to electrically connect the gate and drain of the driving thin film transistor (T1), thereby allowing the driving thin film transistor (T1) to be diode-connected.

[0073] The gate of the first initialization thin film transistor (T4) can be connected to the previous scan line (SLp). The source of the first initialization thin film transistor (T4) can be connected to the source of the second initialization thin film transistor (T7) and the first initialization voltage line (VL1). The drain of the first initialization thin film transistor (T4) can be connected to the first capacitor electrode (CE10) of the storage capacitor (Cst), the source of the compensation thin film transistor (T3), and the gate of the driving thin film transistor (T1). The first initialization thin film transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) to transmit an initialization voltage (Vint1) to the gate of the driving thin film transistor (T1) and perform an initialization operation to initialize the voltage of the gate of the driving thin film transistor (T1).

[0074] The gate of the operation control thin film transistor (T5) is connected to the light emission control line (EL), the operation control source of the operation control thin film transistor (T5) is connected to the driving voltage line (PL), and the drain of the operation control thin film transistor (T5) can be connected to the source of the driving thin film transistor (T1) and the drain of the switching thin film transistor (T2).

[0075] The gate of the light-emitting control thin film transistor (T6) is connected to the light-emitting control line (EL), and the light-emitting control source of the light-emitting control thin film transistor (T6) is connected to the drain of the driving thin film transistor (T1) and the drain of the compensation thin film transistor (T3), and the drain of the light-emitting control thin film transistor (T6) can be electrically connected to the drain of the second initialization thin film transistor (T7) and the first electrode of the light-emitting element (LD).

[0076] The operation control thin-film transistor (T5) and the light emission control thin-film transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the light-emitting element (LD) and the driving current (I) to the light-emitting element (LD) LD Make ) flow.

[0077] The gate of the second initialization thin film transistor (T7) is subsequently connected to the scan line (SLn), the drain of the second initialization thin film transistor (T7) is connected to the drain of the light-emitting control thin film transistor (T6) and the first electrode of the light-emitting element (LD), and the source of the second initialization thin film transistor (T7) is connected to the second initialization voltage line (VL2) to receive the anode initialization voltage (Vint2). The second initialization thin film transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan line (SLn) to initialize the first electrode of the light-emitting element (LD).

[0078] In another embodiment, the second initialization thin-film transistor (T7) can be connected to the light emission control line (EL) and driven according to the light emission control signal (En). Meanwhile, the positions of the source and drain can be swapped depending on the type of transistor (p-type or n-type).

[0079] The storage capacitor (Cst) may include a first capacitor electrode (CE10) and a second capacitor electrode (CE20). The first capacitor electrode (CE10) of the storage capacitor (Cst) is connected to the gate of the driving thin-film transistor (T1), and the second capacitor electrode (CE20) of the storage capacitor (Cst) is connected to the driving voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to the difference between the voltage of the gate of the driving thin-film transistor (T1) and the driving voltage (ELVDD).

[0080] The boosting capacitor (Cbs) may include a first capacitor electrode (CE11) and a second capacitor electrode (CE21). The first capacitor electrode (CE11) of the boosting capacitor (Cbs) is connected to the first capacitor electrode (CE11) of the storage capacitor (Cst), and the second capacitor electrode (CE21) of the boosting capacitor (Cbs) may receive a first scan signal (Sn). The boosting capacitor (Cbs) can compensate for a voltage drop in the gate by increasing the voltage in the gate of the driving thin-film transistor (T1) at the point when the provision of the first scan signal (Sn) is stopped.

[0081] The specific operation of each pixel (PX) according to one embodiment is as follows.

[0082] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization thin film transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving thin film transistor (T1) is initialized by the initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0083] During the data programming period, when a first scan signal (Sn) and a second scan signal (Sn') are supplied through the first current scan line (SL1) and the second current scan line (SL2), the switching thin-film transistor (T2) and the compensation thin-film transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving thin-film transistor (T1) is diode-connected to the turned-on compensation thin-film transistor (T3) and is forward-biased.

[0084] Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving thin-film transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the gate of the driving thin-film transistor (T1).

[0085] A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0086] During the light emission period, the operation control thin-film transistor (T5) and the light emission control thin-film transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control line (EL). The driving current (I) depends on the voltage difference between the gate voltage of the driving thin-film transistor (T1) and the driving voltage (ELVDD). LD ) is generated, and a driving current (I) is generated through the light-emitting control thin-film transistor (T6). LD ) is supplied to the light-emitting element (LD).

[0087] In this embodiment, at least one of the plurality of thin-film transistors (T1 to T7) includes a semiconductor layer containing oxide, and the remainder includes a semiconductor layer containing silicon.

[0088] Specifically, the driving thin-film transistor (T1), which directly affects the brightness of the display device, is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the realization of a high-resolution display device.

[0089] Meanwhile, oxide semiconductors possess high carrier mobility and low leakage current, so the voltage drop is not significant even during long driving times. In other words, since the change in image color due to voltage drop is not significant even during low-frequency driving, low-frequency driving is possible.

[0090] As such, since oxide semiconductors have the advantage of low leakage current, at least one of the compensation thin film transistor (T3) connected to the gate of the driving thin film transistor (T1), the first initialization thin film transistor (T4), and the second initialization thin film transistor (T7) is adopted as an oxide semiconductor to prevent leakage current from flowing to the gate while simultaneously reducing power consumption.

[0091] FIG. 5 is a plan view of a display panel (100) according to an embodiment of the present invention. FIG. 6 is a plan view showing an enlarged view of the AA area of ​​FIG. 5.

[0092] Referring to FIGS. 5 and 6, the display panel (100) may include a display area (DP-A) and a surrounding area (DP-NA). The surrounding area (DP-NA) is adjacent to the display area (DP-A) and may surround at least a portion of the display area (DP-A).

[0093] The display area (DP-A) may include a first area (DP-A1), a second area (DP-A2), and a third area (DP-A3). The first area (DP-A1) may be referred to as a component area, the second area (DP-A2) as an intermediate area or transition area, and the third area (DP-A3) as a general display area or main display area. The first area (DP-A1) and the second area (DP-A2) may also be referred to as auxiliary display areas.

[0094] The first region (DP-A1), the second region (DP-A2), and the third region (DP-A3) can be distinguished by light transmittance or resolution. Light transmittance and resolution are measured within a reference area.

[0095] The first region (DP-A1) has a higher light transmittance compared to the second region (DP-A2) and the third region (DP-A3). This is because the first region (DP-A1) has a lower ratio of the occupied area of ​​the light-shielding structure described later compared to the second region (DP-A2) and the third region (DP-A3). The light-shielding structure may include a conductive pattern of the circuit layer described later, a pixel defining film, a pixel defining pattern, etc.

[0096] The third region (DP-A3) has a higher resolution compared to the first region (DP-A1) or the second region (DP-A2). In the third region (DP-A3), a larger number of light-emitting elements are arranged within a reference area (or the same area) compared to the first region (DP-A1) or the second region (DP-A2).

[0097] When classified based on light transmittance, the first region (DP-A1) may be the first transmittance region, and the second region (DP-A2) and the third region (DP-A3) may be different parts of the second transmittance region that are distinct from the first transmittance region. The transmittance of the second region (DP-A2) and the third region (DP-A3) may be substantially the same. Even if the transmittance of the second region (DP-A2) and the third region (DP-A3) is not the same, because the transmittance of the first region (DP-A1) is significantly higher than the transmittance of the second region (DP-A2) and the third region (DP-A3) respectively, when the first region (DP-A1) is defined as the first transmittance region, the second region (DP-A2) and the third region (DP-A3) may be defined as the second transmittance region.

[0098] When classified based on resolution, the first region (DP-A1) or the second region (DP-A2) may be the first resolution region, and the third region (DP-A3) may be the second resolution region that is distinct from the first resolution region.

[0099] The display panel (100) may include a plurality of pixels (PX). The display panel (100) may include a first pixel (PX1) that emits light in a first area (DP-A1), a second pixel (PX2) that emits light in a second area (DP-A2), and a third pixel (PX3) that emits light in a third area (DP-A3).

[0100] Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be provided in multiple numbers. In this case, each of the first to third pixels (PX1, PX2, PX3) may include a red pixel, a green pixel, and a blue pixel, and, depending on the embodiment, may further include a white pixel.

[0101] The first pixel (PX1) may include a first light-emitting element (LD1) and a first pixel circuit (PC1) that drives the first light-emitting element (LD1), the second pixel (PX2) may include a second light-emitting element (LD2) and a second pixel circuit (PC2) that drives the second light-emitting element (LD2), and the third pixel (PX3) may include a third light-emitting element (LD3) and a third pixel circuit (PC3) that drives the third light-emitting element (LD3). The positions of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) shown in FIG. 5 are illustrated corresponding to the positions of the first, second, and third light-emitting elements (LD1, LD2, LD3).

[0102] The first region (DP-A1) may overlap (or correspond) with the sensing region (1000SA) illustrated in FIG. 1 or the sensing region (100SA) illustrated in FIG. 2. That is, the first region (DP-A1) may be provided in an area that overlaps in a plane with the electronic module (CM, see FIG. 2). For example, an external input (e.g., light) may be provided to the electronic module (CM) through the first region (DP-A1), and an output from the electronic module (CM) may be emitted to the outside through the first region (DP-A1). In this embodiment, the first region (DP-A1) is illustrated as a circular shape, but it may have various shapes such as a polygon, an ellipse, a figure with at least one curved side, or an irregular shape, and is not limited to any one embodiment.

[0103] To secure the area of ​​the transmission region, a smaller number of pixels may be provided in the first region (DP-A1) than in the third region (DP-A3). An area in the first region (DP-A1) where the first light-emitting element (LD1) is not placed may be defined as a transmission region (TA, see FIG. 9). For example, an area in the first region (DP-A1) where the first electrode (AE1, or first pixel electrode, see FIG. 9) of the first light-emitting element (LD1) and the pixel definition pattern (PDP, see FIG. 9) surrounding the first electrode (AE1, see FIG. 9) are not placed may be defined as a transmission region (TA, see FIG. 9).

[0104] Within a unit area or the same area, the number of first pixels (PX1) placed in the first area (DP-A1) may be less than the number of third pixels (PX3) placed in the third area (DP-A3). For example, the resolution of the first area (DP-A1) may be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 16, etc. of the resolution of the third area (DP-A3). For example, the resolution of the third area (DP-A3) may be about 400 ppi or higher, and the resolution of the first area (DP-A1) may be about 200 ppi or 100 ppi. However, this is merely an example and is not specifically limited thereto.

[0105] The first pixel circuit (PC1) of the first pixel (PX1) may not be placed in the first area (DP-A1). For example, the first pixel circuit (PC1) may be placed in the second area (DP-A2) or the surrounding area (DP-NA). In this case, the light transmittance of the first area (DP-A1) may be increased compared to when the first pixel circuit (PC1) is placed in the first area (DP-A1).

[0106] The first light-emitting element (LD1) and the first pixel circuit (PC1) can be electrically connected to each other through a connecting wire (TWL). The connecting wire (TWL) may overlap with the transparent area of ​​the first region (DP-A1). The connecting wire (TWL) may include a transparent conductive wire. The transparent conductive wire may include a transparent conductive material or a light-transmitting material. For example, the connecting wire (TWL) may be formed from a transparent conductive oxide (TCO) film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0107] The second region (DP-A2) is adjacent to the first region (DP-A1). The second region (DP-A2) may enclose at least a portion of the first region (DP-A1). The second region (DP-A2) may be a region having a lower transmittance than the first region (DP-A1). In the present embodiment, the second region (DP-A2) may be spaced apart from the surrounding region (DP-NA). However, it is not limited thereto, and the second region (DP-A2) may be in contact with the surrounding region (DP-NA).

[0108] In the second region (DP-A2), the first pixel circuit (PC1), the second light-emitting element (LD2), and the second pixel circuit (PC2) of the first pixel (PX1) may be disposed. The second region (DP-A2) may have a light transmittance lower than that of the first region (DP-A1) by including the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0109] The third region (DP-A3) is adjacent to the second region (DP-A2). The third region (DP-A3) may be adjacent to the first region (DP-A1). The third region (DP-A3) may be defined as a region having a lower transmittance than the first region (DP-A1). A third light-emitting element (LD3) and a third pixel circuit (PC3) may be disposed in the third region (DP-A3).

[0110] Although not specifically illustrated in FIG. 6, in order to secure a gap with the third light-emitting element (LD3) placed in the third region (DP-A3), the first light-emitting element (LD1) placed in the first region (DP-A1) closest to the third region (DP-A3) may have a circular shape with a larger width in a specific direction. For example, when the first region (DP-A1) is adjacent to the third region (DP-A3) in the second direction (DR2), the width of the first light-emitting element (LD1) in the first direction (DR1) may be larger than the width in the second direction (DR2).

[0111] Each of the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be provided in multiple numbers. The distance between the two first light-emitting elements closest to each other among the first light-emitting elements (LD1) may be greater than the distance between the two third light-emitting elements closest to each other among the third light-emitting elements (LD3). Additionally, the distance between the two second light-emitting elements closest to each other among the second light-emitting elements (LD2) may be greater than the distance between the two light-emitting elements closest to each other among the third light-emitting elements (LD3).

[0112] The first, second, and third light-emitting elements (LD1, LD2, LD3) illustrated in FIG. 6 may correspond to the planar shapes of the first lower electrode (AE1, see FIG. 9) of the first light-emitting element (LD1), the second lower electrode (AE2, see FIG. 8) of the second light-emitting element (LD2), and the third lower electrode (AE3, see FIG. 7) of the third light-emitting element (LD3).

[0113] FIGS. 7 to 9 are cross-sectional views of a display panel (100) according to one embodiment of the present invention.

[0114] FIG. 7 is a cross-sectional view of the third area (DP-A3), which is the main display area; FIG. 8 is a cross-sectional view of the second area (DP-A2); and FIG. 9 is a cross-sectional view of the first area (DP-A1).

[0115] Referring to FIGS. 7 through 9 together, the display panel (100) may include a plurality of insulating layers, a semiconductor pattern, a conductive pattern, and a signal line, etc. The insulating layer, the semiconductor layer, and the conductive layer are formed by methods such as coating or deposition. Subsequently, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. In this way, the semiconductor pattern, the conductive pattern, the signal line, etc. included in the circuit layer (120) and the light-emitting element layer (130) are formed. Subsequently, an encapsulation layer (140) covering the light-emitting element layer (130) may be formed.

[0116] Referring to FIG. 7, the third region (DP-A3) of the display panel (100) shows a silicon thin-film transistor (S-TFT) and an oxide thin-film transistor (O-TFT) included in the third light-emitting element (LD3) and the third pixel circuit (PC3). In the equivalent circuit shown in FIG. 4, the third and fourth thin-film transistors (T3, T4) may be oxide thin-film transistors (O-TFT), and the remaining transistors may be silicon thin-film transistors (S-TFT). FIG. 8 shows a second light-emitting element (LD2), a second pixel circuit (PC2), and a first pixel circuit (PC1). FIG. 9 shows a first light-emitting element (LD1).

[0117] In a display panel (100) of one embodiment, a circuit layer (120) is disposed on a base layer (110). The base layer (110) may have a multilayer structure. For example, the base layer (110) may be a first synthetic resin layer, and a silicon oxide (SiO₂) disposed on the first synthetic resin layer.x It may include a silicon oxide layer, a silicon oxynitride (SiON) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the silicon oxynitride layer. The silicon oxide layer and the silicon oxynitride layer may be referred to as base barrier layers. Each of the first and second synthetic resin layers may comprise a polyimide-based resin. Additionally, each of the first and second synthetic resin layers may comprise at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in this specification, a “~~”-based resin means that it includes a “~~” functional group.

[0118] A barrier layer (br) may be disposed on the base layer (110). The barrier layer (br) may have a multilayer structure. For example, the barrier layer (br) may be silicon oxide (SiO₂). x ) layer, silicon oxide nitride (SiO y N z ) layer, silicon nitride (SiN w It may include a ) layer and / or an amorphous silicon (a-Si) layer. For example, the barrier layer (br) may be silicon oxide (SiO₂). x It may include a ) layer and an amorphous silicon (a-Si) layer.

[0119] A buffer layer (bf) may be disposed on the barrier layer (br). The buffer layer (bf) can prevent metal atoms or impurities from the base layer (110) from diffusing into the semiconductor pattern. Additionally, the buffer layer (bf) can control the rate of heat supply during the crystallization process for forming the semiconductor pattern, thereby ensuring that the semiconductor pattern is formed uniformly.

[0120] In one embodiment, the semiconductor pattern may include a first semiconductor pattern and a second semiconductor pattern, and a silicon thin-film transistor (S-TFT) may be formed from the first semiconductor pattern and an oxide thin-film transistor (O-TFT) may be formed from the second semiconductor pattern. A back metal layer (BML) may be disposed below the silicon thin-film transistor (S-TFT) and the oxide thin-film transistor (O-TFT). The back metal layer (BML) may be disposed overlapping with the first to third pixel circuits (PC1, PC2, PC3). The back metal layer (BML) may block the electrical potential caused by polarization phenomena from affecting the first to third pixel circuits (PC1, PC2, PC3).

[0121] In one embodiment, the back metal layer (BML) may be disposed between the barrier layer (br) and the buffer layer (bf). In one embodiment of the present invention, the back metal layer (BML) may be connected to an electrode or wiring and may receive a static voltage or signal from them. According to one embodiment of the present invention, the back metal layer (BML) may be a floating electrode in a form isolated from other electrodes or wiring.

[0122] The back metal layer (BML) may include a reflective metal. For example, the back metal layer (BML) may include silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), titanium (Ti), and p+-doped amorphous silicon.

[0123] Although not separately described, according to one embodiment of the present invention, a back metal layer (BML) may be spaced apart and disposed below each of a silicon thin film transistor (S-TFT) and an oxide thin film transistor (O-TFT). For example, the back metal layer (BML) may include a first back metal layer disposed below the silicon thin film transistor (S-TFT) and a second back metal layer disposed below the oxide thin film transistor (O-TFT). For example, the first back metal layer may be disposed between a barrier layer (br) and a buffer layer (bf), and the second back metal layer may be disposed between a second insulating layer (20) and a third insulating layer (30).

[0124] The first semiconductor pattern may be placed on the buffer layer (bf). The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern may include low-temperature polysilicon.

[0125] FIG. 7 illustrates only a portion of the first semiconductor pattern disposed on the buffer layer (bf), and the first semiconductor pattern may be disposed in other areas. The first semiconductor pattern may be arranged according to a specific rule across the pixels. The electrical properties of the first semiconductor pattern may differ depending on whether it is doped. The first semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration compared to the first region.

[0126] The conductivity of the first region is greater than that of the second region, and the first region can substantially function as an electrode or a signal line. The second region can substantially correspond to the active region (or channel) of the transistor. In other words, a part of the semiconductor pattern may be the active region of the transistor, another part may be the source or drain of the transistor, and yet another part may be a connecting electrode or a connecting signal line.

[0127] The source region (SE1, or source), active region (AC1, or channel), and drain region (DE1, or drain) of the silicon thin-film transistor (S-TFT) can be formed from a first semiconductor pattern. The source region (SE1) and the drain region (DE1) can extend in opposite directions from the active region (AC1) on a cross-section.

[0128] The first insulating layer (10) may be placed on the buffer layer (bf). The first insulating layer (10) overlaps in common with a plurality of pixels and may cover the first semiconductor pattern. The first insulating layer (10) may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer (10) may be a single layer of silicon oxide. The insulating layer of the circuit layer (120) described below, as well as the first insulating layer (10), may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The inorganic layer may include at least one of the materials described above, but is not limited thereto.

[0129] The gate (GT1) of the silicon thin-film transistor (S-TFT) is placed on the first insulating layer (10). The gate (GT1) may be part of a metal pattern. The gate (GT1) overlaps the active region (AC1). In the process of doping the first semiconductor pattern, the gate (GT1) may function as a mask. The gate (GT1) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0130] The second insulating layer (20) is placed on the first insulating layer (10) and can cover the gate (GT1). The third insulating layer (30) can be placed on the second insulating layer (20).

[0131] The second semiconductor pattern may be placed on the third insulating layer (30). The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, reduced region) has greater conductivity than the region where it is not reduced (hereinafter, non-reduced region). The reduced region substantially serves as the source / drain or signal line of the transistor. The non-reduced region substantially corresponds to the semiconductor region (or channel) of the transistor. In other words, a part of the semiconductor pattern may be the semiconductor region of the transistor, another part may be the source / drain of the transistor, and yet another part may be the signal transmission region.

[0132] The source region (SE2, or source), active region (AC2, or channel), and drain region (DE2, or drain) of the oxide thin film transistor (O-TFT) can be formed from a second semiconductor pattern. The source region (SE2) and the drain region (DE2) can extend in opposite directions from the active region (AC2) on a cross-section.

[0133] The fourth insulating layer (40) may be placed on the third insulating layer (30). The fourth insulating layer (40) overlaps in common with a plurality of pixels and may cover the second semiconductor pattern. The gate (GT2) of the oxide thin film transistor (O-TFT) is placed on the fourth insulating layer (40). The gate (GT2) of the oxide thin film transistor (O-TFT) may be part of the metal pattern. The gate (GT2) of the oxide thin film transistor (O-TFT) overlaps with the active region (AC2).

[0134] The fifth insulating layer (50) is placed on the fourth insulating layer (40) and can cover the gate (GT2). The first connecting electrode (CNE1) can be placed on the fifth insulating layer (50). The first connecting electrode (CNE1) can be connected to the drain region (DE1) of the silicon thin-film transistor (S-TFT) through a contact hole penetrating the first to fifth insulating layers (10, 20, 30, 40, 50).

[0135] A sixth insulating layer (60) may be placed on top of a fifth insulating layer (50). A second connecting electrode (CNE2) may be placed on top of the sixth insulating layer (60). The second connecting electrode (CNE2) may be connected to a first connecting electrode (CNE1) through a contact hole penetrating the sixth insulating layer (60). A seventh insulating layer (70) is placed on top of the sixth insulating layer (60) and may cover the second connecting electrode (CNE2). An eighth insulating layer (80) may be placed on top of the seventh insulating layer (70).

[0136] Each of the sixth insulating layer (60), the seventh insulating layer (70), and the eighth insulating layer (80) may be an organic layer. For example, each of the sixth insulating layer (60), the seventh insulating layer (70), and the eighth insulating layer (80) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0137] A light-emitting element layer (130) including first to third light-emitting elements (LD1, LD2, LD3) may be disposed on a circuit layer (120). The first light-emitting element (LD1) may include a first electrode (AE1, or pixel electrode), a light-emitting layer (EL1), and a second electrode (CE1), the second light-emitting element (LD2) may include a first electrode (AE2, or pixel electrode), a light-emitting layer (EL2), and a second electrode (CE2), and the third light-emitting element (LD3) may include a first electrode (AE3, or pixel electrode), a light-emitting layer (EL3), and a second electrode (CE3). In one example, the second electrodes (CE1, CE2, CE3) of the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) are shown to be spaced apart from each other. However, the embodiments are not limited thereto, and in other embodiments of the present invention, the second electrodes (CE1, CE2, CE3) of the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may have an integral shape and be provided as a common electrode. In this case, the second electrodes (CE1, CE2, CE3) may overlap the transmission region (TA) in a planar manner.

[0138] The first electrode (AE1) of the first light-emitting element (LD1), the first electrode (AE2) of the second light-emitting element (LD2), and the first electrode (AE3) of the third light-emitting element (LD3) may be disposed on the eighth insulating layer (80). Each of the first electrode (AE1) of the first light-emitting element (LD1), the first electrode (AE2) of the second light-emitting element (LD2), and the first electrode (AE3) of the third light-emitting element (LD3) may be a (semi)transparent electrode or a reflective electrode. According to one embodiment of the present invention, each of the first electrode (AE1) of the first light-emitting element (LD1), the first electrode (AE2) of the second light-emitting element (LD2), and the first electrode (AE3) of the third light-emitting element (LD3) may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semitransparent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may comprise at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (AE1) of the first light-emitting element (LD1), the first electrode (AE2) of the second light-emitting element (LD2), and the first electrode (AE3) of the third light-emitting element (LD3) may each comprise a stacked structure of ITO / Ag / ITO.

[0139] The pixel defining film (PDL) and the pixel defining pattern (PDP) may be placed on the eighth insulating layer (80). The pixel defining film (PDL) and the pixel defining pattern (PDP) may contain the same material and may be formed through the same process. Each of the pixel defining film (PDL) and the pixel defining pattern (PDP) may have the property of absorbing light, for example, each of the pixel defining film (PDL) and the pixel defining pattern (PDP) may have the color black. Each of the pixel defining film (PDL) and the pixel defining pattern (PDP) may contain a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof. Each of the pixel defining film (PDL) and the pixel defining pattern (PDP) may correspond to a light-blocking pattern having light-blocking properties.

[0140] A pixel defining pattern (PDP) can be placed in a first region (DP-A1). The pixel defining pattern (PDP) can cover a portion of the first electrode (AE1) of the first light-emitting element (LD1). For example, the pixel defining pattern (PDP) can cover the edge of the first electrode (AE1) of the first light-emitting element (LD1).

[0141] An opening (PDP-OP) that exposes a portion of the first electrode (AE1) may be defined in the pixel definition pattern (PDP). The area where the first electrode (AE1) is exposed through the opening (PDP-OP) may be defined as a first light-emitting area (LA1). The first light-emitting area (LA1) may be provided in multiple numbers corresponding to the number of first light-emitting elements (LD1).

[0142] A pixel defining film (PDL) may be placed in a second region (DP-A2) and a third region (DP-A3). The pixel defining film (PDL) may cover a portion of the first electrode (AE2) of the second light-emitting element (LD2) and the first electrode (AE3) of the third light-emitting element (LD3), respectively. For example, a first opening (PDL-OP1) that exposes a portion of the first electrode (AE2) of the second light-emitting element (LD2) and a second opening (PDL-OP2) that exposes a portion of the first electrode (AE3) of the third light-emitting element (LD3) may be defined in the pixel defining film (PDL). The area where the first electrode (AE2) of the second light-emitting element (LD2) is exposed through the first opening (PDL-OP1) or opening (PDP-OP) may be defined as a second light-emitting area (LA2).

[0143] The pixel defining pattern (PDP) can increase the distance between the edge of the first electrode (AE1) of the first light-emitting element (LD1) and the second electrode (CE1), and the pixel defining film (PDL) can increase the distance between the edge of the first electrode (AE2) of the second light-emitting element (LD2) and the edge of the first electrode (AE3) of the third light-emitting element (LD3) and the second electrodes (CE2, CE3). Therefore, the pixel defining pattern (PDP) and the pixel defining film (PDL) can serve to prevent arcs from occurring at the edges of the first electrodes (AE1, AE2, AE3).

[0144] The area overlapping with the portion where the first electrode (AE1) of the first light-emitting element (LD1) and the pixel definition pattern (PDP) are arranged in the first area (DP-A1) is defined as the element area (DA), and the remaining area can be defined as the transmission area (TA).

[0145] The first electrode (AE1) of the first light-emitting element (LD1) may be electrically connected to the first pixel circuit (PC1) located in the second region (DP-A2). For example, the first electrode (AE1) of the first light-emitting element (LD1) may be electrically connected to the first pixel circuit (PC1) through a connecting wire (TWL) and connecting electrodes (CNE1', CPN). In this case, the connecting wire (TWL) may overlap with the transmission region (TA). Accordingly, the connecting wire (TWL) may include a light-transmitting material. According to one embodiment of the present invention, the connecting electrode (CPN) may be omitted, and the connecting wire (TWL) may be directly connected to the conductive pattern of the first pixel circuit (PC1).

[0146] The connecting wire (TWL) may be placed between the fifth insulating layer (50) and the sixth insulating layer (60), but is not particularly limited thereto. The connecting electrodes (CNE1', CPN) may be placed between the sixth insulating layer (60) and the seventh insulating layer (70).

[0147] The light-emitting layer (EL1) of the first light-emitting element (LD1) may be placed on the first electrode (AE1) of the first light-emitting element (LD1), the light-emitting layer (EL2) of the second light-emitting element (LD2) may be placed on the first electrode (AE2) of the second light-emitting element (LD2), and the light-emitting layer (EL3) of the third light-emitting element (LD3) may be placed on the first electrode (AE3) of the third light-emitting element (LD3). In this embodiment, each of the light-emitting layers (EL1, EL2, EL3) may emit light of at least one color among blue, red, and green.

[0148] The second electrode (CE1, CE2, CE3) can be placed on the light-emitting layers (EL1, EL2, EL3).

[0149] Although not illustrated, a hole control layer may be disposed between the first electrodes (AE1, AE2, AE3) and the light-emitting layers (EL1, EL2, EL3). The hole control layer may include a hole transport layer and may further include a hole injection layer. An electronic control layer may be disposed between the light-emitting layers (EL1, EL2, EL3) and the second electrodes (CE1, CE2, CE3). The electronic control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electronic control layer may be formed commonly in a plurality of pixels (PX, see FIG. 5) using an open mask.

[0150] The encapsulation layer (140) may be disposed on the light-emitting element layer (130). The encapsulation layer (140) may include sequentially stacked inorganic layers (141), organic layers (142), and inorganic layers (143), but the layers constituting the encapsulation layer (140) are not limited thereto.

[0151] Inorganic layers (141, 143) can protect the light-emitting element layer (130) from moisture and oxygen, and organic layer (142) can protect the light-emitting element layer (130) from foreign substances such as dust particles. The inorganic layers (141, 143) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer (142) may include an acrylic-based organic layer, but is not limited thereto.

[0152] In FIG. 9, an electronic module (CM) placed at the bottom of the display panel (100) is additionally illustrated for illustrative purposes. On a plane, the electronic module (CM) may overlap with the first region (DP-A1), and in particular, with the element region (DP) and the transmission region (TA).

[0153] Referring to FIG. 9, the display panel (100) of the present invention may include a first conductive pattern (MT1), a second conductive pattern (MT2), and a third conductive pattern (MT3) disposed in a first region (DP-A1). On a plane, the first to third conductive patterns (MT1, MT2, MT3) overlap with the element region (DA) and do not overlap with the transmission region (TA).

[0154] In a planar plane, the first to third conductive patterns (MT1, MT2, MT3) are superimposed on the first light-emitting element (LD1), specifically superimposed on the first electrode (AE1) of the first light-emitting element (LD1).

[0155] As the first to third conductive patterns (MT1, MT2, MT3) are placed in the device region (DA), they may not interfere with the reception and transmission of light by the electronic module (CM, see FIG. 2) through the transmission region (TA).

[0156] If the first to third conduction patterns (MT1, MT2, MT3) do not exist, reflected light (RL) reflected from the electronic module (CM) may be reflected from the lower surface of the first electrode (AE1) and re-incident into the electronic module (CM). At this time, the shape of the first electrode (AE1) may be visible in the electronic module (CM). For example, if the electronic module (CM) is a camera module, a ghosting phenomenon may occur in which the shape of the first electrode (AE1) is visible in the camera lens as the reflected light (RL) is reflected from the lower surface of the first electrode (AE1) and re-incident into the electronic module (CM). In this case, the reliability of the electronic module (CM) and the reliability of the electronic device (1000) including the electronic module (CM) may be reduced.

[0157] The display panel (100) of the present invention includes first to third conductive patterns (MT1, MT2, MT3) disposed below the first electrode (AE1), thereby providing a rough reflective interface to the reflected light (RL), and can reduce the amount of reflected light (RL) or trap the reflected light (RL) within the first to third conductive patterns (MT1, MT2, MT3). Accordingly, the reflected light (RL) re-incident to the electronic module (CM) can be minimized, and the ghosting phenomenon appearing on the electronic module (CM) can also be mitigated. The user of the electronic device (1000) can clearly see the subject through the electronic module (CM).

[0158] In one embodiment, a first conductive pattern (MT1) may be placed between a barrier layer (br) and a buffer layer (bf). The first conductive pattern (MT1) and the back metal layer (BML, see FIG. 7) may comprise the same material and may be formed through the same process. A second conductive pattern (MT2) may be placed between a first insulating layer (10) and a second insulating layer (20). The second conductive pattern (MT2) and the gate (GT1) of a silicon thin-film transistor (S-TFT) may comprise the same material and may be formed through the same process. A third conductive pattern (MT3) may be placed between a second insulating layer (20) and a third insulating layer (30).

[0159] In one embodiment, the first to third conductive patterns (MT1, MT2, MT3) may include a reflective metal. The first and second conductive patterns (MT1, MT2) may each independently include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but are not particularly limited thereto.

[0160] The third conductive pattern (MT3) may include silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), titanium (Ti), and p+-doped amorphous silicon.

[0161] For example, each of the first to third conductive patterns (MT1, MT2, MT3) may include molybdenum (Mo). However, the embodiments are not limited thereto.

[0162] In a planar arrangement, the first and second conductive patterns (MT1, MT2) are arranged to intersect each other, and the third conductive pattern (MT3) covers the first conductive pattern (MT1) and the second conductive pattern (MT2). ​​Accordingly, reflected light (RL) can be blocked from passing through the first conductive pattern (MT1) and the second conductive pattern (MT2) to proceed to the first electrode (AE1) and re-incident to the electronic module (CM). This will be explained in conjunction with FIG. 10.

[0163] FIG. 10 is a plan view of a device region (DA) according to one embodiment of the present invention.

[0164] FIG. 10 briefly illustrates a plan view of the first to third conductive patterns (MT1, MT2, MT3) placed in the device region (DA).

[0165] Referring to FIG. 10, the first conductive pattern (MT1) and the second conductive pattern (MT2) may intersect each other in a plane. For example, the first conductive pattern (MT1) may extend in a first direction (DR1), and the second conductive pattern (MT2) may extend in a second direction (DR2) that intersects the first direction (DR1). In one embodiment, the first direction (DR1) may be perpendicular to the second direction (DR2). However, the embodiment is not limited thereto, and the second conductive pattern (MT2) may extend in a direction that forms an angle greater than 0° and less than 90° with respect to the first direction (DR1).

[0166] The first conductive pattern (MT1) may include a plurality of first conductive patterns (MT1-a, MT1-b, MT1-c, MT1-d), each of which extends in a first direction (DR1). The plurality of first conductive patterns (MT1-a, MT1-b, MT1-c, MT1-d) may be spaced apart from each other in a second direction (DR2).

[0167] Each of the plurality of first conductive patterns (MT1-a, MT1-b, MT1-c, MT1-d) may have a first width (L1). The first width (L1) may have a range of several micrometers. The first width (L1) is a length measured in a second direction (DR2) which is perpendicular to the extension direction of the first conductive pattern (MT1).

[0168] The spacing between the plurality of first conductive patterns (MT1-a, MT1-b, MT1-c, MT1-d) may be uniform. For example, the plurality of first conductive patterns (MT1-a, MT1-b, MT1-c, MT1-d) may be spaced apart from each other by a first spacing (S1) along a second direction (DR2). The first spacing (S1) may have a range of several micrometers or more and tens of micrometers or less.

[0169] The second conductive pattern (MT2) may include a plurality of second conductive patterns (MT2-a, MT2-b, MT2-c, MT2-d, MT2-e), each of which extends into the second direction (DR2). The plurality of second conductive patterns (MT2-a, MT2-b, MT2-c, MT2-d, MT2-e) may be spaced apart from each other in the first direction (DR1).

[0170] Each of the multiple second conductive patterns (MT2-a, MT2-b, MT2-c, MT2-d, MT2-e) may have a second width (L2). The second width (L2) may have a range of several micrometers. The second width (L2) is a length measured in a first direction (DR1) which is perpendicular to the extension direction of the second conductive pattern (MT2).

[0171] The spacing between the plurality of second conductive patterns (MT2-a, MT2-b, MT2-c, MT2-d, MT2-e) may be uniform. For example, the plurality of second conductive patterns (MT2-a, MT2-b, MT2-c, MT2-d, MT2-e) may be spaced apart from each other by a second spacing (S2) along a first direction (DR1). The second spacing (S2) may have a range of several micrometers or more and tens of micrometers or less.

[0172] A third conductive pattern (MT3) may be disposed on the first conductive pattern (MT1) and the second conductive pattern (MT2). ​​The third conductive pattern (MT3) covers the first conductive pattern (MT1) and the second conductive pattern (MT2), thereby blocking light passing through the first conductive pattern (MT1) and the second conductive pattern (MT2) from proceeding to the first electrode (AE1) and re-inciding into the electronic module (CM).

[0173] FIG. 9 may be a cross-sectional view corresponding to the cutting line A-A' shown in FIG. 10.

[0174] Referring to FIG. 9 and FIG. 10 together, in one embodiment, reflected light (RL) may be incident on a second conductive pattern (MT2), reflected to a first conductive pattern (MT1), and then reflected again from the first conductive pattern (MT1) to be incident on a second conductive pattern (MT2). ​​However, the path and incident point of the reflected light (RL) are not limited to those depicted.

[0175] As reflected light (RL) is trapped between the second conductive pattern (MT2) and the first conductive pattern (MT1), the amount of reflected light (RL) incident on the electronic module (CM) can be minimized. Additionally, since the third conductive pattern (MT3) covers the first and second conductive patterns (MT1, MT2), reflected light (RL) that passes through the first and second conductive patterns (MT1, MT2) can be reflected from the third conductive pattern (MT3) and incident again on the first conductive pattern (MT1) or the second conductive pattern (MT1, MT2). ​​Accordingly, the reliability of the electronic module (CM) can be improved.

[0176] Additionally, as illustrated in FIG. 10, since the first conductive pattern (MT1) and the second conductive pattern (MT2) are arranged to intersect on a plane, the amount of reflected light (RL) that passes through the first conductive pattern (MT1) and the second conductive pattern (MT2) and reaches the third conductive pattern (MT3) is reduced, for example, by 50%. However, the amount of reduction in light is not limited to this, and the amount of reflected light (RL) may be reduced to less than 50% or more than 50% depending on the width and arrangement spacing of each of the first conductive pattern (MT1) and the second conductive pattern (MT2). ​​Accordingly, the amount of reflected light (RL) reaching the electronic module (CM) may be reduced, or there may be no reflected light (RL) incident on the electronic module (CM).

[0177] The reflection path of the reflected light (RL) is explained with reference to FIG. 11a and FIG. 11b.

[0178] FIG. 11a is a cross-sectional view along the cutting line B-B' of FIG. 10. FIG. 11b is a cross-sectional view along the cutting line C-C' of FIG. 10.

[0179] FIG. 11a illustrates a cross-sectional view of a first conductive pattern (MT1) and a second conductive pattern (MT2) along the cutting line B-B'. An intermediate insulating layer (IL1) may be disposed between the first conductive pattern (MT1) and the second conductive pattern (MT2). ​​In one embodiment, the intermediate insulating layer (IL1) may be a buffer layer (bf, see FIG. 9).

[0180] Referring to FIG. 11a, reflected light (RL) can be reflected from the second conductive pattern (MT2) and incident on the first conductive pattern (MT1). Specifically, the first spacing (S1), which is the spacing of the first conductive pattern (MT1) When satisfying (first thickness (Th1) x 2) / (tan θ1) between the first conductive pattern (MT1) and the second conductive pattern (MT2), reflected light (RL) can be reflected from the second conductive pattern (MT2) and incident on the first conductive pattern (MT1). θ1 is the angle formed by the incident path of the reflected light (RL) and the plane parallel to the lower surface of the first conductive pattern (MT1). A first gap (S1) can be set considering θ1 and the first thickness (Th1).

[0181] Subsequently, as reflected light (RL) is incident from the first conductive pattern (MT1) back to the second conductive pattern (MT2), the reflected light (RL) can be trapped between the first conductive pattern (MT1) and the second conductive pattern (MT2). ​​Accordingly, the amount of reflected light (RL) incident on the electronic module (CM, see FIG. 9) can be minimized.

[0182] FIG. 11b illustrates a cross-sectional view of a second conductive pattern (MT2) and a third conductive pattern (MT3) along the cutting line C-C'. An intermediate insulating layer (IL2) may be disposed between the second conductive pattern (MT2) and the third conductive pattern (MT3). In one embodiment, the intermediate insulating layer (IL2) may be the second insulating layer (20, see FIG. 9).

[0183] Referring to FIG. 11b, reflected light (RL) can be reflected from the third conductive pattern (MT3) and incident on the second conductive pattern (MT2). ​​Specifically, the second spacing (S2), which is the spacing of the second conductive pattern (MT2) When satisfying (second thickness (Th2) x 2) / (tan θ2) between the second conductive pattern (MT2) and the third conductive pattern (MT3), reflected light (RL) can be reflected from the third conductive pattern (MT3) and incident on the second conductive pattern (MT2). ​​θ2 is the angle formed by the incident path of the reflected light (RL) and the plane parallel to the lower surface of the second conductive pattern (MT2). ​​A second gap (S2) can be set considering θ2 and the second thickness (Th2).

[0184] Subsequently, as reflected light (RL) is incident from the second conductive pattern (MT2) back to the third conductive pattern (MT3), the reflected light (RL) can be trapped between the second conductive pattern (MT2) and the third conductive pattern (MT3). Accordingly, the amount of reflected light (RL) incident on the electronic module (CM, see FIG. 9) can be minimized.

[0185] FIG. 12 is a cross-sectional view of a display panel (100-1) according to an embodiment of the present invention. Among the configurations shown in FIG. 12, the configurations described in FIG. 1 to FIG. 10 are subject to the aforementioned descriptions, and a detailed description is omitted.

[0186] Referring to FIG. 12, a display panel (100-1) of one embodiment may include a first conductive pattern (MT1-1), a second conductive pattern (MT2-1), and a third conductive pattern (MT3-1) disposed in a first region (DP-A1). On a plane, the first to third conductive patterns (MT1-1, MT2-1, MT3-1) overlap with the element region (DA) and do not overlap with the transmission region (TA).

[0187] In a planar plane, the first to third conductive patterns (MT1-1, MT2-1, MT3-1) are superimposed on the first light-emitting element (LD1), specifically superimposed on the first electrode (AE1) of the first light-emitting element (LD1).

[0188] The positions of the first to third conductive patterns (MT1-1, MT2-1, MT3-1) included in the display panel (100-1) of FIG. 12 may differ from the positions of the first to third conductive patterns (MT1, MT2, MT3) included in the display panel (100) of FIG. 9. In the display panel (100-1) of one embodiment, the first conductive pattern (MT1-1) may be placed between the first insulating layer (10) and the second insulating layer (20). The first conductive pattern (MT1-1) and the gate (GT1) of the silicon thin-film transistor (S-TFT) may contain the same material and may be formed through the same process. The second conductive pattern (MT2-1) may be placed between the second insulating layer (20) and the third insulating layer (30). The third conductive pattern (MT3-1) can be placed between the third insulating layer (30) and the fourth insulating layer (40).

[0189] In one embodiment, the first to third conductive patterns (MT1-1, MT2-1, MT3-1) may include a reflective metal. The first to third conductive patterns (MT1-1, MT2-1, MT3-1) may each independently include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but are not particularly limited thereto.

[0190] For example, each of the first to third conductive patterns (MT1-1, MT2-1, MT3-1) may include molybdenum (Mo). However, the examples are not limited thereto.

[0191] In a plane, the first and second conductive patterns (MT1-1, MT2-1) may be arranged to intersect each other. For example, in a plane, the first and second conductive patterns (MT1-1, MT2-1) may be arranged perpendicular to each other. The third conductive pattern (MT3-1) covers the first and second conductive patterns (MT1-1, MT2-1), thereby blocking reflected light passing through the first and second conductive patterns (MT1-1, MT2-1) from proceeding to the first electrode (AE1).

[0192] For the width and spacing of each of the first to third conductive patterns (MT1-1, MT2-1, MT3-1), the content regarding the first to third conductive patterns (MT1, MT2, MT3) described above in FIG. 10, FIG. 11a, and FIG. 11b may be applied in the same way.

[0193] Referring to FIG. 12, reflected light (RL-1) of one embodiment reflected from an electronic module (CM) may be incident on a third conductive pattern (MT3-1) and reflected in the order of a first conductive pattern (MT1-1), a third conductive pattern (MT3-1), and a second conductive pattern (MT2-1). In this way, reflected light (RL-1) may be trapped between the first to third conductive patterns (MT1-1, MT2-1, MT3-1). However, the path and incident point of the reflected light (RL-1) are not limited to those depicted.

[0194] Specifically, the reflected light (RL-1) can be trapped between the first conductive pattern (MT1-1) and the second conductive pattern (MT2-1) by satisfying the conditions described above in FIG. 11a, and can be trapped between the second conductive pattern (MT2-1) and the third conductive pattern (MT3-1) by satisfying the conditions described above in FIG. 11b.

[0195] The reflected light (RL-1) has its light path changed as it passes through the first conductive pattern (MT1-1) and the second conductive pattern (MT2-1) arranged to intersect each other, and accordingly, the amount of light can be gradually reduced.

[0196] Therefore, even if the reflected light (RL-1) is re-incident into the electronic module (CM, see FIG. 2) after passing through the first to third conduction patterns (MT1-1, MT2-1, MT3-1), the aforementioned ghosting phenomenon can be mitigated.

[0197] FIG. 13 is a graph showing the reflectance (%) according to the angle of incidence (°) of each electronic device of Example 1 and Example 2.

[0198] The electronic device of Example 1 includes the first to third conductivity patterns (MT1, MT2, MT3) shown in FIG. 9. The electronic device of Example 2 includes the first to third conductivity patterns (MT1-1, MT2-1, MT3-1) shown in FIG. 12.

[0199] Additionally, referring to FIG. 10, Example 1 is an electronic device satisfying a first width (L1) = 6 μm, a first gap (S1) = 6 μm, a second width (L2) = 3 μm, and a second gap (S2) = 9 μm, and Example 2 is an electronic device satisfying a first width (L1) = 3 μm, a first gap (S1) = 9 μm, a second width (L2) = 3 μm, and a second gap (S2) = 9 μm.

[0200] In FIG. 13, it can be seen that for Example 1 and Example 2, the reflectance when the angle of incidence is 15°, 30°, 45°, and 60° is lower than the reflectance when the angle of incidence is 0°. Example 1 exhibits the lowest reflectance when the angle of incidence is 45°, and Example 2 exhibits the lowest reflectance when the angle of incidence is 60°.

[0201] Meanwhile, it can be seen that the reflectance (%) of Example 1 is lower than that of Example 2. This is because the spacing between the first to third conductive patterns (MT1, MT2, MT3) in Example 1 is larger than the spacing between the first to third conductive patterns (MT1-1, MT2-1, MT3-1) in Example 2, so there is a larger space for reflected light to be trapped.

[0202] In addition, the first conductive pattern of Example 1 (MT1, see FIG. 9) has silicon oxide (SiO₂) underneath compared to the first conductive pattern of Example 2 (MT1-1, see FIG. 12). x It is determined that the reflectance of reflected light is further reduced by the placement of a barrier layer (br, see FIG. 9) including a ) layer and an amorphous silicon (a-Si) layer.

[0203] Accordingly, silicon oxide (SiO₂) is placed underneath each of the first to third conductive patterns (MT1, MT2, MT3, MT1-1, MT2-1, MT3-1, see FIG. 9 and FIG. 12). x It is thought that when an inorganic layer including a ) layer and an amorphous silicon (a-Si) layer is placed, the reflectance of reflected light (RL, RL-1, see FIG. 9 and FIG. 12) can be further reduced.

[0204] The electronic device of the present invention comprises a first conductive pattern in a circuit layer, a second conductive pattern intersecting the first conductive pattern in a planar plane and disposed on the first conductive pattern, and a third conductive pattern covering the first conductive pattern and the second conductive pattern in a planar plane. Since the first to third conductive patterns are disposed to overlap the first electrode of a first light-emitting element, reflected light from the electronic module may pass through the first to third conductive patterns before reaching the lower surface of the first electrode, thereby reducing the amount of light or trapping it between the first to third conductive patterns. Accordingly, the amount of light reflected from the first electrode and incident on the electronic module can be minimized, and the reliability of the electronic module and the reliability of the electronic device can be improved.

[0205] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0206] Display panel 100 Area 1, Area 2, Area 3 DP-A1, DP-A2, DP-A3 Base layer 110 Pixel 1, Pixel 2, Pixel 3 PX1, PX2, PX3 First, second, and third light-emitting elements LD1, LD2, LD3 1st, 2nd, and 3rd pixel circuits PC1, PC2, PC3 1st to 3rd conduction patterns MT1, MT2, MT3 Pixel Definition Film PDL Pixel definition pattern PDP Electronic Module CM Transmission area TA Device area DA

Claims

Claim 1 A display panel comprising: a base layer including a component region; a circuit layer disposed on the base layer; and a light-emitting element layer disposed on the component region and including a first light-emitting element including a first pixel electrode; wherein the circuit layer comprises: a plurality of first conductive patterns, each extending in a first direction; at least one first intermediate insulating layer disposed on the plurality of first conductive patterns; and a plurality of second conductive patterns disposed on the at least one first intermediate insulating layer, each extending in a second direction intersecting the first direction; wherein, on a plane, each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps the same first light-emitting element. Claim 2 In claim 1, the circuit layer further comprises at least one second intermediate insulating layer disposed on the plurality of second conductive patterns and a third conductive pattern disposed on the at least one second intermediate insulating layer, and each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps the third conductive pattern in a planar manner, a display panel. Claim 3 In claim 2, the component region includes a device region that overlaps the first pixel electrode and a transparent region that does not overlap the first pixel electrode, and the plurality of first conductive patterns, the plurality of second conductive patterns, and the third conductive pattern overlap the first pixel electrode and do not overlap the transparent region, forming a display panel. Claim 4 In claim 2, the circuit layer further comprises a barrier layer including an inorganic material disposed on the base layer, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed on the second insulating layer, wherein the at least one first intermediate insulating layer is the buffer layer and the first insulating layer, the at least one second intermediate insulating layer is the second insulating layer, the plurality of first conductive patterns are disposed between the barrier layer and the buffer layer, the plurality of second conductive patterns are disposed between the first insulating layer and the second insulating layer, and the third conductive pattern is disposed between the second insulating layer and the third insulating layer, forming a display panel. Claim 5 In claim 4, the barrier layer comprises at least one of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and an amorphous silicon layer, forming a display panel. Claim 6 In claim 2, the circuit layer further comprises a barrier layer including an inorganic material disposed on the base layer, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer, wherein at least one first intermediate insulating layer is the second insulating layer, the plurality of first conductive patterns are disposed between the first insulating layer and the second insulating layer, and the plurality of second conductive patterns are disposed between the second insulating layer and the third insulating layer, thereby forming a display panel. Claim 7 A display panel according to claim 1, wherein the plurality of first conductive patterns are spaced apart from each other by a first interval along the second direction, and the first interval is from several micrometers to several tens of micrometers. Claim 8 A display panel according to claim 1, wherein the plurality of second conductive patterns are spaced apart from each other by a second interval along the first direction, and the second interval is from several micrometers to several tens of micrometers. Claim 9 In claim 1, the base layer further includes an intermediate region adjacent to the component region, the light-emitting element layer further includes a second light-emitting element including a second pixel electrode disposed in the intermediate region, and the circuit layer further includes a first pixel circuit and a second pixel circuit each disposed in the intermediate region, wherein the first pixel circuit is electrically connected to the first pixel electrode and the second pixel circuit is electrically connected to the second pixel electrode. Claim 10 In claim 9, the base layer further includes a main display area adjacent to the intermediate area, the light-emitting element layer further includes a third light-emitting element including a third pixel electrode disposed in the main display area, the circuit layer further includes a third pixel circuit each disposed in the main display area, and the third pixel circuit is electrically connected to the third pixel electrode. Claim 11 In claim 1, the display panel in which the first direction on the plane is perpendicular to the second direction. Claim 12 A display panel comprising a base layer, a circuit layer disposed on the base layer, and a light-emitting element layer disposed on the circuit layer, wherein the circuit layer comprises: a plurality of first conductive patterns, each extending in a first direction on the base layer; at least one first intermediate insulating layer covering the plurality of first conductive patterns; a plurality of second conductive patterns disposed on the at least one first intermediate insulating layer, each extending in a second direction intersecting the first direction; at least one second intermediate insulating layer covering the plurality of second conductive patterns; and a third conductive pattern disposed on the at least one second intermediate insulating layer; wherein, in a planar plane, each of the plurality of second conductive patterns intersects the plurality of first conductive patterns, and in a planar plane, each of the plurality of first conductive patterns and the plurality of second conductive patterns overlaps the third conductive pattern. Claim 13 In claim 12, the base layer comprises a component region including a device region and a light-transmitting region, the light-emitting device layer comprises a first light-emitting device superimposed on the device region, and the plurality of first conductive patterns, the plurality of first conductive patterns, and a third conductive pattern are a display panel disposed in the device region. Claim 14 In claim 13, the first light-emitting element comprises a first pixel electrode, a pixel defining pattern exposing at least a portion of the first pixel electrode, a light-emitting layer disposed on the first pixel electrode, and a second pixel electrode disposed on the light-emitting layer, wherein each of the first pixel electrode, the pixel defining pattern, and the light-emitting layer overlaps the element area and does not overlap the transparent area, forming a display panel. Claim 15 In claim 13, the base layer further comprises an intermediate region surrounding at least a portion of the component region, the light-emitting element layer further comprises a second light-emitting element disposed in the intermediate region, and the circuit layer further comprises a first pixel circuit disposed in the intermediate region and electrically connected to the first light-emitting element, and a second pixel circuit disposed in the intermediate region and electrically connected to the second light-emitting element. Claim 16 In claim 15, the base layer further comprises a main display area surrounding at least a portion of the intermediate area, the light-emitting element layer further comprises a third light-emitting element disposed in the main display area, and the circuit layer further comprises a third pixel circuit disposed in the main display area and electrically connected to the third light-emitting element. Claim 17 A display panel according to claim 12, wherein the plurality of first conductive patterns are spaced apart from each other by a first interval in the second direction, and the plurality of second conductive patterns are spaced apart from each other by a second interval in the first direction, and the first interval and the second interval are each independently a length of several micrometers or more and less than or equal to several tens of micrometers. Claim 18 An electronic device comprising: a base layer including a component region including a device region and a transmission region; a light-emitting element layer including a first light-emitting element superimposed on the device region in a planar plane; and a circuit layer disposed between the base layer and the light-emitting element layer, the circuit layer including a first conductive pattern, a second conductive pattern, and a third conductive pattern that are insulated from each other, wherein in a planar plane, the second conductive pattern intersects with the first conductive pattern, in a planar plane, the third conductive pattern completely covers the first conductive pattern and the second conductive pattern, and in a planar plane, the first conductive pattern, the second conductive pattern, and the third conductive pattern superimposed on the device region. Claim 19 An electronic device according to claim 18, further comprising an electronic module that overlaps the component area in a plane. Claim 20 An electronic device according to claim 19, wherein the base layer further comprises an intermediate region adjacent to the component region and not overlapping with the electronic module, the light-emitting element layer further comprises a second light-emitting element disposed in the intermediate region, and the circuit layer further comprises a first pixel circuit disposed in the intermediate region and electrically connected to the first light-emitting element and a second pixel circuit disposed in the intermediate region and connected to the second light-emitting element.

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