Lead frame for bonding copper wire and semiconductor package comprising the lead frame

Abstract

According to one aspect of the present invention, a lead frame for copper wire bonding is provided, wherein the lead frame supports a semiconductor chip and comprises copper, the electrical connection between the semiconductor chip and the lead frame is made of a copper wire, and at least one portion of the lead frame to which the copper wire is bonded has a copper plating layer formed in the (111) direction.

Description

Technology Field

[0001] The present invention relates to a lead frame and a semiconductor package. Background Technology

[0002] As trends toward miniaturization, lightweighting, high speed, and high capacity of electronic products advance, the development of semiconductor packages used in electronic products is accelerating.

[0003] A typical semiconductor package includes a semiconductor chip and a lead frame, the semiconductor chip is mounted on the die pads of the lead frame, and the terminals of the semiconductor chip and the leads of the lead frame are electrically connected by wires.

[0004] In that case, the quality of wire bonding has been improved by performing silver plating or plating having a structure such as Ni / Pd / Au on the part of the lead frame to which the wire, typically made of a material such as gold, is connected.

[0005] Published Patent Application No. 2015-0014685 discloses an ultra-thin gold-palladium alloy plating solution for forming a PPF plating layer of a semiconductor lead frame.

[0006] However, if precious metals such as gold and silver are used for plating the lead frame and the wire used for wire bonding is also made of materials such as gold, the manufacturing cost increases, and economic feasibility deteriorates. The problem to be solved

[0007] According to one aspect of the present invention, the main objective is to provide a lead frame and a semiconductor package having an improved structure. means of solving the problem

[0008] According to one aspect of the present invention, a lead frame for copper wire bonding is provided, wherein the lead frame supports a semiconductor chip and comprises copper, the electrical connection between the semiconductor chip and the lead frame is made of a copper wire, and at least one portion of the lead frame to which the copper wire is bonded has a copper plating layer formed in the (111) direction.

[0009] Here, the copper plating layer grown in the direction of (111) may have a nanotwin structure.

[0010] Here, the copper plating layer can be formed by an electrolytic plating process using a current having at least one of the properties of DC, pulse, and reverse pulse.

[0011] Here, the copper plating layer is formed by an electrolytic plating process, and the current density applied during the electrolytic plating process may be 1 ASD to 30 ASD.

[0012] Here, the copper plating layer may include a seed layer.

[0013] Here, the seed layer can be formed using at least one of vacuum sputtering, electroplating, and electroless plating.

[0014] Here, a coating layer is formed to cover the copper plating layer, and the coating layer can be formed using at least one of a silane compound, a thiol compound, a phosphonic compound, or an azole compound.

[0015] Here, the coating layer may have a thickness of 0.1 nm to 20 nm.

[0016] Here, the copper plating layer grown in the (111) direction may have a fraction of at least 1.1 times compared to the copper plating layer grown in the (200) direction or the (220) direction.

[0017] According to another aspect of the present invention, a semiconductor package is provided comprising: a semiconductor chip; a lead frame that supports the semiconductor chip and includes copper; a mold resin that surrounds at least a portion of the semiconductor chip; and a copper wire that performs an electrical connection between the semiconductor chip and the lead frame, wherein at least a portion of the lead frame to which the copper wire is joined has a copper plating layer formed in the (111) direction. Effects of the invention

[0018] A semiconductor package according to one aspect of the present invention can achieve a semiconductor package with high reliability and reduced manufacturing costs by using a copper wire for wire bonding and forming a copper plating layer grown in the (111) direction on a lead frame for bonding with such copper wire. Brief explanation of the drawing

[0019] FIG. 1 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention. FIGS. 2 to 4 are schematic drawings illustrating various embodiments of part A shown in FIG. 1. Specific details for implementing the invention

[0020] Hereinafter, the present invention according to a preferred embodiment will be described in detail with reference to the attached drawings. Furthermore, in this specification and drawings, redundant descriptions are omitted for components having substantially the same configuration by using the same reference numerals, and parts in the drawings may be exaggerated in terms of size, length ratio, etc., to aid understanding.

[0021] The present invention will become clear from the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0022] Meanwhile, the terms used in this specification are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in this specification, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Terms such as "first," "second," etc., may be used to describe various components, but the components should not be limited by these terms. The terms are used solely for the purpose of distinguishing one component from another.

[0023] FIG. 1 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention, and FIGS. 2 to 4 are schematic drawings illustrating various embodiments of part A shown in FIG. 1.

[0024] As illustrated in FIG. 1, a semiconductor package (100) according to one embodiment of the present invention comprises a semiconductor chip (110), a lead frame (120), a mold resin (130), a copper plating layer (140), and a copper wire (150).

[0025] The semiconductor chip (110) has a plurality of terminal portions (110a) on its upper side.

[0026] The lead frame (120) is formed by stamping or etching a base metal material containing copper, wherein copper, copper alloy (C194 Alloy, C7025, C1100, C1020, C192, C19410), etc. can be used as the base metal material.

[0027] The lead frame (120) includes a die pad (121) and a lead (122).

[0028] The die pad (121) is configured to support the semiconductor chip (110) and can be attached to the semiconductor chip (110) using an adhesive material (S), etc.

[0029] A semiconductor chip (110) is placed on a copper plating layer (140) placed on a die pad (121), and an Anti-EBO treatment, such as the application or coating of an Anti-EBO (Anti-epoxy bleed out) material, can be performed on the portion of the die pad (121) where the semiconductor chip (110) is placed.

[0030] Meanwhile, the lead (122) is positioned adjacent to the die pad (121) and consists of an inner lead (122a) and an outer lead (122b).

[0031] The internal lead (122a) is a part placed inside the mold resin (130) and is electrically connected to the terminal part (110a) of the semiconductor chip (110) by a copper wire (150), thereby performing the function of transmitting an electrical signal input to the semiconductor chip (110) or output from the semiconductor chip (110) to the external lead (122b).

[0032] The external lead (122b) is positioned outside the mold resin (130) and extends from the internal lead (122a) to be electrically connected to the circuit pattern of a substrate (not shown) to be mounted thereafter.

[0033] Meanwhile, the terminal portion (110a) of the semiconductor chip (110) and the internal lead (122a) are electrically connected by a copper wire (150), and the copper wire (150) is installed by a wire bonding process.

[0034] The copper wire (150) is made of a material including copper (Cu), copper alloy, etc. That is, the copper wire (150) can be made of a material that includes not only pure copper but also copper and other materials.

[0035] The mold resin (130) surrounds and protects at least a portion of the semiconductor chip (110).

[0036] The mold resin (130) is for encapsulating a semiconductor chip (110), a die pad (121), an internal lead (122a), and a copper wire (150), and comprises an epoxy molding compound containing an epoxy material.

[0037] According to the present embodiment, the mold resin (130) includes an epoxy material, but the present invention is not limited thereto. That is, there are no particular limitations on the material of the mold resin according to the present invention. That is, the material of the mold resin according to the present invention may be made of a material other than epoxy, provided that it has non-conductive properties and can protect the semiconductor chip, etc.

[0038] Meanwhile, the copper plating layer (140) is positioned to cover the entire surface of the die pad (121) and the lead (122).

[0039] The copper plating layer (140) according to the present embodiment is arranged to cover the entire surface of the die pad (121) and the lead (122), but the present invention is not limited thereto. That is, according to the present invention, the copper plating layer (140) can be arranged in various ways, such as being selectively placed only on the part of the lead frame (120) where the copper wire (150) is joined, or being selectively placed only on the front surface of the lead frame (120), and masking techniques such as a chain mask, rubber mask, DFR, EDPR, etc., can be used for such selective placement.

[0040] As shown in FIG. 2, a copper plating layer (140) is formed on the surface of the lead (122), and the copper plating layer (140) grows in the (111) direction and has a nano-twinned structure.

[0041] A copper plating layer (140) grown in the (111) direction may have a high fraction of intensity that is at least 1.1 times greater than that of a copper plating layer grown in the (200) direction or (220) direction.

[0042] The growth of such a copper plating layer (140) can be formed by an electrolytic plating process using a current having at least one of DC, pulse, or reverse pulse properties, and the thickness can be formed to be 0.5㎛ to 20㎛.

[0043] The current density applied during the electroplating process of this embodiment may be 1 ASD to 30 ASD, preferably a current density of 10 ASD or less. When a carbon plating is formed using a high current density of 10 ASD or more, a surface area ratio of S-Ratio 1.3 or more may be achieved.

[0044] In the electroplating process of this embodiment, a rectifier section (on-off ratio) that is not applied in the pulsed current waveform can be set, and the pulsed current can be set to operate in the range from on (1):off (1) ms to on (500):off (500) ms.

[0045] The copper plating electrolyte used in the electroplating process of this embodiment may be a copper sulfate-based solution, and the ratio of Cu:H2SO4 may be configured in the range of 5 to 10:5 to 100. It may include SPS (bis-(3-sulfopropyl) disulfide), etc. as a reduction promoter, and PEG (Polyethylene glycol) and PEI (Polyethylenimine), etc. as inhibitors.

[0046] The electroplating process of this embodiment can be performed using a roll-to-roll continuous production facility, and sheet-type facilities such as strip-to-strip and panel-to-panel can also be used.

[0047] Meanwhile, in the process of forming the copper plating layer (140), an electrolytic degreasing and oxide film removal process can be performed using a sodium hydroxide (NaOH) solution before the plating process, and the oxide on the degreasing surface can be removed with a sulfuric acid (H2SO4) or sodium persulfate solution, and a soft etching process can be applied as needed.

[0048] Meanwhile, as a variation of the present embodiment, the copper plating layer (140) may include a seed layer (140a) as shown in FIG. 3. That is, the seed layer (140a) may be formed first in order to form the copper plating layer (140) on the surface of the lead (122).

[0049] Such a seed layer (140a) can help grow the copper plating layer (140) in the direction of (111).

[0050] The seed layer (140a) can be formed using at least one of vacuum sputtering, electroplating, and electroless plating, and can be configured to include at least one of copper (Cu), cobalt (Co), titanium (Ti), and ruthenium (Ru).

[0051] After forming the seed layer (140a), the remaining portion (140b) of the copper plating layer (140) can be formed by the electrolytic plating method mentioned in the above-described embodiment.

[0052] In addition, as another variation of the present embodiment, an additional coating layer (160) can be formed to cover the copper plating layer (140) formed as shown in FIG. 4.

[0053] The coating layer (160) may be composed of silicon dioxide (SiO2) by coating with a silane compound. The silane compound may be an amino ethoxysilane series such as aminopropyltriethoxysilane (APTES), acrylsilane (MPTMS), or epoxysilane (GPTMS), and the coating of the silane compound may be performed by immersion using a concentration of 0.001 g / L to 10 g / L.

[0054] The coating layer (160) may have a thickness of 0.1 nm to 20 nm, and the formed coating layer (160) prevents surface oxidation, improves the bonding performance between coppers, and also has the function of preventing peeling from the mold resin (130).

[0055] In the case of a variation of the present embodiment, a silane compound was used to form the coating layer (160), but the present invention is not limited thereto. That is, according to the present invention, various organic / inorganic coating layers, such as a self-assembly monolayer (SAM) coating layer using a thiol compound, a phosphonic compound, an azole compound, etc., can be formed to form the coating layer (160).

[0056] In other variations of the present embodiment, the coating layer (160) is formed to cover only the copper plating layer (140), but the present invention is not limited thereto. That is, according to the present invention, the coating layer (160) can be configured to also cover the surface of the copper wire (150).

[0057] Hereinafter, with reference to FIGS. 1 and 2, we will examine the method of manufacturing a semiconductor package (100) according to the present embodiment.

[0058] The manufacturer forms the shape of the lead frame (120) by stamping or etching, and then forms a copper plating layer (140) on the surface of the die pad (121) and the lead (122) using electrolytic plating. The copper plating layer (140) according to the present embodiment is formed on the entire surface of the die pad (121) and the lead (122), but as described above, the copper plating layer (140) may be formed only on a part of the lead (122), that is, the part where the copper wire (150) is joined, or on the front surface of the lead frame (120).

[0059] The formed copper plating layer (140) is grown in the (111) direction, and such a dense growth structure accelerates migration during the wire bonding process with the copper wire (150) to achieve Void Free, while the dense cubic structure prevents diffusion from the raw material of the lead frame (120) and enables direct wire bonding to the copper area of ​​the lead frame containing copper with excellent quality.

[0060] Next, a semiconductor chip (110) is placed on a die pad (121), and the terminal portion (110a) of the semiconductor chip (110) and the copper plating layer (140) are joined and connected with a copper wire (150).

[0061] Next, an encapsulation process is performed using a mold resin (130) to form a semiconductor package (100) as shown in FIG. 1.

[0062] As described above, according to the semiconductor package (100) and lead frame (120) of the present embodiment, a copper plating layer (140) grown in the (111) direction is formed on the surface of the lead frame (120), and a highly reliable wire bonding structure can be realized by performing wire bonding using a copper wire (150) on the copper plating layer (140). In particular, such a wire bonding structure can reduce manufacturing costs by not plating precious metals such as gold or silver in the wire bonding area compared to the prior art.

[0063] Some aspects of the present invention have been described with reference to embodiments illustrated in the accompanying drawings, but this is merely illustrative and will be understood by those skilled in the art that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims. Industrial applicability

[0064] The semiconductor package according to the present embodiment can be applied to the industry that manufactures lead frames and semiconductor packages. Explanation of the symbols

[0065] 100: Semiconductor package 110: Semiconductor chip 120: Lead frame 130: Mold resin 140: Copper plating layer 150: Copper wire 160: Coating layer

Claims

Claim 1 A lead frame that supports a semiconductor chip and includes copper, wherein the electrical connection between the semiconductor chip and the lead frame is made of a copper wire, a seed layer is formed on the lead frame, and a copper plating layer is grown in the (111) direction on the formed seed layer, wherein the copper plating layer grown in the (111) direction has a fraction of at least 1.1 times compared to the copper plating layer grown in the (200) direction or the (220) direction, and the portion of the lead frame where the copper wire is bonded is the portion where the copper plating layer grown in the (111) direction is disposed. Claim 2 A lead frame for copper wire bonding, wherein the copper plating layer grown in the (111) direction has a nanotwin structure. Claim 3 A lead frame for copper wire bonding according to claim 1, wherein the copper plating layer is formed by an electrolytic plating process using a current having at least one of the properties of DC, pulse, and reverse pulse. Claim 4 A lead frame for copper wire bonding according to claim 1, wherein the copper plating layer is formed by an electrolytic plating process, and the current density applied during the electrolytic plating process is 1 ASD to 30 ASD. Claim 5 delete Claim 6 A lead frame for copper wire bonding according to claim 1, wherein the seed layer is formed using at least one of vacuum sputtering, electroplating, and electroless plating. Claim 7 A lead frame for copper wire bonding according to claim 1, wherein a coating layer is formed to cover the copper plating layer, and the coating layer is formed using at least one of a silane compound, a thiol compound, a phosphonic compound, and an azole compound. Claim 8 In claim 7, the lead frame for copper wire bonding, wherein the coating layer has a thickness of 0.1 nm to 20 nm. Claim 9 delete Claim 10 A semiconductor chip; a lead frame that supports the semiconductor chip and includes copper; a mold resin that surrounds at least a portion of the semiconductor chip; a copper wire that performs an electrical connection between the semiconductor chip and the lead frame; and a semiconductor package comprising a seed layer formed on the lead frame and a copper plating layer grown in the (111) direction on the formed seed layer, wherein the copper plating layer grown in the (111) direction has a fraction of at least 1.1 times compared to the copper plating layer grown in the (200) direction or the (220) direction, and the portion of the lead frame where the copper wire is joined is the portion where the copper plating layer grown in the (111) direction is disposed.

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