Semiconductor devices and method for manufacturing semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other perpendicularly on the active region; gate structures extending in a second direction intersecting the active region and the plurality of channel layers on the substrate, each including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on the upper surface of the gate electrode; source / drain regions disposed on the active region at least one side of each of the gate structures and in contact with the plurality of channel layers; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between the source / drain regions adjacent to each other; and contact structures in contact with the source / drain regions on the source / drain regions, wherein the upper surface of the separation structure is disposed at a height lower than the upper surface of the gate capping layer in a direction perpendicular to the upper surface of the substrate.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are underway to develop semiconductor devices including FinFETs with three-dimensional channel structures in order to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved reliability. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other perpendicularly on the active region; gate structures extending in a second direction intersecting the active region and the plurality of channel layers on the substrate, each including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on the upper surface of the gate electrode; source / drain regions disposed on the active region at least one side of each of the gate structures and in contact with the plurality of channel layers; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between the source / drain regions adjacent to each other; and contact structures in contact with the source / drain regions on the source / drain regions, wherein the upper surface of the separation structure may be disposed at a height lower than the upper surface of the gate capping layer in a direction perpendicular to the upper surface of the substrate.

[0008] A semiconductor device according to exemplary embodiments comprises: an active region extending in a first direction on a substrate; gate structures extending in a second direction intersecting the active region on the substrate and including a gate electrode and a gate capping layer disposed on the gate electrode; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between adjacent gate structures and separating the active region; and an upper surface of the separation structure may be disposed at a level between the uppermost surface of the gate structure and the lower surface of the gate structure.

[0009] A method for manufacturing a semiconductor device according to exemplary embodiments may include the steps of: forming a sacrificial gate structure comprising a sacrificial layer on an active region of a substrate; removing the sacrificial layer and forming a gate structure comprising a gate electrode and a first material of a silicon nitride series; forming an intermediate insulating layer on the gate structure, and then forming a separation opening that penetrates at least a portion of the intermediate insulating layer, the gate structure, and the substrate and is disposed between adjacent gate structures; forming a separation pattern within the separation opening that comprises a second material of a silicon nitride series and has a lower hardness or lower density than the gate capping layer; and a planarization process step of removing a portion of the separation pattern and the entire intermediate insulating layer so as to expose the upper surface of the gate capping layer. Effects of the invention

[0011] When forming a separation structure, a contact structure can be stably formed by performing a planarization process after depositing an insulating material within the opening so that the insulating layer on top of the gate structure is completely removed. Accordingly, a semiconductor device with improved reliability can be provided.

[0012] When forming a separation structure, the density or hardness of the gate capping layer of the gate structure and the separation structure are formed differently from each other, so that a contact structure can be stably formed in a subsequent process.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 2 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 3 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 4a and FIGS. 4b are cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIG. 5 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 8 to 24 are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0016] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments.

[0018] FIG. 2 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 2 illustrates cross-sections of the semiconductor device of FIG. 1 taken along cutting lines II' and II-II'. For convenience of explanation, FIG. 1 and FIG. 2 illustrate only the main components of the semiconductor device.

[0019] Referring to FIGS. 1 and 2, a semiconductor device (1000a) may include a substrate (101), an active region (105) on the substrate (101), channel structures (140) including a plurality of channel layers (141, 142, 143) spaced apart perpendicularly from each other on the active region (105), source / drain regions (150) in contact with the plurality of channel layers (141, 142, 143), gate structures (160) extending across the active region (105), contact structures (180) connected to the source / drain regions (150), and a separation structure (200a) between the source / drain regions (150). The gate structure (160) may include a gate dielectric layer (162), a gate electrode (165), gate spacer layers (164), and a gate capping layer (166). The semiconductor device (1000a) may further include a separation spacer layer (168) disposed on the side of the separation structure (200a). However, depending on the embodiment, the separation spacer layer (168) may be omitted. The semiconductor device (1000a) may further include a first insulating layer (184) disposed on the separation structure (200a). The semiconductor device (1000a) may further include device isolation layers (110), internal spacer layers (130), an etch stop layer (185), a second insulating layer (195), and a conductive via (190). The semiconductor device (1000a) may further include a separation insulating layer (132) disposed on both side walls of the separation structure (200a) and a plurality of dummy channel layers (140'').

[0020] A semiconductor device (1000a) may include a plurality of transistors, and a plurality of regions including each of the transistors may be defined. Additionally, a plurality of other regions capable of separating each of the transistors may be defined in the semiconductor device (1000a). For example, in the semiconductor device (1000a), a first transistor region (TR1), a second transistor region (TR2), and a separation region (SR) between the first transistor region (TR1) and the second transistor region (TR2) may be defined on a substrate (101). The first and second transistor regions (TR1, TR2) may each include a channel structure (140) on an active region (105), a gate structure (160) surrounding the channel structure (140), and source / drain regions (150) in contact with the channel structure (140) on the active region (105). The first and second transistor regions (TR1, TR2) may each be NMOS and PMOS regions, or transistor regions of the same type. The separation region (SR) can separate the first transistor region (TR1) and the second transistor region (TR2) from each other in a first direction, e.g., the x direction. The separation region (SR) may include separation spacer layers (168) and a separation structure (200a).

[0021] In the semiconductor device (1000a), the active region (105) has a fin structure, and the gate electrode (165) may be disposed between the active region (105) and the channel structure (140), between a plurality of channel layers (141, 142, 143) of the channel structures (140), and on top of the channel structure (140). Accordingly, the semiconductor device (1000a) may include a gate-all-around type field-effect transistor formed by channel structures (140), source / drain regions (150), and gate structures (160).

[0022] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0023] The device isolation layer (110) can define an active region (105) on the substrate (101). The device isolation layer (110) can be formed, for example, by a shallow trench isolation (STI) process. According to embodiments, the device isolation layer (110) may further include a region that extends deeper and has a step downwards from the substrate (101). The device isolation layer (110) may expose a portion of the upper part of the active region (105). According to embodiments, the device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the active region (105). The device isolation layer (110) may be made of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0024] The active region (105) is defined by the device isolation layer (110) within the substrate (101) and may be positioned to extend in a first direction, e.g., the x-direction. The active region (105) may have a structure protruding from the substrate (101). The top of the active region (105) may be positioned to protrude to a predetermined height from the upper surface of the device isolation layer (110). The active region (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). However, on both sides of the gate structures (160), the active region (105) on the substrate (101) may be partially recessed, and source / drain regions (150) may be positioned on the recessed active region (105). The active region (105) may include impurities or doping regions containing impurities.

[0025] The channel structure (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region (105), for example, in the z-direction, on the active region (105). The first to third channel layers (141, 142, 143) may be spaced apart from the upper surface of the active region (105) while being connected to the source / drain region (150). The first to third channel layers (141, 142, 143) may have a width equal to or similar to that of the active region (105) in the y-direction and a width equal to or similar to that of the gate structure (160) in the x-direction. However, according to the embodiments, the first to third channel layers (141, 142, 143) may have a reduced width such that their sides are located at the bottom of the gate structure (160) in the x direction.

[0026] The first to third channel layers (141, 142, 143) may be made of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first to third channel layers (141, 142, 143) may be made of, for example, the same material as the substrate (101). According to embodiments, the first to third channel layers (141, 142, 143) may include an impurity region located in a region adjacent to the source / drain region (150). The number and shape of the channel layers (141, 142, 143) forming a channel structure (140) may vary in the embodiments. For example, according to embodiments, the channel structure (140) may further include a channel layer disposed on the upper surface of the active region (105).

[0027] Source / drain regions (150) may be disposed on the active region (105) on both sides of the channel structure (140). The source / drain region (150) may be disposed to cover the upper surface of the active region (105) at the sides of each of the first to third channel layers (141, 142, 143) of the channel structure (140) and at the bottom of the source / drain region (150). The source / drain region (150) may be disposed by partially recessing the upper part of the active region (105), but the presence and depth of the recess may vary in the embodiments. The source / drain region (150) may be a semiconductor layer comprising silicon (Si) and may contain impurities of different types and / or concentrations.

[0028] A gate structure (160) may be positioned to extend in one direction, e.g., in the y-direction, intersecting the active region (105) and channel structures (140) on top of the active region (105) and channel structures (140). A channel region of transistors may be formed in the active region (105) and channel structures (140) intersecting the gate structure (160). The gate structure (160) may include a gate electrode (165), a gate dielectric layer (162) between the gate electrode (165) and a plurality of channel layers (141, 142, 143), gate spacer layers (164) on the sides of the gate electrode (165), and a gate capping layer (166) on the upper surface of the gate electrode (165).

[0029] The gate dielectric layer (162) may be positioned between the active region (105) and the gate electrode (165) and between the channel structure (140) and the gate electrode (165), and may be positioned to cover at least some of the faces of the gate electrode (165). For example, the gate dielectric layer (162) may be positioned to surround all faces except the top face of the gate electrode (165). The gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacer layers (164), but is not limited thereto. The gate dielectric layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It can be any one of ), and praseodymium oxide (Pr2O3).

[0030] The gate electrode (165) may be disposed extending above the channel structure (140) and filling between a plurality of channel layers (141, 142, 143) above the active region (105). The gate electrode (165) may be spaced apart from the plurality of channel layers (141, 142, 143) by a gate dielectric layer (162). The gate electrode (165) may include a conductive material and may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The gate electrode (165) may be composed of two or more multilayers.

[0031] A gate capping layer (166) may be disposed on top of a gate electrode (165). The gate capping layer (166) may be disposed to extend along the upper surface of the gate electrode (165) in a second direction, e.g., the y-direction. Sides of the gate capping layer (166) may be surrounded by gate spacer layers (164). The gate capping layer (166) may include a material that is etch-selective with respect to an intermediate insulating layer (183) described with reference to FIGS. 17 through 20. The gate capping layer (166) may include a material that is etch-selective with respect to a first insulating layer (184). The gate capping layer (166) may include a first material of the silicon nitride family. The silicon nitride family material may be, for example, SiN, SiCN, SiON, and SiOCN. The gate capping layer (166) may have at least one of density and hardness higher than the separation structure (200a) described later.

[0032] Gate spacer layers (164) are disposed on both sides of the gate electrode (165) and may extend in a z-direction perpendicular to the upper surface of the substrate (101). Gate spacer layers (164) may be disposed on both sides of the gate electrode (165) and on both sides of the gate capping layer (166). Gate spacer layers (164) may insulate the source / drain regions (150) from the gate electrodes (165). The gate spacer layers (164) may be formed in a multilayer structure according to the embodiments. The gate spacer layers (164) may include at least one of oxide, nitride, oxynitride, and silicon nitride series materials. In an exemplary embodiment, the upper surface of each gate spacer layer (164) may be substantially co-planar with the upper surface of the gate capping layer (166), but is not limited thereto.

[0034] Internal spacer layers (130) may be arranged parallel to the gate electrode (165) between the channel structures (140). The internal spacer layers (130) may be arranged on both sides of the gate structure (140) along a first direction, e.g., the x direction, on the lower surface of each of the first to third channel layers (141, 142, 143). The internal spacer layers (130) may have an outer surface that is substantially co-planar with the outer surface of the first to third channel layers (141, 142, 143). At the bottom of the third channel layer (143), the gate electrode (165) may be electrically separated from the source / drain regions (150) by the internal spacer layers (130). The inner spacer layers (130) may have a shape in which the side facing the gate electrode (165) is rounded inwardly convex toward the gate electrode (165), but is not limited thereto. The inner spacer layers (130) may be made of oxide, nitride, and oxynitride. In other embodiments, the inner spacer layers (130) may be omitted.

[0036] The separation structure (200a) may be positioned on the substrate (101) to extend in a second direction, e.g., the y direction, intersecting the active region (105). The separation structure (200a) may extend in a direction perpendicular to the upper surface of the substrate (101), e.g., the z direction. The separation structure (200a) may be positioned between adjacent source / drain regions (150).

[0037] The isolation structure (200a) may include an insulating material. The isolation structure (200a) may include a second material of the silicon nitride series. For example, the isolation structure (200a) may include at least one of SiN, SiCN, SiON, and SiOCN, but is not limited thereto. The isolation structure (200a) may have at least one of density and hardness lower than that of the gate capping layer (166). The second material of the isolation structure (200a) may have at least one of density and hardness lower than that of the first material of the gate capping layer (166). Since the isolation structure (200a) has a lower density and / or lower hardness than that of the gate capping layer (166), in the planarization process for removing the intermediate insulating layer (183) described with reference to FIG. 20, the upper surface of the isolation structure (200a) may be positioned to have a lower height than the upper surface of the gate capping layer (166) in the vertical direction of the substrate.

[0038] The upper surface of the separation structure (200a) may be positioned at a height level between the upper surface of the gate structure (160) and the lower surface of the gate structure (160). The upper surface of the separation structure (200a) may be located at a height lower than the upper surface of the gate capping layer (166) in the z-direction perpendicular to the upper surface of the substrate (101). The upper surface of the separation structure (200a) may be positioned at a height level between the lower surface of the gate electrode (165) and the upper surface of the gate capping layer (166). The upper surface of the separation structure (200a) may be located at a height lower than the upper surface of the gate spacer layer (164) in the z-direction perpendicular to the upper surface of the substrate (101). The upper surface of the separation structure (200a) may be positioned at a level between the upper surface of the gate capping layer (166) and the lower surface of the gate capping layer (166), but is not limited thereto. For example, the upper surface of the separation structure (200a) may be positioned lower than the lower surface of the gate capping layer (166).

[0039] In exemplary embodiments, the separation structure (200a) may have a slanted side in which the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto. The lower portion of the separation structure (200a) may have a flat surface and may have a convex or pointed shape facing the substrate (101), but is not limited thereto.

[0040] The bottom of the separation structure (200a) may be positioned lower than the bottom of the active region (105) by a predetermined depth. For example, the separation structure (200a) may extend in the z-direction toward the substrate (101) from the top and penetrate the active region (105), and the bottom of the separation structure (200a) may be positioned lower than the bottom of the active region (105). In other exemplary embodiments, the bottom of the separation structure (200a) may be positioned lower than the bottom of the source / drain regions (150) but higher than the bottom of the active region (105), but is not limited thereto.

[0042] The semiconductor device (1000a) may further include a first insulating layer (184) disposed on the upper surface of a separation structure (200a). The first insulating layer (184) may be disposed on the upper surface of the separation structure (200a). The first insulating layer (184) may be disposed between the etch stop layer (185) and the separation structure (200a) in the z-direction. The separation structure (200a) may not be in contact with the etch stop layer (185) and may be disposed spaced apart from the etch stop layer (185). In an exemplary embodiment, a side of the first insulating layer (184) may be in contact with a contact structure (180). The first insulating layer (184) may include an insulating material. For example, the first insulating layer (184) may include an oxide or a compound including silicon.

[0044] The separation spacer layers (168) may be positioned at the same height in the z-direction perpendicular to the upper surface of the substrate (101) as the gate spacer layers (164) and may be disposed on both sides of the separation structure (200a). The separation spacer layers (168) may have the same shape as the gate spacer layers (164) removed by a predetermined width in the x-direction from one side. One side of the separation spacer layers (168) may include a surface inclined with respect to the substrate (101). However, the shape of the separation spacer layers (168) is not limited thereto and may have the same shape as the gate spacer layers (164). In exemplary embodiments, the separation spacer layers (168) may be formed as a multilayer structure. In other embodiments, the separation spacer layers (168) may be omitted.

[0045] The upper surface of the separation spacer layers (168) may be positioned at a height lower than the upper surface of the gate capping layer (166) in the z-direction. The upper surface of the separation spacer layers (168) may be positioned at a height lower than the upper surface of the gate spacer layers (164) in the z-direction. Although the upper surface of the separation spacer layers (168) is depicted as being positioned at substantially the same level as the upper surface of the separation structure (200a) in the z-direction, it is not limited thereto. For example, the upper surface of the separation spacer layers (168) may be positioned at a level higher than the upper surface of the separation structure (200a) and lower than the upper surface of the gate capping layer (166).

[0046] The separation spacer layers (168) may include the same material as the gate spacer layers (164). The separation spacer layers (164) may include at least one of oxide, nitride, oxynitride, and silicon nitride series materials.

[0048] The semiconductor device (1000a) may further include separation insulating layers (132) and a plurality of dummy channel layers (140'') disposed between the separation structure (200a) and the source / drain region (150) in the x direction. Accordingly, the sides of the separation structures (200a) may not come into contact with each side of the adjacent source / drain region (150). On the sides of the separation structure (200a), a portion of the channel structure (140) and a portion of the internal spacer layers (130) that come into contact with the sides facing the separation structure (200a) may be disposed in a residual form. The separation insulating layers (132) may be disposed between each of the plurality of dummy channel layers (141'', 142'', 143'') in the z direction in a residual form of the internal spacer layers (130). The separated insulating layers (132) may contain the same material as the internal spacer layers (130). A plurality of dummy channel layers (140'') may contain the same material as the channel structure (140) in a form in which a part of the channel structure (140) remains.

[0050] The contact structure (180) can be connected to the source / drain region (150) by penetrating the etch stop layer (185) and the second insulating layer (195), and can apply an electrical signal to the source / drain region (150). The contact structure (180) can be placed on the source / drain region (150) as shown in FIG. 1, and, depending on the embodiments, may be placed to have a longer length along the y-direction than the source / drain region (150). The contact structure (180) may have a slanted side such that the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto. The contact structure (180) may extend from the top, for example, below the third channel layer (143). The contact structure (180) may be recessed to a height corresponding to the upper surface of the second channel layer (142), for example, but is not limited thereto. In exemplary embodiments, the contact structure (180) may be positioned to contact along the upper surface of the source / drain region (150) without recessing the source / drain region (150).

[0051] The upper surface of the contact structure (180) may be located at the same height as the upper surface of the gate structure (160) in the z direction, but is not limited thereto. At least one upper surface of the contact structures (180) may be positioned higher than the upper surface of the separation structure (200a) in the z direction. The upper surface of the contact structure (180) may be positioned higher than the separation spacer layers (168) in the z direction.

[0052] The contact structure (180) may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo).

[0054] The etch stop layer (185) may include a material having etch selectivity with respect to the second insulating layer (195). The etch stop layer (185) may be, for example, a dielectric layer or a metal oxide layer. The etch stop layer (185) may include, for example, aluminum oxide, aluminum nitride, aluminum oxynitride, silicon nitride, silicon carbide, or a combination thereof.

[0056] The second insulating layer (195) may include an insulating material. For example, the second insulating layer (195) may include at least one of an oxide, a nitride, and an oxynitride.

[0057] A conductive via (190) may be disposed on a contact structure (180) and electrically connected to the contact structure (180). The conductive via (190) may penetrate an etch stop layer (185) and a second insulating layer (195). The conductive via (190) may have a slanted side such that the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto.

[0059] Next, with reference to FIGS. 3 to 6, a modified embodiment of the semiconductor device of the present invention will be described. Descriptions identical to those described above with reference to FIGS. 1 and 2 will be omitted.

[0061] FIG. 3 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0062] Referring to FIG. 3, unlike the embodiment described above with reference to FIG. 2, the semiconductor device (1000b) is configured such that the separation structure (200b) is positioned between adjacent source / drain regions (150), and the two sides of the separation structure (200b) may each come into contact with the adjacent source / drain regions (150). In an exemplary embodiment, on the sides of the separation structure (200b), a portion of the channel structure (140) and a portion of the internal spacer layers (130) that are in contact with the sides of the source / drain regions (150) facing the separation structure (200b) may not remain. That is, the separation insulating layers (132) and a plurality of dummy channel layers (140'') described with reference to FIG. 2 may not be positioned on the sides of the separation structure (200b).

[0064] FIGS. 4a and FIGS. 4b are cross-sectional views illustrating a semiconductor device according to exemplary embodiments.

[0065] Referring to FIG. 4a, the semiconductor device (1000c) may include contact structures (180a, 180b, 180c, 180d) having different vertical thicknesses in the z direction, which is a vertical direction of the upper surface of the substrate (101).

[0066] In an exemplary embodiment, the contact structures (180a, 180b, 180c, 180d) may include a first contact structure (180a, 180b) and a second contact structure (180c, 180d) having upper surfaces positioned at different levels. In an exemplary embodiment, at least one upper surface of the contact structures (180a, 180b, 180c, 180d) may be positioned at a height lower than the upper surface of the separation structure (200c) in the z-direction. The upper surface of the first contact structures (180a, 180b) may be positioned higher than the upper surface of the separation structure (200c) in the z-direction. The upper surface of the first contact structures (180a, 180b) may be positioned at substantially the same level as the upper surface of the gate structure (160), but is not limited thereto. For example, the upper surface of the first contact structure (180a, 180b) may be positioned at a higher level than the upper surface of the gate structure (160) in the z direction. The upper surface of the first contact structure (180a, 180b) may be positioned at substantially the same level as the upper surface of the gate capping layer (166), but is not limited thereto. The upper surface of the second contact structure (180c, 180d) may be positioned lower than the upper surface of the separation structure (200c) in the z direction. The upper surface of the second contact structure (180c, 180d) may be positioned lower than the upper surface of the gate structure (160) in the z direction. The upper surface of the second contact structure (180c, 180d) may be positioned lower than the upper surface of the gate capping layer (166) in the z direction.

[0067] A second contact structure (180c, 180d) having a top surface positioned at a level lower than the height level of the top surface of the separation structure (200c) may be disposed on both sides of the separation structure (200c). However, even in this case, the second contact structures (180c, 180d) may include a portion having a top surface positioned at substantially the same height as the gate structure (160) or at a level higher than the gate structure (160) in an area not illustrated. A first contact structure (180a) and a second contact structure (180c) having different height levels of top surfaces may be disposed on each side of a gate structure (160), but are not limited thereto. For example, contact structures having top surfaces having substantially the same height level may be disposed on both sides of the gate structure (160). The arrangement and height of the contact structures (180a, 180b, 180c, 180d) may vary depending on the embodiments.

[0068] Each of the first contact structure (180a, 180b) and the second contact structure (180c, 180d) may include portions having different vertical thicknesses in the y direction. That is, the first contact structure (180a, 180b) may include a portion having an upper surface positioned at a lower level than the upper surface of the illustrated first contact structure (180a, 180b) in the y direction. The second contact structure (180c, 180d) may include a portion having an upper surface positioned at a higher or lower height level than the upper surface of the illustrated second contact structure (180c, 180d) in the y direction. For example, at least one of the contact structures (180a, 180b, 180c, 180d) may have a stepped shape or a stepped shape with different height levels of upper surfaces in the y direction, but is not limited thereto.

[0069] The semiconductor device (1000c) may further include a third insulating layer (184a) disposed on the upper surface of the second contact structure (180c, 180d) and the upper surface of the separation structure (200c). In an exemplary embodiment, the third insulating layer (184a) may surround at least a portion of the upper surface and side surface of the separation structure (200c). The third insulating layer (184a) may include an insulating material, for example, an oxide.

[0071] Referring to FIG. 4b, the semiconductor device (1000d) may include contact structures (180e, 180f, 180g, 180h) having different vertical thicknesses in the z direction, which is a vertical direction of the upper surface of the substrate (101).

[0072] In an exemplary embodiment, the contact structures (180e, 180f, 180g, 180h) may include a first contact structure (180e, 180f) and a second contact structure (180g, 180h) having upper surfaces positioned at different levels. In an exemplary embodiment, at least one upper surface of the contact structures (180e, 180f, 180g, 180h) may be positioned at a height lower than the upper surface of the separation structure (200d) in the z-direction. The upper surface of the first contact structure (180e, 180f) may be positioned higher than the upper surface of the separation structure (200d) in the z-direction. The upper surface of the first contact structure (180e, 180f) may be positioned at substantially the same level as the upper surface of the gate structure (160), but is not limited thereto. The upper surface of the first contact structure (180e, 180f) may be positioned at substantially the same level as the upper surface of the gate capping layer (166), but is not limited thereto. The upper surface of the second contact structure (180g, 180h) may be positioned lower than the upper surface of the separation structure (200c) in the z-direction. The upper surface of the second contact structure (180g, 180h) may be positioned lower than the upper surface of the gate structure (160) in the z-direction. The upper surface of the second contact structure (180g, 180h) may be positioned lower than the upper surface of the gate capping layer (166) in the z-direction.

[0073] A second contact structure (180g) having an upper surface positioned at a level lower than the height level of the upper surface of the separation structure (200d) may be disposed on one side of the separation structure (200d). A first contact structure (180f) having an upper surface positioned at a level higher than the height level of the upper surface of the separation structure (200d) may be disposed on the other side of the separation structure (200d). A first contact structure (180e) and a second contact structure (180g) having different height levels of upper surfaces may be disposed on each side of the gate structure (160), but are not limited thereto. However, the placement and height of such contact structures may be varied according to the embodiments.

[0074] Each of the first contact structure (180e, 180f) and the second contact structure (180g, 180h) may include portions having different vertical thicknesses in the y direction. That is, the first contact structure (180e, 180f) may include a portion having an upper surface positioned at a lower level than the upper surface of the illustrated first contact structure (180e, 180f) in the y direction. The second contact structure (180g, 180h) may include a portion having an upper surface positioned at a higher or lower height level than the upper surface of the illustrated second contact structure (180g, 180h) in the y direction. For example, at least one of the contact structures (180e, 180f, 180g, 180h) may have a stepped shape or a stepped shape with different height levels of upper surfaces in the y direction, but is not limited thereto.

[0075] The semiconductor device (1000d) may further include a third insulating layer (184b) disposed on the upper surface of the second contact structure (180g) and the upper surface of the separation structure (200d). In an exemplary embodiment, the third insulating layer (184b) may surround at least a portion of the upper surface and side surface of the separation structure (200d). The third insulating layer (184a) may include an insulating material, for example, an oxide.

[0077] FIG. 5 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0078] Referring to FIG. 5, cross-sections of a semiconductor device (1000e) including a FinFET are illustrated, wherein a gate structure (160) surrounds three sides of an active region (105), for example, the top surface and sides along the y-direction of the active region (105). Unlike the embodiment of FIG. 2, the semiconductor device (1000e) may not include a plurality of channel layers. The semiconductor device (1000e) may include a channel region that is part of the active region (105) and is surrounded by the gate structure (160).

[0079] The separation structure (200e) may penetrate the gate structure (160) and the channel region, and the bottom of the separation structure (200e) may be located below the bottom of the active region (105). The sides of the separation structure (200e) may not come into contact with the sides of the adjacent source / drain regions (150). In another embodiment, the sides of the separation structure (200e) may come into contact with the sides of the adjacent source / drain regions (150). The bottom of the separation structure (200e) may have a flat surface or a convex shape, but is not limited thereto and may have various shapes.

[0081] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0082] Referring to FIG. 6, the width of the active region (105a) and the channel structure (140a) of the semiconductor device (1000f) may differ from that of the embodiment of FIG. 2. The active region (105a) and the channel structure (140a) may have a relatively small width, and accordingly, a plurality of channel layers (141a, 142a, 143a) of the channel structure (140a) may each have a circular or elliptical shape with a small difference between the lengths of the major and minor axes in a cross-section along the y direction.

[0084] Figure 7 is a flowchart illustrating a method for manufacturing a semiconductor device.

[0085] Referring to FIG. 7, a semiconductor device manufacturing method (S1) may include a step of forming a sacrificial gate structure (S10), a step of forming a gate structure (S20), a step of forming a separation opening (S30), a step of depositing a separation pattern within the separation opening (S40), and a planarization process step (S50). In exemplary embodiments, the semiconductor device manufacturing method (S1) may further include a contact structure forming step (S60). In exemplary embodiments, the semiconductor device manufacturing method (S1) may further include a conductive via forming step.

[0086] In the step of forming a sacrificial gate structure (S10), sacrificial gate structures including a sacrificial layer can be formed on the active region of the substrate.

[0087] In the step of forming a sacrificial gate structure (S10), active structures may be formed by removing a portion of a substrate including an active region. Next, sacrificial gate structures having a line shape extending in one direction intersecting the active structures may be formed on the active structures. Each sacrificial gate structure may include sacrificial gate layers and a gate mask pattern layer. The sacrificial gate layers may be patterned using a gate mask pattern layer. The sacrificial gate layers may each be an insulating layer and a conductive layer, but are not limited thereto, and may consist of a single layer. For example, the sacrificial gate layers may include silicon oxide or polysilicon, etc. The gate mask pattern layer may include silicon oxide and / or silicon nitride.

[0089] In the gate structure formation step (S20), the sacrificial layers within the sacrificial gate structure may be removed, and gate structures may be formed by sequentially stacking a gate dielectric layer, a gate electrode comprising a conductive material, and a gate capping layer comprising a silicon nitride-based material. The gate capping layer may include a first silicon nitride-based material. The silicon nitride-based material may be, for example, SiN, SiCN, SiON, and SiOCN.

[0091] In the step of forming a separation opening (S30), after forming an intermediate insulating layer on the gate structure, at least one of the gate structures and at least a portion of the substrate can be removed to form a separation opening disposed between adjacent gate structures and separating the active region of the substrate.

[0093] In the step of forming a separation pattern (S40), a second material of the silicon nitride series may be deposited within the separation opening. In the step of forming a separation pattern (S40), a separation pattern having a lower hardness and / or lower density than the gate capping layer may be formed within the separation opening. In an exemplary embodiment, the separation pattern may be deposited by a deposition method different from the method of depositing the gate capping layer. A portion of the separation pattern may be positioned to penetrate the intermediate insulating layer. The portion of the separation pattern penetrating the intermediate insulating layer may be referred to as a first portion of the separation pattern. The first portion of the separation pattern positioned within the intermediate insulating layer may have a shape in which the width in the x-direction increases as it moves away from the upper surface of the substrate.

[0095] In the planarization process step (S50), a portion of the separation pattern and the entire intermediate insulating layer can be removed so that the upper surface of the gate capping layer is exposed. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, can be performed using a slurry that selectively removes oxides rather than silicon nitride-based materials to expose the upper surface of the gate capping layer. At this time, since the separation pattern has a lower density and / or lower hardness than the gate capping layer, it can be removed together by the planarization process. Accordingly, the first portion of the separation pattern and the entire intermediate insulating layer disposed inside the intermediate insulating layer can be removed together. Since the first portion of the separation pattern, which has a shape of widening width, is removed together, a defect in the formation of a contact hole can be prevented in the subsequent contact structure formation step (S60).

[0096] In the planarization process step (S50), since the density or hardness of the separation pattern is smaller than the density or hardness of the gate capping layer, the separation pattern is removed more than the gate capping layer, so that the upper surface of the separation pattern can be positioned at a lower height than the upper surface of the gate capping layer in a vertical direction on the substrate.

[0098] In the contact structure formation step (S60), a contact structure that is electrically connected by contacting the source / drain region or the gate structure can be formed. After forming a first insulating layer on the gate structure and the separation structure, a through hole can be formed by removing a portion of the first insulating layer and the gate structure. A contact structure can be formed by embedding a conductive material in the through hole. Since the first insulating layer is formed after removing a portion of the separation structure and the entire intermediate insulating layer in the planarization process step (S50), the vertical thickness of the first insulating layer can be formed substantially uniformly. Accordingly, the through hole can be stably formed in the region where the contact structure is to be formed.

[0100] FIGS. 8 through 24 are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 8 through 24 describe an example of a method for manufacturing a semiconductor device of FIG. 2.

[0101] FIGS. 8 to 13 are drawings illustrating an embodiment of the dummy gate structure forming step (S10) described with reference to FIG. 7.

[0102] Referring to FIG. 8, sacrificial layers (120) and channel layers (141, 142, 143) can be alternately stacked on a substrate (101).

[0103] The sacrificial layers (120) may be layers that are replaced by the gate dielectric layer (162) and the gate electrode (165) as shown in FIG. 2 through a subsequent process. The sacrificial layers (120) may be made of a material having etch selectivity with respect to the channel layers (141, 142, 143). The channel layers (141, 142, 143) may include a material different from the sacrificial layers (120). The sacrificial layers (120) and the channel layers (141, 142, 143) may include a semiconductor material including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layers (120) may include silicon germanium (SiGe), and the channel layers (141, 142, 143) may include silicon (Si).

[0104] The sacrificial layers (120) and channel layers (141, 142, 143) can be formed by performing an epitaxial growth process using the substrate (101) as a seed. The number of layers of channel layers (141, 142, 143) alternately stacked with the sacrificial layer (120) can be varied in the embodiments.

[0106] Referring to FIG. 9, active structures can be formed by removing a portion of the substrate (101) and a stacked structure of sacrificial layers (120) and channel layers (141, 142, 143).

[0107] The active structure may include sacrificial layers (120) and channel layers (141, 142, 143) that are alternately stacked, and may further include an active region (105) formed so as to protrude onto the upper surface of the substrate (101) by removing a portion of the substrate (101). The active structures may be formed in a line shape extending in one direction, for example, in the x direction, and may be spaced apart from each other in the y direction.

[0108] In the area where a portion of the substrate (101) has been removed, an insulating material is embedded, and then a recess is formed so that an active region (105) protrudes, thereby forming device isolation layers (110). The upper surface of the device isolation layers (110) may be formed lower than the upper surface of the active region (105).

[0110] Referring to FIG. 10, sacrificial gate structures (170) and gate spacer layers (164) can be formed on the active structures.

[0111] The sacrificial gate structures (170) may be sacrificial structures formed in a region where a gate dielectric layer (162) and a gate electrode (165) are disposed on top of the channel structures (140) through a subsequent process as shown in FIG. 2. The sacrificial gate structure (170) may include first and second sacrificial gate layers (172, 175) and a gate mask pattern layer (176) that are sequentially stacked. The first and second sacrificial gate layers (172, 175) may be patterned using the gate mask pattern layer (176). The first and second sacrificial gate layers (172, 175) may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first and second sacrificial gate layers (172, 175) may be formed as a single layer. For example, the first sacrificial gate layer (172) may include silicon oxide, and the second sacrificial gate layer (175) may include polysilicon. The gate mask pattern layer (176) may comprise silicon oxide and / or silicon nitride. The sacrificial gate structures (170) may have a line shape extending in one direction intersecting the active structures. The sacrificial gate structures (170) may extend in the y direction, for example, and be spaced apart from each other in the x direction.

[0112] Gate spacer layers (164) may be formed on both side walls of the sacrificial gate structures (170). The gate spacer layers (164) may be formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structures (170) and the active structures, and then performing anisotropic etching. The gate spacer layers (164) may include, for example, at least one of oxide, nitride, oxynitride, and silicon nitride series materials.

[0114] Referring to FIG. 11, channel structures (140) can be formed by removing exposed sacrificial layers (120) and channel layers (141, 142, 143) between sacrificial gate structures (170) to form a recess area (RC).

[0115] By using the sacrificial gate structures (170) and gate spacer layers (164) as a mask, the exposed sacrificial layers (120) and channel layers (141, 142, 143) can be removed. By doing so, the channel layers (141, 142, 143) have a limited length along the x-direction and form a channel structure (140). As in the embodiment of FIG. 10b, at the bottom of the sacrificial gate structures (170), the sacrificial layers (120) and channel structure (140) may be partially removed from the sides so that both sides along the x-direction are located at the bottom of the sacrificial gate structures (170) and gate spacer layers (164).

[0117] Referring to FIG. 12, the exposed sacrificial layers (120) can be partially removed from the side.

[0118] The sacrificial layers (120) can be selectively etched with respect to the channel structures (140) by, for example, a wet etching process and removed to a predetermined depth from the side along the x direction. The sacrificial layers (120) may have inwardly concave sides by such side etching. However, the shape of the side of the sacrificial layers (120) is not limited to that shown.

[0120] Referring to FIG. 13, internal spacer layers (130) can be formed in the area where the sacrificial layers (120) have been removed.

[0121] The inner spacer layers (130) can be formed by burying an insulating material in the area where the sacrificial layers (120) have been removed and removing the insulating material deposited on the outside of the channel structures (140). The inner spacer layers (130) may be formed of the same material as the gate spacer layers (164), but are not limited thereto.

[0123] Referring to FIG. 14, source / drain regions (150) can be formed on active regions (105) on both sides of the sacrifice gate structures (170).

[0124] Source / drain regions (150) can be formed by performing an epitaxial growth process. The source / drain regions (150) can be connected laterally to a plurality of channel layers (141, 142, 143) of channel structures (140) and can be in contact with internal spacer layers (130) between the channel layers (141, 142, 143). The source / drain regions (150) may contain impurities by in-drilling doping and may include a plurality of layers having different doping elements and / or doping concentrations.

[0125] As such, the semiconductor device manufacturing method (S1) described with reference to FIG. 7 may further include a source / drain region forming step between the sacrificial gate structure forming step (S10) and the gate structure forming step (S20).

[0127] FIGS. 15 and 16 illustrate an embodiment of the gate structure forming step (S20) described with reference to FIG. 7.

[0128] Referring to FIG. 15, a lower insulating layer (182) can be formed, and the sacrificial layers (120) and sacrificial gate structures (170) can be removed.

[0129] The lower insulating layer (182) can be formed by forming an insulating film covering the sacrificial gate structures (170) and source / drain regions (150) and performing a flattening process.

[0130] The sacrificial layers (120) and sacrificial gate structures (170) can be selectively removed with respect to the gate spacer layers (164), the lower insulating layer (182), and the channel structures (140). First, the sacrificial gate structures (170) can be removed to form upper gap regions (UR), and then the sacrificial layers (120) exposed through the upper gap regions (UR) can be removed to form lower gap regions (LR). For example, if the sacrificial layers (120) contain silicon germanium (SiGe) and the channel structures (140) contain silicon (Si), the sacrificial layers (120) can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source / drain regions (150) can be protected by the lower insulating layer (182) and the internal spacer layers (130).

[0132] Referring to FIG. 16, gate structures (160) can be formed within the upper gap regions (UR) and lower gap regions (LR).

[0133] Gate dielectric layers (162) may be formed to conformally cover the inner surfaces of the upper gap regions (UR) and lower gap regions (LR). Gate electrodes (165) may be formed to completely fill the upper gap regions (UR) and lower gap regions (LR), and then removed from the upper gap regions (UR) to a predetermined depth from the top. A gate capping layer (166) may be formed in the area where the gate electrodes (165) have been removed from the upper gap regions (UR). By doing so, gate structures (160) comprising the gate dielectric layer (162), gate electrodes (165), gate spacer layers (164), and gate capping layer (166) may be formed. In an exemplary embodiment, the gate capping layer (166) may comprise a silicon nitride-based material.

[0134] At least one of the gate structures (160) may be a dummy gate structure (160') from which a portion is removed in a subsequent process. At least one of the channel structures (140) may be a dummy channel structure (140') from which a portion is removed together with the dummy gate structure (160') in a subsequent process, corresponding to the dummy gate structure (160').

[0136] FIG. 17 illustrates an embodiment of the separation opening forming step (S30) described with reference to FIG. 7.

[0137] Referring to FIG. 17, an intermediate insulating layer (183) can be formed on top of the gate structures (160) and the lower insulating layer (182), and a separation opening (T) can be formed that extends below the bottom of the active region (105) through the intermediate insulating layer (183), the dummy gate structure (160'), and the dummy channel structure (140'). Accordingly, a portion of the dummy gate structure (160') and a portion of the dummy channel structure (140') can be removed.

[0138] The intermediate insulating layer (183) may include a material having an etch selectivity with the gate capping layer (166). The intermediate insulating layer (183) may include an oxide or a compound including silicon. For example, the intermediate insulating layer (183) may include TEOS (TetraEthylOrthoSilicate).

[0139] The separation opening (T) may extend in a second direction, for example, in the y-direction, intersecting the active region (105). The separation opening (T) may have a slanted side such that the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio. The lower portion of the separation opening (T) may have a flat surface and may have a convex or pointed shape facing the substrate (101), but is not limited thereto. The lower portion of the separation opening (T) may be positioned lower than the lower portion of the active region (105).

[0140] As the separation opening (T) is formed, a portion of the dummy gate spacer layers (164') of the dummy gate structure (160') is removed, and a portion of the dummy gate spacer layers (164') that are not removed may remain as separation spacer layers (168) on the sides of the separation opening (T).

[0141] As the separation opening (T) is formed, a portion of the dummy channel layers (140') is removed, and the dummy channel layers (140') may remain on the sides of the separation opening (T). In an exemplary embodiment, a portion of the internal spacer layers (130') (see FIG. 16) disposed on both sides of the dummy gate structure (160') may be removed and remain as a separation insulating layer (132).

[0143] FIGS. 18 and 19 illustrate an embodiment of the separation pattern deposition step (S40) described with reference to FIG. 7.

[0144] Referring to FIG. 18, a separation pattern (200P) can be formed to fill the interior of the separation opening (T) and cover the upper part of the intermediate insulating layer (183). The separation pattern (200P) may have a lower density or lower hardness than the gate capping layer (166). The separation pattern (200P) may include a silicon nitride-based material and may have a lower density or lower hardness than the gate capping layer (166). The method of depositing the silicon nitride-based material included in the separation pattern (200P) may differ from the method of depositing the silicon nitride-based material included in the gate capping layer (166).

[0145] Referring to FIG. 19, a flattening process can be performed so that the portion covering the upper part of the intermediate insulating layer (183) of the separation pattern (200P) is removed. Accordingly, the upper surface of the intermediate insulating layer (183) can be exposed.

[0147] FIG. 20 illustrates an embodiment of a flattening process step (S50) described with reference to FIG. 7.

[0148] Referring to FIG. 20, through a Chemical Mechanical Polishing (CMP) process, the entire intermediate insulating layer (183) and a portion of the separation pattern (200P) can be removed to form a separation structure (200a).

[0149] In order to prevent instability in the formation of the contact structure caused by non-uniformity of the thickness of the intermediate insulating layer (183) and separation pattern (200P) placed inside the intermediate insulating layer (183) when forming a subsequent contact structure, a flattening process can be performed to remove the entire intermediate insulating layer (183).

[0150] In an exemplary embodiment, the separation pattern (200P) and the gate capping layer (166) each comprise a silicon nitride-based material, and the intermediate insulating layer (183) may comprise an oxide or a silicon-based compound. Since the density or hardness of the separation pattern (200P) is lower than the density or hardness of the gate capping layer (166), a portion of the separation pattern (200P) may be removed together during the process of removing the intermediate insulating layer (183). Accordingly, a portion of the separation pattern (200P) penetrating the intermediate insulating layer (183) and the entire intermediate insulating layer (183) may be removed together, thereby exposing the upper surface of the gate structure (160) and the upper surface of the lower insulating layer (182). As the planarization process is performed, the upper surface of the gate capping layer (166) may be exposed. In this case, since the density or hardness of the separation pattern (200P) is smaller than the density or hardness of the gate capping layer (166), when performing the planarization process, a separation structure (200a) having an upper surface at a lower level than the upper surface of the gate capping layer (166) can be formed.

[0152] FIGS. 21 to 24 illustrate an embodiment of the contact structure forming step (S60) described with reference to FIG. 7.

[0153] Referring to FIG. 21, a first insulating layer (184) can be formed on the gate structure (160) and the lower insulating layer (182). The first insulating layer (184) may include an oxide or a compound including silicon.

[0154] Referring to FIG. 22, in the area corresponding to the contact structure (180) of FIG. 2, the lower insulating layer (182) and the first insulating layer (184) can be removed to form a penetrating contact hole (H). By performing the flattening process described with reference to FIG. 20, the vertical thickness of the first insulating layer (184) can be formed substantially uniformly, and no separation pattern can exist within the first insulating layer (184). Accordingly, the etching process can be stably performed to remove the area corresponding to the contact structure (180) of FIG. 2, thereby preventing defects in the formation of the contact hole (H).

[0156] Referring to FIGS. 23 and 24, a contact structure (180) can be formed by embedding a conductive material inside a contact hole (H) and performing a flattening process. According to exemplary embodiments, the upper surface of the contact structure (180) may be formed to be positioned at substantially the same level as the upper surface of the gate structure (160), but is not limited thereto.

[0157] Next, after forming the etching stop layer (185) and the second insulating layer (195), a portion of each of the etching stop layer (185) and the second insulating layer (195) can be removed. Next, a conductive material can be embedded in the portion of the etching stop layer (185) and the second insulating layer (195) from which the portion has been removed to form a conductive via (190) that contacts the contact structure.

[0159] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0161] 101: Substrate 105: Active region 110: Device isolation layer 120: Sacrificial layer 130: Internal spacer layer 132: Separating insulation layer 140: Channel structure 140'': Dummy channel layers 141, 142, 143: Channel layer 150: Source / drain region 160: Gate structure 162: Gate dielectric layer 164: Gate spacer layer 165: Gate electrode 166: Gate capping layer 168: Separation spacer layer 170: Sacrifice Gate Structure 183: Intermediate Insulation Layer 184: First insulating layer 180: Contact structure 185: Etching stop layer 195: Second insulating layer 190: Challenging vias

Claims

Claim 1 A semiconductor device comprising: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other and perpendicularly on the active region; gate structures extending in a second direction intersecting the active region and the plurality of channel layers on the substrate, each including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on the upper surface of the gate electrode; source / drain regions disposed on the active region at least one side of each of the gate structures and in contact with the plurality of channel layers; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between the source / drain regions adjacent to each other; a first insulating layer disposed on the upper surface of the separation structure; and contact structures on the source / drain regions that contact the source / drain regions, wherein the upper surface of the separation structure is disposed at a height lower than the upper surface of the gate capping layer and higher than the lower surface of the gate capping layer in a direction perpendicular to the upper surface of the substrate, and the upper surface of the first insulating layer forms a co-plane with the upper surface of the gate structure. Claim 2 A semiconductor device according to claim 1, further comprising: an etch stop layer disposed on the gate structures, the first insulating layer, and the contact structures; a second insulating layer disposed on the etch stop layer; and a conductive via penetrating the second insulating layer and the etch stop layer to contact at least some of the contact structures. Claim 3 A semiconductor device according to claim 2, wherein the separation structure and the etching stop layer are spaced apart from each other. Claim 4 In claim 1, the separation structure is a semiconductor device having at least one of density and hardness smaller than that of the gate capping layer. Claim 5 A semiconductor device according to claim 1, wherein the separation structure and the gate capping layer each comprise a silicon nitride-based material. Claim 6 A semiconductor device according to claim 1, further comprising internal spacer layers disposed on both sides of the gate structure along the first direction on each lower surface of the plurality of channel layers, and having an outer surface that forms a co-plane with the outer surface of the plurality of channel layers. Claim 7 A semiconductor device according to claim 6, further comprising a plurality of dummy channel layers disposed between the separation structure and the source / drain regions and a separation insulating layer disposed between each of the plurality of dummy channel layers, wherein the plurality of dummy channel layers comprise the same material as the plurality of channel layers and the separation insulating layer comprises the same material as the internal spacer layers. Claim 8 A semiconductor device according to claim 1, wherein at least one upper surface of the contact structures is positioned higher than the upper surface of the separation structure in a direction perpendicular to the upper surface of the substrate. Claim 9 A semiconductor device comprising: an active region extending in a first direction on a substrate; gate structures extending in a second direction intersecting the active region on the substrate and including a gate electrode and a gate capping layer disposed on the gate electrode; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between adjacent gate structures and separating the active region; source / drain regions disposed on the active region at least on one side of each of the gate structures; contact structures in contact with each of the source / drain regions; and a first insulating layer disposed on the upper surface of the separation structure, wherein the upper surface of the separation structure is disposed at a level lower than the upper surface of the gate structure and at a level higher than the lower surface of the gate capping layer, the upper surface of the first insulating layer is co-plane with the upper surface of the gate structure and the upper surface of the contact structures, and the upper surface of the source / drain regions is disposed at a level lower than the upper surface of the separation structure. Claim 10 A method for manufacturing a semiconductor device comprising: forming sacrificial gate structures including a sacrificial layer on an active region of a substrate; removing the sacrificial layer and forming gate structures including a gate capping layer each comprising a gate electrode and a first material of the silicon nitride family; forming an intermediate insulating layer on the gate structures, and then forming a separation opening that penetrates the intermediate insulating layer, at least one of the gate structures, and at least a portion of the substrate and is disposed between the gate structures adjacent to each other; forming a separation pattern having a second material of the silicon nitride family within the separation opening and having a hardness or density smaller than that of the gate capping layer; a planarization process step of removing a portion of the separation pattern to form a separation structure so that the upper surface of the gate capping layer is exposed, and removing the entire intermediate insulating layer; and forming a first insulating layer disposed on the upper surface of the separation structure, wherein the upper surface of the separation structure is disposed at a height lower than the upper surface of the gate capping layer and higher than the lower surface of the gate capping layer, and the upper surface of the first insulating layer forms a co-plane with the upper surface of the gate structure.

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