Semiconductor package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a first structure having a first insulating layer and a bonding pad penetrating the first insulating layer on one surface; a second structure having a second insulating layer disposed on the other surface and bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the bonding pad, and a test pad structure penetrating the second insulating layer and bonded to the first surface, wherein the test pad structure comprises: a test pad disposed on the bottom surface of an opening penetrating the second insulating layer; and a bonding layer filling the opening and covering the test pad, wherein the test pad has a protrusion on the surface in contact with the bonding layer, and the protrusion has a flat surface at a higher level than the other surface.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor package. Background Technology

[0003] With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In line with this trend, semiconductor packaging methods that involve stacking multiple semiconductor chips on a single semiconductor substrate or stacking packages on top of each other are becoming increasingly common. As multiple semiconductor chips or packages are stacked in this manner, it is becoming crucial to verify the normal operation of each individual chip or package. To verify the normal operating status of the stacked semiconductor chips or packages, an Electrical Die Sorting Test (EDS) is performed by applying current to the test pads of the chips and packages; however, during this process, the test pads can become deformed, acting as a cause for defects in subsequent processes. The problem to be solved

[0005] The problem to be solved by the present invention is to provide a semiconductor package with improved yield and reliability. means of solving the problem

[0007] One embodiment of the present invention provides a semiconductor package comprising: a first structure having a first insulating layer and a bonding pad penetrating the first insulating layer on one surface; a second structure having a second insulating layer disposed on the other surface and bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the bonding pad, and a test pad structure penetrating the second insulating layer and bonded to the first surface, wherein the test pad structure comprises: a test pad disposed on the bottom surface of an opening penetrating the second insulating layer; and a bonding layer filling the opening and covering the test pad, wherein the test pad has a protrusion on the surface in contact with the bonding layer, and the protrusion has a flat surface at a higher level than the other surface.

[0008] One embodiment of the present invention provides a semiconductor package comprising: a lower structure having an upper insulating layer and an upper bonding pad penetrating the upper insulating layer; a lower insulating layer bonded to the upper insulating layer, a bonding pad structure penetrating the lower insulating layer and bonded to the bonding pad, and a test pad structure penetrating the lower insulating layer and bonded to the upper surface of the upper insulating layer, wherein the test pad structure comprises: a test pad disposed on the bottom surface of an opening penetrating the lower insulating layer; and a bonding layer filling the opening and covering the test pad, wherein the test pad has a thickness smaller than that of the lower insulating layer and has a lower surface at a higher level than that of the lower insulating layer.

[0009] One embodiment of the present invention provides a semiconductor package comprising: a substructure; and a plurality of semiconductor chips on the substructure, wherein the plurality of semiconductor chips include first and second semiconductor chips in direct contact, wherein the first semiconductor chip has a surface having a first insulating layer and a bonding pad penetrating the first insulating layer, and the first semiconductor chip has a other surface bonded to the one surface, a second insulating layer disposed on the other surface and bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the bonding pad, and a test pad structure penetrating the second insulating layer and bonded to the one surface, wherein the test pad structure includes a test pad disposed on the bottom surface of an opening penetrating the second insulating layer; and a bonding layer filling the opening and covering the test pad, wherein the test pad has a thickness smaller than that of the second insulating layer and has a bottom surface at a higher level than that of the second insulating layer. Effects of the invention

[0011] According to embodiments of the present invention, a semiconductor package with improved reliability and yield can be provided by flattening the protrusions on the surface of a test pad and covering them with a bonding layer.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention. Figure 2 is an enlarged view of part 'A' of Figure 1. Figure 3 is an enlarged view of section 'B' of Figure 2. Figures 4 and 5 are variations of the test pad shown in Figure 3. FIG. 6 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention. Figure 7 is an enlarged view of section 'C' of Figure 6. Figure 8 is an enlarged view of section 'D' of Figure 7. Figures 9 and 10 are variations of the test pad shown in Figure 7. FIG. 11 is a process flow diagram illustrating an exemplary example of a method for forming a semiconductor package according to one embodiment of the present invention. FIGS. 12 to 15 are cross-sectional views illustrating exemplary examples of a method for forming a semiconductor package according to one embodiment of the present invention. FIGS. 16 and 17 are cross-sectional views illustrating exemplary examples of a method for forming a semiconductor package according to one embodiment of the present invention. FIGS. 18 and 19 are cross-sectional views illustrating exemplary examples of a method for forming a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention

[0016] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0018] An exemplary example of a semiconductor package according to an embodiment of the present invention is described with reference to FIGS. 1 to 3. FIG. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, FIG. 2 is an enlarged view of portion 'A' of FIG. 1, and FIG. 3 is an enlarged view of portion 'B' of FIG. 2.

[0020] Referring to FIGS. 1 and 2, a semiconductor package (1A) may include a base (10), a substructure (100) coupled to the base (10) by a connecting structure (50) on the base (10), and a plurality of semiconductor chips (200) on the substructure (100). The semiconductor package (1A) may further include a mold layer (300) covering the plurality of semiconductor chips (200).

[0021] The base (10) can be a printed circuit board or a semiconductor chip.

[0022] The substructure (100) may be a plurality of semiconductor chips (200) and other substructure semiconductor chips. However, the technical concept of the present invention is not limited thereto. For example, the substructure (100) may be an interposer substrate.

[0023] A plurality of semiconductor chips (200) may include one or more lower semiconductor chips (200A, 200B, 200C) and an upper semiconductor chip (200D) on one or more lower semiconductor chips (200A, 200B, 200C). The plurality of lower semiconductor chips (200A, 200B, 200C) may have the same shape or the same structure as each other.

[0025] Each of the plurality of semiconductor chips (200) may be a memory semiconductor chip or a logic semiconductor chip. For example, the memory semiconductor chip may be a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory chip such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory), and the logic semiconductor chip may be a microprocessor, an analog device, or a digital signal processor. For example, the semiconductor package (1A) of the present embodiment may be used for HBM (High Bandwidth Memory) products or EDP (Electro Data Processing) products, etc.

[0027] Each of the plurality of semiconductor chips (200) may include a semiconductor body (210), a semiconductor internal circuit region (235) below the semiconductor body (210), a lower insulating layer (250) below the semiconductor internal circuit region (235), a bonding pad structure (BPS-1), and a test pad structure (EPS-1). Each of the lower semiconductor chips (200A, 200B, 200C) among the plurality of semiconductor chips (200) may further include an upper insulating layer (290) and an upper bonding pad (291) on the semiconductor body (210). Each of the lower semiconductor chips (200A, 200B, 200C) among the plurality of semiconductor chips (200) may further include a semiconductor protection insulating layer (270) between the semiconductor body (210) and the upper insulating layer (290).

[0028] Each of the lower semiconductor chips (200A, 200B, 200C) may further include a through electrode structure (220) that penetrates the semiconductor body (210) and electrically connects the upper bonding pad (291) and the semiconductor internal wiring (240). The through electrode structure (220) may include a through electrode (230) formed of a conductive material such as copper and an insulating spacer (225) surrounding the side of the through electrode (230).

[0030] Each of the plurality of semiconductor chips (200) may have a front side (201F) in contact with a semiconductor chip located relatively lower, and a back side (201B) positioned opposite the front side (201F). Each side (201S) of the plurality of semiconductor chips (200) may extend from the edge of the back side (201B) in a direction substantially perpendicular to the back side (201B). Among the semiconductor chips (200), the upper insulating layer (290) of the semiconductor chip located relatively lower, the lower insulating layer (250) of the semiconductor chip located relatively upper, and the test pad structure (EPS-1) may be joined while in contact with each other, and the upper bonding pad (291) of the semiconductor chip located relatively lower and the bonding pad structure (BPS-2) of the semiconductor chip located relatively upper may be joined while in contact with each other. Accordingly, semiconductor chips (200) can be stacked sequentially by being joined with the upper insulating layer (290), the lower insulating layer (250), and the test pad structure (EPS-1) in contact with each other, and by being joined with the semiconductor upper bonding pad (291) and the bonding pad structure (BPS-1) in contact with each other.

[0031] Among the lower semiconductor chips (200A, 200B, 200C), the lowest semiconductor chip (200A) can be bonded while in contact with the lower structure (100). For example, the lower insulating layer (250) and the test pad structure (EPS-1) of the lowest semiconductor chip (200A) can be bonded while in contact with the upper insulating layer (190) of the lower structure (100), and the bonding pad structure (BPS-1) of the lowest semiconductor chip (200A) can be bonded while in contact with the upper pad (195) of the lower structure (100).

[0033] The semiconductor body (210) may be a semiconductor substrate, and the semiconductor internal circuit region (235) may be placed on the front (210F) of each of the plurality of semiconductor chips (200).

[0035] The semiconductor internal circuit region (235) may include a semiconductor internal circuit (215) and a semiconductor internal wiring (240) that electrically connects the semiconductor internal circuit (215) and the bonding pad structure (BPS-1). The semiconductor internal circuit (215) and the semiconductor internal wiring (240) may be disposed within a semiconductor internal insulating layer (245).

[0037] The upper insulating layer (290) and the lower insulating layer (250) can be formed from an insulating material, such as silicon oxide, that can be bonded while in contact with each other. However, the upper insulating layer (290) and the lower insulating layer (250) are not limited to silicon oxide and may be formed from SiCN, etc. According to an embodiment, the lower insulating layer (250) may include a first insulating layer (256) and a second insulating layer (257) (see FIG. 3). For example, the first insulating layer (256) may be formed from TEOS (Tetraethylorthosilicate), and the second insulating layer (257) may be formed from PE-SiN.

[0039] The bonding pad structure (BPS-1) may include a connecting pad (254) and a lower bonding pad (255). The connecting pad (254) connects the semiconductor internal wiring (240) and the lower bonding pad (255) and may be made of a conductive material. For example, the connecting pad (254) may be made of aluminum or an aluminum alloy. The lower bonding pad (255) may be made of the same material as the upper bonding pad (255) so as to be bonded while in direct contact with the upper bonding pad (255). The lower bonding pad (255) may be made of a conductive material. For example, the lower bonding pad (255) may be made of any one of copper, nickel, gold, silver, or an alloy thereof.

[0041] With reference to FIGS. 2 and FIG. 3, a test pad structure (EPS-1) is described. The test pad structure (EPS-1) may include a test pad (251) and a bonding layer (252). An opening (253) penetrating a lower insulating layer (250) may be connected to the lower surface (251B) of the test pad (251). The bonding layer (252) may be filled inside the opening (253) to cover the test pad (251). The test pad (251) is a terminal for performing Electrical Die Sorting (EDS) on each of a plurality of semiconductor chips (200).

[0042] The test pad (251) may be made of a conductive material. According to an embodiment, the test pad (251) may be made of the same material as the connecting pad (254) of the bonding pad structure (BPS-1). For example, the test pad (251) may be made of aluminum or an aluminum alloy. The width of the test pad (251) may be greater than the width of the connecting pad (254) of the bonding pad structure (BPS-1). The lower surface (251B) of the test pad (251) may be formed as a flat surface overall, but in some areas, a concave portion (251C) and a protrusion (251P) formed during the EDS test process may be formed. Additionally, a flat surface (251F) formed by a flattening process may be formed at the end of the protrusion (251P). For example, the flattening process may be a mechanical polishing process or a chemical mechanical polishing process. The flat surface (251F) of the test pad (251) may be located at a higher level than the lower surface (250B) of the lower insulation layer (250). Additionally, the flat surface (251F) of the test pad (251) may be located at a lower level than the lower surface of the connection pad (254).

[0044] The bonding layer (252) may be positioned to cover the lower surface (251B) of the test pad (251) and to fill the opening (253) of the upper insulating layer (290). The bonding layer (252) may be formed of an insulating material that is the same material as the lower insulating layer (250) so that it can be bonded while in contact with the lower insulating layer (250). For example, the bonding layer (252) may be formed of silicon oxide. However, the bonding layer (252) is not limited to silicon oxide and may be formed of SiCN, etc. The lower surface (252B) of the bonding layer (252) may be coplanar with the lower surface (250B) of the lower insulating layer (250).

[0046] The EDS test is a test for determining whether a plurality of semiconductor chips are normal or defective by contacting a probe to each test pad (251) of a plurality of semiconductor chips formed on a wafer and applying a specific current. During the process of contacting the probe to the test pad (251), marks caused by the probe are left on the surface of the test pad (251). The part that came into direct contact with the probe is scratched by the probe to form a concave portion (251C), and a pile-up protrusion (251P) may be formed around the perimeter of the concave portion (251C). The protrusion (251P) is formed with an uneven height and may be formed to have a height greater than the lower surface (250B) of the lower insulating layer (250). Such a protrusion (251P) may cause a step difference on the bonding surface during the process of bonding the semiconductor chips together. To prevent this, a process of flattening the bonding surface is performed. A protrusion (251P) having a height greater than that of the lower surface (250B) of the lower insulating layer (250) is exposed to the bonding surface during the bonding surface flattening process. Since the protrusion (251P) is formed of a conductive material, it can contaminate the chamber where the flattening process is performed.

[0048] In one embodiment, the protrusion (251P) of the test pad (251) is flattened to form a flat surface (251F) having a higher level than the lower surface (250B) of the sub-insulating layer (250), and is covered with a bonding layer (252), so that the protrusion (251P) is prevented from being exposed to the bonding surface during the process of flattening the bonding surface. Therefore, the chamber can be prevented from being contaminated during the process of flattening the bonding surface.

[0050] Next, with reference to FIGS. 4 and FIGS. 5, a modified example of a test pad of a semiconductor package according to an embodiment of the present invention will be described. FIGS. 4 and FIGS. 5 are modified examples of the test pad (251) shown in FIGS. 3. Since the configurations indicated by the same reference numerals as those in the previously described embodiment are identical to those in the previously described embodiment, a detailed description is omitted. In the previously described embodiment, the height of the protrusion was lowered by performing a mechanical polishing process or a chemical mechanical polishing process on the protrusion, whereas in the previously described embodiment, the height of the protrusion (1251P) was lowered by performing a dry etching process or a wet etching process on the test pad (1251). Therefore, in the case of the previously described embodiment, a flat surface may not be formed at the end of the protrusion (1251P).

[0052] Referring to FIG. 4, in one embodiment, a test pad (1251) may have a groove (1251R) formed on the lower surface (1251B) of the test pad (1251), having a side wall (1251S) extending from the side wall of the opening (253) of the lower insulating layer (250). The groove (1251R) may be formed to have a depth (ED1) of about 1 μm or more on the lower surface (1251B) of the test pad (1251). The groove (1251R) may be formed by performing a dry etching process on the lower surface (1251B) of the test pad (1251). Accordingly, a flat surface formed by dry etching may be formed on the bottom surface (1251RB) of the groove (1251R). According to the embodiment, some areas of the bottom surface (1251RB) may retain concave portions (1251C) and protrusions (1251P) that were not removed by dry etching, but similar to the previously described embodiment, the level of the protrusions (1251P) may be located at a higher level than the lower surface (250B) of the lower insulating layer (250). Therefore, in the case of one embodiment, as in the previously described embodiment, the protrusions (1251P) can be prevented from being exposed to the bonding surface. Thus, during the process of flattening the bonding surface, contamination of the chamber can be prevented.

[0054] Referring to FIG. 5, in one embodiment, a test pad (2251) may have a groove (2251R) formed on the lower surface (2251B) of the test pad (2251), having a side wall (2251S) that is laterally etched at the lower side wall of the opening (253) of the lower insulating layer (250). The groove (2251R) may be formed to have a depth (ED2) of about 1 μm or more on the lower surface (2251B) of the test pad (2251). The groove (2251R) may be formed by performing a wet etching process on the lower surface (2251B) of the test pad (2251). Accordingly, a flat surface formed by wet etching may be formed on the lower surface (2251RB) of the groove (2251R). According to the embodiment, some areas of the lower surface (2251RB) of the groove (2251R) may retain a concave portion (2251C) and a protrusion (2251P) that were not removed by wet etching, but similar to the embodiment described above, the level of the protrusion (2251P) may be located at a higher level than the lower surface (250B) of the lower insulating layer (250). Therefore, in the case of one embodiment, as in the embodiment described above, the protrusion (2251P) can be prevented from being exposed to the bonding surface. Thus, during the process of flattening the bonding surface, contamination of the chamber can be prevented.

[0056] Next, a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 6 to 8. FIG. 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, FIG. 7 is an enlarged view of portion 'C' of FIG. 6, and FIG. 8 is an enlarged view of portion 'D' of FIG. 7. Compared to the semiconductor package of FIG. 1, the embodiment has a difference in that the bonding layer (552) is formed of a conductive material, and a dummy bonding pad (592) penetrating the lower insulating layer (550) is further disposed in the region bonded to the bonding layer (552). Since the other configurations are identical to the semiconductor package of FIG. 1 described above, a detailed description is omitted. The 500 series configurations of FIG. 6 to 8 can be understood as corresponding to the 200 series configurations of FIG. 1 to 3, respectively.

[0058] Referring to FIGS. 6 and 7, a semiconductor package (1B) may include a base (10), a substructure (100) coupled to the base (10) by a connecting structure (50) on the base (10), and a plurality of semiconductor chips (500) on the substructure (100). The semiconductor package (1B) may further include a mold layer (300) covering the plurality of semiconductor chips (500).

[0059] A plurality of semiconductor chips (500) may include one or more lower semiconductor chips (500A, 500B, 500C) and an upper semiconductor chip (200D) on one or more lower semiconductor chips (500A, 500B, 500C).

[0060] Each of the plurality of semiconductor chips (500) may include a semiconductor body (510), a semiconductor internal circuit region (535) below the semiconductor body (510), a lower insulating layer (550) below the semiconductor internal circuit region (535), a bonding pad structure (BPS-2), and a test pad structure (EPS-2). Each of the lower semiconductor chips (500A, 500B, 500C) among the plurality of semiconductor chips (500) may further include an upper insulating layer (590), an upper bonding pad (591), and a dummy bonding pad (592) on the semiconductor body (510).

[0062] A dummy bonding pad (592) may be positioned to correspond to an area that is bonded to the bonding layer (552) of the test pad structure (EPS-2). The dummy bonding pad (592) may be made of the same material as the bonding layer (552) so as to be bonded while in direct contact with the bonding layer (552) made of a conductive material. The dummy bonding pad (592) may be made of a conductive material. For example, the dummy bonding pad (592) may be made of copper, nickel, gold, silver, or an alloy thereof.

[0063] Each of the lower semiconductor chips (500A, 500B, 500C) among the plurality of semiconductor chips (500) may further include a semiconductor protective insulating layer (570) between the semiconductor body (510) and the upper insulating layer (590).

[0064] Among the semiconductor chips (500), the upper insulating layer (590) of the semiconductor chip located relatively lower and the lower insulating layer (550) of the semiconductor chip located relatively upper can be joined by contacting each other, the dummy bonding pad (592) of the semiconductor chip located relatively lower and the test pad structure (EPS-2) of the semiconductor chip located relatively upper can be joined by contacting each other, and the upper bonding pad (591) of the semiconductor chip located relatively lower and the bonding pad structure (BPS-2) of the semiconductor chip located relatively upper can be joined by contacting each other. Accordingly, the semiconductor chips (500) can be stacked sequentially by the upper insulating layer (590) and the lower insulating layer (550) being joined by contacting each other, the dummy bonding pad (592) and the test pad structure (EPS-2) being joined by contacting each other, and the upper bonding pad (591) and the bonding pad structure (BPS-2) being joined by contacting each other.

[0066] Referring to FIG. 8, the test pad structure (EPS-2) may include a test pad (551) and a bonding layer (552). An opening (553) penetrating a lower insulating layer (550) may be connected to the lower surface (551B) of the test pad (551). The bonding layer (552) may be filled inside the opening (553) to cover the test pad (551).

[0067] The test pad (551) may be made of a conductive material. According to an embodiment, the test pad (551) may be made of the same material as the connecting pad (554) of the bonding pad structure (BPS-1). For example, the test pad (551) may be made of aluminum or an aluminum alloy. The lower surface (551B) of the test pad (551) may be formed as a flat surface overall, but a concave portion (551C) and a protrusion (551P) formed during the EDS test process may be formed in some areas. Similar to the protrusion of FIG. 1 described above, a flat surface (551F) formed by a flattening process may be formed at the end of the protrusion (551P), and the flattening process may be a mechanical polishing process or a chemical mechanical polishing process. Since the protrusion (551P) has the same configuration as the protrusion of FIG. 1 described above, a detailed description is omitted.

[0069] The bonding layer (552) can be positioned to cover the lower surface (551B) of the test pad (551) and to fill the opening (553) of the upper insulating layer (550). The bonding layer (552) can be formed of a conductive material that is the same material as the dummy bonding pad (592) so that it can be bonded while in contact with the dummy bonding pad (592). For example, the bonding layer (552) can be made of any one of copper, nickel, gold, silver, or an alloy thereof. In this way, since the bonding layer (552) is made of the same conductive material as the dummy bonding pad (592), it can have a higher conductivity compared to the case where the bonding layer (552) is made of an insulating material. Thus, the heat generation efficiency of the semiconductor package (1B) can be further improved.

[0071] Next, with reference to FIGS. 9 and FIGS. 10, a modified example of a test pad of a semiconductor package according to an embodiment of the present invention will be described. FIGS. 9 and FIGS. 10 are modified examples of the test pad (251) shown in FIGS. 7. FIGS. 9 and FIGS. 10 are modified examples of the test pad (251) shown in FIGS. 4 and FIGS. 5, respectively. Since configurations indicated by the same reference numerals as those in the previously described embodiment are identical to those in the previously described embodiment, a detailed description is omitted. In the embodiment of FIGS. 4 and FIGS. 5, the bonding layer is formed of an insulating material and is bonded while in contact with a lower insulating layer. On the other hand, in the embodiment of FIGS. 9 and FIGS. 10, the bonding layer is formed of a conductive material and is bonded while in contact with a dummy bonding pad.

[0073] Referring to FIG. 9, in one embodiment, a test pad (1551) may have a groove (1551R) formed on the lower surface (1551B) of the test pad (1551), having a side wall (1551S) extending from the side wall of the opening (1553) of the lower insulating layer (1550). The groove (1551R) may be formed by performing a dry etching process on the lower surface (1551B) of the test pad (1551). Accordingly, a flat surface formed by dry etching may be formed on the bottom surface (1551RB) of the groove (1551R). According to the embodiment, some areas of the bottom surface (1551RB) may retain a recess (1551C) and a protrusion (1551P) that were not removed by dry etching, but similar to the previously described embodiment, the level of the protrusion (1551P) may be located at a higher level than the bottom surface (1550B) of the lower insulating layer (1550). Therefore, in the case of one embodiment, as in the previously described embodiment, the protrusion (1551P) can be prevented from being exposed to the bonding surface. Thus, contamination of the chamber can be prevented during the process of flattening the bonding surface. In addition, the bonding layer (1552) is made of the same conductive material as the dummy bonding pad (1592), so that it may have higher conductivity compared to the case where the bonding layer (1552) is made of an insulating material. Therefore, the heat generation efficiency of the semiconductor package (1B) can be further improved.

[0075] Referring to FIG. 10, in one embodiment, a test pad (2551) may have a groove (2551R) disposed on the lower surface (2551B) of the test pad (2551), having a side wall (2551S) that is laterally etched at the lower side wall of the opening (2553) of the lower insulating layer (2550). The groove (2551R) may be formed by performing a wet etching process on the lower surface (2551B) of the test pad (2551). Accordingly, a flat surface formed by wet etching may be formed on the lower surface (2551RB) of the groove (2551R). According to the embodiment, some areas of the lower surface (2551RB) of the groove (2551R) may retain a concave portion (2551C) and a protrusion (2551P) that were not removed by wet etching, but similar to the embodiment described above, the level of the protrusion (2551P) may be located at a higher level than the lower surface (2550B) of the lower insulating layer (2550). Therefore, in the case of one embodiment, as in the embodiment described above, the protrusion (2551P) may be prevented from being exposed to the bonding surface. Thus, contamination of the chamber during the process of flattening the bonding surface may be prevented. In addition, the bonding layer (2552) is made of the same conductive material as the dummy bonding pad (2592), so it may have higher conductivity compared to the case where the bonding layer (2592) is made of an insulating material. Therefore, the heat generation efficiency of the semiconductor package (1B) can be further improved.

[0077] Next, referring to FIGS. 11 to 15, a method for forming a semiconductor package according to an embodiment of the present invention will be described. FIG. 11 is a process flow diagram showing an exemplary example of a method for forming a semiconductor package according to an embodiment of the present invention, and FIGS. 12 to 15 are cross-sectional views showing exemplary examples of a method for forming a semiconductor package according to an embodiment of the present invention.

[0079] Referring to FIG. 12, a wafer (W) having a plurality of semiconductor chips formed on the upper surface of a chuck (2) can be placed on the upper surface of the chuck (2), and a probe (4) can be brought into contact with each test pad (251) exposed on the bottom surface of an opening (253) formed in the lower insulating layer (250) of the plurality of semiconductor chips to perform an EDS test. The upper surface (250US) of the lower insulating layer (250) may be the front surface (201F) of the embodiment of FIG. 2. A concave portion (251C), which is a scratch mark made by the probe (4), may be formed in the area of ​​the surface of the test pad (251) that is in direct contact with the probe (4). Additionally, a protruding portion (251P) formed by the test pad (251) may be formed around the concave portion (251C). The protruding portion (251P) may be formed with a height (H1) greater than that of the upper surface (250US) of the lower insulating layer (250).

[0081] Referring to FIGS. 11 and 13, the protrusion (251P) of the test pad (251) can be flattened through the opening (253) (S10). The flattening of the protrusion (251P) can be performed through a mechanical polishing process or a chemical mechanical polishing process. During the process of flattening the protrusion (251P), the end of the protrusion (251P) may be polished to form a flat surface (251F). After the flattening process is completed, a cleaning process may be performed to clean the inside of the opening (253). The flattening process may be performed until the flat surface (251F) is lowered by at least about 1 μm from the upper surface (250US) of the lower insulating layer (250), when the thickness of the test pad (251) is about 2 to 3 μm and the height (H3) of the opening (253) is about 3 to 4 μm. Accordingly, the flat surface (251F) may have a height difference (H2) of at least about 1 μm or more with the upper surface (250US) of the lower insulating layer (250). However, it is not limited to this, and it is sufficient to polish only to a height such that the end of the protrusion (251P) is not exposed during the process of flattening the bonding layer filled in the opening (253) in a subsequent process. When applying a chemical mechanical polishing process, a slurry with a high selectivity ratio for the conductive material can be used to selectively polish the protrusion (251P) made of the conductive material while minimizing polishing of the lower insulating layer (250).

[0083] Referring to FIGS. 11 and 14, a bonding layer (252) can be formed to cover the upper surface (250US) of the lower insulating layer (250) and the test pad (251) within the opening (253) (S20). The bonding layer (252) can be formed by depositing an insulating material or a conductive material. For example, the insulating material may be at least one of silicon oxide and SiCN, and the conductive material may be any one of copper, nickel, gold, silver, or an alloy thereof.

[0085] Referring to FIGS. 11 and FIGS. 15, the bonding layer (252) can be flattened (S30). The flattening of the bonding layer (252) can be performed through a chemical mechanical polishing process. The flattening process can be performed until the lower insulating layer (250) is exposed. Afterward, the wafer (W) can be cut into individual semiconductor chips to separate them into multiple semiconductor chips, and the separated multiple semiconductor chips can be stacked to manufacture a semiconductor package.

[0087] Referring to FIGS. 16 and 17, a method for forming a semiconductor package according to an embodiment of the present invention will be described. FIGS. 16 and 17 can be understood as a subsequent process of FIG. 12 of the previously described embodiment.

[0088] Referring to FIG. 16, the protrusion (1251P) of the test pad (1251) can be flattened through the opening (253). The flattening of the protrusion (1251P) can be performed through a dry etching process (E1). After the flattening process is completed, a cleaning process can be performed to clean the inside of the opening (253). When the dry etching process (E1) is performed, the upper surface of the test pad (1251) is anisotropically etched in a vertical direction, so that a groove (1251R) can be formed on the upper surface of the test pad (1251). In this process, the surface of the protrusion (1251P) is also anisotropically etched, so the height of the protrusion (1251P) can be reduced. The dry etching process can be performed until the end of the protrusion (1251P) is lowered by at least about 1 μm from the upper surface (250US) of the lower insulating layer (250), when the thickness of the test pad is about 2 to 3 μm and the height of the opening (253) is about 3 to 4 μm. However, it is not limited to this, and it is sufficient to etch only to a height such that the end of the protrusion (1251P) is not exposed during the subsequent process of flattening the bonding layer filled in the opening (253).

[0090] Referring to FIG. 17, a bonding layer (1252) can be formed to cover the upper surface of the test pad (1251) within the opening (253) and the lower insulating layer (250). The bonding layer (1252) can be formed by depositing an insulating material or a conductive material. For example, the insulating material may be at least one of silicon oxide and SiCN, and the conductive material may be any one of copper, nickel, gold, silver, or an alloy thereof. Subsequently, the process and subsequent processes shown in FIG. 15 can be performed to manufacture a semiconductor package.

[0092] Referring to FIGS. 18 and 19, a method for forming a semiconductor package according to an embodiment of the present invention will be described. FIGS. 18 and 19 can be understood as a subsequent process of FIG. 12 of the previously described embodiment.

[0093] Referring to FIG. 18, the protrusion (2251P) of the test pad (2251) can be flattened through the opening (253). The flattening of the protrusion (2251P) can be performed through a wet etching process (E2). After the flattening process is completed, a cleaning process can be performed to clean the inside of the opening (253). When the wet etching process (E2) is performed, the upper surface of the test pad (2251) is isotropically etched, and a groove (2251R) having a side wall (2251S) that is laterally etched can be formed at the lower side wall of the opening (253) of the lower insulating layer (250). In this process, the surface of the protrusion (2251P) is also isotropically etched, so the height of the protrusion (2251P) can be reduced. When the thickness of the test pad is about 2 to 3 μm and the height of the opening (253) is about 3 to 4 μm, the wet etching process can be performed until the end of the protrusion (2251P) is lowered by at least about 1 μm from the upper surface (250US) of the lower insulating layer (250). However, it is not limited to this, and it is sufficient to etch only to a height such that the end of the protrusion (2251P) is not exposed during the subsequent process of flattening the bonding layer filled in the opening (253).

[0095] Referring to FIG. 19, a bonding layer (2252L) can be formed to cover the upper surface of the test pad (2251) and the lower insulating layer (250) within the opening (253). The bonding layer (2252L) can be formed by depositing an insulating material or a conductive material. For example, the insulating material may be at least one of silicon oxide and SiCN, and the conductive material may be any one of copper, nickel, gold, silver, or an alloy thereof. Subsequently, the process and subsequent processes shown in FIG. 15 can be performed to manufacture a semiconductor package.

[0097] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0099] 1A, 1B Semiconductor Package 10: Base 100: Substructure 200, 500: Semiconductor chip 250: Lower insulation layer 251: Test pad 252: Bonding layer 254: Connection pad 255: Lower bonding pad 290: Upper insulation layer 291: Upper bonding pad BPS-1, BSP-2: Bonding pad structure EPS-1, EPS-2: Test pad structures

Claims

Claim 1 A semiconductor package comprising: a first structure having a first insulating layer and a bonding pad penetrating the first insulating layer on one surface; a second structure having a second insulating layer disposed on the other surface and bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the bonding pad, and a test pad structure penetrating the second insulating layer and bonded to the one surface of the first structure, wherein the test pad structure comprises: a test pad disposed within an opening penetrating the second insulating layer; and a bonding layer filling the opening and covering the lower surface of the test pad, wherein the test pad has a protrusion on the surface in contact with the bonding layer, and the protrusion has a flat surface at a higher level than the other surface of the second structure. Claim 2 A semiconductor package according to claim 1, wherein the bonding layer comprises the same material as the first insulating layer. Claim 3 A semiconductor package according to claim 1, wherein the first structure further comprises a dummy bonding pad that is disposed penetrating the first insulating layer at a position corresponding to the bonding pad structure and includes the same material as the bonding pad. Claim 4 In paragraph 3, the dummy bonding pad comprises the same material as the bonding layer and is bonded to the bonding layer in a semiconductor package. Claim 5 In claim 1, the test pad is made of a material different from the bonding layer, and the test pad is made of a material including aluminum (Al) in a semiconductor package. Claim 6 A semiconductor package according to claim 1, wherein the bonding pad structure further comprises: a lower bonding pad forming the other surface; and a connecting pad disposed on the upper portion of the lower bonding pad. Claim 7 In claim 6, the connection pad is a semiconductor package comprising the same material as the test pad. Claim 8 In claim 6, the semiconductor package in which the width of the test pad is larger than the width of the connection pad. Claim 9 In claim 6, the flat surface of the protrusion has a lower level than the lower surface of the connection pad in a semiconductor package. Claim 10 A semiconductor package according to claim 1, wherein the test pad is contacted by a probe that supplies current in an Electrical Die Sorting Test of the second structure, and the protrusion is an area where the surface of the test pad is piled up by contact with the probe. Claim 11 In claim 1, the second structure comprises a semiconductor body and a semiconductor internal circuit region below the semiconductor body, and the second insulating layer, the bonding pad structure, and the test pad structure are disposed below the semiconductor internal circuit region in a semiconductor package. Claim 12 A semiconductor package according to claim 1, wherein the second structure further comprises a semiconductor body and a through electrode that penetrates the semiconductor body and is electrically connected to the bonding pad. Claim 13 A semiconductor package comprising: a lower structure having an upper insulating layer and an upper bonding pad penetrating the upper insulating layer; an upper structure having a lower insulating layer bonded to the upper insulating layer, a bonding pad structure penetrating the lower insulating layer and bonded to the bonding pad, and a test pad structure penetrating the lower insulating layer and bonded to the upper surface of the upper insulating layer, wherein the test pad structure comprises: a test pad disposed within an opening penetrating the lower insulating layer; and a bonding layer filling the opening and covering the lower surface of the test pad, wherein the test pad has a thickness smaller than that of the lower insulating layer, and the lower surface of the test pad is disposed at a higher level than that of the lower insulating layer. Claim 14 A semiconductor package according to claim 13, wherein the lower surface of the test pad has a protrusion, and a flat surface is disposed at the end of the protrusion. Claim 15 In claim 13, the lower surface of the test pad has a groove portion disposed therein having a side wall extending from the side wall of the opening of the lower insulating layer. Claim 16 In claim 13, the lower surface of the test pad extends from the side wall of the opening of the lower insulating layer and a laterally etched groove is disposed at the side wall of the opening in the semiconductor package. Claim 17 delete Claim 18 A semiconductor package according to claim 13, wherein the lower structure further comprises a dummy bonding pad that is disposed penetrating the upper insulating layer at a position corresponding to the bonding pad structure and comprises the same material as the bonding pad. Claim 19 In claim 18, the dummy bonding pad comprises the same material as the bonding layer and is bonded to the semiconductor package. Claim 20 A semiconductor package comprising: a substructure; and a plurality of semiconductor chips on the substructure, wherein the plurality of semiconductor chips include first and second semiconductor chips in direct contact, wherein the first semiconductor chip has a surface having a first insulating layer and a bonding pad penetrating the first insulating layer, and the second semiconductor chip has a surface bonded to the surface, wherein the second insulating layer disposed on the surface bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the bonding pad, and a test pad structure penetrating the second insulating layer and bonded to the surface, wherein the test pad structure includes a test pad disposed on the bottom surface of an opening penetrating the second insulating layer; and a bonding layer filling the opening and covering the test pad, wherein the test pad has a thickness smaller than that of the second insulating layer and has a bottom surface at a higher level than that of the second insulating layer.

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