Display device

Abstract

A display device according to one embodiment comprises a substrate, a first partition portion disposed on the substrate and extending in one direction, second partition portions adjacent to each other with the first partition portion in between, and connecting portions connecting the first partition portion and the second partition portions, a first electrode disposed on the first partition portion, a second electrode disposed on any one of the second partition portions, and a third electrode disposed on another of the second partition portions, a first insulating layer disposed on the partition, the first electrode, the second electrode, and the third electrode, and light-emitting elements disposed between the first electrode and the second electrode and between the first electrode and the third electrode, wherein at least one of the first electrode, the second electrode, and the third electrode includes a protrusion protruding toward another electrode adjacent in a planar direction, and the first insulating layer may include an opening that exposes the protrusion.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] A device for displaying images of a display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, as a light-emitting display panel, it may include a light-emitting element; for example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as light-emitting materials and inorganic light-emitting diodes that use inorganic materials as light-emitting materials. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of improving the brightness of a subpixel by minimizing the light-emitting elements placed in the non-light-emitting region within the subpixel.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a substrate, a first partition portion disposed on the substrate and extending in one direction, second partition portions adjacent to each other with the first partition portion in between, and connecting portions connecting the first partition portion and the second partition portions, a first electrode disposed on the first partition portion, a second electrode disposed on any one of the second partition portions, and a third electrode disposed on another of the second partition portions, a first insulating layer disposed on the partition, the first electrode, the second electrode, and the third electrode, and light-emitting elements disposed between the first electrode and the second electrode and between the first electrode and the third electrode, wherein at least one of the first electrode, the second electrode, and the third electrode includes a protrusion protruding toward another electrode adjacent in a planar direction, and the first insulating layer may include an opening that exposes the protrusion.

[0007] The above connecting parts extend in another direction intersecting the above one direction and can be formed integrally with the first bulkhead part and the second bulkhead part.

[0008] The above connecting portions may include a first connecting portion connecting the second partition portion and the first partition portion disposed on one side of the first partition portion, and a second connecting portion connecting the second partition portion and the first partition portion disposed on the other side of the first partition portion.

[0009] The first connecting part and the second connecting part are spaced apart from each other with the first partition part in between, and can be aligned with each other in the other direction intersecting the one direction.

[0010] The above protrusion may include a first protrusion protruding from the second electrode toward the first electrode and a second protrusion protruding from the third electrode toward the first electrode.

[0011] The first protrusion may overlap with the first connecting part, and the second protrusion may overlap with the second connecting part.

[0012] The first electrode includes relatively narrow concave portions, and the concave portions may include a first concave portion corresponding to the first protrusion and a second concave portion corresponding to the second protrusion.

[0013] The end of the first protrusion may be disposed within the first concave portion in a planar shape, and the end of the second protrusion may be disposed within the second concave portion in a planar shape.

[0014] The above protrusion may include a first protrusion protruding from the first electrode toward the second electrode and a second protrusion protruding from the third electrode toward the first electrode.

[0015] The first electrode includes a first concave portion with a relatively narrow width, the first concave portion corresponds to the second protrusion, and the end of the second protrusion may be disposed within the first concave portion in a planar manner.

[0016] The above protrusion may include a first protrusion protruding from the first electrode toward the third electrode and a second protrusion protruding from the second electrode toward the first electrode.

[0017] The first electrode includes a first concave portion with a relatively narrow width, the first concave portion corresponds to the second protrusion, and the end of the second protrusion may be disposed within the first concave portion in a planar manner.

[0018] The above protrusion may include a first protrusion protruding from the first electrode toward the second electrode and a second protrusion protruding from the first electrode toward the second electrode.

[0019] Additionally, a display device according to one embodiment comprises a substrate, a first partition portion extending in one direction disposed on the substrate, a partition including second partition portions spaced apart from each other with the first partition portion in between, a first electrode disposed on the first partition portion, a second electrode disposed on any one of the second partition portions, and a third electrode disposed on the other of the second partition portions, a first insulating layer disposed on the partition, the first electrode, the second electrode, and the third electrode, light-emitting elements disposed between the first electrode and the second electrode and between the first electrode and the third electrode, and a via layer disposed between the substrate and the partition and including a via protrusion protruding toward the first insulating layer, wherein at least one of the first electrode, the second electrode, and the third electrode includes a protrusion protruding toward another electrode adjacent in a planar direction, and the first insulating layer may include an opening that exposes the protrusion.

[0020] The above via protrusion extends in another direction intersecting the above one direction and can be formed integrally with the above via layer.

[0021] The above via protrusion overlaps with the above protrusion, and the extension direction of the above via protrusion and the above protrusion may be parallel.

[0022] The first electrode includes a relatively narrow concave portion in an area corresponding to the protrusion, and the opening may overlap with the concave portion, the protrusion, and the via protrusion.

[0023] At the above opening, the upper surface of the first insulating layer can be aligned and matched with the upper surfaces of the second electrode and the third electrode.

[0024] It further includes a bank layer disposed on the first insulating layer and separating the light-emitting region, wherein the via protrusion, the protrusion and the opening may be disposed within the light-emitting region.

[0025] The light-emitting elements include a first light-emitting element and a second light-emitting element disposed between the first electrode and the second electrode, and a third light-emitting element and a fourth light-emitting element disposed between the first electrode and the third electrode, and may further include a first connecting electrode in contact with one end of the first light-emitting element, a second connecting electrode in contact with the other end of the first light-emitting element and one end of the second light-emitting element, a third connecting electrode in contact with the other end of the second light-emitting element and one end of the third light-emitting element, a fourth connecting electrode in contact with the other end of the third light-emitting element and one end of the fourth light-emitting element, and a fifth connecting electrode in contact with the other end of the fourth light-emitting element.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] According to the display device of the embodiments, the number of non-luminous light-emitting elements can be reduced by preventing ink from being applied to the center of the light-emitting region. Accordingly, the brightness of the subpixel can be improved by increasing the number of effective light-emitting elements.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is an equivalent circuit diagram of a subpixel of a display device according to one embodiment. FIG. 3 is a plan view showing one subpixel of a display device according to one embodiment. Figure 4 is a plan view schematically showing the electrodes and partitions of one subpixel of Figure 3. FIG. 5 is a cross-sectional view taken along the line Q1-Q1' of FIG. 3. FIG. 6 is a cross-sectional view taken along the line Q2-Q2' of FIG. 4. Figure 7 is a cross-sectional view taken along the line Q3-Q3' of Figure 4. Figure 8 is another cross-sectional view taken along the line Q2-Q2' of Figure 4. Figure 9 is another cross-sectional view taken along the line Q3-Q3' of Figure 4. FIG. 10 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 11 is a plan view showing a portion of a subpixel area of ​​a display device according to another embodiment. FIG. 12 is a cross-sectional view taken along the line Q4-Q4' of FIG. 11. FIG. 13 is a plan view showing a portion of a subpixel area of ​​a display device according to another embodiment. FIG. 14 is a cross-sectional view taken along the line Q5-Q5' of FIG. 13. FIG. 15 is a plan view showing a portion of a subpixel area of ​​a display device according to another embodiment. FIG. 16 is a cross-sectional view taken along the line Q6-Q6' of FIG. 15. FIG. 17 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 18 is a plan view schematically showing the electrodes and partitions of one subpixel of FIG. 17. FIG. 19 is a cross-sectional view taken along the line Q7-Q7' of FIG. 17 and FIG. 18. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0036] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0037] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0038] In the drawing describing the display device (10), a first direction (DR1), a second direction (DR2), and a third direction (DR3) are defined. The first direction (DR1) and the second direction (DR2) may be directions perpendicular to each other within a single plane. The third direction (DR3) may be a direction perpendicular to the plane where the first direction (DR1) and the second direction (DR2) are located. The third direction (DR3) is perpendicular to each of the first direction (DR1) and the second direction (DR2). In the embodiment describing the display device (10), the third direction (DR3) represents the thickness direction of the display device (10).

[0039] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a rectangular shape in which the first direction (DR1) in the plane includes a longer side than the second direction (DR2). As another example, the display device (10) may have a rectangular shape in which the second direction (DR2) in the plane includes a longer side than the first direction (DR1). However, it is not limited thereto and may have a shape such as a square, a square with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) and a display area (DPA) having a rectangular shape in which the first direction (DR1) is longer than the second direction (DR2) are illustrated.

[0040] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0041] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged alternately in a stripe type or a pentile type. Additionally, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0042] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0043] FIG. 2 is an equivalent circuit diagram of a subpixel of a display device according to one embodiment.

[0044] Referring to FIG. 2, each subpixel (SPXn) of a display device (10) according to one embodiment includes, in addition to a light-emitting element (ED), three transistors (T1, T2, T3) and one storage capacitor (Cst).

[0045] The light-emitting element (ED) emits light according to the current supplied through the first transistor (T1). The light-emitting element (ED) can emit light of a specific wavelength range by means of an electrical signal transmitted from the first electrode and the second electrode connected to both ends.

[0046] One end of the light-emitting element (ED) is connected to the source electrode of the first transistor (T1), and the other end can be connected to a second voltage wiring (VL2) to which a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring (VL1) is supplied.

[0047] The first transistor (T1) adjusts the current flowing from the first voltage wiring (VL1), to which the first power supply voltage is supplied, to the light-emitting element (ED) according to the voltage difference between the gate electrode and the source electrode. For example, the first transistor (T1) may be a driving transistor for driving the light-emitting element (ED). The gate electrode of the first transistor (T1) may be connected to the source electrode of the second transistor (T2), and the source electrode of the first transistor (T1) may be connected to one end of the light-emitting element (ED). The drain electrode of the first transistor (T1) may be connected to the first voltage wiring (VL1), to which the first power supply voltage is applied.

[0048] The second transistor (T2) is turned on by a scan signal of the first scan line (SL1) to connect the data line (DTL) to the gate electrode of the first transistor (T1). The gate electrode of the second transistor (T2) is connected to the first scan line (SL1), the source electrode is connected to the gate electrode of the first transistor (T1), and the drain electrode can be connected to the data line (DTL).

[0049] The third transistor (T3) is turned on by a scan signal from the second scan line (SL2) to connect the initial voltage wire (VIL) to one end of the light-emitting element (ED). The gate electrode of the third transistor (T3) is connected to the second scan line (SL2), the drain electrode is connected to the initial voltage wire (VIL), and the source electrode may be connected to one end of the light-emitting element (ED) or the source electrode of the first transistor (T1). In the drawings, the first scan line (SL1) and the second scan line (SL2) are shown separately, but are not limited thereto. In some embodiments, the first scan line (SL1) and the second scan line (SL2) may be formed as a single wire, in which case the second transistor (T2) and the third transistor (T3) may be turned on simultaneously by the same scan signal.

[0050] In one embodiment, the source electrode and drain electrode of each transistor (T1, T2, T3) are not limited to those described above, and may be the opposite. Additionally, each of the transistors (T1, T2, T3) may be formed as a thin film transistor. Furthermore, although FIG. 2 describes each transistor (T1, T2, T3) as being formed as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is not limited thereto. That is, each transistor (T1, T2, T3) may be formed as a P-type MOSFET, or some may be formed as an N-type MOSFET and others as a P-type MOSFET.

[0051] A storage capacitor (Cst) is formed between the gate electrode and the source electrode of the first transistor (T1). The storage capacitor (Cst) stores the difference voltage between the gate voltage and the source voltage of the first transistor (T1).

[0052] Hereinafter, the structure of a subpixel (PX) of a display device (10) according to one embodiment will be described in detail with further reference to other drawings.

[0053] FIG. 3 is a plan view showing one subpixel of a display device according to one embodiment. FIG. 4 is a plan view schematically showing the electrodes and partitions of one subpixel of FIG. 3. FIG. 5 is a cross-sectional view taken along the line Q1-Q1' of FIG. 3. FIG. 6 is a cross-sectional view taken along the line Q2-Q2' of FIG. 4. FIG. 7 is a cross-sectional view taken along the line Q3-Q3' of FIG. 4.

[0054] Referring to FIGS. 3 through 7, a plurality of subpixels (SPXn, n is 1 to 3) constituting a plurality of pixels of a display device (10) may be included. For example, one pixel may include three subpixels (SPXn), among which the first subpixel may emit light of a first color, the second subpixel may emit light of a second color, and the third subpixel may emit light of a third color. As an example, the first color may be red, the second color may be green, and the third color may be blue. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. In another embodiment, each subpixel (SPXn) may emit blue light. Additionally, the pixel may include a larger number of subpixels (SPXn).

[0055] Each subpixel (SPXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region. The light-emitting region (EMA) is an area where light-emitting elements (ED: ED1, ED2, ED3, ED4) are arranged and light of a specific wavelength range is emitted, and the non-light-emitting region may be an area where light-emitting elements (ED) are not arranged and light emitted from the light-emitting elements (ED) does not reach, so no light is emitted. The light-emitting region (EMA) may include an area where light-emitting elements (ED) are arranged and may include an area where light emitted from the light-emitting elements (ED) is emitted to an area adjacent to the light-emitting elements (ED).

[0056] Not limited thereto, the light-emitting region (EMA) may also include an area where light emitted from light-emitting elements (EDs) is reflected or refracted by other members and emitted. Multiple light-emitting elements (EDs) are placed in each subpixel (SPXn), and the light-emitting region (EMA) may be formed by including the area where they are placed and an adjacent area.

[0057] The light-emitting regions (EMAs) of the subpixel (SPXn) may each have a substantially uniform area, but are not limited thereto. In some embodiments, each light-emitting region (EMA) of each subpixel (SPXn) may have a different area depending on the color or wavelength of light emitted from the light-emitting elements (EDs) placed in the corresponding subpixel.

[0058] Additionally, each subpixel (SPXn) may further include sub-regions (SA: SA1, SA2) placed in a non-emissive region. The sub-regions (SA) may be placed in the second direction (DR2) of the emitting region (EMA) and in the direction opposite to the second direction (DR2), and may be placed between the emitting regions (EMA) of neighboring subpixels (SPXn) in the second direction (DR2) and in the direction opposite to the second direction (DR2). For example, each subpixel (SPXn) may have the first sub-region (SA1) and the second sub-region (SA2) spaced apart from each other in the second direction (DR2) with the emitting regions (EMA) in between. However, this is not limited thereto, and the emitting regions (EMA) and sub-regions (SA) may have an arrangement different from that of FIG. 3.

[0059] A bank layer (BNL) is disposed between the sub-regions (SA) and the light-emitting regions (EMA), and the spacing between them may vary depending on the width of the bank layer (BNL). Light is not emitted because light-emitting elements (ED) are not disposed in the sub-regions (SA), but some of the electrodes (RME: RME1, RME2, RME3) disposed in each sub-pixel (SPXn) may be disposed therein. Some of the electrodes (RME) disposed in different sub-pixels (SPXn) may be disposed separated from each other in the first separation portion (ROP1) of the first sub-region (SA1) and the second separation portion (ROP2) of the second sub-region (SA2).

[0060] The bank layer (BNL) may be arranged in a grid pattern across the entire front of the display area (DPA), including portions extending in the first direction (DR1) and the second direction (DR2) on the plane. The bank layer (BNL) may be arranged across the boundaries of each subpixel (SPXn) to distinguish neighboring subpixels (SPXn). Additionally, the bank layer (BNL) may be arranged to surround the light-emitting area (EMA) placed for each subpixel (SPXn) to distinguish them.

[0061] The display device (10) may include a plurality of electrodes (RME), partitions (BP), light-emitting elements (ED: ED1, ED2, ED3, ED4), and connecting electrodes (CNE: CNE1, CNE2, CNE3, CNE4, CNE5). The following description will be explained with reference to the drawings.

[0062] A display device (10) may include a substrate (SUB) and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the substrate (SUB). The semiconductor layer, the conductive layer, and the insulating layers may each constitute a circuit layer and a display element layer of the display device (10).

[0063] Specifically, the substrate (SUB) may be an insulating substrate. The substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Additionally, the substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The substrate (SUB) includes a display area (DPA) and a non-display area (NDA) surrounding it, and the display area (DPA) may include a light-emitting area (EMA) and sub-areas (SA) that are part of the non-light-emitting area.

[0064] The first conductive layer may be disposed on a substrate (SUB). The first conductive layer may include a lower metal layer (BML), a first voltage line (VL1), and a second voltage line (VL2). The lower metal layer (BML) is disposed to overlap with the first active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the first active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0065] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) may be applied to the first voltage wiring (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) may be applied to the second voltage wiring (VL2). The first voltage wiring (VL1) may be electrically connected to the first transistor (T1) through a conductive pattern of the second conductive layer (e.g., a second conductive pattern (CDP2)). The second voltage wiring (VL2) may be electrically connected to the second electrode (RME2) through a conductive pattern of the third conductive layer (e.g., a third conductive pattern (CDP3)).

[0066] In the drawings, the first voltage line (VL1) and the second voltage line (VL2) are illustrated as being disposed in the first conductive layer, but are not limited thereto. In some embodiments, the first voltage line (VL1) and the second voltage line (VL2) may be disposed in the third conductive layer and directly electrically connected to the first transistor (T1) and the second electrode (RME2), respectively.

[0067] A buffer layer (BL) may be disposed on a first conductive layer and a first substrate (SUB). The buffer layer (BL) is formed on the first substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the first substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0068] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0069] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In an exemplary embodiment, the semiconductor layer may include polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0070] In the drawing, one first transistor (T1) and one second transistor (T2) are shown arranged in a subpixel (SPXn) of the display device (10), but the display device (10) is not limited thereto and may include a larger number of transistors.

[0071] A first gate insulating layer (GI) is disposed on a semiconductor layer. The first gate insulating layer (GI) can serve as a gate insulating film for each transistor (T1, T2). In the drawings, the first gate insulating layer (GI) is illustrated as being patterned together with the gate electrodes (G1, G2) of the second conductive layer and partially disposed between the second conductive layer and the active layer (ACT1, ACT2) of the semiconductor layer, but is not limited thereto. In some embodiments, the first gate insulating layer (GI) may be disposed entirely on the buffer layer (BL) covering the semiconductor layer.

[0072] The second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of the storage capacitor.

[0073] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0074] The third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a plurality of conductive patterns (CDP1, CDP2, CDP3) and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2). Some of the conductive patterns (CDP1, CDP2, CDP3) electrically connect the conductive layers or semiconductor layers of different layers to each other and may serve as source / drain electrodes of transistors (T1, T2).

[0075] The first conductive pattern (CDP1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The first conductive pattern (CDP1) can contact the lower metal layer (BML) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The first conductive pattern (CDP1) can serve as the first source electrode (S1) of the first transistor (T1). The first conductive pattern (CDP1) can be electrically connected to the first electrode (RME1) or the first connection electrode (CNE1). The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0076] The second conductive pattern (CDP2) can contact the second voltage wiring (VL2) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The second voltage wiring (VL2) can transmit the second power supply voltage to the second connecting electrode (CNE2) through the third conductive pattern (CDP3).

[0077] The third conductive pattern (CDP3) can contact the first voltage wiring (VL1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). Additionally, the second conductive pattern (CDP2) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The second conductive pattern (CDP2) electrically connects the first voltage wiring (VL1) to the first transistor (T1) and can serve as the first drain electrode (D1) of the first transistor (T1).

[0078] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1).

[0079] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0080] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the same is stacked alternately. However, it is not limited thereto, and the buffer layer (BL), the first gate insulating layer (GI), the first interlayer insulating layer (IL1), and the first protective layer (PV1) may be formed into a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer (IL1) may be made of an organic insulating material such as polyimide (PI).

[0081] Additionally, the second conductive layer and the third conductive layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, they are not limited thereto.

[0082] A via layer (VIA) may be disposed on the first protective layer (PV1) in the display area (DPA). The via layer (VIA) may include an organic insulating material, such as polyimide (PI), to compensate for the step difference caused by the underlying conductive layers and to form a flat upper surface. However, in some embodiments, the via layer (VIA) may be omitted.

[0083] A display device (10) is a display element layer disposed on a via layer (VIA) and may include a partition (BP), a plurality of electrodes (RME) and a bank layer (BNL), a plurality of light-emitting elements (ED) and a plurality of connecting electrodes (CNE). Additionally, the display device (10) may include insulating layers (PAS1, PAS2, PAS3).

[0084] A partition (BP) may be placed directly on a via layer (VIA). The partition (BP) may include a first partition portion (BP1) and a second partition portion (BP2). The second partition portion (BP2) may be placed across subpixels (SPXn) adjacent in a first direction (DR1). For example, the partition (BP) may include a first partition portion (BP1) placed at each subpixel (SPXn) and a second partition portion (BP2) placed across different subpixels (SPXn).

[0085] The first partition (BP1) is positioned in the light-emitting region (EMA) of the subpixel (SPXn) and may have a shape extending in the second direction (DR2). The first partition (BP1) may be positioned between the second partitions (BP2) and spaced apart from each other. The first partition (BP1) may be formed as an island shape extending in the second direction (DR2) with a narrow width in the light-emitting region (EMA) of each subpixel (SPXn) on the front of the display area (DPA).

[0086] The second partition (BP2) may be positioned across the light-emitting region (EMA) and the non-light-emitting region of the subpixel (SPXn). The second partition (BP2) may have a shape that extends in the second direction (DR2) and may be spaced apart from each other in the first direction (DR1). The second partitions (BP2) may have the same width, but are not limited thereto and may have different widths. The length of the second partition (BP2) extended in the second direction (DR2) may be greater than the length of the second direction (DR2) of the light-emitting region (EMA) surrounded by the bank layer (BNL). However, they are not limited thereto, and the length of the second partition (BP2) extended in the second direction (DR2) may be smaller than the length of the second direction (DR2) of the light-emitting region (EMA) surrounded by the bank layer (BNL).

[0087] The first partition section (BP1) is positioned at the center of the light-emitting region (EMA), and the second partition sections (BP2) are positioned spaced apart from the first partition section (BP1). The first partition section (BP1) and the second partition sections (BP2) may be positioned alternately along the first direction (DR1). Light-emitting elements (ED) may be positioned between the first partition section (BP1) and the second partition sections (BP2).

[0088] The first bulkhead section (BP1) and the second bulkhead section (BP2) have the same length in the second direction (DR2), but the width measured in the first direction (DR1) may be different. The portion of the bank layer (BNL) extended in the second direction (DR2) may overlap with the second bulkhead sections (BP2) in the thickness direction (e.g., the third direction (DR3)).

[0089] The partition (BP) may further include a first connecting part (CP1) and a second connecting part (CP2) connecting the first partition part (BP1) and the second partition part (BP2). The first connecting part (CP1) may be positioned in the light-emitting region (EMA) of the subpixel (SPXn) and may have a shape extending in the first direction (DR1). The first connecting part (CP1) may be positioned between the first partition part (BP1) and the second partition part (BP2) to connect the first partition part (BP1) and the second partition part (BP2). For example, the first partition part (BP1) may be positioned between the first partition part (BP1) and the second partition part (BP2) which is positioned to the left of the first partition part (BP1).

[0090] The second connecting portion (CP2) is positioned in the light-emitting region (EMA) of the subpixel (SPXn) and may have a shape that extends in the first direction (DR1). The second connecting portion (CP2) may be positioned between the first partition portion (BP1) and the second partition portion (BP2) to connect the first partition portion (BP1) and the second partition portion (BP2). For example, the first partition portion (BP1) may be positioned between the first partition portion (BP1) and the second partition portion (BP2) positioned to the right of the first partition portion (BP1).

[0091] The first connection portion (CP1) and the second connection portion (CP2) may be spaced apart from each other with the first partition portion (BP1) in between. The first connection portion (CP1) and the second connection portion (CP2) may be aligned and matched with each other in the first direction (DR1). The first connection portion (CP1) and the second connection portion (CP2) may be positioned approximately at the center of the light-emitting region (EMA) of the subpixel (SPXn) so as not to overlap with the bank layer (BNL) in the thickness direction. The first connection portion (CP1) and the second connection portion (CP2) may be positioned in the region that divides the length of the first partition portion (BP1) extended in the second direction (DR2). The width of each of the first connection portion (CP1) and the second connection portion (CP2) in the second direction (DR2) may be smaller than the width of the first partition portion (BP1) in the first direction (DR1). However, this is not limited thereto, and the width of each of the first connecting part (CP1) and the second connecting part (CP2) in the second direction (DR2) may be greater than or equal to the width of the first bulkhead part (BP1) in the first direction (DR1).

[0092] The first bulkhead section (BP1), the second bulkhead section (BP2), the first connecting section (CP1), and the second connecting section (CP2) can be connected to each other to form a single body. For example, the first bulkhead section (BP1) and the second bulkhead section (BP2) can be connected to the first connecting section (CP1) and the second connecting section (CP2) to form a single body.

[0093] The first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer (VIA). The protruding portions of the first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) may have inclined or curved sides. Unlike as illustrated in the drawings, each component of the first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) may have an outer surface in the shape of a semicircle or a semi-ellipse in the cross-sectional view.

[0094] The first connecting portion (CP1) and the second connecting portion (CP2) may have a predetermined thickness in the third direction (DR3). The thickness of each of the first connecting portion (CP1) and the second connecting portion (CP2) may be smaller than the thickness of the first partition portion (BP1) and the second partition portion (BP2). For example, the thickness of each of the first connecting portion (CP1) and the second connecting portion (CP2) may be about 1000 Å to about 5000 Å.

[0095] The first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) can be formed simultaneously. For example, the first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) can be formed simultaneously using a halftone mask after coating with an organic insulating material. The first partition (BP1), the second partition (BP2), the first connection (CP1), and the second connection (CP2) may include, but are not limited to, an organic insulating material such as polyimide (PI).

[0096] Multiple electrodes (RME) may be arranged in a shape extending in one direction for each subpixel (SPXn). Multiple electrodes (RME) may be arranged extending in a second direction (DR2) across the light-emitting region (EMA) and sub-region (SA) of the subpixel (SPXn), and may be arranged spaced apart from each other in a first direction (DR1). The electrodes (RME) may be electrically connected to a light-emitting element (ED) described later. However, they are not limited thereto, and the electrodes (RME) may not be electrically connected to the light-emitting element (ED).

[0097] The display device (10) may include a first electrode (RME1), a second electrode (RME2), and a third electrode (RME3). The first electrode (RME1) may be placed at the center of each subpixel (SPXn), the second electrode (RME2) may be placed to the left of the first electrode (RME1) and may be placed across adjacent subpixels (SPXn), and the third electrode (RME3) may be placed to the right of the first electrode (RME1) and may be placed across adjacent subpixels (SPXn).

[0098] The first electrode (RME1) is positioned at the center of the subpixel (SPXn), and the portion positioned in the light-emitting region (EMA) may be positioned on the first partition (BP1). The first electrode (RME1) may extend from the first sub-region (SA1) positioned above the light-emitting region (EMA) in the opposite direction of the second direction (DR2) to the second sub-region (SA2) positioned below the light-emitting region (EMA). The first electrode (RME1) may have a shape in which the width measured in the first direction (DR1) varies depending on the position, and at least the portion overlapping with the light-emitting element (ED) in the light-emitting region (EMA) may have a width greater than that of the first partition (BP1).

[0099] The first electrode (RME1) may include a concave portion (GR: GR1, GR2) that extends in the second direction (DR2) but narrows in width toward the first direction (DR1). The concave portion (GR) is positioned within the light-emitting region (EMA) of each subpixel (SPXn), and may be concavely recessed on one side of the first electrode (RME1) in the plane toward the first direction (DR1) or in the direction opposite to the first direction (DR1). The concave portion (GR) may include a first concave portion (GR1) positioned on one side of the first electrode (RME1) facing the second electrode (RME2), and a second concave portion (GR2) positioned on the other side of the first electrode (RME1) facing the third electrode (RME3).

[0100] The first concave portion (GR1) may be formed in a shape in which one side of the first electrode (RME1) facing the second electrode (RME2) is concavely recessed in the first direction (DR1). The second concave portion (GR2) may be formed in a shape in which the other side of the first electrode (RME1) facing the third electrode (RME3) is concavely recessed in the direction opposite to the first direction (DR1). The depth of the first concave portion (GR1) and the second concave portion (GR2) may each be the same as the depth of the concave portion into the center of the first electrode (RME1). Additionally, the width of the first concave portion (GR1) and the second concave portion (GR2) may each be the same as the width in the second direction (DR2). For example, the first concave portion (GR1) and the second concave portion (GR2) may be symmetrical to each other with respect to any straight line extending from the center of the first electrode (RME1) in the second direction (DR2). Although FIGS. 3 and 4 show that the corners of the first concave portion (GR1) and the second concave portion (GR2) are right angles, they are not limited thereto and may have rounded corners such as semicircles or semi-ellipses.

[0101] The second electrode (RME2) may include a portion extending in the second direction (DR2) and a portion that widens around the light-emitting region (EMA). According to one embodiment, the second electrode (RME2) may include a first stem portion (RM_S1) extending in the second direction (DR2) and a first extension portion (RM_B1) connected to or extending from the first stem portion (RM_S1) and having a width in the first direction (DR1) that is wider than that of the first stem portion (RM_S1). Additionally, the second electrode (RME2) may include a first protrusion portion (RM_P1) protruding from the first extension portion (RM_B1) in the first direction (DR1).

[0102] The first stem portion (RM_S1) is positioned to overlap with the portion extending in the first direction (DR1) of the bank layer (BNL) and may be positioned on one side of the second direction (DR2) of the sub-regions (SA1, SA2). The second electrode (RME2) may be positioned between the first sub-regions (SA1) and between the second sub-regions (SA2) of the sub-pixels (SPXn) adjacent to the first stem portion (RM_S1) in the second direction (DR2). The first stem portion (RM_S1) is positioned between the sub-regions (SA1, SA2) adjacent to the second direction (DR2), and a portion of it may protrude into the sub-regions (SA1, SA2).

[0103] The first extension portion (RM_B1) is positioned opposite to the first direction (DR1) from the center of the subpixel (SPXn) and may be positioned on the second partition portion (BP2). The second electrode (RME2) may have a shape in which the width of the first direction (DR1) increases at the intersection of the portion extending in the second direction (DR2) of the bank layer (BNL) and the portion extending in the first direction (DR1). The first extension portion (RM_B1) is positioned across the light-emitting region (EMA) of the subpixels (SPXn) adjacent to the first direction (DR1) and may be positioned to overlap with the region between the subpixels (SPXn). The first extension portion (RM_B1) may overlap with the portion positioned between adjacent subpixels (SPXn) among the portions extending in the opposite direction of the first direction (DR1) of the bank layer (BNL).

[0104] The first protrusion (RM_P1) is positioned approximately at the center of the subpixel (SPXn) and may be positioned on the first connection portion (CP1) of the second partition portion (BP2). The width of the first protrusion (RM_P1) in the second direction (DR2) may be greater than the width of the first connection portion (CP1) in the second direction (DR2). The first protrusion (RM_P1) may cover the upper surface of the first connection portion (CP1) and the sides in the second direction (DR2). The first protrusion (RM_P1) may protrude toward the first electrode (RME1) from one side of the second electrode (RME2) facing the first electrode (RME1). The first protrusion (RM_P1) may be positioned in a shape inserted into the first recess (GR1) of the first electrode (RME1) in a planar shape. For example, the end of the first protrusion (RM_P1) can be placed within the first recess (GR1) of the first electrode (RME1).

[0105] The third electrode (RME3) may include a portion extending in the second direction (DR2) and a portion that widens around the light-emitting region (EMA). According to one embodiment, the third electrode (RME3) may include a second stem portion (RM_S2) extending in the second direction (DR2) and a second extension portion (RM_B2) connected to or extending from the second stem portion (RM_S2) and having a width in the first direction (DR1) that is wider than that of the second stem portion (RM_S2). Additionally, the third electrode (RME3) may include a second protrusion portion (RM_P2) protruding from the second extension portion (RM_B2) in the opposite direction to the first direction (DR1).

[0106] When viewed from the subpixel (SPXn) illustrated in FIGS. 3 and 4, the second electrode (RME2) may be positioned to the left of the first electrode (RME1) and the third electrode (RME3) may be positioned to the right. When viewed from the subpixel (SPXn) adjacent to the first direction (DR1) of the subpixel (SPXn), the third electrode (RME3) may extend beyond the bank layer (BNL) to function as the second electrode (RME2). In this specification, the second electrode (RME2) and the third electrode (RME3) are described separately based on one subpixel (SPXn), but when viewing the entire display device (10), the second electrode (RME2) and the third electrode (RME3) may be the same electrode.

[0107] The second stem portion (RM_S2) of the third electrode (RME3) is positioned to overlap with the portion extending in the first direction (DR1) of the bank layer (BNL) and may be positioned on one side of the second direction (DR2) of the sub-regions (SA1, SA2). The third electrode (RME3) may be positioned such that the second stem portion (RM_S2) is positioned between the first sub-regions (SA1) and between the second sub-regions (SA2) of the sub-pixels (SPXn) adjacent in the second direction (DR2). The second stem portion (RM_S2) is positioned between the sub-regions (SA1, SA2) adjacent in the second direction (DR2), and a portion of it may protrude into the sub-regions (SA1, SA2).

[0108] The second extension portion (RM_B2) is positioned in the first direction (DR1) from the center of the subpixel (SPXn) and can be positioned on the second partition portion (BP2) positioned on the right. The third electrode (RME3) may have a shape in which the width of the first direction (DR1) increases at the intersection of the portion extending in the second direction (DR2) of the bank layer (BNL) and the portion extending in the first direction (DR1). The second extension portion (RM_B2) is positioned across the light-emitting region (EMA) of the subpixels (SPXn) adjacent in the first direction (DR1) and can be positioned to overlap with the region between the subpixels (SPXn). The second extension portion (RM_B2) may overlap with the portion positioned between adjacent subpixels (SPXn) among the portions extending in the first direction (DR1) of the bank layer (BNL).

[0109] The second protrusion (RM_P2) is positioned approximately at the center of the subpixel (SPXn) and may be positioned on the second connection portion (CP2) of the second partition portion (BP2). The width of the second protrusion (RM_P2) in the second direction (DR2) may be greater than the width of the second connection portion (CP2) in the second direction (DR2). The second protrusion (RM_P2) may cover the upper surface of the second connection portion (CP2) and the sides in the second direction (DR2). The second protrusion (RM_P2) may protrude toward the first electrode (RME1) from one side of the third electrode (RME3) facing the first electrode (RME1). The second protrusion (RM_P2) may be positioned in a shape inserted into the second recess (GR2) of the first electrode (RME1) in a planar shape. For example, the end of the second protrusion (RM_P2) can be placed within the second recess (GR2) of the first electrode (RME1).

[0110] The width measured in the first direction (DR1) of the first electrode (RME1) may be greater than the width of the first stem portion (RM_S1) of the second electrode (RME2) and the second stem portion (RM_S2) of the third electrode (RME3), respectively, but smaller than the width of the first extension portion (RM_B1) and the second extension portion (RM_B2), respectively. The width of the first stem portion (RM_S1) of the second electrode (RME2) and the second stem portion (RM_S2) of the third electrode (RME3) may be relatively small so that they can be placed between sub-regions (SA1, SA2), whereas the width of the first extension portion (RM_B1) and the second extension portion (RM_B2) may be larger than that of the first electrode (RME1). The first electrode (RME1) may be positioned to cover both sides of the first direction (DR1) of the first partition (BP1), and the second electrode (RME2) and the third electrode (RME3) may be positioned to cover both sides of the first direction (DR1) of the second partition (BP2). The gap between the first partition (BP1) and the second partition (BP2) may be larger than the gap between the first electrode (RME1) and the second electrode (RME2), and between the first electrode (RME1) and the third electrode (RME3).

[0111] The first electrode (RME1) can contact the first conductive pattern (CDP1) of the third conductive layer through the first electrode contact hole (CTD) in the portion that overlaps with the portion extended in the first direction (DR1) of the bank layer (BNL). The second electrode (RME2) can contact the second conductive pattern (CDP2) of the third conductive layer through the second electrode contact hole (CTS) in the first stem portion (RM_S1). The first electrode (RME1) is positioned so that the portion placed in the first sub-region (SA1) overlaps with the first contact hole (CT1), and the second electrode (RME2) includes the portion protruding in the second direction (DR2) from the first stem portion (RM_S1) and the portion placed in the first sub-region (SA1), and can overlap with the second contact hole (CT2) in the protruding portion.

[0112] The first electrode (RME1) is positioned up to the separation portion (ROP1, ROP2) of the sub-regions (SA1, SA2), whereas the second electrode (RME2) may not be separated from the sub-regions (SA1, SA2). One second electrode (RME2) and one third electrode (RME3) extend in the second direction (DR2) and may have a shape that widens near the light-emitting region (EMA) of each sub-pixel (SPXn).

[0113] According to one embodiment, the display device (10) may include a wiring connection electrode (EP) disposed in a first sub-region (SA1) and positioned between first electrodes (RME1) of different sub-pixels (SPXn). In a second sub-region (SA2), no wiring connection electrode (EP) is disposed, and the first electrodes (RME1) of other sub-pixels (SPXn) adjacent in a second direction (DR2) may be spaced apart from each other.

[0114] The first electrode (RME1) may be spaced apart from the wiring connection electrode (EP) in the first sub-region (SA1) with the first separation part (ROP1) in between. Two first separation parts (ROP1) may be arranged in the first sub-region (SA1), and the wiring connection electrode (EP) may be spaced apart from the first electrode (RME1) with the first separation part (ROP1) in between. One second separation part (ROP2) may be arranged in the second sub-region (SA2), and different first electrodes (RME1) may be spaced apart in the first direction (DR1).

[0115] The wiring connection electrode (EP) can be connected to the third conductive pattern (CDP3) of the third conductive layer through a third electrode contact hole (CTA) penetrating the via layer (VIA). The first electrode (RME1) is formed in a state connected to the wiring connection electrode (EP), and an electrical signal applied to place light-emitting elements (ED) can be applied from the first voltage wiring (VL1) to the first electrode (RME1) through the wiring connection electrode (EP). In the process of placing the light-emitting elements (ED), signals are applied to the first voltage wiring (VL1) and the second voltage wiring (VL2), and these can be transmitted to the first electrode (RME1) and the second electrode (RME2), respectively.

[0116] Meanwhile, the second electrode contact hole (CTS) may have a different relative position to the third electrode contact hole (CTA). The second electrode contact hole (CTS) may be positioned in the second sub-region (SA2), and the third electrode contact hole (CTA) may be positioned in the first sub-region (SA1). This may be because the second electrode contact hole (CTS) and the third electrode contact hole (CTA) each expose the upper surface of different conductive patterns (CDP2, CPD3), and the position of each electrode contact hole may be determined accordingly.

[0117] Each of the plurality of electrodes (RME) may include a highly reflective conductive material. For example, the electrode (RME) may be a highly reflective material that includes a metal such as silver (Ag), copper (Cu), or aluminum (Al), or an alloy including aluminum (Al), nickel (Ni), or lanthanum (La). The electrode (RME) may reflect light emitted from the light-emitting element (ED) and traveling to the sides of the barriers (BP) toward the upper direction of each subpixel (SPXn).

[0118] However, not limited thereto, each electrode (RME) may further include a transparent conductive material. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0119] A first insulating layer (PAS1) may be disposed on a via layer (VIA), a partition (BP), and a plurality of electrodes (RME). The first insulating layer (PAS1) may be disposed on the via layer (VIA) to cover the plurality of electrodes (RME) and the partition (BP). Additionally, the first insulating layer (PAS1) may not be disposed on the first separation portion (ROP1) of the first sub-region (SA1) and the second separation portion (ROP2) of the second sub-region (SA2). The first insulating layer (PAS1) can protect the plurality of electrodes (RME) while simultaneously insulating different electrodes (RME) from each other. Additionally, the first insulating layer (PAS1) may prevent a light-emitting element (ED) disposed thereon from being damaged by direct contact with other components. In an exemplary embodiment, the first insulating layer (PAS1) may have a step formed such that a portion of its upper surface is recessed between electrodes (RME) spaced apart in a first direction (DR1). Light-emitting elements (EDs) are disposed on the upper surface of the first insulating layer (PAS1) where the step is formed, and a space may be formed between the light-emitting elements (EDs) and the first insulating layer (PAS1). The space may be filled with a second insulating layer (PAS2) described later.

[0120] The first insulating layer (PAS1) may include a plurality of contact holes (CT1, CT2) that expose a portion of the upper surface of each electrode (RME). The plurality of contact holes (CT1, CT2) penetrate the first insulating layer (PAS1), and the first connecting electrode (CNE1) and the second connecting electrode (CNE2), described later, may each contact the electrodes (RME) exposed through the contact holes (CT1, CT2).

[0121] Additionally, the first insulating layer (PAS1) may include an opening (OP) that exposes a portion of the upper surface of each electrode (RME) and a portion of the upper surface of the partition (BP). The opening (OP) may be formed by removing the first insulating layer (PAS1) to expose a portion of the upper surface of the lower electrodes (RME) and a portion of the upper surface of the partition (BP). The opening (OP) may overlap in a third direction (DR3) with the recesses (GR) of the first electrode (RME1), the first protrusion (RM_P1) of the second electrode (RME2), and the second protrusion (RM_P2) of the third electrode (RME3). Additionally, the opening (OP) may overlap in a third direction (DR3) with the first connection (CP1) and the second connection (CP2) of the first partition (BP1) and the second partition (BP2).

[0122] A bank layer (BNL) may be disposed on a first insulating layer (PAS1). The bank layer (BNL) may be disposed in a grid pattern including portions extending in a first direction (DR1) and a second direction (DR2) in a planar view, and may be disposed across the boundaries of each subpixel (SPXn) to distinguish neighboring subpixels (SPXn). Additionally, the bank layer (BNL) is disposed to surround a light-emitting region (EMA) and sub-regions (SA), and the area partitioned and opened by the bank layer (BNL) may be the light-emitting region (EMA) and the sub-region (SA), respectively.

[0123] The bank layer (BNL) may have a certain height, and in some embodiments, the height of the upper surface of the bank layer (BNL) may be higher than that of the partition wall (BP), and its thickness may be equal to or greater than that of the partition wall (BP). However, it is not limited thereto, and the height of the upper surface of the bank layer (BNL) may be equal to or less than that of the partition wall (BP), and its thickness may be smaller than that of the partition wall (BP). The bank layer (BNL) can prevent ink from overflowing into a sub-pixel (SPX) adjacent to the second direction (DR2) or into a sub-region (SA) located in the first direction (DR1) during the inkjet printing process in the manufacturing process of the display device (10). The bank layer (BNL) can prevent ink in which different light-emitting elements (ED) are dispersed for each other sub-pixel (SPXn) from mixing with each other. The bank layer (BNL) may include polyimide like the partition wall (BP), but is not limited thereto.

[0124] Light-emitting elements (EDs) may be disposed in a light-emitting region (EMA). Light-emitting elements (EDs) may be disposed on a first insulating layer (PAS1) between partitions (BPs). Light-emitting elements (EDs) may be disposed such that one extended direction is parallel to the upper surface of the substrate (SUB). As described below, the light-emitting elements (EDs) may include a plurality of semiconductor layers disposed along the one extended direction, and the plurality of semiconductor layers may be sequentially disposed along a direction parallel to the upper surface of the substrate (SUB). However, not limited thereto, if the light-emitting elements (EDs) have a different structure, the plurality of semiconductor layers may be disposed in a direction perpendicular to the substrate (SUB).

[0125] The light-emitting elements (EDs) placed in each subpixel (SPXn) can emit light of different wavelengths depending on the material of the semiconductor layer. However, they are not limited to this, and the light-emitting elements (EDs) placed in each subpixel (SPXn) may include a semiconductor layer of the same material and emit light of the same color. The light-emitting elements (EDs) can be electrically connected to the conductive layers under the electrode (RME) and via layer (VIA) by contacting the connecting electrodes (CNE), and can emit light of a specific wavelength when an electrical signal is applied.

[0126] According to one embodiment, light-emitting elements (ED) are disposed on electrodes (RME) spaced apart in a first direction (DR1) between partitions (BP1, BP2) and can be divided into light-emitting elements (ED: ED1, ED2, ED3, ED4) disposed on different electrodes (RME). The light-emitting elements (ED) can be disposed between the first partition section (BP1) and the second partition section (BP2). According to one embodiment, the light-emitting elements (ED) include a first light-emitting element (ED1) and a third light-emitting element (ED3) disposed between the first partition section (BP1) and the second partition section (BP2) disposed on the left side, and may include a second light-emitting element (ED2) and a fourth light-emitting element (ED4) disposed between the first partition section (BP1) and the second partition section (BP2) disposed on the right side.

[0127] The first light-emitting element (ED1) and the third light-emitting element (ED3) may be placed on the first electrode (RME1) and the second electrode (RME2), and the second light-emitting element (ED2) and the fourth light-emitting element (ED4) may be placed on the first electrode (RME1) and the third electrode (RME3). However, each light-emitting element (ED) may not be distinguished according to the position in which it is placed in the light-emitting region (EMA), but may be distinguished according to the connection relationship with the connecting electrode (CNE) described later. Depending on the arrangement structure of the connecting electrodes (CNE), the connecting electrodes (CNE) that each light-emitting element (ED) contacts at both ends may be different, and the light-emitting elements (ED) may be distinguished according to the type of connecting electrode (CNE) that they contact.

[0128] After forming a bank layer (BNL) on the first insulating layer (PAS1), the light-emitting elements (ED) described above can be sprayed onto a light-emitting region (EMA) in a dispersed state within a predetermined ink and aligned between electrodes (RME). As shown in FIG. 3, connecting electrodes (CNE) capable of contacting both sides of the light-emitting elements (ED) are not placed in the center of the light-emitting region (EMA), so that the light-emitting elements (ED) do not emit light even when aligned in the center of the light-emitting region (EMA).

[0129] According to one embodiment, a display device (10) can be provided that minimizes non-emitting light-emitting elements (EDs) by not applying ink to the center of the light-emitting area (EMA) even when ink in which light-emitting elements (EDs) are dispersed is sprayed into the light-emitting area (EMA).

[0130] FIG. 8 is another cross-sectional view taken along the line Q2-Q2' of FIG. 4. FIG. 9 is another cross-sectional view taken along the line Q3-Q3' of FIG. 4. FIG. 8 and FIG. 9 respectively show the partition wall (BP), electrodes (RME), and first insulating layer (PAS1) illustrated in FIG. 4, and respectively show an ink with a light-emitting element (ED) dispersed thereon applied thereon.

[0131] Referring to FIG. 8 and FIG. 9 in conjunction with FIG. 4, each subpixel (SPXn) may have each electrode (RME) and partition (BP) disposed in the center of the light-emitting region (EMA). As described above, a first connecting portion (CP1) and a second connecting portion (CP2) connecting the first partition portion (BP1) and the second partition portion (BP2) are disposed in the center of the light-emitting region (EMA). The first electrode (RME1) has concave portions (GR), the second electrode (RME2) has a first protrusion (RM_P1) that protrudes toward the first concave portion (GR1) and covers the first connecting portion (CP1), and the third electrode (RME3) has a second protrusion (RM_P2) that protrudes toward the second concave portion (GR2) and covers the second connecting portion (CP2). A first insulating layer (PAS1) is disposed on each electrode (RME) and partition (BP), and the first insulating layer (PAS1) includes an opening (OP) that exposes the lower electrodes (RME) and partition (BP).

[0132] In the opening (OP), the upper surface of the partition (BP) can generally be covered by electrodes (RME). For example, the second electrode (RME2) and the first protrusion (RM_P1) of the second electrode (RME2) cover one side of the second partition (BP2) and the first connection (CP1), and the third electrode (RME3) and the second protrusion (RM_P2) of the third electrode (RME3) cover the other side of the second partition (BP2) and the second connection (CP2). Additionally, the first electrode (RME1) covers the upper surface of the first partition (BP1). That is, the electrodes (RME) can be exposed and positioned in most of the area exposed by the opening (OP).

[0133] Ink (INK) containing dispersed light-emitting elements (ED) can be sprayed onto the upper and lower sides of the light-emitting region (EMA), respectively. Since the first insulating layer (PAS1) covers most of the light-emitting region (EMA), the ink (INK) spreads along the surface of the first insulating layer (PAS1) and stops upon encountering the surfaces of the electrodes (RME) exposed at the openings (OP) of the first insulating layer (PAS1). In other words, when the ink (INK) spreads along the surface of the first insulating layer (PAS1) and encounters the surfaces of the electrodes (RME), which are made of a material different from the first insulating layer (PAS1), the spreading of the ink stops due to the difference in the contact angle with the ink. Accordingly, the application of ink to the center of the light-emitting region (EMA) is minimized, thereby reducing the number of non-light-emitting elements (ED).

[0134] In addition, in one embodiment, a first connecting portion (CP1) and a second connecting portion (CP2) are formed to connect the first partition portion (BP1) and the second partition portion (BP2), and a first protrusion (RM_P1) of the second electrode (RME2) and a second protrusion (RM_P2) of the third electrode (RME3) are formed to cover the first connecting portion (CP1) and the second connecting portion (CP2). A step difference may be formed between the second electrode (RME2) and the third electrode (RME3) by the first connecting portion (CP1) and the second connecting portion (CP2). If a first insulating layer (PAS1) is formed and a portion of the first insulating layer (PAS1) is removed to form an opening (OP), the upper surface of the first insulating layer (PAS1) and the upper surfaces of the second electrode (RME2) and the third electrode (RME3) may be aligned and matched with each other. That is, in the area where the first connection part (CP1) and the second connection part (CP2) are arranged, the height of the upper surface of the second electrode (RME2) or the third electrode (RME3) from the via layer (VIA) may be the same as the height of the upper surface of the first insulating layer (PAS1) from the via layer (VIA) in the area where the first connection part (CP1) and the second connection part (CP2) are not arranged.

[0135] If the first connection part (CP1) and the second connection part (CP2) are not formed, the height of the second electrode (RME2) or the third electrode (RME3) at the opening (OP) of the first insulating layer (PAS1) becomes lower than the height of the first insulating layer (PAS1), which may cause a groove to form. This groove forms a difference in height, causing ink to spread into the opening (OP) of the first insulating layer (PAS1), thereby making it difficult to prevent ink from spreading to the center of the light-emitting region (EMA).

[0136] Referring again to FIGS. 3 and FIGS. 5, connecting electrodes (CNE; CNE1, CNE2, CNE3, CNE4, CNE5) may be disposed on a plurality of electrodes (RME) and partitions (BP1, BP2). Each of the plurality of connecting electrodes (CNE) may have a shape extending in one direction and may be spaced apart from each other. Each connecting electrode (CNE) may be in contact with a light-emitting element (ED) and electrically connected to a lower conductive layer.

[0137] The connection electrodes (CNE) may include a first connection electrode (CNE1), a second connection electrode (CNE2), a third connection electrode (CNE3), a fourth connection electrode (CNE4), and a fifth connection electrode (CNE5) disposed in each subpixel (SPXn).

[0138] The first connecting electrode (CNE1) may have a shape that generally extends in the second direction (DR2) and may be disposed on the first electrode (RME1). The first connecting electrode (RME1) may partially overlap with the first electrode (RME1) and the first partition (BP1) and may be disposed across the light-emitting region (EMA) and sub-regions (SA1, SA2). The second connecting electrode (CNE2) may extend diagonally and have a donut-shaped detour and may be disposed on the third electrode (RME3). The second connecting electrode (CNE2) may partially overlap with the third electrode (RME3) and the second partition (BP2) and may be disposed across the light-emitting region (EMA) and the first sub-region (SA1). The first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be disposed on the upper side of the light-emitting region (EMA) of the sub-pixel (SPXn).

[0139] The third connecting electrode (CNE3) has a donut-shaped bypass that extends diagonally and then extends in the second direction (DR2), and can be placed on the second electrode (RME2) and the first electrode (RME1). The third connecting electrode (CNE3) partially overlaps with the first electrode (RME1) and the second electrode (RME2), and can partially overlap with the first partition (BP1) and the second partition (BP2). The third connecting electrode (CNE3) is generally placed in the light-emitting region (EMA) and can be placed extending from the upper side to the lower side within the light-emitting region (EMA) of the subpixel (SPXn).

[0140] The fourth connecting electrode (CNE4) may extend in the second direction (DR2) and have a donut-shaped detour and be positioned on the third electrode (RME3) and the first electrode (RME1). The fourth connecting electrode (CNE4) may partially overlap with the first electrode (RME1) and the third electrode (RME3), and may partially overlap with the first partition (BP1) and the second partition (BP2). The fourth connecting electrode (CNE4) is generally positioned in the light-emitting region (EMA) and may be positioned extending from the upper side to the lower side of the light-emitting region (EMA) of the subpixel (SPXn).

[0141] The fifth connecting electrode (CNE5) has a donut-shaped bypass that extends in the first direction (DR1) and is bent in the second direction (DR2), and can be placed on the first electrode (RME1) and the second electrode (RME2). The fifth connecting electrode (CNE5) partially overlaps with the first electrode (RME1) and the second electrode (RME2), and can partially overlap with the first partition (BP1) and the second partition (BP2). The fifth connecting electrode (CNE4) is generally placed in the light-emitting region (EMA) and can be placed on the lower side of the light-emitting region (EMA) of the subpixel (SPXn).

[0142] The second connecting electrode (CNE2), the third connecting electrode (CNE3), the fourth connecting electrode (CNE4), and the fifth connecting electrode (CNE5) are each formed with a donut-shaped bypass, and the first connecting electrode (CNE1) may be formed as a bent linear shape without a bypass.

[0143] Corresponding to the arrangement structure of the connecting electrodes (CNE), a plurality of light-emitting elements (ED) can be classified into different light-emitting elements (ED) depending on the connecting electrode (CNE) to which both ends contact. A first light-emitting element (ED1) may contact the first connecting electrode (CNE1) and the third connecting electrode (CNE3), and a second light-emitting element (ED2) may contact the second connecting electrode (CNE2) and the fourth connecting electrode (CNE4). A third light-emitting element (ED3) may contact the third connecting electrode (CNE3) and the fifth connecting electrode (CNE5), and a fourth light-emitting element (ED4) may contact the fourth connecting electrode (CNE4) and the fifth connecting electrode (CNE5).

[0144] As described below, the light-emitting elements (ED) can have their two ends in an extended direction separated from each other and can be connected in series through connecting electrodes (CNE) that contact the two ends. The display device (10) can include a larger number of light-emitting elements (ED) for each subpixel (SPXn) and can configure their series connection so that the amount of light emitted per unit area can be increased.

[0145] FIG. 10 is a schematic diagram of a light-emitting element according to one embodiment.

[0146] Referring to FIG. 10, the light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0147] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction but has a partially inclined outer surface.

[0148] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0149] The first semiconductor layer (31) may be an n-type semiconductor. The first semiconductor layer (31) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, Se, etc.

[0150] The second semiconductor layer (32) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) is Al x Ga y In 1-x-yIt may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0151] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer. For example, the light-emitting device (ED) may further include other semiconductor layers disposed between the first semiconductor layer (31) and the light-emitting layer (36), or between the second semiconductor layer (32) and the light-emitting layer (36). The semiconductor layer disposed between the first semiconductor layer (31) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer (32) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0152] The light-emitting layer (36) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, if the light-emitting layer (36) has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN.

[0153] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0154] The electrode layer (37) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0155] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (10) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0156] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, the insulating film (38) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0157] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO₂ x It may include at least one of ). In the drawings, the insulating film (38) is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0158] The insulating film (38) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0159] Additionally, the outer surface of the insulating film (38) may be surface-treated. The light-emitting element (ED) may be sprayed onto the electrode and aligned in a dispersed state within a predetermined ink. Here, in order for the light-emitting element (ED) to remain dispersed without aggregating with other adjacent light-emitting elements (ED) within the ink, the surface of the insulating film (38) may be treated to be hydrophobic or hydrophilic.

[0160] Hereinafter, other embodiments of the display device (10) will be described with reference to other drawings.

[0161] FIG. 11 is a plan view showing a portion of a subpixel of a display device according to another embodiment. FIG. 12 is a cross-sectional view taken along the line Q4-Q4' of FIG. 11. FIG. 13 is a plan view showing a portion of a subpixel of a display device according to yet another embodiment. FIG. 14 is a cross-sectional view taken along the line Q5-Q5' of FIG. 13. FIG. 15 is a plan view showing a portion of a subpixel of a display device according to yet another embodiment. FIG. 16 is a cross-sectional view taken along the line Q6-Q6' of FIG. 15. FIG. 11, FIG. 13, and FIG. 15 show other examples of area A of FIG. 4.

[0162] Referring to FIGS. 11 and 12, this embodiment differs from the embodiments of FIGS. 3 to 9 described above in that the first protrusion (RM_P1) of the second electrode (RME2) is omitted, and the third protrusion (RM_P3) is placed instead of the first concave portion (GR1) of the first electrode (RME1). Hereinafter, descriptions that overlap with the embodiments described above will be omitted, and the differences will be explained.

[0163] The first electrode (RME1) may include a third protrusion (RM_P3) disposed on one side facing the second electrode (RME2). The third protrusion (RM_P3) may protrude toward the second electrode (RME2) from one side of the first electrode (RME1) facing the second electrode (RME2), and may protrude in the opposite direction of the first direction (DR1). The third protrusion (RM_P3) may be disposed spaced apart from the second electrode (RME2) in the first direction (DR1). The third protrusion (RM_P3) may be disposed overlapping with the first connecting part (CP1) connecting the first partition part (BP1) and the second partition part (BP2). The width of the third protrusion (RM_P3) in the second direction (DR2) may be greater than the width of the first connection part (CP1) in the second direction (DR2) and may cover both sides of the first connection part (CP1) in the second direction (DR2). The second electrode (RME2) may be arranged such that one side facing the first electrode (RME1) extends parallel to the second direction (DR2).

[0164] In this embodiment, unlike the embodiments of FIGS. 3 to 9, a third protrusion (RM_P3) protruding from the first electrode (RME1) to the second electrode (RME2) can be provided so that the electrodes (RME) are generally exposed within the opening (OP) of the first insulating layer (PAS1). Accordingly, the application of ink to the center of the light-emitting region (EMA) can be minimized, thereby reducing the number of non-light-emitting light-emitting elements (ED).

[0165] Referring to FIGS. 13 and 14, this embodiment differs from the embodiments of FIGS. 3 to 9 described above in that the second protrusion (RM_P2) of the third electrode (RME3) is omitted, and the fourth protrusion (RM_P4) is placed instead of the second concave portion (GR2) of the first electrode (RME1). Hereinafter, descriptions that overlap with the embodiments described above will be omitted, and the differences will be explained.

[0166] The first electrode (RME1) may include a fourth protrusion (RM_P4) disposed on one side facing the third electrode (RME3). The fourth protrusion (RM_P4) may protrude toward the third electrode (RME3) from one side of the first electrode (RME1) facing the third electrode (RME3) and may protrude in a first direction (DR1). The fourth protrusion (RM_P4) may be disposed spaced apart from the third electrode (RME3) in the first direction (DR1). The fourth protrusion (RM_P4) may be disposed overlapping with a second connecting part (CP2) connecting the first partition part (BP1) and the second partition part (BP2). The width of the fourth protrusion (RM_P4) in the second direction (DR2) may be greater than the width of the second connection part (CP2) in the second direction (DR2), and may cover both sides of the second connection part (CP2) in the second direction (DR2). The third electrode (RME3) may be arranged such that one side facing the first electrode (RME1) extends parallel to the second direction (DR2).

[0167] In this embodiment, unlike the embodiments of FIGS. 3 to 9, a fourth protrusion (RM_P4) protruding from the first electrode (RME1) to the third electrode (RME3) can be provided so that the electrodes (RME) are generally exposed within the opening (OP) of the first insulating layer (PAS1). Accordingly, the application of ink to the center of the light-emitting region (EMA) can be minimized, thereby reducing the number of non-light-emitting light-emitting elements (ED).

[0168] Referring to FIGS. 15 and 16, the present embodiment differs from the embodiments of FIGS. 3 to 9 described above in that the first protrusion (RM_P1) of the second electrode (RME2) and the second protrusion (RM_P2) of the third electrode (RME3) are omitted, the third protrusion (RM_P3) is placed in place of the first concave portion (GR1) of the first electrode (RME1), and the fourth protrusion (RM_P4) is placed in place of the second concave portion (GR2). Hereinafter, descriptions that overlap with the embodiments described above will be omitted, and the differences will be explained.

[0169] The first electrode (RME1) may include a third protrusion (RM_P3) and a fourth protrusion (RM_P4). The third protrusion (RM_P3) may be disposed on one side of the first electrode (RME1) facing the second electrode (RME2). The third protrusion (RM_P3) may protrude toward the second electrode (RME2) from one side of the first electrode (RME1) facing the second electrode (RME2), and may protrude in the opposite direction of the first direction (DR1). The third protrusion (RM_P3) may be disposed spaced apart from the second electrode (RME2) in the first direction (DR1). The third protrusion (RM_P3) may be disposed overlapping with the first connecting part (CP1) connecting the first partition part (BP1) and the second partition part (BP2). The width of the third protrusion (RM_P3) in the second direction (DR2) may be greater than the width of the first connection part (CP1) in the second direction (DR2), and may cover both sides of the first connection part (CP1) in the second direction (DR2).

[0170] The fourth protrusion (RM_4) may be disposed on one side of the first electrode (RME1) facing the third electrode (RME3). The fourth protrusion (RM_P4) may protrude toward the third electrode (RME3) from one side of the first electrode (RME1) facing the third electrode (RME3) and may protrude in the first direction (DR1). The fourth protrusion (RM_P4) may be disposed spaced apart from the third electrode (RME3) in the first direction (DR1). The fourth protrusion (RM_P4) may be disposed overlapping with the second connecting part (CP2) connecting the first partition part (BP1) and the second partition part (BP2). The width of the fourth protrusion (RM_P4) in the second direction (DR2) may be greater than the width of the second connection part (CP2) in the second direction (DR2), and may cover both sides of the second connection part (CP2) in the second direction (DR2). The third electrode (RME3) may be arranged such that one side facing the first electrode (RME1) extends parallel to the second direction (DR2).

[0171] The second electrode (RME2) may be arranged such that one side facing the first electrode (RME1) extends parallel to the second direction (DR2). The third electrode (RME3) may be arranged such that one side facing the first electrode (RME1) extends parallel to the second direction (DR2).

[0172] In this embodiment, unlike the embodiments of FIGS. 3 to 9, a third protrusion (RM_P4) protruding to the second electrode (RME2) and a fourth protrusion (RM_P4) protruding to the third electrode (RME3) are provided on the first electrode (RME1), so that the electrodes (RME) are generally exposed within the opening (OP) of the first insulating layer (PAS1). Accordingly, the application of ink to the center of the light-emitting region (EMA) is minimized, thereby reducing the number of non-light-emitting light-emitting elements (ED).

[0173] FIG. 17 is a plan view showing one subpixel of a display device according to another embodiment. FIG. 18 is a plan view schematically showing the electrodes and partitions of one subpixel of FIG. 17. FIG. 19 is a cross-sectional view taken along the line Q7-Q7' of FIG. 17 and FIG. 18.

[0174] Referring to FIGS. 17 to 19, the present embodiment differs from the embodiments of FIGS. 3 to 9 described above in that the first connection portion (CP1) and the second connection portion (CP2) of the partition wall (BP) are omitted, and a via protrusion (VIP) is formed in the via layer (VIA) to replace the connection portions (CP1, CP2). Hereinafter, descriptions that overlap with the embodiments described above will be omitted, and the differences will be explained.

[0175] Referring to FIGS. 17 through 19, a via layer (VIA) according to one embodiment may include a via protrusion (VIP) protruding in a third direction (DR3). The via protrusion (VIP) may be positioned at the center of a subpixel (SPXn) and may be an island-shaped pattern extending in a first direction (DR1). The via protrusion (VIP) may overlap with a first partition (BP1) and not overlap with a second partition (BP2). The via protrusion (VIP) may be positioned between the second partitions (BP2). The via protrusion (VIP) may overlap with a first protrusion (RM_P1) of a second electrode (RME2) and a second protrusion (RM_P2) of a third electrode (RME3), and the extension direction of the via protrusion (VIP) may be positioned parallel to them. A via protrusion (VIP) may be placed in an area that divides the length of the first partition (BP1) extended in the second direction (DR2). The width of the via protrusion (VIP) in the second direction (DR2) may be smaller than the width of the first protrusion (RM_P1) or the second protrusion (RM_P2) in the second direction (DR2).

[0176] The via protrusion (VIP) may be integrally formed with the via layer (VIA). The via protrusion (VIP) may have a predetermined thickness in the third direction (DR3). The thickness of the via protrusion (VIP) may be smaller than the thickness of the first partition (BP1) and the second partition (BP2). For example, the thickness of the via protrusion (VIP) may be about 1000 Å to about 5000 Å.

[0177] Meanwhile, in FIGS. 17 to 19, via protrusions (VIPs) are shown arranged in an island-like pattern on each subpixel (SPXn), but are not limited thereto and may be a continuous linear arrangement extending to a plurality of adjacent subpixels (SPXn) in the first direction (DR1).

[0178] In this embodiment, by forming a via protrusion (VIP) on the via layer (VIA) to form a step difference between the second electrode (RME2) and the third electrode (RME3), the height of the second and third electrodes (RME2, RME3) within the opening (OP) of the first insulating layer (PAS1) can be formed to be the same as the height of the first insulating layer (PAS1). Accordingly, even if ink in which light-emitting elements (EDs) are dispersed is sprayed into the light-emitting region (EMA), the ink is not applied to the center of the light-emitting region (EMA), thereby minimizing non-light-emitting light-emitting elements (EDs). In addition, the brightness of the subpixel (SPXn) can be improved by increasing the number of effective light-emitting elements (EDs).

[0179] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0180] 10: Display device SUB: Board VIA: Via layer VIP: Via protrusion BP: Bulkhead BP1, 2: First and second bulkhead sections CP1, 2: First and second connecting parts RME1~3: First to third electrodes CNE1~5: 1st to 5th connecting electrodes PAS1~3: 1st to 3rd insulating layers ED: Light-emitting element ED1~4: First to fourth light-emitting elements BNL: Bank layer RM_P1~P4: 1st to 4th protrusions GR1, 2: 1st and 2nd recesses OP: Opening

Claims

Claim 1 A display device comprising: a substrate; a first partition portion extending in one direction disposed on the substrate, a second partition portion adjacent to each other with the first partition portion in between, and a connecting portion connecting the first partition portion and the second partition portions; a first electrode disposed on the first partition portion, a second electrode disposed on any one of the second partition portions, and a third electrode disposed on the other of the second partition portions; a first insulating layer disposed on the partition, the first electrode, the second electrode, and the third electrode; and light-emitting elements disposed between the first electrode and the second electrode and between the first electrode and the third electrode, wherein at least one of the first electrode, the second electrode, and the third electrode includes a protrusion protruding toward another electrode adjacent in a plane, and the first insulating layer includes an opening that exposes the protrusion. Claim 2 In claim 1, the connecting portions extend in the other direction intersecting the one direction and are integrally formed with the first bulkhead portion and the second bulkhead portion. Claim 3 A display device according to claim 1, wherein the connecting portions include a first connecting portion connecting the second partition portion and the first partition portion disposed on one side of the first partition portion, and a second connecting portion connecting the second partition portion and the first partition portion disposed on the other side of the first partition portion. Claim 4 In claim 3, the first connecting part and the second connecting part are spaced apart from each other with the first partition part in between, and are mutually aligned in another direction intersecting the first direction. Claim 5 In claim 3, the display device comprises a first protrusion protruding from the second electrode toward the first electrode and a second protrusion protruding from the third electrode toward the first electrode. Claim 6 A display device according to claim 5, wherein the first protrusion overlaps the first connecting part and the second protrusion overlaps the second connecting part. Claim 7 A display device according to claim 5, wherein the first electrode comprises relatively narrow concave portions, and the concave portions comprise a first concave portion corresponding to the first protrusion and a second concave portion corresponding to the second protrusion. Claim 8 A display device according to claim 7, wherein the end of the first protrusion is disposed within the first concave portion in a planar shape, and the end of the second protrusion is disposed within the second concave portion in a planar shape. Claim 9 In claim 3, the display device comprises a first protrusion protruding from the first electrode toward the second electrode and a second protrusion protruding from the third electrode toward the first electrode. Claim 10 A display device according to claim 9, wherein the first electrode includes a first concave portion having a relatively narrow width, the first concave portion corresponds to the second protrusion, and the end of the second protrusion is disposed within the first concave portion in a planar manner. Claim 11 In claim 3, the display device comprises a first protrusion protruding from the first electrode toward the third electrode and a second protrusion protruding from the second electrode toward the first electrode. Claim 12 A display device according to claim 11, wherein the first electrode includes a first concave portion having a relatively narrow width, the first concave portion corresponds to the second protrusion, and the end of the second protrusion is disposed within the first concave portion in a planar manner. Claim 13 In claim 3, the protrusion comprises a first protrusion protruding from the first electrode toward the second electrode and a second protrusion protruding from the first electrode toward the second electrode, forming a display device. Claim 14 A display device comprising: a substrate; a partition wall disposed on the substrate and including a first partition wall portion extending in one direction and second partition wall portions spaced apart from each other with the first partition wall portion in between; a first electrode disposed on the first partition wall portion, a second electrode disposed on any one of the second partition wall portions, and a third electrode disposed on the other of the second partition wall portions; a first insulating layer disposed on the partition wall, the first electrode, the second electrode, and the third electrode; light-emitting elements disposed between the first electrode and the second electrode, and between the first electrode and the third electrode; and a via layer disposed between the substrate and the partition wall and including a via protrusion protruding toward the first insulating layer, wherein at least one of the first electrode, the second electrode, and the third electrode includes a protrusion protruding toward another electrode adjacent in a planar direction, and the first insulating layer includes an opening that exposes the protrusion. Claim 15 In claim 14, the via protrusion extends in another direction intersecting the one direction and is integrally formed with the via layer. Claim 16 A display device according to claim 14, wherein the via protrusion overlaps with the protrusion, and the extension direction of the via protrusion and the protrusion are parallel. Claim 17 In claim 14, the first electrode includes a relatively narrow concave portion in an area corresponding to the protrusion, and the opening overlaps the concave portion, the protrusion, and the via protrusion, forming a display device. Claim 18 In claim 14, a display device in which the upper surface of the first insulating layer at the opening is aligned and matched with the upper surfaces of the second electrode and the third electrode. Claim 19 A display device according to claim 14, further comprising a bank layer disposed on the first insulating layer and separating a light-emitting region, wherein the via protrusion, the protrusion, and the opening are disposed within the light-emitting region. Claim 20 In claim 19, the light-emitting elements include a first light-emitting element and a second light-emitting element disposed between the first electrode and the second electrode, and a third light-emitting element and a fourth light-emitting element disposed between the first electrode and the third electrode, and further include a first connecting electrode in contact with one end of the first light-emitting element, a second connecting electrode in contact with the other end of the first light-emitting element and one end of the second light-emitting element, a third connecting electrode in contact with the other end of the second light-emitting element and one end of the third light-emitting element, a fourth connecting electrode in contact with the other end of the third light-emitting element and one end of the fourth light-emitting element, and a fifth connecting electrode in contact with the other end of the fourth light-emitting element.

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