Wafer for chip level test and test method using the same

Abstract

A wafer for chip level testing according to one embodiment of the present invention comprises a ceramic wafer having a circular shape and made of ceramic, and a plurality of holder modules provided on the ceramic wafer, each having a single semiconductor chip mounted thereon. Each of the plurality of holder modules includes a mounting groove in which a single semiconductor chip is mounted, a first stopper provided on a first side of the mounting groove to prevent movement of the single semiconductor chip mounted inside the mounting groove, and a second stopper provided on a second side of the mounting groove to prevent movement of the single semiconductor chip mounted inside the mounting groove.

Description

Technology Field

[0001] This specification relates to a wafer for chip-level testing and a method for testing using the same. Background Technology

[0002] Semiconductor chips undergo wafer testing and packaging testing. Wafer testing is a primary test of multiple semiconductor chips on a wafer produced through semiconductor manufacturing processes before packaging; it verifies the chips' functionality to select good products. Once wafer testing is complete, a swaing process is performed to cut the wafer into pieces. The semiconductor chips on the cut wafer undergo a packaging process and are sealed. Packaging testing is a secondary test of the semiconductor chips after packaging is complete.

[0003] As explained earlier, wafer testing is generally performed before the wafer cutting process; the wafer to be tested is fixed onto a probe, and the test can be conducted using a tester. However, there may be cases where testing of the semiconductor chip is required after the wafer cutting process and before the packaging process.

[0004] Conventionally, to test a single semiconductor chip, a separate frame wafer is used to conduct the test on the single semiconductor chip.

[0005] Figure 1 is a diagram showing an example in which a single semiconductor chip is placed on a frame wafer.

[0006] Referring to FIG. 1, the frame wafer (1) may consist of a tape (20) having a circular shape and a ring frame (10) having a ring shape that supports the tape (20) at the outer edge of the tape (20). A single semiconductor chip (30) may be attached to the tape (20) and fixed to the frame wafer (1).

[0007] A frame wafer (1) to which multiple single semiconductor chips (30) are attached must be loaded onto a prober to perform testing with a tester. Since the frame wafer (1) is different from a wafer produced through a semiconductor process, a separate frame prober is required to load the frame wafer (1).

[0008] Since purchasing frame probes incurs additional costs, it is common for users to either not acquire them or to equip only a small number of them. In such cases, there are issues such as the inability to perform tests on a single semiconductor chip or test delays caused by long waiting times. The problem to be solved

[0009] The present invention has the technical objective of providing a chip-level test wafer capable of testing a single semiconductor chip using a general prober, and a method for testing using the same. means of solving the problem

[0010] A wafer for chip level testing according to one embodiment of the present invention comprises a ceramic wafer having a circular shape and made of ceramic, and a plurality of holder modules provided on the ceramic wafer, each having a single semiconductor chip mounted thereon. Each of the plurality of holder modules includes a mounting groove in which a single semiconductor chip is mounted, a first stopper provided on a first side of the mounting groove to prevent movement of the single semiconductor chip mounted inside the mounting groove, and a second stopper provided on a second side of the mounting groove to prevent movement of the single semiconductor chip mounted inside the mounting groove.

[0011] A method for testing using a wafer for chip-level testing according to another embodiment of the present invention includes the steps of: preparing a wafer equipped with a plurality of holder modules; mounting single semiconductor chips on each of the plurality of holder modules; and introducing the wafer on which the single semiconductor chips are mounted into a probe to perform a test on each of the single semiconductor chips. Effects of the invention

[0012] Since the present invention allows wafers for chip-level testing to be handled even with a standard probe, there is no need to add a separate frame probe. Accordingly, the present invention can reduce costs and enables rapid testing of a single semiconductor chip using a standard probe.

[0013] In addition, the present invention allows a wafer for chip-level testing to be applied to single semiconductor chips of various sizes. Brief explanation of the drawing

[0014] Figure 1 is a diagram showing an example in which a single semiconductor chip is placed on a frame wafer. FIG. 2 is a schematic diagram showing a semiconductor device test system according to one embodiment of the present invention. FIG. 3 is a plan view schematically showing a wafer for chip level testing according to one embodiment of the present invention. Figure 4 is a plan view showing the configuration of the holder module of Figure 3. Figure 5 is a cross-sectional view showing an example of I-I' of Figure 4. Figure 6 is a cross-sectional view showing an example of II-II' of Figure 4. Figure 7 is a cross-sectional view showing an example of III-III' of Figure 4. FIG. 8 is a flowchart illustrating a method of testing using a wafer for chip-level testing according to one embodiment of the present invention. Specific details for implementing the invention

[0015] Throughout the specification, identical reference numbers denote substantially identical components. In the following description, detailed descriptions of components and functions known in the art may be omitted if they are not related to the core components of the invention. The meanings of the terms described in this specification should be understood as follows.

[0016] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0017] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0018] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0019] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0020] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0021] Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

[0022] FIG. 2 is a diagram schematically showing the configuration of a semiconductor test system according to one embodiment of the present invention.

[0023] Referring to FIG. 2, a semiconductor test system according to one embodiment of the present invention includes a wafer (Wafer, 100) for chip level testing, a prober (Prober, 200), a probe card (Probe card, 400), and a tester (Tester, 500).

[0024] A wafer (100) for chip-level testing may have multiple single semiconductor chips placed on it. The single semiconductor chips placed on the wafer (100) for chip-level testing may be loaded into a probe (200) and tested by a tester (500).

[0025] The probe (200) can move and align a wafer (100) for chip-level testing to be tested to a test position. To this end, the probe (200) may include a wafer chuck (210) and a chuck transfer device (220).

[0026] The wafer chuck (210) can fix the chip level test wafer (100) so that the tester (500) can test each of the single semiconductor chips placed on the chip level test wafer (100). The wafer chuck (210) may have a vacuum passage formed inside to fix the chip level test wafer (100) by adsorbing it with a vacuum.

[0027] The chuck transfer device (220) can move and align the wafer chuck (210) to a test position. The chuck transfer device (220) can align the wafer chuck (210) to a test position while moving it in the east-west-north-south and up-down directions.

[0028] In one embodiment, the prober (200) may further include a robot arm that takes a wafer (100) for chip level testing out of a cassette and transports it to a wafer chuck (210).

[0029] The probe card (400) can serve to connect the wafer (100) for chip-level testing and the tester (500). Specifically, the probe card (400) includes a plurality of probe needles that contact individual semiconductor chips and can be electrically connected to the individual semiconductor chips through the plurality of probe needles. The probe card (400) can input a test signal generated by the tester (500) to the individual semiconductor chips placed on the wafer (100) for chip-level testing. Additionally, the probe card (400) can receive a measurement signal from the individual semiconductor chips placed on the wafer (100) for chip-level testing and transmit it to the tester (500).

[0030] The tester (500) can generate a test signal to test each of the single semiconductor chips placed on the wafer (100) for chip-level testing, and can transmit the generated test signal to each of the single semiconductor chips through the probe card (400). In addition, the tester (500) can receive a measurement signal from each of the single semiconductor chips placed on the wafer (100) for chip-level testing through the probe card (400).

[0031] A semiconductor test system according to one embodiment of the present invention is characterized by including a wafer (100) for chip-level testing to perform a test on a single semiconductor chip after a cutting process on the wafer is performed and before a packaging process. Hereinafter, the wafer (100) for chip-level testing will be described in more detail with reference to FIGS. 3 to 7.

[0032] FIG. 3 is a plan view schematically showing a wafer for chip level testing according to an embodiment of the present invention, and FIG. 4 is a plan view showing the configuration of the holder module of FIG. 3. FIG. 5 is a cross-sectional view showing an example of I-I' of FIG. 4, FIG. 6 is a cross-sectional view showing an example of II-II' of FIG. 4, and FIG. 7 is a cross-sectional view showing an example of III-III' of FIG. 4.

[0033] Referring to FIGS. 3 to 7, a wafer (100) for chip level testing may include a ceramic wafer (105) and a plurality of holder modules (110).

[0034] The ceramic wafer (105) may have a circular shape similar to a general wafer and may be made of ceramic. Since the ceramic wafer (105) is formed similarly to a general wafer, the semiconductor test system according to one embodiment of the present invention may be able to handle the wafer (100) for chip level testing even in a general prober (200).

[0035] A plurality of holder modules (110) may be provided on a ceramic wafer (105). A single semiconductor chip (120) is disposed on each of the plurality of holder modules (110), and the single semiconductor chip (120) can be fixed on the ceramic wafer (105).

[0036] A plurality of holder modules (110) may be spaced apart from each other on a ceramic wafer (105) at a certain distance. At this time, the plurality of holder modules (110) may be arranged in a line in a first direction (X-axis direction) and a second direction (Y-axis direction) as shown in FIG. 3, but are not necessarily limited thereto.

[0037] In another embodiment, a plurality of holder modules (110) may be arranged in a zigzag shape. In this case, the number of holder modules (110) that can be placed on a ceramic wafer (105) having a circular shape may be increased. Accordingly, the number of single semiconductor chips (120) that can be placed on a wafer (100) for chip level testing may also be increased, so the semiconductor test system according to one embodiment of the present invention can shorten the test time as the number of single semiconductor chips (120) that can be tested at once increases.

[0038] Each of these plurality of holder modules (110) may include a seating groove (125), a first stopper (132), and a second stopper (134) as shown in FIG. 4.

[0039] A single semiconductor chip (120) can be seated in the mounting groove (125). The mounting groove (125) can be formed to be concavely recessed from the upper surface to the lower surface of the ceramic wafer (105). The mounting groove (125) may correspond to the location where the single semiconductor chip (120) to be tested is placed. By having the single semiconductor chip (120) seated in the mounting groove (125), the single semiconductor chip (120) can be prevented from easily detaching.

[0040] The mounting groove (125) can be formed with a planar area larger than that of a typical single semiconductor chip (120). A wafer (100) for chip level testing according to one embodiment of the present invention can enable single semiconductor chips (120) of various sizes to be mounted in the mounting groove (125) by forming the planar area of ​​the mounting groove (125) of the holder module (110) to be larger. Accordingly, the wafer (100) for chip level testing according to one embodiment of the present invention can enable testing of various types of single semiconductor chips (120).

[0041] The first stopper (132) is provided on the first side of the mounting groove (125) and can block the movement of a single semiconductor chip (120) mounted inside the mounting groove (125). Specifically, the first stopper (132) can block the movement of the single semiconductor chip (120) in a first direction (X-axis direction).

[0042] The first stopper (132) can come into contact with the single semiconductor chip (120) on the first side. The first stopper (132) can prevent the single semiconductor chip (120) from moving in the first direction (X-axis direction) by pressing the single semiconductor chip (120) in the first direction (X-axis direction) on the first side that comes into contact with the single semiconductor chip (120).

[0043] At this time, the first stopper (132) may have a first side surface that is inclined, with the upper side protruding more than the lower side. Accordingly, the present invention can reduce the contact area between the first stopper (132) and the single semiconductor chip (120) and minimize damage to the single semiconductor chip (120) from the outside, such as the first stopper (132).

[0044] In one embodiment, each of the plurality of holder modules (110) may further include a first moving groove (152) that guides the first stopper (132) to move in a first direction (X-axis direction). The first moving groove (152) may extend in the first direction (X-axis direction) and be connected to the first side of the seating groove (125). The first stopper (132) may be placed inside the first moving groove (152) and move in the first direction (X-axis direction) along the first moving groove (152) to the seating groove (125).

[0045] In one embodiment, each of the plurality of holder modules (110) may further comprise a first pin spring (142) that elastically supports the first stopper (132). The first pin spring (142) is provided between the inner surface of the first moving groove (152) and the second side of the first stopper (132) to elastically support the first stopper (132). Here, the second side of the first stopper (132) may be the opposite side of the first side that contacts the single semiconductor chip (120). Accordingly, the present invention can improve the fixing force within the mounting groove (125) of the single semiconductor chip (120).

[0046] A second stopper (134) is provided on the second side of the mounting groove (125) to prevent movement of a single semiconductor chip (120) mounted inside the mounting groove (125). Specifically, the second stopper (134) can prevent movement of the single semiconductor chip (120) in a second direction (Y-axis direction).

[0047] The second stopper (134) can come into contact with the single semiconductor chip (120) on the first side. The second stopper (134) can prevent the single semiconductor chip (120) from moving in the second direction (Y-axis direction) by pressing the single semiconductor chip (120) in the second direction (Y-axis direction) on the first side that comes into contact with the single semiconductor chip (120).

[0048] At this time, the second stopper (134) may have a first side surface that is inclined, with the upper side protruding more than the lower side. Accordingly, the present invention can reduce the contact area between the second stopper (134) and the single semiconductor chip (120) and minimize damage to the single semiconductor chip (120) from the outside, such as the second stopper (134).

[0049] In one embodiment, each of the plurality of holder modules (110) may further include a second moving groove (154) that guides the second stopper (134) to move in a second direction (Y-axis direction). The second moving groove (154) may extend in the second direction (Y-axis direction) and be connected to the second side of the seating groove (125). The second stopper (134) may be placed inside the second moving groove (154) and move in the second direction (Y-axis direction) along the second moving groove (154) to the seating groove (125).

[0050] In one embodiment, each of the plurality of holder modules (110) may further be provided with a second pin spring (144) that elastically supports the second stopper (134). The second pin spring (144) is provided between the inner surface of the second moving groove (154) and the second side of the second stopper (134) to elastically support the second stopper (134). Here, the second side of the second stopper (134) may be the opposite side of the first side that contacts the single semiconductor chip (120). Accordingly, the present invention can improve the fixing force within the mounting groove (125) of the single semiconductor chip (120).

[0051] In one embodiment, each of the plurality of holder modules (110) may further include a fixing part (160) for fixing a first stopper (132) and a second stopper (134). The fixing part (160) is provided between the first stopper (132) and the ceramic wafer (105) to fix the first stopper (132) so that it does not detach from the ceramic wafer (105). As shown in FIG. 6, the fixing part (160) may be provided with a groove into which the first stopper (132) can be fitted. At this time, the first stopper (132) may be provided with a protrusion in which the lower portion of each of the third side and the fourth side positioned opposite the third side protrudes. Here, the third side and the fourth side may be positioned between the first side and the second side. The fixing part (160) can prevent the first stopper (132) from detaching from the fixing part (160) by fitting the protrusion of the first stopper (132) into the groove.

[0052] Additionally, the fixing part (160) is provided between the second stopper (134) and the ceramic wafer (105) to fix the second stopper (134) so ​​that it does not detach from the ceramic wafer (105). The fixing part (160) may be provided with a groove into which the second stopper (134) can be fitted. At this time, the second stopper (134) may be provided with a protrusion in which the lower portion of each of the third side and the fourth side positioned opposite the third side protrudes. Here, the third side and the fourth side may be positioned between the first side and the second side. The fixing part (160) can prevent the second stopper (134) from detaching from the fixing part (160) by fitting the protrusion of the second stopper (134) into the groove.

[0053] As shown in FIG. 4, the fixed portion (160) may be formed in an 'L' shape by connecting from the area where the first stopper (132) is placed to the area where the second stopper (134) is placed, but is not necessarily limited thereto. In another embodiment, the fixed portion (160) may include a first fixed portion provided in the area where the first stopper (132) is placed and a second fixed portion provided in the area where the second stopper (134) is placed.

[0054] In a semiconductor device test system according to one embodiment of the present invention, since the wafer (100) for chip-level testing can be handled even with a general probe (200), there is no need to add a separate frame probe. Accordingly, the semiconductor device test system according to one embodiment of the present invention can reduce costs and enables rapid testing of a single semiconductor chip (120) using a general probe (200).

[0055] In addition, the chip level test wafer (100) according to one embodiment of the present invention can be applied to single semiconductor chips of various sizes. Accordingly, the semiconductor device test system according to one embodiment of the present invention can be configured to handle various types of single semiconductor chips with one type of chip level test wafer (100).

[0056] FIG. 8 is a flowchart illustrating a method of testing using a wafer for chip-level testing according to one embodiment of the present invention.

[0057] Referring to FIG. 8, first, a wafer (100) for chip level testing is prepared, which is equipped with a plurality of holder modules (110) (S801). At this time, each of the plurality of holder modules (110) may include a seating groove (125), a first stopper (132), and a second stopper (134) as described in FIG. 3 to 7.

[0058] Next, single semiconductor chips (120) are placed on each of the plurality of holder modules (110) (S801). Specifically, single semiconductor chips (120) can be placed in the mounting groove (125) of each of the plurality of holder modules (110). Here, the single semiconductor chips (120) may be semiconductor chips that have undergone wafer testing, a cutting process for the wafer, and a packaging process. One such single semiconductor chip (120) can be placed on each of the plurality of holder modules (110).

[0059] The first stopper (132) of each of the plurality of holder modules (110) can block movement of a single semiconductor chip (120) in a first direction (X-axis direction). Additionally, the second stopper (134) of each of the plurality of holder modules (110) can block movement of a single semiconductor chip (120) in a second direction (Y-axis direction). Accordingly, each of the single semiconductor chips (120) can be fixed inside the mounting groove (125) by the first stopper (132) and the second stopper (134).

[0060] Next, a chip-level test wafer (100) on which single semiconductor chips (120) are mounted is placed into a probe (200), and a test is performed on each of the single semiconductor chips (120) (S803).

[0061] A wafer (100) for chip-level testing, on which single semiconductor chips (120) are mounted, can be moved to a wafer chuck (210) of a probe (200) by a robot arm. The wafer chuck (210) can be moved and aligned to a test position together with the wafer (100) for chip-level testing by a chuck transfer device (220). Each of the single semiconductor chips (120) can receive a test signal from a tester (500) and perform a test.

[0062] When the test is completed, the single semiconductor chips (120) are removed from the multiple holder modules (110) (S804).

[0063] Those skilled in the art to which the present invention pertains will understand that the above-described invention may be implemented in other specific forms without altering its technical concept or essential features.

[0064] Additionally, the methods described herein may be implemented at least partially using one or more computer programs or components. These components may be provided as a series of computer instructions via a computer-readable or machine-readable medium including volatile and non-volatile memory. The instructions may be provided as software or firmware and may be implemented wholly or partially in hardware configurations such as ASICs, FPGAs, DSPs, or other similar devices. The instructions may be configured to be executed by one or more processors or other hardware configurations, which perform or are capable of performing all or part of the methods and procedures disclosed herein when executing the series of computer instructions.

[0065] Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of the invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the invention. Explanation of the symbols

[0066] 100: Wafer for chip-level testing 105: Ceramic wafer 110: Holder module 125: Seating groove 132: 1st Stopper 134: 2nd Stopper 152: 1st Move Home 154: 2nd Move Home 142: 1st pin spring 144: 2nd pin spring 160: Fixed part

Claims

Claim 1 A wafer for chip level testing, comprising: a ceramic wafer made of ceramic having a circular shape; and a plurality of holder modules provided on the ceramic wafer, each having a single semiconductor chip placed thereon, wherein each of the plurality of holder modules includes: a mounting groove in which the single semiconductor chip is placed; a first stopper provided on a first side of the mounting groove and preventing movement of the single semiconductor chip placed inside the mounting groove; a second stopper provided on a second side of the mounting groove and preventing movement of the single semiconductor chip placed inside the mounting groove; and a fixing part disposed between the ceramic wafer and the first stopper and the second stopper, and connected from an area where the first stopper is disposed to an area where the second stopper is disposed. Claim 2 A wafer for chip level testing according to claim 1, wherein the first stopper blocks movement of the single semiconductor chip in a first direction, and the second stopper blocks movement of the single semiconductor chip in a second direction perpendicular to the first direction. Claim 3 A wafer for chip level testing according to claim 2, further comprising: a first moving groove connected at the first side of the seating groove that guides the first stopper to move in the first direction; and a second moving groove connected at the second side of the seating groove that guides the second stopper to move in the second direction. Claim 4 A wafer for chip level testing according to claim 3, further comprising: a first pin spring provided between the inner surface of the first moving groove and the first stopper and elastically supporting the first stopper; and a second pin spring provided between the inner surface of the second moving groove and the second stopper and elastically supporting the second stopper. Claim 5 A wafer for chip level testing according to claim 1, wherein the fixing part is provided with a groove into which the first stopper and the second stopper can be fitted, thereby fixing the first stopper and the second stopper so as not to detach from the ceramic wafer. Claim 6 In claim 1, the first stopper and the second stopper each have a side in contact with the single semiconductor chip such that the upper side protrudes more than the lower side, forming a wafer for chip level testing. Claim 7 A method for testing using a wafer for chip level testing, comprising: a step of preparing a wafer having a plurality of holder modules, each having a first stopper provided on a first side of a mounting groove and a second stopper provided on a second side, and a fixing part connected from an area where the first stopper is placed to an area where the second stopper is placed; a step of mounting single semiconductor chips on each of the plurality of holder modules; and a step of introducing the wafer on which the single semiconductor chips are mounted into a prober and performing a test on each of the single semiconductor chips. Claim 8 In claim 7, the step of mounting the single semiconductor chips comprises mounting the single semiconductor chips in the mounting grooves provided in each of the plurality of holder modules, a method of testing using a wafer for chip level testing. Claim 9 In claim 7, the step of mounting the single semiconductor chips comprises mounting the single semiconductor chips, using the first stopper to block movement of the mounted single semiconductor chip in a first direction, and using the second stopper to block movement of the mounted single semiconductor chip in a second direction, a method of testing using a wafer for chip level testing. Claim 10 A method for testing using a wafer for chip-level testing, comprising the step of removing the single semiconductor chips from the plurality of holder modules when the above test is completed, in accordance with claim 7. Claim 11 A method of testing using a wafer for chip level testing, wherein the fixing part is provided with a groove into which the first stopper and the second stopper can be fitted, and the first stopper and the second stopper are fixed so as not to detach from the wafer.

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