Controller for power converter and power management integrated circuit

Abstract

The present embodiment relates to the control of a power converter and provides a control technique that reflects the AC component of an error signal into a SAW signal to cancel each other out, in order to minimize the influence of noise entering the feedback loop.

Description

Technology Field

[0001] The present embodiment relates to a power converter. More specifically, it relates to the control of a power converter. Background Technology

[0002] Display devices include power management circuits. Power management circuits are also referred to as Power Management Integrated Circuits, or PMICs for short.

[0003] Power management integrated circuits primarily perform the function of converting and supplying system power, provided by sources such as commercial power sources or batteries, to suit the characteristics of the components included in the display device. For example, if the voltage of the system power differs from the operating voltage of the components, the power management integrated circuit converts the system power voltage before supplying it to each component.

[0004] Power management integrated circuits include a feedback loop to regulate the output voltage supplied to components to a constant level. If noise is introduced into this feedback loop, the output voltage may not be regulated to a constant level and could fluctuate.

[0005] Since display devices generate significant noise during the pixel driving process, there is a high likelihood that noise will enter the feedback loop of power management integrated circuits. Accordingly, various studies are being conducted to minimize the impact of noise on power management integrated circuits. The problem to be solved

[0006] Against this backdrop, the objective of the present embodiment is to provide a technology that minimizes the influence of noise in a power management integrated circuit. In particular, the objective of the present embodiment is to provide a technology that minimizes the influence of noise entering the feedback loop of a power management integrated circuit on the output voltage of the power management integrated circuit. means of solving the problem

[0007] To achieve the aforementioned objective, in one aspect, the present embodiment provides a power converter controller comprising: an error signal generator that generates an error signal according to the difference between a sensing voltage and a reference voltage of a power converter including a power semiconductor; a SAW signal generator that generates a SAW signal; an AC component reflector that reflects the AC component of the error signal into the SAW signal; and a PWM signal generator that generates a Pulse Width Modulation (PWM) signal to control the power semiconductor by comparing the SAW signal and the error signal.

[0008] In another aspect, the present embodiment provides a power management integrated circuit comprising: a power semiconductor included in a power converter; and a controller that transmits a gate signal to the gate of the power semiconductor to regulate the output of the power converter, wherein a capacitor is disposed between the line of an error signal generated according to the difference between the sensing voltage and the reference voltage of the power converter and the line of a SAW signal.

[0009] The output of the power converter can be supplied to a display driver that drives pixels at a constant frame rate. Effects of the invention

[0010] As described above, according to the present embodiment, the influence of noise on a power management integrated circuit can be minimized. In particular, according to the present embodiment, the influence of noise entering the feedback loop of the power management integrated circuit on the output voltage of the power management integrated circuit can be minimized, and the output voltage of the power management integrated circuit can be stably regulated. Brief explanation of the drawing

[0011] FIG. 1 is a configuration diagram of a display device according to one embodiment. FIG. 2 is a configuration diagram of a power converter according to one embodiment. FIG. 3 is a configuration diagram of a controller according to one embodiment. Figure 4 is a main waveform diagram of a controller without an AC component reflector. Figure 5 is a diagram showing that, in one embodiment, the AC component of the error signal is reflected in the signal. FIG. 6 is a main waveform diagram of a controller having an AC component reflector according to one embodiment. FIG. 7 is a configuration diagram of a SAW signal generator and an AC component reflector according to one embodiment. FIG. 8 is a diagram showing an example in which a buffer is further included in a controller according to one embodiment. Specific details for implementing the invention

[0012] FIG. 1 is a configuration diagram of a display device according to one embodiment.

[0013] Referring to FIG. 1, the display device (100) may include a power converter (110), a timing controller (120), a source driver (130), a gate driver (140), and a display panel (150), etc.

[0014] The power converter (110) can supply power to the timing controller (120), source driver (130), gate driver (140), and display panel (150), etc.

[0015] The power converter (110) can supply a first driving voltage (VTM) to the timing controller (120). The timing controller (120) can perform operations on image data using the first driving voltage (VTM).

[0016] The power converter (110) can supply a second driving voltage (VSD) to the source driver (130). The source driver (130) can drive pixels (P) placed on the display panel (150) using the second driving voltage (VSD).

[0017] The power converter (110) can supply a third driving voltage (VGD) to the gate driver (140). The gate driver (140) can generate a scan signal (SCN) using the third driving voltage (VGD).

[0018] The power converter (110) can supply power required for the display panel (150) according to the type of the display panel (150). If the display panel (150) is an LCD (Liquid Crystal Display) panel, the power converter (110) can supply a common voltage to a common electrode placed on the display panel (150).

[0019] When the display panel (150) is an OLED (Organic Light Emitting Diode) panel, the power converter (110) can supply a base voltage to the cathode electrodes of the OLEDs placed on the display panel (150) and can supply a pixel driving voltage to the anode electrodes of the OLEDs.

[0020] The timing controller (120) can process image data received from an external device to suit the characteristics of the display panel (150) and transmit the processed image data (RGB) to the source driver (130). Additionally, the timing controller (120) can transmit a data control signal (DCS) to the source driver (130) to control and set the source driver (130).

[0021] The timing controller (120) can transmit a gate control signal (GCS) to the gate driver (140) to control the scan timing for the display panel (150). Additionally, the timing controller (120) can transmit a power control signal (PCS) to the power converter (110) to control the power converter (110).

[0022] Video data (RGB), data control signal (DCS), gate control signal (GCS), and power control signal (PCS) can be transmitted in frame units. For example, if the frame rate is 120Hz, each signal can be transmitted once every 1 / 120 second, and if the frame rate is 240Hz, each signal can be transmitted once every 1 / 240 second. Such periodic signal transmission by the timing controller (120) can be a noise source for the power converter (110).

[0023] The source driver (130) can convert the grayscale value of each pixel (P) included in the image data (RGB) into a data voltage (VD) and supply it to each pixel (P).

[0024] The source driver (130) can transmit data voltages (VD) on a line-by-line basis. For example, the source driver (130) can select one of a plurality of lines formed on the display panel (150) and simultaneously transmit data voltages (VDs) for pixels placed on that line. Here, the selection of the line can be determined by a scan signal (SCN) transmitted by the gate driver (140).

[0025] Transmission of data voltage (VD) may consume a relatively large amount of power. Furthermore, this large amount of power consumption may occur on a line-by-line basis and may be recognized as a noise source by the power converter (110).

[0026] These various noises in the display device (100) can be introduced into the feedback loop of the power converter (110). Accordingly, the power converter (110) according to one embodiment includes a controller to minimize the influence of these noises on the regulation of output voltages—such as the first driving voltage (VTM), the second driving voltage (VSD), the third driving voltage (VGD), etc.

[0027] FIG. 2 is a configuration diagram of a power converter according to one embodiment.

[0028] Referring to FIG. 2, the power converter (110) may include a power management integrated circuit (210) and a power stage (220), etc.

[0029] The power converter (110) may include an inductor (L), an output capacitor (Co), a first power semiconductor (SW), and a second power semiconductor (D), etc.

[0030] Large passive components such as an inductor (L) and an output capacitor (Co) are placed in the power stage (220), and a first power semiconductor (SW) and a second power semiconductor (D) that can be included in the integrated circuit can be embedded in the power management integrated circuit (210). Alternatively, if necessary, the second power semiconductor (D) can be placed in the power stage (220).

[0031] The first power semiconductor (SW) is a transistor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the second power semiconductor (D) may be a diode. Depending on the embodiment, the second power semiconductor (D) may also be a controllable transistor, in which case the power converter (110) is referred to as a synchronous type.

[0032] Depending on the arrangement and connection relationship of the inductor (L), output capacitor (Co), first power semiconductor (SW), and second power semiconductor (D), the power conversion device (110) may be called a buck converter, a boost converter, a buck-boost converter, a flyback converter, etc. The present embodiment is not limited to such specific types of converters, and can be applied to any device that converts power using power semiconductors. For convenience of explanation, a boost converter will be used as an example for the following description.

[0033] When the first power semiconductor (SW) is turned on, the input voltage (VIN) is applied to the inductor (L), and electrical energy is stored in the inductor (L). Then, when the first power semiconductor (SW) is turned off, the electrical energy stored in the inductor (L) is transferred to the output capacitor (Co) through the second power semiconductor (D), thereby forming an output voltage (VO). At this time, the magnitude of the output voltage (VO) can be adjusted according to the turn-on time of the first power semiconductor (SW).

[0034] The power management integrated circuit (210) may include a controller (212) and a switch circuit (214), and the controller (212) may regulate the output voltage (VO) by periodically turning on and off a first power semiconductor (SW) included in the switch circuit (214).

[0035] The controller (212) can generate a gate signal (VGA) of a first power semiconductor (SW) using the sensing voltage (VFB) and sensing current (ISW) of the power converter (110). The sensing voltage (VFB) can be generated through a feedback resistor (Rfb) placed at the output terminal of the power stage (220), and the sensing current (ISW) can be generated through a sensing resistor (Rsw) connected in series with the first power semiconductor (SW). Here, the sensing voltage (VFB) corresponds to the output voltage (VO) of the power converter (110), and the sensing current (ISW) corresponds to the current flowing through the inductor (L) and the output current of the power converter (110).

[0036] The controller (212) can regulate the output voltage (VO) of the power converter (110) to a constant size using the sensing voltage (VFB), and can regulate the output current of the power converter (110) to a constant size using the sensing current (ISW).

[0037] When a controller (212) regulates the output voltage (VO) of a power converter (110) using only the sensing voltage (VFB), it is called voltage control, and when it regulates the output of a power converter (110) using both the sensing current (ISW) and the sensing voltage (VFB), it is called current control. For convenience of explanation, the following description will focus on examples of voltage control.

[0038] Meanwhile, the sensing voltage (VFB) is obtained through a feedback resistor (Rfb) placed at the output terminal of the power converter (110). If noise occurs in the load connected to the output voltage (VO), the noise can be introduced into the sensing voltage (VFB) through the feedback resistor (Rfb).

[0039] Although not shown in the drawing, noise may be introduced through other paths. For example, noise may be introduced through a control loop compensation circuit included in the controller (212).

[0040] A controller according to one embodiment may include a configuration for eliminating the influence of noise introduced from the outside, for example, noise introduced through a sensing voltage (VFB) or through a control loop compensation circuit.

[0041] FIG. 3 is a configuration diagram of a controller according to one embodiment.

[0042] Referring to FIG. 3, the controller (210) may include an error signal generator (310), a SAW signal generator (320), an AC component reflector (330), a PWM (Pulse Width Modulation) signal generator (340), and a gate controller (350), etc.

[0043] The error signal generator (310) can generate an error signal (Ve) based on the difference between the sensing voltage (VFB) and the reference voltage (Vref) of the power converter including the power semiconductor.

[0044] The error signal generator (310) may include an error amplifier (EA), a control loop compensation circuit (312), etc.

[0045] The error amplifier (EA) can amplify and output the difference between the sensing voltage (VFB) and the reference voltage (Vref). The amplification ratio of the error amplifier (EA) can affect the control loop gain. The designer can increase or decrease the control loop gain by adjusting the amplification ratio of the error amplifier (EA).

[0046] The output of the error amplifier (EA) can be transmitted to the control loop compensation circuit (312). The control loop compensation circuit (312) is a circuit for compensating the control loop gain and may include a plurality of capacitors to form a state. The control loop compensation circuit (312) may be configured as a PID (Proportional Integral Derivative) control circuit using a plurality of capacitors and a plurality of resistors.

[0047] The voltage formed at the output of the error amplifier (EA) connected to the control loop compensation circuit (312) can form an error signal (Ve). Alternatively, the output of the error amplifier (EA) can form an error signal (Ve) by passing through a buffer, etc., described later.

[0048] The SAW signal generator (320) can generate a SAW signal. The SAW signal is a name given in the past because its waveform resembles the shape of a saw tooth, but recently, a signal that is compared with an error signal (Ve) to generate a PWM signal is also called a SAW signal.

[0049] The PWM signal generator (340) can generate a PWM signal (PWM) to control the power semiconductor by comparing the SAW signal and the error signal (Ve).

[0050] And, the gate controller (350) can generate a gate signal (VGA) according to the PWM signal (PWM) and transmit the gate signal (VGA) to the power semiconductor.

[0051] Meanwhile, as mentioned above, noise may be introduced into the sensing voltage (VFB), and this noise may be transmitted as an error signal (Ve) through the error amplifier (EA).

[0052] Alternatively, noise may be introduced through the control loop compensation circuit (312), and this noise may be transmitted as an error signal (Ve) through the error amplifier (EA).

[0053] If the sensing voltage (VFB) or the control loop compensation circuit (312) has a terminal exposed to the outside of the integrated circuit, there is a high possibility of such noise being introduced, but even if that is not the case, noise can be introduced as an error signal (Ve) through various paths.

[0054] When the power converter reaches a stable state, the error signal (Ve) can effectively take the form of DC (direct current). However, if noise is introduced into this error signal (Ve), the noise may appear in the form of AC (alternating current).

[0055] The AC component reflector (330) can reflect the AC component (Ve_ac) from the error signal (Ve) into the SAW signal (SAW) to minimize the influence of noise. In this way, the AC component (Ve_ac) appears in the error signal (Ve) and the AC component (Ve_ac) appears in the SAW signal (SAW), but since these common AC components (Ve_ac) are canceled out by the PWM signal generator (340), they do not affect the PWM signal (PWM).

[0056] To understand the function of the AC component reflector (330), the main waveform in the controller when the AC component reflector (330) is not present and the main waveform in the controller when the AC component reflector (330) is present are compared.

[0057] Figure 4 is a main waveform diagram of a controller without an AC component reflector.

[0058] Referring to FIG. 4, the rising edge of the gate signal (VGA) can be formed according to the set signal (SET). Also, the falling edge of the gate signal (VGA) can be formed according to the rising edge of the PWM signal (PWM). The set signal (SET) occurs at regular intervals, and this period is also referred to as the switching period. The period during which the gate signal (VGA) has a high level (hereinafter referred to as the 'on period') becomes the turn-on time of the power semiconductor, and the output of the power converter is controlled according to the proportion of the gate signal (VGA)'s on period in the switching period.

[0059] Generally, when the output is stable, the ON period of the gate signal (VGA) in each switching cycle is maintained constant. However, as exemplified in the second switching cycle of FIG. 4, if noise is introduced into the error signal (Ve), the ON period of the gate signal (VGA) may vary.

[0060] The falling edge of the gate signal (VGA) is formed according to the rising edge of the PWM signal (PWM), where the rising edge of the PWM signal (PWM) occurs at the moment when the SAW signal (SAW') becomes greater than the error signal (Ve). If the error signal (Ve) has a higher level than the SAW signal (SAW'), the PWM signal (PWM) has a low level, and if the error signal (Ve) has a lower level than the SAW signal (SAW'), the PWM signal (PWM) can have a high level. According to this mode of operation, the rising edge of the PWM signal (PWM) is formed at the moment when the SAW signal (SAW') becomes greater than the error signal (Ve).

[0061] Meanwhile, as shown in the second switching cycle in Fig. 4, when an AC component (Ve_ac) caused by noise appears in the error signal (Ve), the moment when the SAW signal (SAW') becomes larger than the error signal (Ve) changes, and the ON period of the gate signal (VGA) also changes. As seen in Fig. 4, it can be observed that the length of the ON period (T1, T3) of the gate signal (VGA) in the first and third switching cycles without noise is different from the ON period (T2) of the gate signal (VGA) in the second switching cycle with noise.

[0062] For reference, the level of the SAW signal (SAW') may gradually increase at the start of each switching cycle, decrease at the rising edge of the RESET signal, and then increase again at the falling edge of the RESET signal. This falling edge of the RESET signal may mark the start of each switching cycle.

[0063] Meanwhile, a controller according to one embodiment can solve the problem illustrated in FIG. 4 by reflecting the AC component of the error signal into the signal through an AC component reflector.

[0064] Figure 5 is a diagram showing that, in one embodiment, the AC component of the error signal is reflected in the signal.

[0065] Referring to FIG. 5, the controller can generate an original SAW signal (SAW'), extract an AC component (Ve_ac) from an error signal (Ve), and then synthesize the AC component (Ve_ac) with the original SAW signal (SAW') to generate a SAW signal (SAW).

[0066] Unlike the original SAW signal, the SAW signal generated in this way may contain an additional AC component (Ve_ac) corresponding to noise.

[0067] FIG. 6 is a main waveform diagram of a controller having an AC component reflector according to one embodiment.

[0068] Referring to FIG. 6, the rising edge of the gate signal (VGA) can be formed according to the set signal (SET). Also, the falling edge of the gate signal (VGA) can be formed according to the rising edge of the PWM signal (PWM). The set signal (SET) can occur at regular intervals.

[0069] The falling edge of the gate signal (VGA) is formed according to the rising edge of the PWM signal (PWM), where the rising edge of the PWM signal (PWM) occurs at the moment when the SAW signal becomes greater than the error signal (Ve). If the error signal (Ve) has a higher level than the SAW signal (SAW), the PWM signal (PWM) has a low level, and if the error signal (Ve) has a lower level than the SAW signal (SAW), the PWM signal (PWM) can have a high level. According to this mode of operation, the rising edge of the PWM signal (PWM) is formed at the moment when the SAW signal becomes greater than the error signal (Ve).

[0070] The AC component (Ve_ac) of the error signal (Ve) can be reflected in the SAW signal. As shown in the second switching cycle in Fig. 6, when the AC component (Ve_ac) caused by noise appears in the error signal (Ve), the AC component (Ve_ac) also appears in the SAW signal by the AC component reflector.

[0071] Since an AC component (Ve_ac) caused by noise appears in both the error signal (Ve) and the SAW signal being compared, the lengths of the ON periods (T1, T2, T3) of the gate signal (VGA) in each switching cycle become substantially the same.

[0072] FIG. 7 is a configuration diagram of a SAW signal generator and an AC component reflector according to one embodiment.

[0073] Referring to FIG. 7, the SAW signal generator (320) may include a current source (IS), an integrating capacitor (CI), and a reset switch (TR).

[0074] A current source (IS) and an integrating capacitor (CI) constitute a ramp signal generator. A current of a constant magnitude from the current source (IS) can charge the integrating capacitor (CI). Accordingly, the voltage of the integrating capacitor (CI) can increase in the form of a ramp signal. The voltage of the integrating capacitor (CI) can be reset to a reset voltage (Vr) when the reset switch (TR) is turned on. The reset switch (TR) is periodically turned on and off by a reset signal (RESET), and according to the period of this reset signal (RESET), the ramp signal generator can periodically generate a ramp signal. And, according to this period, the integrating capacitor (CI) can be reset to a constant voltage.

[0075] The ramp signal generated by the ramp signal generator may be the original SAW signal shown in FIG. 3 (see SAW' in FIG. 3). The SAW signal generator (320) can generate a SAW signal using this ramp signal.

[0076] In the ramp signal generator, the current source (IS) is connected to one side of the integrating capacitor (CI), and a line transmitting an error signal (Ve) can be connected to the other side of the integrating capacitor (CI).

[0077] The integrating capacitor (CI) can function as a DC blocking capacitor, and the AC component reflector (330) can reflect the AC component into the SAW signal through this DC blocking capacitor. Since the SAW signal is formed on one side of the DC blocking capacitor and a line transmitting the error signal (Ve) is connected to the other side of the DC blocking capacitor, the DC component of the error signal (Ve) is blocked by the DC blocking capacitor, and only the AC component is reflected into the SAW signal.

[0078] As explained above, this embodiment can be applied not only to voltage control but also to current control. When applied to current control, the SAW signal generator (330) can generate a SAW signal by combining the sensing current of the power converter with the ramp signal.

[0079] FIG. 8 is a diagram showing an example in which a buffer is further included in a controller according to one embodiment.

[0080] Referring to FIG. 8, the controller (800) may include an error signal generator (810), a SAW signal generator (320), an AC component reflector (330), a PWM signal generator (340), and a gate controller (350), etc.

[0081] The error signal generator (810) can generate an error signal (Ve) based on the difference between the sensing voltage (VFB) and the reference voltage (Vref) of the power converter including the power semiconductor.

[0082] The error signal generator (810) may include an error amplifier (EA), a control loop compensation circuit (312), a buffer (814), etc.

[0083] The error amplifier (EA) can amplify and output the difference between the sensing voltage (VFB) and the reference voltage (Vref). The amplification ratio of the error amplifier (EA) can affect the control loop gain. The designer can increase or decrease the control loop gain by adjusting the amplification ratio of the error amplifier (EA).

[0084] The output (EAO) of the error amplifier (EA) can be transmitted to the control loop compensation circuit (312). The control loop compensation circuit (312) is a circuit for compensating the control loop gain and may include a plurality of capacitors to form a state. The control loop compensation circuit (312) may be configured as a PID (Proportional Integral Derivative) control circuit using a plurality of capacitors and a plurality of resistors.

[0085] The output (EAO) of the error amplifier (EA) connected to the control loop compensation circuit (312) can form an error signal (Ve) by passing through the buffer (814). The error signal generator (810) can amplify and output the difference between the sensing voltage (VFB) and the reference voltage (Vref) using the error amplifier (EA), buffer the output (EAO) of the error amplifier (EA) using the buffer (814), and generate an error signal (Ve) through the output of the buffer (814).

[0086] The buffer (814) is a device with a high input impedance and a low output impedance. When the buffer (814) is used, the effect of the AC component reflector (330) on the control loop gain can be minimized.

[0087] The AC component reflector (330) may be placed between the output side of the buffer (814) and the SAW signal generator (320). Additionally, the control loop compensation circuit (312) may be connected to the input side of the buffer (814). The AC component reflector (330) may include a capacitor, and the effect of the capacitor included in the AC component reflector (330) on the control loop compensation circuit (312) can be minimized by separation by the buffer (814).

[0088] The description of the SOS signal generator (320), AC component reflector (330), PWM signal generator (340), and gate controller (350) is replaced with the description made with reference to FIGS. 3 to 7.

[0089] As described above, according to the present embodiment, the influence of noise on a power management integrated circuit can be minimized. In particular, according to the present embodiment, the influence of noise entering the feedback loop of the power management integrated circuit on the output voltage of the power management integrated circuit can be minimized, and the output voltage of the power management integrated circuit can be stably regulated.

Claims

Claim 1 A power converter controller comprising: an error signal generator that generates an error signal based on the difference between the sensing voltage and the reference voltage of a power converter including a power semiconductor; a SAW signal generator that generates a SAW signal; an AC component reflector that extracts an AC component included in the error signal and reflects it equally in the SAW signal to provide a common AC component to the SAW signal and the error signal; and a PWM signal generator that compares the SAW signal and the error signal, and generates a PWM (Pulse Width Modulation) signal in which the influence of the AC component is removed by causing the common AC component to cancel each other out. Claim 2 In claim 1, the power converter controller further includes a gate controller that generates a gate signal according to the PWM signal and transmits the gate signal to the power semiconductor, wherein the gate controller forms a rising edge of the gate signal according to a SET signal and forms a falling edge of the gate signal according to the rising edge of the PWM signal. Claim 3 In claim 1, the AC component reflector includes a DC blocking capacitor, and the power converter controller reflects the AC component to the SOS signal through the DC blocking capacitor. Claim 4 In claim 1, the SOS signal generator includes a ramp signal generator that periodically generates a ramp signal, and generates the SOS signal using the ramp signal, the ramp signal generator includes a current source and an integrating capacitor, the current source is connected to one side of the integrating capacitor and the other side of the integrating capacitor is connected to a line through which the error signal is transmitted, and the integrating capacitor is periodically reset to a constant voltage, thereby forming a power converter controller. Claim 5 In paragraph 4, the SOS signal generator is a power converter controller that generates the SOS signal by synthesizing the sensing current of the power converter with the ramp signal. Claim 6 In claim 1, the error signal generator comprises an error amplifier that amplifies and outputs the difference between the sensing voltage and the reference voltage, and a buffer that buffers the output of the error amplifier, and generates the error signal with the output of the buffer, wherein the AC component reflector is disposed between the output side of the buffer and the SAW signal generator, and the error signal generator further comprises a control loop compensation circuit connected to the input side of the buffer. Claim 7 A power semiconductor included in a power converter; and a controller that transmits a gate signal to the gate of the power semiconductor to regulate the output of the power converter, and has a capacitor disposed between the line of an error signal and the line of a SAW signal generated according to the difference between the sensing voltage and the reference voltage of the power converter, wherein the controller extracts an AC component included in the error signal using a current source and the capacitor and reflects it equally in the SAW signal to impart a common AC component to the SAW signal and the error signal, and compares the SAW signal and the error signal, thereby generating a PWM (Pulse Width Modulation) signal in which the influence of the AC component is removed by causing the common AC component to cancel each other out. Claim 8 In claim 7, one side of the capacitor is connected to the current source, and the other side of the capacitor is connected to the line of the error signal, and the controller is a power management integrated circuit that generates the SOS signal by synthesizing the voltage on one side of the capacitor and the sensing current of the power converter. Claim 9 In claim 8, the controller comprises an error amplifier that amplifies and outputs the difference between the sensing voltage and the reference voltage, and a buffer that buffers the output of the error amplifier, and generates the error signal with the output of the buffer, and the capacitor is a power management integrated circuit disposed between a line formed on the output side of the buffer and a line of the SOS signal. Claim 10 In claim 7, a control loop compensation circuit is connected to the line of the error signal, the output of the power converter is supplied to a display driver that drives pixels at a constant frame rate, and the capacitor is a power management integrated circuit that is a DC blocking capacitor that blocks DC components and transmits AC components. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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