Double-sided cooling power module
Patent Information
- Application Number
- KR1020210176417
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-12-10
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2041-12-10
Smart Images

Figure 112021143338874-PAT00009_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a method for manufacturing a double-sided cooling type power module and the power module. Background Technology
[0002] Interest in and development of hybrid and electric vehicles are increasing. These eco-friendly vehicles are equipped with power conversion devices, such as inverters, that convert power supplied from rechargeable batteries or hydrogen fuel cells into power for motor driving.
[0003] This power conversion device is equipped with a power module on which a power semiconductor chip for power conversion is mounted.
[0004] Meanwhile, to reduce the size of the inverter system, a single-phase (2 in 1) molded module is being applied, and to maximize the cooling effect, a double-sided cooling power module capable of cooling on both the upper and lower sides relative to the chip is being developed.
[0005] Among power semiconductors, the development of power modules utilizing SiC devices has recently been active. To achieve high output, multiple SiC MOSFET chips are arranged in parallel, and development is proceeding with the application of double-sided cooling module structural designs to enhance cooling efficiency.
[0006] As shown in FIG. 1, the structure of a conventional double-sided cooling power module has applied a structure called a spacer (4) between the upper source portion of the chip and the upper substrate to secure space for a bonding wire to connect the gate and source signals on the upper surface of the chip (1) to the substrate (2). This spacer (4) structure is made of a Cu-based metal to transmit current and heat, and a thickness of at least 1.2 mm is required to secure space for the bonding wire. As a result, the spacer (4) repeatedly expands and contracts due to the heat generated during the operation of the power module, and the resulting thermal stress is transferred to the upper surface of the chip (1) placed directly below, causing defects or destruction of the device.
[0007] Recently, research has been conducted to remove spacers by deleting wire bonding connections on the top of the chip in order to prevent damage and destruction to the top of the chip caused by such thick spacers.
[0008] However, since the function of the existing signal bonding connection must be implemented through bonding, the bonding material separated into each electrode must be transferred and maintained even after bonding in order for the source electrode and gate signal sections on the top of the chip to be bonded separately.
[0009] The structure for this is as shown in FIG. 2, and for this purpose, a protruding structure with a thickness of at least 0.5 mm (5, protrusion in FIG. 2) is applied, and it is manufactured through the process of FIG. 3 to FIG. 8.
[0010] First, a semiconductor chip (1) is moved using a chuck to an Ag film on which an Ag paste layer is attached by an OCA release agent coating layer on a base film, so that it comes into contact with the Ag paste layer (6) as shown in FIG. 4, and the semiconductor chip (1) is transferred as shown in FIG. 5.
[0011] Then, as shown in FIG. 6, the substrate (2) having the Cu-based protrusion (5) formed thereon is moved using a chuck to come into contact with the Ag bonding layer (7) as in FIG. 7, and the Ag bonding layer (7) is transferred to the protrusion (5) as in FIG. 8. Then, the bond is achieved as in FIG. 2 through pressure sintering.
[0012] Although the structure with the protrusions applied in this manner can eliminate thick metal spacers by removing wire bonding and directly bonding to the chip, since a transfer process is required to transfer the bonding Ag material to the bonding area for direct bonding with the chip, the module manufacturing process proceeds by placing a protruding structure of 0.5 mm or more on the substrate instead of a flat substrate, then transferring the bonding material to the protrusions, and bonding it to the chip.
[0013] In the conventional method, the bonding material of an Ag film can be directly transferred to a pre-separated protrusion that matches the gate electrode and the source electrode. The Ag bonding material transferred separately to the individual electrodes in this way then comes into contact with the top of the chip, and pressure sintering is performed to realize each bond. In other words, the purpose of arranging the protrusion connected to the top of the chip is to transfer the Ag bonding material to the source and gate electrodes divided on the top of the chip.
[0014] There are two main methods for fabricating insulated circuit boards with protrusions: the TPC (Thick Printing Copper) method, which creates the protrusion shape by continuously applying Cu paste, and the method of bonding a metal-based protrusion shape to the insulated circuit board. Among these, the continuous application method of Cu paste, such as TPC, has limitations in achieving the thickness of 500㎛ required for the transfer of the Ag film material for bonding. Therefore, the method of bonding a metal protrusion shape to the substrate is widely used for the transfer and sintering bonding of the Ag film.
[0015] The method of bonding protrusions to a substrate is generally carried out via brazing; therefore, the distribution of voids occurring in the brazing joint must be controlled to a minimum, and the thickness of the substrate including the protrusions must be precisely controlled. If the void distribution is excessive, problems such as reduced electrical and thermal transfer characteristics may occur, and if the thickness is not uniform, non-uniform bonding may occur during pressure sintering after the placement of multiple parallel chips.
[0016] The matters described in the background technology above are intended to aid in understanding the background of the invention and may include matters that are not prior art already known to those skilled in the art to which this technology belongs. Prior art literature
[0017] Korean Patent Publication No. 10-2021-0076862 The problem to be solved
[0018] The present invention has been devised to solve the aforementioned problems, and the purpose of the present invention is to provide a method for manufacturing a double-sided cooling power module and a double-sided cooling power module that can directly bond a chip and a substrate by separately arranging a bonding material on each of the gate and source electrode portions on the upper part of the chip without protrusions. means of solving the problem
[0019] A method for manufacturing a double-sided cooling power module according to one aspect of the present invention comprises the steps of: dividing a bonding material on a base film into two regions and patterning it; placing a semiconductor chip on the patterned bonding material; pressing the semiconductor chip to transfer the patterned bonding material onto one side of the semiconductor chip; placing the bonding material of the semiconductor chip on an upper electrode layer formed on an upper substrate so as to be in contact with it; and pressing and heating the semiconductor chip to sinter the upper bonding layer.
[0020] Here, the upper electrode layer is characterized by having a first region and a second region formed separately and spaced apart.
[0021] And, the step of arranging the bonding material of the semiconductor chip to be in contact is characterized by arranging the two regions of the bonding material to be in contact with the first region and the second region, respectively.
[0022] In addition, the two separated regions of the bonding material are characterized by being formed separately to correspond to the gate electrode and source electrode of the semiconductor chip, respectively.
[0023] And, the patterning step is characterized by removing the area surrounding the two areas of the bonding material.
[0024] In addition, the method further includes the step of placing another side of the semiconductor chip on a lower electrode layer formed on a lower substrate after the step of sintering the upper bonding layer, and the step of applying pressure and heating to the semiconductor chip to sinter the lower bonding layer interposed between the semiconductor chip and the lower electrode layer.
[0025] Next, a method for manufacturing a double-sided cooling power module according to another aspect of the present invention comprises the steps of: arranging a bonding material on a base film to be in contact with an upper electrode layer formed on an upper substrate; transferring the bonding material onto the upper electrode layer by dividing it into two regions and patterning it; arranging one side of a semiconductor chip to be in contact with the patterned bonding material; and sintering the upper bonding layer by applying pressure and heating to the semiconductor chip.
[0026] In addition, the upper electrode layer is characterized by having a first region and a second region formed separately and spaced apart.
[0027] In addition, the step of transferring the bonding material onto the upper electrode layer by dividing it into two regions and patterning them is characterized by patterning the two regions of the bonding material so that they correspond to the first region and the second region.
[0028] In particular, the two separated regions of the bonding material are characterized by being formed separately to correspond to the gate electrode and source electrode of the semiconductor chip, respectively.
[0029] Furthermore, the step of transferring the bonding material onto the upper electrode layer by dividing it into two regions and patterning them is characterized by removing the region surrounding the two regions of the bonding material.
[0030] In addition, the method further includes the step of placing another side of the semiconductor chip on a lower electrode layer formed on a lower substrate after the step of sintering the upper bonding layer, and the step of applying pressure and heating to the semiconductor chip to sinter the lower bonding layer interposed between the semiconductor chip and the lower electrode layer.
[0031] Next, a double-sided cooling power module according to one aspect of the present invention comprises a semiconductor chip, an upper substrate bonded to the upper surface of the semiconductor chip, and a lower substrate bonded to the lower surface of the semiconductor chip, wherein the semiconductor chip is directly bonded to an upper electrode formed on the upper substrate.
[0032] In addition, the bonding material interposed between the upper surface of the semiconductor chip and the upper electrode is characterized by being patterned into two regions.
[0033] Alternatively, the upper electrode layer is characterized in that the first region and the second region are spaced apart and separated, and the two regions of the bonding material are in contact with the first region and the second region, respectively.
[0034] In addition, the two separated regions of the bonding material are characterized by being formed separately to correspond to the gate electrode and source electrode of the semiconductor chip, respectively.
[0035] Meanwhile, the upper electrode layer is characterized by having a groove formed on the surface adjacent to the upper bonding layer, which is not bonded to the upper bonding layer.
[0036] In addition, the depth of the groove is 50㎛ or more, and the linear distance in the plane direction from the end of the groove to the end of the semiconductor chip is 100㎛ or more. Effects of the invention
[0037] The effects that can be obtained by implementing the ultra-thin power module proposed in the present invention are as follows.
[0038] Unnecessary structures such as protrusions or spacers between the chip and the substrate can be eliminated, thereby maximizing the dissipation of heat generated during chip operation, improving thermal conductivity, and lowering the module operating temperature.
[0039] When analyzing the heat distribution for each module structure based on a unit structure cell with only one chip, the maximum chip surface temperature is 102.7°C for the thin structure proposed in the present invention. This value is 3.5% lower than the value of 106.4°C for the Cu-based alloy protrusion structure and 8% lower than the value of 110.1°C for the structure with a Cu-based spacer. This reduction in maximum temperature can be interpreted as a result of lowering thermal stress.
[0040] (Total cell size 20 x 20 mm², 5 x 5 mm² SiC chip center placement, device heat generation 2.16E10 W / ㎥, cooling water temperature 65℃)
[0041] In addition, in the case of the thin module, the total thickness of the module can be reduced to 2.1 mm or less by eliminating unnecessary structures, and through this, it can be calculated that the thermal resistance characteristics of the module in the vertical direction are reduced by 23% compared to the protruding structure module and by 27% compared to the spacer-applied structure module.
[0042] In addition, the removal of unnecessary structures shortens the distance between the chip and the power terminal, which can improve the module's electrical characteristics, such as on-resistance and inductance.
[0043] In addition, since the proposed technology can eliminate unnecessary structures existing between the chip and the substrate, the material cost of said structures can be eliminated and the process cost for implementing said structures can be reduced, thereby improving the cost competitiveness of the module. Brief explanation of the drawing
[0044] Figures 1 and 2 illustrate examples of conventional power modules. FIGS. 3 to 8 sequentially illustrate the manufacturing process of the power module of FIG. 2. FIG. 9 illustrates a double-sided cooling power module according to one embodiment of the present invention. FIGS. 10 to 19 sequentially illustrate the manufacturing process of a double-sided cooling type power module according to the first embodiment of the present invention. FIGS. 20 to 24 sequentially illustrate the manufacturing process of a double-sided cooling power module according to a second embodiment of the present invention. FIG. 25 illustrates a double-sided cooling power module according to an application embodiment of the present invention. Specific details for implementing the invention
[0045] In order to fully understand the present invention, the operational advantages of the present invention, and the objectives achieved by the implementation of the present invention, reference must be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described therein.
[0046] In describing preferred embodiments of the present invention, known technologies or repetitive descriptions that may unnecessarily obscure the essence of the invention will be shortened or omitted.
[0047] FIG. 9 illustrates a double-sided cooling type power module according to one embodiment of the present invention, and FIGS. 10 to 19 sequentially illustrate the manufacturing process of a double-sided cooling type power module according to a first embodiment of the present invention.
[0048] Hereinafter, a first embodiment of a double-sided cooling type power module and a method for manufacturing a double-sided cooling type power module according to an embodiment of the present invention will be described with reference to FIGS. 9 to 19.
[0049] In this invention, to realize a double-sided cooling power module, thick spacers or protruding structures arranged for the purpose of electrical and thermal connection between the top of the chip and the top substrate are eliminated, and a thin module structure is proposed that directly connects the top electrode portion of the chip with the electrode portion of the top circuit board.
[0050] In order to eliminate the protrusions that performed the transfer function of bonding materials in the existing module structure and to directly bond the top of the chip and the electrode portion of the top substrate, this proposal proposes a method to directly transfer an Ag material for chip-substrate bonding to the top surface of the chip or the electrode portion of the top substrate. Two transfer methods are proposed: one is a method in which parts of the bonding material present on the Ag film that are not needed for bonding are removed using a block, and then the remaining bonding material remaining on the film is transferred to the top of the chip. The other is a method in which the bonding material is transferred to the top substrate by applying heat and pressure to a protruding block on the back surface of the bonding Ag film.
[0051] If a bonding material can be separately placed on each of the gate and source electrode portions located on the upper part of the chip in this manner, direct bonding between the chip and the substrate can be achieved even without the presence of protrusions.
[0052] If the substrate and the chip can be directly bonded without protrusions, the current and heat transfer paths can be shortened, which can improve module characteristics and eliminate problems caused by the formation of protrusions in advance.
[0053] A double-sided cooling power module according to one embodiment of the present invention for this purpose has ceramic substrates (21, 31) stacked on top of and bottom of a semiconductor chip (10) as shown in FIG. 1, and is directly bonded to electrode layers (22, 32) formed on the ceramic substrates (21, 31) by bonding layers (40, 50, Ag sintering layer) without spacers.
[0054] The method for manufacturing a double-sided cooling power module according to the first embodiment is a method of removing parts of the bonding material present in an Ag film that are not necessary for bonding using a block, and then transferring the remaining bonding material remaining in the film to the top of the chip.
[0055] First, to form an upper bonding layer (40) as shown in FIG. 10, a block of a certain shape is placed above a bonding material (41) coated on a base film, and as shown in FIG. 11, the block is lowered to come into contact with the bonding material (41) and the block is pressed and heated.
[0056] The block is a block patterned in a certain shape, having a protrusion (b1) protruding from a flat plate as shown in FIG. 11, and the protrusion (b1) surrounds and partitions two regions, and the two regions (s1, s2) are formed separately corresponding to the gate electrode and source electrode of the semiconductor chip (10).
[0057] Accordingly, as shown in FIG. 12, the bonding material (42) in the area corresponding to the protrusion (b1) of the block is transferred to the block, and an upper bonding layer (40-1, 40-2) corresponding to the two areas (s1, s2) of the block and separated into two areas remains on the base film.
[0058] Next, a semiconductor chip (10) is placed on the upper side of the patterned upper bonding layer (40) using a chuck as shown in FIG. 13, and lowered as shown in FIG. 14 so that the semiconductor chip (10) comes into contact with the upper bonding layer (40) and is then pressed and heated.
[0059] Next, as shown in Fig. 15, the upper junction layer (40-1, 40-2) is transferred onto the semiconductor chip (10).
[0060] Next, as shown in FIG. 16, a semiconductor chip (10) is placed on an upper substrate (21) having upper electrode layers (22) formed on both sides, and the upper bonding layers (40-1, 40-2) are oriented toward the upper substrate (21).
[0061] Here, the upper electrode layer (22) is formed with a first region (22-1) and a second region (22-2) spaced apart, and as shown in FIG. 17, the semiconductor chip (10) is positioned downward so that the two regions of the upper bonding layer (40) each come into contact with the first region (22-1) and the second region (22-2).
[0062] Then, as shown in FIG. 18, the upper part of the semiconductor chip (10) is pressed using a heating jig to sinter the upper bonding layer (40).
[0063] Likewise, a lower surface of a semiconductor chip (10) is positioned by interposing a lower bonding layer (50) on a lower electrode layer (32) formed on a lower substrate (31), and the lower surface of the semiconductor chip (10) is pressed to sinter the lower bonding layer (50), thereby manufacturing a power module as shown in FIG. 9.
[0064] The module structure proposed in this invention aims to implement a double-sided cooling type module by directly bonding the upper surface of the chip to the substrate, thereby eliminating the reduction in heat exchange performance caused by the presence of structures such as spacers or protrusions, and proposing a thin power module structure in which the cooling unit and the chip are close together.
[0065] It is a double-sided cooling power module structure composed of two or more transistors capable of on / off control, with insulating circuit boards present on the upper and lower parts of the chip, respectively.
[0066] The structure involves the upper gate electrode and source electrode of the chip being directly bonded to the electrode of the upper substrate. The bonding method may utilize processes such as Ag sintering or soldering. The present invention proposes a pressure-type Ag sintering bond that eliminates issues of bonding material bleeding and high-temperature defects.
[0067] Next, FIGS. 20 to 24 sequentially illustrate the manufacturing process of a double-sided cooling power module according to a second embodiment of the present invention.
[0068] The method for manufacturing a double-sided cooling power module according to the second embodiment is a method in which a protruding block is applied to the back surface of a bonding Ag film with heat and pressure to transfer a bonding material to an upper substrate.
[0069] First, to form an upper bonding layer (40) as shown in FIG. 20, a bonding material (41) coated on a base film is placed on an upper substrate (21) on which an upper electrode layer (22) is formed, so as to face the upper substrate (21), and a block of a certain shape is placed on the upper side of the base film, and the block is lowered as shown in FIG. 21 so that the block, the bonding material (41), and the upper substrate (21) come into contact, and the block is pressed and heated.
[0070] The block is a block patterned in a certain shape, having two protrusions (b2) that protrude from a flat plate and are spaced apart from each other as shown in FIG. 21, and the two regions are formed separately corresponding to the gate electrode and source electrode of the semiconductor chip (10).
[0071] Here, the upper electrode layer (22) is also formed with a first region (22-1) and a second region (22-2) separated and spaced apart, and the two regions of the block correspond to the first region (22-1) and the second region (22-2), respectively.
[0072] Accordingly, as shown in FIG. 22, the area corresponding to the protrusion of the block is transferred to the upper electrode layer (22) to form the upper bonding layer (40-1, 40-2), and the bonding material (42) that was not transferred remains on the base film.
[0073] Next, a semiconductor chip (10) is placed on the upper side of the upper bonding layer (40), which is patterned and divided into two regions as shown in FIG. 23, using a chuck, and lowered as shown in FIG. 24 so that the semiconductor chip (10) comes into contact with the upper bonding layer (40-1, 40-2) and is then pressed and heated.
[0074] Next, the upper substrate (21) and the lower substrate (31) are sequentially pressed in the same manner as in FIGS. 16 and 17 to sinter the upper bonding layer (40-1, 40-2) and the lower bonding layer (50), thereby manufacturing a power module as shown in FIG. 9.
[0075] Next, FIG. 25 illustrates a double-sided cooling power module according to an application embodiment of the present invention, and only the parts that differ from the previously described embodiment will be explained.
[0076] When the upper electrode layer (22) formed on the upper substrate (21) is bonded to the upper part of the chip (10), a thin bonding portion is formed between the chip (10) and the substrate (21), so insulation problems such as a short circuit may occur between the end of the chip (10) and the electrode layer (22) of the upper substrate (21). To prevent this, in the application embodiment, a groove structure with a step is arranged around the electrode layer (22) of the upper substrate (21) that is bonded to the chip (10), thereby securing a distance that allows for insulation between the electrode layer (22) of the upper substrate and the end of the chip (10).
[0077] That is, a groove (23) is formed on the upper electrode layer (22) adjacent to the upper bonding layer (40), and the groove (23) may have a cross-section that is square or circular, etc.
[0078] In the case of general EMC (Epoxy Molding Compound) materials, the dielectric breakdown strength characteristic is approximately 40 V / ㎛, so insulation of approximately 1000 V is possible based on a thickness of 25㎛ for the pressure sintered joint, but this is not suitable for withstand voltages of 1200 V or higher.
[0079] Therefore, it is necessary to widen the gap so that a thickness greater than that of the sintered joint can be maintained between the electrodes, and it is necessary to secure a gap so that insulation of 2000V or more can be secured by assuming EMC filling between the end portion of the chip (10) and the electrode layer (22) of the upper substrate (21). To this end, in the present proposal, a groove structure with a step is arranged around the electrode portion of the upper substrate that is bonded to the chip to secure insulation characteristics, and the depth of the groove (23) may vary depending on the difference in characteristics of the insulating material such as EMC, but it is preferable that the depth be 50㎛ or more so that insulation of 2000V or more can be secured, and a recess is formed at a position of 100㎛ or more on the upper surface of the chip (10) so that the end portion of the chip (10) can maintain insulation.
[0080] That is, it is preferable that the length from the end of the groove (23) to the end of the upper bonding layer (40) to the end of the semiconductor chip (10) be 100 μm or more.
[0081] Meanwhile, for the electrical circuit configuration of the module, the upper substrate (21) and the lower substrate (31) can be connected by an electrical connection, and such connection can be implemented by placing structures such as chip elements or spacers. For this purpose, a bonding process such as Ag sintering or soldering can be utilized.
[0082] In addition, the power terminal can be connected to the upper or lower substrate by sintering, soldering, or welding, and the signal pin terminal can be bonded to the substrate or connected between the signal terminal and the substrate by wire bonding, etc.
[0083] Although the present invention has been described above with reference to the illustrated drawings, it is obvious to those skilled in the art that it is not limited to the described embodiments and can be modified and varied in various ways without departing from the spirit and scope of the invention. Accordingly, such modifications or variations should be deemed to fall within the scope of the claims of the present invention, and the scope of rights of the present invention should be interpreted based on the appended claims. Explanation of the symbols
[0084] 10 : Semiconductor chip 21: Upper substrate 22 : Upper electrode layer 31: Lower substrate 32: Lower electrode layer 40: Upper bonding layer 50 : Lower bonding layer
Claims
Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 A double-sided cooling power module comprising: a semiconductor chip; an upper substrate bonded to the upper surface of the semiconductor chip; and a lower substrate bonded to the lower surface of the semiconductor chip, wherein the semiconductor chip is directly bonded to an upper electrode formed on the upper substrate, and wherein a bonding material interposed between the upper surface of the semiconductor chip and the upper electrode is patterned by being divided into two regions, wherein the upper electrode layer is formed with a first region and a second region separated and the two regions of the bonding material are in contact with the first region and the second region, respectively, and wherein a groove is formed on a surface adjacent to the bonding material that is not bonded to the bonding material of the upper electrode layer, and wherein the groove is not bonded to the semiconductor chip. Claim 14 delete Claim 15 delete Claim 16 A double-sided cooling power module according to claim 13, characterized in that the two separated regions of the bonding material are each formed to correspond to the gate electrode and source electrode of the semiconductor chip. Claim 17 delete Claim 18 A double-sided cooling power module according to claim 13, characterized in that the depth of the groove is 50 μm or more, and the linear distance in the plane direction from the end of the groove to the end of the semiconductor chip is 100 μm or more.
Citation Information
Patent Citations
Substrate structure in internal power module and manufacturing method thereof
JP2020205410A
Power module of double-faced cooling and method for manufacturing thereof
KR1020190110376A