Display device

Abstract

A display device is provided. The display device comprises a substrate, data lines disposed on the substrate to which data voltages are applied, scan lines disposed on the substrate to which scan signals are applied, and a pixel connected to any one of the data lines and at least one of the scan lines. The pixel comprises a light-emitting element, a driving transistor that supplies a driving current flowing between a first electrode and a second electrode to the light-emitting element according to the data voltage of the data lines applied to a gate electrode, a first transistor disposed between the gate electrode and the second electrode of the driving transistor, and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data lines.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. For example, display devices are being applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. Display devices may be flat panel displays, such as Liquid Crystal Display Devices, Field Emission Display Devices, and Light Emitting Display Devices.

[0003] Since each pixel of the display panel includes a light-emitting element capable of emitting light on its own, the light-emitting display device can display an image without a backlight unit that provides light to the display panel. Each pixel of the light-emitting display device may include a light-emitting element, a driving transistor that controls the amount of driving current supplied to the light-emitting element from a driving voltage line according to the data voltage of a data line applied to a gate electrode, and a plurality of switching transistors that turn on in response to a scan signal of a scan line. At this time, among the plurality of switching transistors, a switching transistor positioned adjacent to the data line may be affected by changes in the voltage of the data line. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device that can prevent or reduce the influence of a switching transistor placed adjacent to a data line on voltage changes of the data line.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] In one embodiment for solving the above problem, a display device comprises a substrate, data lines disposed on the substrate to which data voltages are applied, scan lines disposed on the substrate to which scan signals are applied, and a pixel connected to any one of the data lines and at least one of the scan lines. The pixel comprises a light-emitting element, a driving transistor that supplies a driving current flowing between a first electrode and a second electrode to the light-emitting element according to the data voltage of the data lines applied to a gate electrode, a first transistor disposed between the gate electrode and the second electrode of the driving transistor, and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data lines.

[0007] The device further comprises first driving voltage lines disposed on the substrate to which a first driving voltage is applied, wherein the pixel is connected to any one of the first driving voltage lines, and the shielding electrode may be connected to the first driving voltage line.

[0008] The first transistor may include a first-1 transistor comprising a gate electrode connected to any one of the at least one scan wiring and a second electrode connected to the gate electrode of the driving transistor, and a first-2 transistor comprising a gate electrode connected to the scan wiring and a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the first electrode of the first-1 transistor.

[0009] The shielding electrode can overlap the first electrode of the first-1 transistor and the first-2 drain electrode of the first-2 transistor in the thickness direction of the substrate.

[0010] The pixel may further include a second transistor that supplies the data voltage of the data wiring to the gate electrode of the driving transistor, and a third-1 transistor comprising a gate electrode connected to another scan wiring among the at least one scan wiring and a source electrode connected to the gate electrode of the driving transistor.

[0011] The shielding electrode may include a connection portion that extends in one direction and is connected to the first driving voltage wiring, a protrusion portion that extends from the connection portion in another direction intersecting the one direction, and a shielding portion that protrudes from the protrusion portion and overlaps the first electrode of the first-1 transistor and the second electrode of the first-2 transistor in the thickness direction of the substrate.

[0012] The above connection is positioned between the scan line and the other scan line in the above one direction and may not overlap with the scan line and the other scan line in the thickness direction of the substrate.

[0013] The above protrusion is adjacent to the data wiring adjacent to the pixel among the data wirings in the other direction, and can overlap with the data wiring adjacent to the pixel in the thickness direction of the substrate.

[0014] The above shielding part may be extended in the above one direction.

[0015] The above protrusion may be adjacent to the data wiring adjacent to the pixel among the data wirings in the other direction, and may not overlap with the data wiring adjacent to the pixel in the thickness direction of the substrate.

[0016] The pixel further includes a first connecting electrode that connects the gate electrode of the driving transistor and the second electrode of the first-1 transistor and is disposed on the same layer as the data wiring, and the first connecting electrode may be adjacent to the connecting part in one direction and adjacent to the protrusion in the other direction.

[0017] The first driving voltage wiring includes a first sub-driving voltage wiring extending in one direction and a second sub-driving voltage wiring extending in another direction intersecting the one direction, and the shielding electrode may be connected to the first sub-driving voltage wiring.

[0018] The scan wiring and the gate electrode of the driving transistor are disposed on a gate insulating film disposed on the substrate, the shielding electrode and the second sub-driving voltage wiring are disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first and second electrodes of the driving transistor are disposed on a second interlayer insulating film disposed on the shielding electrode and the second sub-driving voltage wiring, and the data wiring may be disposed on a first organic film disposed on the first sub-driving voltage wiring and the first and second electrodes of the driving transistor.

[0019] The first sub-driving voltage wiring can be connected to the shielding electrode through a first contact hole penetrating the second interlayer insulating film.

[0020] The shielding electrode is disposed on the substrate, the scan wiring and the gate electrode of the driving transistor are disposed on a buffer film disposed on the shielding electrode, the second sub-driving voltage wiring is disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first and second electrodes of the driving transistor are disposed on a second interlayer insulating film disposed on the second sub-driving voltage wiring, and the data wiring may be disposed on a first organic film disposed on the first sub-driving voltage wiring and the first and second electrodes of the driving transistor.

[0021] The first sub-driving voltage wiring can be connected to the shielding electrode through a first contact hole penetrating the buffer film, the buffer film, the first interlayer insulating film, and the second interlayer insulating film.

[0022] The pixel further includes a second transistor that supplies the data voltage to the gate electrode of the driving transistor, and a data connection electrode that connects the data wiring and the first electrode of the second transistor, and the shielding electrode may overlap with the data connection electrode in the thickness direction of the substrate.

[0023] The shielding electrode may include a protrusion extending in a different direction intersecting the first sub-driving voltage wiring, and a shielding portion extending from the protrusion and overlapping with at least a portion of the first transistor in the thickness direction of the substrate.

[0024] The above shielding electrode can be electrically floating.

[0025] The shielding electrode can be positioned apart from the first driving voltage wiring.

[0026] The first driving voltage wiring includes a first sub-driving voltage wiring extending in one direction and a second sub-driving voltage wiring extending in another direction intersecting the one direction, and the shielding electrode may protrude from the second sub-driving voltage wiring.

[0027] The shielding electrode can be extended in the above one direction.

[0028] The shielding electrode may intersect with at least one scan wire.

[0029] The scan wiring and the gate electrode of the driving transistor may be disposed on a gate insulating film disposed on the substrate, the second sub-driving voltage wiring may be disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first and second electrodes of the driving transistor may be disposed on a second interlayer insulating film disposed on the second sub-driving voltage wiring, and the data wiring and the shielding electrode may be disposed on a first organic film disposed on the first sub-driving voltage wiring and the first and second electrodes of the driving transistor.

[0030] The shielding electrode can be connected to the second sub-driving voltage wiring through a first contact hole penetrating the first organic film and the second interlayer insulating film.

[0031] In one embodiment for solving the above problem, the display device comprises a light-emitting element, a driving transistor that supplies a driving current flowing between a first electrode and a second electrode according to a data voltage of a data line applied to a gate electrode to the light-emitting element, a first transistor disposed adjacent to another data line adjacent to the data line, and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data line and the other data line.

[0032] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0033] According to the display device of the embodiments, the shielding electrode may overlap with at least a portion of the transistor positioned adjacent to the data wiring in the thickness direction of the substrate. In this case, the shielding electrode may be positioned between the transistor positioned adjacent to the data wiring and the data wiring to act as a barrier. Therefore, the first electrode or the second electrode of the transistor positioned adjacent to the data wiring may be reduced from being affected by the data voltage transition of the data wiring.

[0034] In addition, according to the display device of the embodiments, by reducing the overlapping area of ​​the shielding electrode and the data wiring in the thickness direction of the substrate or by arranging the shielding electrode and the data wiring so that they do not overlap, the parasitic capacitance formed between the shielding electrode and the data wiring can be reduced. Therefore, the influence of the shielding electrode and the first driving voltage wiring on the data voltage transition of the data wiring can be reduced.

[0035] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0036] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a plan view showing a display device according to one embodiment. FIG. 3 is a block diagram showing a display device according to one embodiment. FIG. 4 is a circuit diagram showing a subpixel in detail according to one embodiment. FIG. 5 is a plan view showing a subpixel in detail according to one embodiment. Figure 6 is a plan view showing area A of Figure 5 in detail. Figure 7 is a cross-sectional view showing an example of I-I' of Figure 5. FIG. 8 is a cross-sectional view showing an example of II-II' of FIG. 5. Figure 9 is an example diagram showing horizontal crosstalk that occurs when a shielding electrode overlaps with data wiring. FIG. 10 is a plan view showing a subpixel in detail according to another embodiment. Figure 11 is a plan view showing area B of Figure 10 in detail. FIG. 12 is a cross-sectional view showing an example of III-III' of FIG. 10. FIG. 13 is a plan view showing a subpixel in detail according to another embodiment. Figure 14 is a plan view showing the area C of Figure 13 in detail. FIG. 15 is a cross-sectional view showing an example of IV-IV' of FIG. 13. FIG. 16 is a cross-sectional view showing another example of Ⅳ-Ⅳ' of FIG. 13. FIG. 17 is a plan view showing a subpixel in detail according to another embodiment. Figure 18 is a plan view showing the D region of Figure 17 in detail. FIG. 19 is a cross-sectional view showing another example of V-V' of FIG. 17. FIG. 20 is a plan view showing a subpixel in detail according to another embodiment. FIG. 21 is a plan view showing the D region of FIG. 20 in detail. FIG. 22 is a cross-sectional view showing an example of VI-VI' of FIG. 20. FIG. 23 is a plan view showing a subpixel in detail according to another embodiment. FIG. 24 is a plan view showing the area E of FIG. 23 in detail. FIG. 25 is a cross-sectional view showing an example of Ⅶ-Ⅶ' of FIG. 23. FIG. 26 is a plan view showing a subpixel in detail according to another embodiment. Figure 27 is a plan view showing the F region of Figure 26 in detail. FIG. 28 is a cross-sectional view showing an example of Ⅷ-Ⅷ' of FIG. 26. Specific details for implementing the invention

[0037] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0038] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0039] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0040] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0041] Specific embodiments will be described below with reference to the attached drawings.

[0042] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a plan view showing a display device according to one embodiment. FIG. 3 is a block diagram showing a display device according to one embodiment.

[0043] In the present specification, the first direction (X-axis direction) may be a direction parallel to the short side of the planar display device (10), for example, the horizontal direction of the display device (10). The second direction (Y-axis direction) may be a direction parallel to the long side of the planar display device (10), for example, the vertical direction of the display device (10). The third direction (Z-axis direction) may be the thickness direction of the display panel (100).

[0044] Referring to FIGS. 1 to 3, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0045] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro light-emitting diode (LED). Although the following description focuses on the display device (10) being an organic light-emitting display device, the present invention is not limited thereto.

[0046] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0047] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) that intersects the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0048] The display panel (100) may include a main area (MA) and a sub area (SA). The main area (MA) may include a display area (DA) in which sub pixels (SP) are formed to display an image, and a non-display area (NDA) which is a peripheral area of ​​the display area (DA). In the display area (DA), not only the sub pixels (SP) but also scan lines (SL), light-emitting lines (EL), data lines (DL), and a first driving voltage line (VDDL) connected to the sub pixels (SP) may be arranged.

[0049] Scan lines (SL) and light-emitting lines (EL) can be formed parallel to each other in a first direction (X-axis direction). Data lines (DL) can be formed parallel to each other in a second direction (Y-axis direction) that intersects the first direction (X-axis direction).

[0050] The first driving voltage wiring (VDDL) may be formed parallel to the second direction (Y-axis direction) in the display area (DA). The first driving voltage wiring (VDDL) formed parallel to the second direction (Y-axis direction) in the display area (DA) may be connected to each other in the non-display area (NDA). Alternatively, the first driving voltage wiring (VDDL) may include a first sub-driving voltage wiring formed parallel to the second direction (Y-axis direction) in the display area (DA) and a second sub-driving voltage wiring formed parallel to the first direction (X-axis direction).

[0051] Each of the subpixels (SP) may be connected to at least one of the scan lines (SL), any one of the data lines (DL), at least one of the light-emitting lines (EL), and the first driving voltage line (VDDL). FIG. 2 illustrates that each of the subpixels (SP) is connected to two scan lines (SL), one data line (DL), one light-emitting line (EL), and the first driving voltage line (VDDL), but is not limited thereto. For example, each of the subpixels (SP) may be connected to three scan lines (SL) instead of two scan lines (SL).

[0052] Each of the subpixels (SP) may include a driving transistor, at least one transistor (ST1, ST2, ST3, ST4, ST5, ST6 in FIG. 4), a light-emitting element, and a capacitor. The transistor is turned on when a scan signal is applied from the scan line (SL), thereby allowing the data voltage of the data line (DL) to be applied to the gate electrode of the driving transistor (DT). The driving transistor (DT) can emit light by supplying a driving current to the light-emitting element according to the data voltage applied to the gate electrode. The driving transistor (DT) and at least one transistor (ST) may be thin film transistors. The light-emitting element may emit light according to the driving current of the driving transistor (DT). The light-emitting element may be an organic light-emitting diode comprising a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may serve to maintain the data voltage applied to the gate electrode of the driving transistor (DT) for a predetermined period.

[0053] The non-display area (NDA) can be defined as the area extending from the outside of the display area (DA) to the edge of the display panel (100). In the non-display area (NDA), a scan driver (400) for applying scan signals to scan lines (SL), fan-out lines (FL) between data lines (DL) and the display driving circuit (200), and pads (DP) connected to the display driving circuit (200) may be disposed. The display driving circuit (200) and the pads (DP) may be disposed on one side edge of the display panel (100). The pads (DP) may be disposed closer to one side edge of the display panel (100) than the display driving circuit (200).

[0054] A sub-region (SA) may protrude in a second direction (Y-axis direction) from one side of a main region (MA). As shown in FIG. 2, the length of the sub-region (SA) in the first direction (X-axis direction) is smaller than the length of the main region (MA) in the first direction (X-axis direction), and the length of the sub-region (SA) in the second direction (Y-axis direction) may be smaller than the length of the main region (MA) in the second direction (Y-axis direction), but is not limited thereto.

[0055] The sub-region (SA) can be bent and placed on the lower surface of the display panel (100). The sub-region (SA) can overlap with the main region (MA) in the thickness direction (Z-axis direction) of the substrate. Pads (DP) and a display driving circuit (200) can be placed in the sub-region (SA).

[0056] The scan driving unit (400) can be connected to the display driving circuit (200) through a plurality of scan control wires (SCL). The scan driving unit (400) can receive a scan control signal (SCS) and a light emission control signal (ECS) from the display driving circuit (200) through a plurality of scan control wires (SCL).

[0057] As shown in FIG. 3, the scan driving unit (400) may include a scan signal output unit (410) and a light emission signal output unit (420). The scan signal output unit (410) may generate scan signals according to a scan control signal (SCS) and sequentially output the scan signals to scan wires (SL). The light emission signal output unit (420) may generate light emission signals according to a light emission control signal (ECS) and sequentially output the light emission signals to light emission wires (EL).

[0058] The scan driving unit (400) may include a plurality of thin-film transistors. The scan driving unit (400) may be formed on the same layer as the thin-film transistors of the subpixels (SP). Alternatively, the scan driving unit (400) may be formed on a different layer from the thin-film transistors of the subpixels (SP).

[0059] In FIG. 2, the scan driving unit (400) is exemplified as being formed on one side of the display area (DA), for example, on the left non-display area (NDA), but is not limited thereto. For example, the scan driving unit (400) may be formed on both sides of the display area (DA), for example, on the left and right non-display areas (NDA).

[0060] The display driving circuit (200) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (200) may be attached to the circuit board (300) using a COF (chip on film) method. The display driving circuit (200) may include a timing control unit (210), a data driving unit (220), and a power supply unit (230) as shown in FIG. 3.

[0061] The timing control unit (210) receives digital video data (DATA) and timing signals from the circuit board (300). The timing control unit (210) can generate a scan control signal (SCS) to control the operation timing of the scan signal output unit (410) according to the timing signals, generate a light emission control signal (ECS) to control the operation timing of the light emission signal output unit (420), and generate a data control signal (DCS) to control the operation timing of the data driving unit (220). The timing control unit (210) can output the scan control signal (SCS) to the scan signal output unit (410) and the light emission control signal (ECS) to the light emission signal output unit (420) through a plurality of scan control wires (SCL). The timing control unit (210) can output the digital video data (DATA) and the data control signal (DCS) to the data driving unit (220).

[0062] The data driver (220) converts digital video data (DATA) into analog positive / negative data voltages and outputs them to data lines (DL) through fan-out lines (FL). Subpixels (SP) are selected by scan signals of the scan driver (400), and data voltages are supplied to the selected subpixels (SP).

[0063] The power supply unit (230) can generate a first driving voltage and supply it to the first driving voltage wiring (VDDL). Additionally, the power supply unit (230) can generate a second driving voltage and supply it to the cathode electrode of each organic light-emitting diode of the subpixels (SP). The first driving voltage may be a high potential voltage for driving the organic light-emitting diode, and the second driving voltage may be a low potential voltage for driving the organic light-emitting diode. That is, the first driving voltage may have a higher potential than the second driving voltage.

[0064] The circuit board (300) can be attached to the pads (DP) using an anisotropic conductive film. As a result, the lead wires of the circuit board (300) can be electrically connected to the pads (DP). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0065] FIG. 4 is a circuit diagram showing a subpixel in detail according to one embodiment.

[0066] Referring to FIG. 4, a subpixel (SP) can be connected to a k-1 (k is a positive integer greater than or equal to 2) scan line (Sk-1), a k-th scan line (Sk), and a j (j is a positive integer) data line (Dj). Additionally, the subpixel (SP) can be connected to a first driving voltage line (VDDL) to which a first driving voltage is supplied, an initialization voltage line (VIL) to which an initialization voltage (Vini) is supplied, and a second driving voltage line (VSSL) to which a second driving voltage is supplied.

[0067] A subpixel (SP) includes a driving transistor (DT), a light-emitting element (LE), switching elements (switching transistors), and a capacitor (C1). The switching elements (switching transistors) include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0068] The driving transistor (DT) may include a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode. The driving current (Ids) flowing through the channel of the driving transistor (DT) is proportional to the square of the difference between the voltage (Vgs) between the gate electrode and the source electrode of the driving transistor (DT) and the threshold voltage, as shown in Equation 1.

[0069]

[0070] In mathematical equation 1, k' represents the proportionality constant determined by the structure and physical characteristics of the driving transistor, Vgs represents the gate-source voltage of the driving transistor, and Vth represents the threshold voltage of the driving transistor.

[0071] The light-emitting element (LEL) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LEL) can be proportional to the driving current (Ids).

[0072] The light-emitting element (LEL) may be an organic light-emitting diode comprising an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a micro light-emitting diode.

[0073] The anode electrode of the light-emitting element (LEL) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode can be connected to the second driving voltage line (VSSL). A parasitic capacitance (Cel) may be formed between the anode electrode and the cathode electrode of the light-emitting element (LEL).

[0074] The first transistor (ST1) may be a dual transistor comprising a first-1 transistor (ST1-1) and a first-2 transistor (ST1-2). The first-1 transistor (ST1-1) and the first-2 transistor (ST1-2) are turned on by a scan signal of the k-th scan wiring (Sk) to connect the gate electrode of the driving transistor (DT) with the second electrode. That is, when the first-1 transistor (ST1-1) and the first-2 transistor (ST1-2) are turned on, the gate electrode of the driving transistor (DT) and the second electrode are connected, so the driving transistor (DT) is driven as a diode. The gate electrode of the first-1 transistor (ST1-1) is connected to the k-th scan wiring (Sk), the first electrode is connected to the second electrode of the first-2 transistor (ST1-2), and the second electrode can be connected to the gate electrode of the driving transistor (DT). The gate electrode of the first-second transistor (ST1-2) is connected to the k-th scan wiring (Sk), the first electrode is connected to the second electrode of the driving transistor (DT), and the second electrode can be connected to the first electrode of the first-first transistor (ST1-1).

[0075] The second transistor (ST2) is turned on by a scan signal of the k-th scan line (Sk) to connect the first electrode of the driving transistor (DT) and the j-th data line (Dj). The gate electrode of the second transistor (ST2) is connected to the k-th scan line (Sk), the first electrode is connected to the first electrode of the driving transistor (DT), and the second electrode can be connected to the data line (Dj).

[0076] The third transistor (ST3) may be a dual transistor comprising the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2). The third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) are turned on by a scan signal of the k-1 scan line (Sk-1) to connect the gate electrode of the driving transistor (DT) to the initialization voltage line (VIL). The gate electrode of the driving transistor (DT) may be discharged to the initialization voltage of the initialization voltage line (VIL). The gate electrode of the third-1 transistor (ST3-1) is connected to the k-1 scan line (Sk-1), the first electrode is connected to the gate electrode of the driving transistor (DT), and the second electrode may be connected to the first electrode of the third-2 transistor (ST3-2). The gate electrode of the 3-2 transistor (ST3-2) is connected to the k-1 scan wiring (Sk-1), the first electrode is connected to the second electrode of the 3-1 transistor (ST3-1), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0077] The fourth transistor (ST4) is turned on by the scan signal of the k-th scan wiring (Sk) to connect the anode electrode of the light-emitting element (LEL) and the initialization voltage wiring (VIL). The anode electrode of the light-emitting element (LEL) can be discharged with the initialization voltage. The gate electrode of the fourth transistor (ST4) is connected to the k-th scan wiring (Sk), the first electrode is connected to the anode electrode of the light-emitting element (LEL), and the second electrode is connected to the initialization voltage wiring (VIL).

[0078] The fifth transistor (ST5) is turned on by a light emission control signal of the k-th light emission wiring (Ek) to connect the first electrode of the driving transistor (DT) and the first driving voltage wiring (VDDL). The gate electrode of the fifth transistor (ST5) is connected to the k-th light emission wiring (Ek), the first electrode is connected to the first driving voltage wiring (VDDL), and the second electrode is connected to the source electrode of the driving transistor (DT).

[0079] The sixth transistor (ST6) is connected between the second electrode of the driving transistor (DT) and the anode electrode of the light-emitting element (LEL). The sixth transistor (ST6) is turned on by a light-emitting control signal of the k-th light-emitting wiring (Ek) to connect the second electrode of the driving transistor (DT) and the anode electrode of the light-emitting element (LEL). The gate electrode of the sixth transistor (ST6) is connected to the k-th light-emitting wiring (Ek), the first electrode is connected to the second electrode of the driving transistor (DT), and the second electrode is connected to the anode electrode of the light-emitting element (LEL). When both the fifth transistor (ST5) and the sixth transistor (ST6) are turned on, a driving current (Ids) can be supplied to the light-emitting element (LEL).

[0080] A capacitor (C1) is formed between the second electrode of the driving transistor (DT) and the first driving voltage line (VDDL). One electrode of the capacitor (C1) is connected to the second electrode of the driving transistor (DT), and the other electrode can be connected to the first driving voltage line (VDDL).

[0081] If the first electrode of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is a source electrode, the second electrode may be a drain electrode. Alternatively, if the first electrode of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is a drain electrode, the second electrode may be a source electrode.

[0082] The active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed of any one of polysilicon, amorphous silicon, and oxide semiconductor. When the semiconductor layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is formed of polysilicon, the process for forming it may be a low-temperature polysilicon (LTPS) process.

[0083] In addition, Figure 4 describes the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) as being formed as P-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but is not limited thereto and may be formed as N-type MOSFETs.

[0084] The first driving voltage of the first driving voltage line (VDDL), the second driving voltage of the second driving voltage line (VSSL), and the initialization voltage of the initialization voltage line (VIL) can be set by considering the characteristics of the driving transistor (DT), the characteristics of the light-emitting element (LEL), etc. For example, the voltage difference between the initialization voltage and the data voltage supplied to the source electrode of the driving transistor (DT) can be set to be smaller than the threshold voltage of the driving transistor (DT).

[0085] FIG. 5 is a plan view showing a subpixel in detail according to one embodiment. FIG. 6 is a plan view showing area A of FIG. 5 in detail.

[0086] Referring to FIGS. 5 and 6, the subpixel (SP) may include a driving transistor (DT), first to sixth transistors (ST1 to ST6), a capacitor (C1), a first connection electrode (BE1), a second connection electrode (VIE), a data connection electrode (DCE), and a shielding electrode (SHE).

[0087] The subpixel (SP) can overlap with the k-1 scan line (Sk-1), the k scan line (Sk), the k light-emitting line (Ek), the j data line (Dj), the first driving voltage line (VDDL1), and the initialization voltage line (VIL) in the third direction (Z-axis direction). The subpixel (SP) can be connected to the k-1 scan line (Sk-1), the k scan line (Sk), the j data line (Dj), and the first driving voltage line (VDDL1) through the first to sixth transistors (ST1 to ST6). The k-1 scan line (Sk-1), the k scan line (Sk), the k light-emitting line (Ek), and the initialization voltage line (VIL) can be extended in the first direction (X-axis direction). The j data line (Dj) can be extended in the second direction (Y-axis direction).

[0088] The first driving voltage wiring (VDDL1) may include a first sub-driving voltage wiring (SVDDL1) and a second sub-driving voltage wiring (SVDDL2). The first sub-driving voltage wiring (SVDDL1) may extend in a second direction (Y-axis direction), and the second sub-driving voltage wiring (SVDDL2) may extend in a first direction (X-axis direction). The first sub-driving voltage wiring (SVDDL1) may be positioned between the j-th data wiring (Dj) and the first connecting electrode (BE1) in the first direction (X-axis direction). The second sub-driving voltage wiring (SVDDL2) may be positioned between the k-th scan wiring (Sk) and the k-th light emission wiring (Ek) in the second direction (Y-axis direction). The first sub-driving voltage wiring (SVDDL1) may be connected to the second sub-driving voltage wiring (SVDDL2) through the eighth contact hole (CNT8).

[0089] The driving transistor (DT) may include an active layer (DT_ACT), a gate electrode (DT_G), a first electrode (DT_S), and a second electrode (DT_D). The active layer (DT_ACT) of the driving transistor (DT) may overlap with the gate electrode (DT_G) of the driving transistor (DT) in a third direction (Z-axis direction). The gate electrode (DT_G) may be placed on the active layer (DT_ACT) of the driving transistor (DT).

[0090] The gate electrode (DT_G) can be connected to the first connection electrode (BE1) through the first connection contact hole (BCNT1). The first connection electrode (BE1) can be connected to the second electrode (D1-1) of the first-1 transistor (ST1-1) through the second connection contact hole (BCNT2). Since the first connection electrode (BE1) extends in the second direction (Y-axis direction), it can intersect with the k-th scan wiring (Sk).

[0091] The first electrode (DT_S) of the driving transistor (DT) can be connected to the first electrode (S2) of the second transistor (ST2). The second electrode (DT_D) of the driving transistor (DT) can be connected to the first electrode (S1-2) of the first-second transistor (ST1-2) and the first electrode (S6) of the sixth transistor (ST6).

[0092] The first transistor (ST1) may be formed as a dual transistor. The first transistor (ST1) may include a first-1 transistor (ST1-1) and a first-2 transistor (ST1-2).

[0093] The first-1 transistor (ST1-1) may include an active layer (ACT1-1), a gate electrode (G1-1), a first electrode (S1-1), and a second electrode (D1-1). The gate electrode (G1-1) of the first-1 transistor (ST1-1) may be part of the k-th scan wiring (Sk), and may be an overlapping region of the active layer (ACT1-1) of the first-1 transistor (ST1-1) and the k-th scan wiring (Sk) in the third direction (Z-axis direction). The first electrode (S1-1) of the first-1 transistor (ST1-1) may be connected to the second electrode (D1-2) of the first-2 transistor (ST1-2). The second electrode (D1-1) of the first-1 transistor (ST1-1) may be connected to the first connection electrode (BE1) through a second connection contact hole (BCNT2).

[0094] The first-second transistor (ST1-2) may include an active layer (ACT1-2), a gate electrode (G1-2), a first electrode (S1-2), and a second electrode (D1-2). The gate electrode (G1-2) of the first-second transistor (ST1-2) may be part of the k-th scan wiring (Sk), and may be an overlapping region of the active layer (ACT1-2) of the first-second transistor (ST1-2) and the k-th scan wiring (Sk) in the third direction (Z-axis direction). The first electrode (S1-2) of the first-second transistor (ST1-2) may be connected to the second electrode (DT_D) of the driving transistor (DT). The second electrode (D1-2) of the first-second transistor (ST1-2) may be connected to the first electrode (S1-1) of the first-first transistor (ST1-1).

[0095] The second transistor (ST2) may include an active layer (ACT2), a gate electrode (G2), a first electrode (S2), and a second electrode (D2). The gate electrode (G2) of the second transistor (ST2) may be part of the k-th scan wiring (Sk) and may be an overlapping region of the active layer (ACT2) of the second transistor (ST2) and the k-th scan wiring (Sk) in the third direction (Z-axis direction). The first electrode (S2) of the second transistor (ST2) may be connected to the first electrode (DT_S) of the driving transistor (DT). The second electrode (D2) of the second transistor (ST2) may be connected to the data connection electrode (DCE) through the third contact hole (CNT3). The data connection electrode (DCE) may be connected to the j-th data wiring (Dj) through the data contact hole (DCNT).

[0096] The third transistor (ST3) may be formed as a dual transistor. The third transistor (ST3) may include a third-1 transistor (ST3-1) and a third-2 transistor (ST3-2).

[0097] The third-1 transistor (ST3-1) may include an active layer (ACT3-1), a gate electrode (G3-1), a first electrode (S3-1), and a second electrode (D3-1). The gate electrode (G3-1) of the third-1 transistor (ST3-1) may be part of the k-1 scan wiring (Sk-1) and may be an overlapping region between the active layer (ACT3-1) of the third-1 transistor (ST3-1) and the k-1 scan wiring (Sk-1). The first electrode (S3-1) of the third-1 transistor (ST3-1) may be connected to the first connection electrode (BE1) through a second connection contact hole (CNT2). The second electrode (D3-1) of the third-1 transistor (ST3-1) may be connected to the first electrode (S3-2) of the third-2 transistor (ST3-2).

[0098] The third-2 transistor (ST3-2) may include an active layer (ACT3-2), a gate electrode (G3-2), a first electrode (S3-2), and a second electrode (D3-2). The gate electrode (G3-2) of the third-2 transistor (ST3-2) may be part of the k-1 scan wiring (Sk-1) and may be an overlapping region between the active layer (ACT3-2) of the third-2 transistor (ST3-2) and the k-1 scan wiring (Sk-1). The first electrode (S3-2) of the third-2 transistor (ST3-2) may be connected to the second electrode (D3-1) of the third-1 transistor (ST3-1). The second electrode (D3-2) of the third-2 transistor (ST3-2) may be connected to the second connection electrode (VIE) through the fourth contact hole (CNT4).

[0099] The fourth transistor (ST4) may include an active layer (ACT4), a gate electrode (G4), a first electrode (S4), and a second electrode (D4). The gate electrode (G4) of the fourth transistor (ST4) may be part of the k-th scan wiring (Sk) and may be an overlapping region between the active layer (ACT4) of the fourth transistor (ST4) and the k-th scan wiring (Sk). The first electrode (S4) of the fourth transistor (ST4) may be connected to the first anode connection electrode (ANDE1) through the sixth contact hole (CNT6). The anode electrode of the light-emitting element may be connected to the first anode connection electrode (ANDE1) through the second anode connection electrode (ANDE2). (See FIG. 7) The second electrode (D4) of the fourth transistor (ST4) may be connected to the second connection electrode (VIE) through the fourth contact hole (CNT4). The initial voltage wiring (VIL) is connected to the second connection electrode (VIE) through the fifth contact hole (CNT5), and the second connection electrode (VIE) can be connected to the second electrode (D3-2) of the third-second transistor (ST3-2) and the second electrode (D4) of the fourth transistor (ST4) through the fourth contact hole (CNT4). The second connection electrode (VIE) extends in the second direction (Y-axis direction) and can be positioned to intersect the k-1 scan wiring (Sk-1).

[0100] The fifth transistor (ST5) may include an active layer (ACT5), a gate electrode (G5), a first electrode (S5), and a second electrode (D5). The gate electrode (G5) of the fifth transistor (ST5) may be part of the k-th light-emitting control wiring (ELk) and may be an overlapping region between the active layer (ACT5) of the fifth transistor (ST5) and the k-th light-emitting control wiring (ELk). The first electrode (S5) of the fifth transistor (ST5) may be connected to the first sub-driving voltage wiring (SVDDL1) through the seventh contact hole (CNT7). The second electrode (D5) of the fifth transistor (ST5) may be connected to the first electrode (DT_S) of the driving transistor (DT).

[0101] The sixth transistor (ST6) may include an active layer (ACT6), a gate electrode (G6), a first electrode (S6), and a second electrode (D6). The gate electrode (G6) of the sixth transistor (ST6) may be part of the k-th light-emitting control wiring (ELk) and may be an overlapping region between the active layer (ACT6) of the sixth transistor (ST6) and the k-th light-emitting control wiring (ELk). The first electrode (S6) of the sixth transistor (ST6) may be connected to the second electrode (DT_D) of the driving transistor (DT). The second electrode (D6) of the sixth transistor (ST6) may be connected to the first anode connection electrode (ANDE1) through the sixth contact hole (CNT6).

[0102] The first electrode (CE11) of the capacitor (C1) is part of the gate electrode (DT_G) of the driving transistor (DT), and the second electrode (CE12) of the capacitor (C1) may be a second sub-driving voltage line (SVDDL2) that overlaps with the gate electrode (DT_G) of the driving transistor (DT).

[0103] The shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). The first transistor (ST1) may be positioned closest to the j+1 data line (Dj+1) among the first to sixth transistors (ST1 to ST6).

[0104] Specifically, as shown in FIGS. 5 and 6, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) may be placed adjacent to the j+1 data line (Dj+1). In this case, a parasitic capacitance may be formed between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1), and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1). The parasitic capacitance may be a fringe capacitance. Due to the above parasitic capacitance, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) may be affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0105] The shielding electrode (SHE) can overlap the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). Due to the shielding electrode (SHE), the parasitic capacitance can be reduced. Therefore, the influence of the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) on the data voltage transition of the j+1 data line (Dj+1) can be reduced.

[0106] The shielding electrode (SHE) may include a connection portion (CNP) and a shielding portion (SHP). The connection portion (CNP) may be connected to a first sub-driving voltage line (SVDDL1) adjacent to a j+1 data line (Dj+1) in a first direction (X-axis direction). The connection portion (CNP) may be connected to the first sub-driving voltage line (SVDDL1) through a first contact hole (CNT1).

[0107] The connection portion (CNP) may overlap with the first sub-drive voltage wiring (SVDDL1) in the third direction (Z-axis direction). In the overlapping area between the first sub-drive voltage wiring (SVDDL1) and the connection portion (CNP), the length of the connection portion (CNP) in the first direction (X-axis direction) may be longer than the length of the first sub-drive voltage wiring (SVDDL1) in the first direction (X-axis direction).

[0108] The connection portion (CNP) may be extended in a second direction (Y-axis direction). In the second direction (Y-axis direction), one end of the connection portion (CNP) may be adjacent to the k-1 scan line (Sk-1), and the other end of the connection portion (CNP) may be adjacent to the k-th scan line (Sk).

[0109] The shielding portion (SHP) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). The shielding portion (SHP) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction).

[0110] The shielding portion (SHP) may protrude from the connection portion (CNP) and extend in a first direction (X-axis direction). The shielding portion (SHP) may intersect with the j+1 data wiring (Dj+1).

[0111] FIG. 7 is a cross-sectional view showing an example of I-I' of FIG. 5. FIG. 8 is a cross-sectional view showing an example of II-II' of FIG. 5.

[0112] Referring to FIGS. 7 and 8, a thin film transistor layer (TFTL), a light-emitting element layer (EML), and an encapsulation layer (TFE) can be sequentially formed on a substrate (SUB1).

[0113] The thin film transistor layer (TFTL) includes a light-blocking layer (BML), a buffer layer (BF), an active layer (ACT), a first gate layer (GTL1), a second gate layer (GTL2), a first data metal layer (DTL1), a second data metal layer (DTL2), a gate insulating layer (130), a first interlayer insulating layer (141), a second interlayer insulating layer (142), a protective layer (150), a first organic layer (160), and a second organic layer (161).

[0114] A light-blocking layer (BML) may be formed on one side of the substrate (SUB1). The light-blocking layer (BML) may overlap the active layer (DT_ACT) of the driving transistor (DT) in a third direction (Z-axis direction) to block light incident on the active layer (DT_ACT) of the driving transistor (DT), but is not limited thereto. Alternatively, the light-blocking layer (BML) may overlap the active layer (DT_ACT) of the driving transistor (DT) and the active layers (ACT1~ACT6) of the first to sixth transistors (ST1~ST6) in a third direction (Z-axis direction) to block light incident on the active layer (DT_ACT) of the driving transistor (DT) as well as the active layers (ACT1~ACT6) of the first to sixth transistors (ST1~ST6). The third direction (Z-axis direction) may be the thickness direction of the substrate (SUB1). The light-blocking layer (BML) can be formed as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0115] A buffer film (BF) may be formed on the light-blocking layer (BML). The buffer film (BF) may be formed on one side of the substrate (SUB1) to protect the organic light-emitting layer (172) of the thin-film transistors and the light-emitting element layer (EML) from moisture penetrating through the substrate (SUB1), which is susceptible to moisture permeability. The buffer film (BF) may be composed of a plurality of inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as a multilayer film in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film (BF) may be omitted.

[0116] An active layer (ACT) may be formed on a substrate (SUB1) or a buffer film (BF). The active layer (ACT) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. When the active layer (ACT) is made of polycrystalline silicon or an oxide semiconductor, the ion-doped active layer (ACT) may be conductive. Accordingly, the active layer (ACT) may include the active layers (DT_ACT, ACT1~ACT6) of the driving transistor (DT) and the first to sixth transistors (ST1~ST6), as well as source electrodes (DT_S, S1, S2-1, S2-2, S3-1, S3-2, S4, S5, S6) and drain electrodes (DT_D, D1, D2-1, D2-2, D3-1, D3-2, D4, D5, D6).

[0117] A gate insulating film (130) may be formed on the active layer (ACT). The gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0118] A first gate layer (GTL1) may be formed on the gate insulating film (130). The first gate layer (GTL1) may include the gate electrode of the driving transistor (DT) and the gate electrodes (G1 to G6) of the first to sixth transistors (ST1 to ST6), as well as scan wires (Sk-1, Sk) and light-emitting wires (Ek). The first gate layer (GTL1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0119] A first interlayer insulating film (141) may be formed on the first gate layer (GTL1). The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film (141) may include a plurality of inorganic films.

[0120] A second gate layer (GTL2) may be formed on the first interlayer insulating film (141). The second gate layer (GTL2) may include an initial voltage line (VIL), a second sub-drive voltage line (SVDDL2), and a shielding electrode (SHE). The second gate layer (GTL2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0121] A second interlayer insulating film (142) may be formed on the second gate layer (GTL2). The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film (142) may include a plurality of inorganic films.

[0122] A first data metal layer (DTL1) may be formed on the second interlayer insulating film (142). The first data metal layer (DTL1) may include a first sub-drive voltage wiring (SVDDL1), a first connection electrode (BE1), a second connection electrode (VIE), a data connection electrode (DCE), and a first anode connection electrode (ANDE1). The first data metal layer (DTL1) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0123] A first organic film (160) may be formed on the first data metal layer (DTL1) to flatten the step difference caused by the active layer (ACT), the first gate layer (GTL1), the second gate layer (GTL2), and the first data metal layer (DTL1). The first organic film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0124] Meanwhile, a protective film (150) may be additionally formed between the first data metal layer (DTL1) and the first organic film (160). The protective film (150) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0125] A second data metal layer (DTL2) may be formed on the first organic film (160). The second data metal layer (DTL2) may include data wirings (Dj, Dj+1) and a second anode connection electrode (ANDE2). The second data metal layer (DTL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0126] A second organic film (161) for flattening the step difference may be formed on the second data metal layer (DTL2). The second organic film (161) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0127] It should be noted that although the driving transistor (DT) and the first to sixth transistors (ST1 to ST6) are exemplified as being formed in a top gate configuration where the gate electrode is located on the upper side of the active layer as shown in FIGS. 7 and 8, they are not limited thereto. That is, the driving transistor (DT) and the first to sixth transistors (ST1 to ST6) may be formed in a bottom gate configuration where the gate electrode is located on the lower side of the active layer, or in a double gate configuration where the gate electrode is located on both the upper and lower sides of the active layer.

[0128] The first connection contact hole (BCNT1) may be a hole that penetrates the first interlayer insulating film (141) and the second interlayer insulating film (142) to expose the gate electrode (DT_G) of the driving transistor (DT). The first connection electrode (BE1) may be connected to the gate electrode (DT_G) of the driving transistor (DT) through the first connection contact hole (BCNT1).

[0129] The second connection contact hole (BCNT2) may be a hole that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) to expose the second electrode (D1-1) of the first-1 transistor (ST1-1). The first connection electrode (BE1) may be connected to the second electrode (D1-1) of the first-1 transistor (ST1-1) through the second connection contact hole (BCNT2).

[0130] The data contact hole (DCNT) may be a hole that penetrates the first organic film (160) and exposes the data connection electrode (DCE). Each of the data wires (Dj, Dj+1) may be connected to the data connection electrode (DCE) through the data contact hole (DCNT).

[0131] The first contact hole (CNT1) may be a hole that penetrates the second interlayer insulating film (142) to expose the shielding electrode (SHE). The first sub-power voltage wiring (SVDDL1) may be connected to the shielding electrode (SHE) through the first contact hole (CNT1).

[0132] The third contact hole (CNT3) may be a hole that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) to expose the second electrode (D2) of the second transistor (ST2). The data connection electrode (DCE) may be connected to the second electrode (D2) of the second transistor (ST2) through the third contact hole (CNT3).

[0133] The fourth contact hole (CNT4) may be a hole that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) to expose the second electrode (D1) of the first transistor (ST1) and the third electrode (D3-2) of the third-second transistor (ST3-2). The second connection electrode (VIE) may be connected to the first electrode (D1-2) of the first-second transistor (ST1-2) and the third electrode (D3-2) of the third-second transistor (ST3-2) through the fourth contact hole (CNT4).

[0134] The fifth contact hole (CNT5) may be a hole that penetrates the second interlayer insulating film (142) to expose the initial voltage wiring (VIL). The second connecting electrode (VIE) may be connected to the initial voltage wiring (VIL) through the fifth contact hole (CNT5).

[0135] The sixth contact hole (CNT6) may be a hole that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) to expose the second electrode (D6) of the sixth transistor (ST6). The first anode connection electrode (ANDE1) may be connected to the second electrode (D6) of the sixth transistor (ST6) through the sixth contact hole (CNT6).

[0136] The seventh contact hole (CNT7) may be a hole that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) to expose the first electrode (S5) of the fifth transistor (ST5). The first sub-drive voltage wiring (SVDDL1) may be connected to the first electrode (S5) of the fifth transistor (ST5) through the seventh contact hole (CNT7).

[0137] The eighth contact hole (CNT8) may be a hole that penetrates the second interlayer insulating film (142) to expose the second sub-drive voltage wiring (SVDDL2). The first sub-drive voltage wiring (SVDDL1) may be connected to the second sub-drive voltage wiring (SVDDL2) through the eighth contact hole (CNT8).

[0138] The first anode contact hole (AND_CNT1) may be a hole that penetrates the protective film (150) and the first organic film (160) to expose the first anode connecting electrode (ANDE1). The second anode connecting electrode (ANDE2) may be connected to the first anode connecting electrode (ANDE1) through the first anode contact hole (AND_CNT1).

[0139] The second anode contact hole (AND_CNT2) may be a hole that penetrates the second organic film (161) to expose the second anode connecting electrode (ANDE2).

[0140] A light-emitting element layer (EML) is formed on the thin-film transistor layer (TFTL). The light-emitting element layer (EML) includes light-emitting elements (170) and a pixel defining film (180).

[0141] The light-emitting elements (170) and the pixel defining film (180) are formed on the second organic film (161). Each of the light-emitting elements (170) may include a first electrode (171), an organic light-emitting layer (172), and a second electrode (173).

[0142] The first electrode (171) can be formed on the first organic film (160). The first electrode (171) can be connected to the second anode connecting electrode (ANDE2) through the second anode contact hole (AND_CNT2).

[0143] In a top emission structure that emits light in the direction of the second electrode (173) based on the organic light-emitting layer (172), the first electrode (171) can be formed of a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0144] A pixel defining film (180) may be formed to partition the first electrode (171) on the second organic film (161) to serve to define the light-emitting region (EA) of each of the sub-pixels (SP). The pixel defining film (180) may be formed to cover the edge of the first electrode (171). The pixel defining film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0145] Each light-emitting region (EA) of the subpixels (SP) represents a region in which a first electrode (171), an organic light-emitting layer (172), and a second electrode (173) are sequentially stacked, and holes from the first electrode (171) and electrons from the second electrode (173) combine with each other in the organic light-emitting layer (172) to emit light.

[0146] An organic light-emitting layer (172) is formed on the first electrode (171) and the pixel defining film (180). The organic light-emitting layer (172) may include an organic material and emit a predetermined color. For example, the organic light-emitting layer (172) may include a hole transporting layer, an organic material layer, and an electron transporting layer. Among the subpixels (SP), the organic light-emitting layer (172) of the first subpixel emits light of a first color, the organic light-emitting layer (172) of the second subpixel emits light of a second color, and the organic light-emitting layer (172) of the third subpixel emits light of a third color. Alternatively, the organic light-emitting layers (172) of the subpixels (SP) may emit white light, in which case the first subpixel may overlap with a color filter layer of the first color, the second subpixel may overlap with a color filter layer of the second color, and the third subpixel may overlap with a color filter layer of the third color. For example, the first color may be red, the second color may be green, and the third color may be blue, but is not limited thereto.

[0147] A second electrode (173) is formed on an organic light-emitting layer (172). The second electrode (173) may be formed to cover the organic light-emitting layer (172). The second electrode (173) may be a common layer formed in common on subpixels (SP). A capping layer may be formed on the second electrode (173).

[0148] In the upper light-emitting structure, the second electrode (173) can be formed from a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode (173) is formed from a semi-transmissive conductive material, the light emission efficiency can be increased by the micro cavity.

[0149] An encapsulation layer (TFE) may be formed on the light-emitting element layer (EML). The encapsulation layer (TFE) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). Additionally, the encapsulation layer (TFE) may include at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust.

[0150] Alternatively, a substrate is disposed on the light-emitting element layer (EML) instead of the encapsulation layer (TFE), and the space between the light-emitting element layer (EML) and the substrate may be empty under a vacuum or a filler film may be disposed therein. The filler film may be an epoxy filler film or a silicon filler film.

[0151] According to the embodiment illustrated in FIGS. 7 and 8, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). For example, the shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). The shielding electrode (SHE) may act as a barrier between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1), and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1). Therefore, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) can be reduced from being affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0152] Meanwhile, in FIG. 6, the shielding portion (SHP) of the shielding electrode (SHE) may intersect with the j+1 data line (Dj+1). As a result, a parasitic capacitance may be formed between the shielding portion (SHP) of the shielding electrode (SHE) and the j+1 data line (Dj+1). Due to the parasitic capacitance, the first driving voltage of the first driving voltage line (VDDL1) may be affected by the data voltage transition of the j+1 data line (Dj+1).

[0153] For example, as shown in FIG. 9, when the central area of ​​the display panel (100) displays a black image (B) and the remaining area displays a gray image (G), the data voltage applied to the subpixels (SP) displaying the black image (B) may be higher than the data voltage applied to the subpixels (SP) displaying the gray image (G).

[0154] The first driving voltage of the first driving voltage wiring (VDDL1) can be increased at the boundary between the gray image (G) at the top of the black image (B) and the black image (B). As a result, the subpixels (SP) that are supposed to display the gray image (G) display white, thereby causing horizontal crosstalk in which a white line (WL) is visible to the user.

[0155] Additionally, the first driving voltage of the first driving voltage wiring (VDDL1) may decrease at the boundary between the black image (B) and the gray image (G) at the bottom of the black image (B). As a result, the subpixels (SP) that are supposed to display the gray image (G) display black, thereby causing horizontal crosstalk in which a black line (BL) is visible to the user.

[0156] In the following, a display device (10) capable of reducing the influence of a first transistor (ST1) placed adjacent to a data line on voltage changes in the data line and simultaneously preventing horizontal crosstalk from occurring will be described in detail.

[0157] FIG. 10 is a plan view showing a subpixel in detail according to another embodiment. FIG. 11 is a plan view showing region B of FIG. 10 in detail. FIG. 12 is a cross-sectional view showing an example of III-III' of FIG. 10.

[0158] The embodiments of FIGS. 10 to 12 differ from the embodiments of FIGS. 5 to 8 in that the shielding electrode (SHE) does not overlap with the j-th data wiring (Dj) in the third direction (Z-axis direction) and is connected to the first sub-driving voltage wiring (SVDDL1) adjacent to the j-th data wiring (Dj) in the first direction (X-axis direction).

[0159] Referring to FIGS. 10 to 12, the shielding electrode (SHE) may include a connecting portion (CNP), a protrusion (PRP), and a shielding portion (SHP).

[0160] The connection part (CNP) can be connected to the first sub-drive voltage line (SVDDL1) adjacent to the j-th data line (Dj) in the first direction (X-axis direction). The connection part (CNP) can be connected to the first sub-drive voltage line (SVDDL1) through the first contact hole (CNT1).

[0161] The connection portion (CNP) may overlap with the first sub-drive voltage wiring (SVDDL1) in the third direction (Z-axis direction). In the overlapping area between the first sub-drive voltage wiring (SVDDL1) and the connection portion (CNP), the length of the connection portion (CNP) in the first direction (X-axis direction) may be longer than the length of the first sub-drive voltage wiring (SVDDL1) in the first direction (X-axis direction).

[0162] The connecting portion (CNP) may be extended in a second direction (Y-axis direction). In the second direction (Y-axis direction), one end of the connecting portion (CNP) may be adjacent to the k-1 scan line (Sk-1), and the other end of the connecting portion (CNP) may be adjacent to the k-th scan line (Sk). The connecting portion (CNP) may be positioned between the k-1 scan line (Sk-1) and the k-th scan line (Sk) in the second direction (Y-axis direction). The connecting portion (CNP) may not overlap with the k-1 scan line (Sk-1) and the k-th scan line (Sk) in the third direction (Z-axis direction).

[0163] The protrusion (PRP) may protrude from the connection portion (CNP) and extend in a first direction (X-axis direction). One end of the protrusion (PRP) may overlap with the j+1 data wiring (Dj+1) in a third direction (Z-axis direction). One end of the protrusion (PRP) may overlap with the data connection electrode (DCE) in a third direction (Z-axis direction). In a second direction (Y-axis direction), the protrusion (PRP) may be positioned between the second connection electrode (VIE) and the first-1 gate electrode (G1-1). The protrusion (PRP) may not overlap with the second connection electrode (VIE) and the first-1 gate electrode (G1-1) in a third direction (Z-axis direction).

[0164] The shielding portion (SHP) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). The shielding portion (SHP) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction).

[0165] The shielding portion (SHP) may protrude from the protrusion (PRP) and extend in a second direction (Y-axis direction). The shielding portion (SHP) may protrude from one end of the protrusion (PRP). In the second direction (Y-axis direction), one end of the shielding portion (SHP) may be adjacent to the k-th scan line (Sk). The shielding portion (SHP) may not overlap with the k-th scan line (Sk) in a third direction (Z-axis direction).

[0166] The first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) may be formed on a buffer film (BF), and a shielding electrode (SHE) may be formed on a first interlayer insulating film (141). Additionally, a first sub-drive voltage wiring (SVDDL1) and a data connection electrode (DCE) may be formed on a second interlayer insulating film (142), and a j+1 data wiring (Dj+1) may be formed on a first organic film (160).

[0167] The first connecting electrode (BE1) is adjacent to the connecting portion (CNP) in the first direction (X-axis direction) and may be adjacent to the protrusion (PRP) in the second direction (Y-axis direction).

[0168] According to the embodiment illustrated in FIGS. 10 to 12, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). For example, the shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). The shielding electrode (SHE) may be positioned between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1) and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1) to serve as a barrier. Therefore, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) can be reduced from being affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0169] Table 1 shows the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) in the embodiments of FIGS. 5 to 8, and the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) in the embodiments of FIGS. 10 to 12. As shown in Table 1, by reducing the overlapping area between the shielding electrode (SHE) and the j+1 data line (Dj+1), the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) can be reduced. Therefore, the influence of the first driving voltage line (VDDL) on the data voltage transition of the data lines (Dj, Dj+1) can be reduced.

[0170] Examples in FIGS. 5 to 8 Examples in FIGS. 10 to 12 Capacitance 3.13×10 -14 F 1.23×10 -14 F

[0172] FIG. 13 is a plan view showing a subpixel in detail according to another embodiment. FIG. 14 is a plan view showing region C of FIG. 13 in detail. FIG. 15 is a cross-sectional view showing an example of IV-IV' of FIG. 13.

[0173] The embodiments of FIGS. 13 to 15 differ from the embodiments of FIGS. 10 to 12 in that the shielding electrode (SHE) does not overlap with the j+1 data wiring (Dj+1) in the third direction (Z-axis direction).

[0174] Referring to FIGS. 13 to 15, a protrusion (PRP) of the shielding electrode (SHE) may protrude from the connection portion (CNP) and extend in a first direction (X-axis direction). In the first direction (X-axis direction), one end of the protrusion (PRP) may be adjacent to the j+1 data wiring (Dj+1). In the first direction (X-axis direction), one end of the protrusion (PRP) may be adjacent to the data connection electrode (DCE). The protrusion (PRP) may not overlap with the j+1 data wiring (Dj+1) in the third direction (Z-axis direction). The protrusion (PRP) may not overlap with the data connection electrode (DCE) in the third direction (Z-axis direction).

[0175] In the second direction (Y-axis direction), the protrusion (PRP) may be positioned between the second connecting electrode (VIE) and the first-1 gate electrode (G1-1). In the third direction (Z-axis direction), the protrusion (PRP) may not overlap with the second connecting electrode (VIE) and the first-1 gate electrode (G1-1).

[0176] The first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) may be formed on a buffer film (BF), and a shielding electrode (SHE) may be formed on a first interlayer insulating film (141). Additionally, a first sub-drive voltage wiring (SVDDL1) and a data connection electrode (DCE) may be formed on a second interlayer insulating film (142), and a j+1 data wiring (Dj+1) may be formed on a first organic film (160).

[0177] Table 2 shows the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) in the embodiments of FIGS. 5 to 8, and the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) in the embodiments of FIGS. 10 to 12. As shown in Table 1, by reducing the overlapping area between the shielding electrode (SHE) and the j+1 data line (Dj+1), the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) can be reduced. Therefore, the influence of the first driving voltage line (VDDL) on the data voltage transition of the data lines (Dj, Dj+1) can be reduced.

[0178] Examples in FIGS. 10 to 12 Examples in FIGS. 13 to 15 Capacitance 1.23×10 -14 F 0.88×10 -14 F

[0180] Meanwhile, as shown in FIGS. 14 and 15, in order to minimize the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1), the distance (DIS) between the protrusion (PRP) and the j+1 data line (Dj+1) in the first direction (X-axis direction) may be approximately 1 μm or more.

[0181] FIG. 16 is a cross-sectional view showing another example of IV-IV' of FIG. 13. (BML)

[0182] The embodiment of FIG. 16 differs from the embodiment of FIG. 15 in that a shielding electrode (SHE) is formed on a substrate (SUB1) and a buffer film (BF) is formed on the shielding electrode (SHE).

[0183] Referring to FIG. 16, the first sub-drive voltage wiring (SVDDL1) can be connected to the shielding electrode (SHE) through a first contact hole (CNT1) penetrating the buffer film (BF), the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0184] As shown in FIG. 16, due to the shielding electrode (SHE), coupling caused by parasitic capacitance formed between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1), and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1) can be reduced. Therefore, the influence of the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) on the data voltage transition of the j+1 data line (Dj+1) can be reduced.

[0185] FIG. 17 is a plan view showing a subpixel in detail according to another embodiment. FIG. 18 is a plan view showing region D of FIG. 17 in detail. FIG. 19 is a cross-sectional view showing another example of V-V' of FIG. 17.

[0186] The embodiments of FIGS. 17 to 19 differ from the embodiments of FIGS. 13 to 15 only in that data wirings (Dj, Dj+1, Dj+2) are formed on the first data metal layer (DTL1), the data connection electrode (DCE) and the data contact hole (DCNT) are omitted, and each of the data wirings (Dj, Dj+1) is connected to the second electrode (D2) of the second transistor (ST2) through the third contact hole (CNT3). Therefore, a detailed description of the embodiments of FIGS. 17 to 19 is omitted.

[0187] FIG. 20 is a plan view showing a subpixel in detail according to another embodiment. FIG. 21 is a plan view showing region D of FIG. 20 in detail. FIG. 22 is a cross-sectional view showing an example of VI-VI' of FIG. 20.

[0188] The embodiments of FIGS. 20 to 22 differ from the embodiments of FIGS. 13 to 15 in that the shielding electrode (SHE) is placed on the same layer as the first sub-drive voltage wiring (SVDDL1) and extends from the first sub-drive voltage wiring (SVDDL1).

[0189] Referring to FIGS. 20 to 22, the shielding electrode (SHE) may include a protrusion (PRP) and a shielding portion (SHP).

[0190] The protrusion (PRP) may protrude from the first sub-drive voltage line (SVDDL1) and extend in a first direction (X-axis direction). One end of the protrusion (PRP) may be adjacent to the j+1 data line (Dj+1). In the first direction (X-axis direction), one end of the protrusion (PRP) may be adjacent to the data connection electrode (DCE). The protrusion (PRP) may not overlap with the j+1 data line (Dj+1) in a third direction (Z-axis direction). The protrusion (PRP) may not overlap with the data connection electrode (DCE) in a third direction (Z-axis direction).

[0191] The protrusion (PRP) may be positioned between the second connecting electrode (VIE) and the first-1 gate electrode (G1-1) in the second direction (Y-axis direction). The protrusion (PRP) may not overlap with the second connecting electrode (VIE) and the first-1 gate electrode (G1-1) in the third direction (Z-axis direction).

[0192] The shielding portion (SHP) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). The shielding portion (SHP) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction).

[0193] The shielding portion (SHP) may protrude from the protrusion (PRP) and extend in a second direction (Y-axis direction). The shielding portion (SHP) may protrude from one end of the protrusion (PRP). In the second direction (Y-axis direction), one end of the shielding portion (SHP) may be adjacent to the k-th scan line (Sk). The shielding portion (SHP) may not overlap with the k-th scan line (Sk) in a third direction (Z-axis direction).

[0194] The first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) are formed on a buffer film (BF), the shielding electrode (SHE), the first sub-drive voltage wiring (SVDDL1), and the data connection electrode (DCE) are formed on the second interlayer insulating film (142), and the j+1 data wiring (Dj+1) can be formed on the first organic film (160).

[0195] According to the embodiment illustrated in FIGS. 20 to 22, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). For example, the shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). The shielding electrode (SHE) may be positioned between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1) and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1) to serve as a barrier. Therefore, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) can be reduced from being affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0196] In addition, since the shielding electrode (SHE) and the j+1 data line (Dj+1) do not overlap in the third direction (Z-axis direction), the parasitic capacitance formed between the shielding electrode (SHE) and the j+1 data line (Dj+1) can be reduced. Therefore, the influence of the first driving voltage line (VDDL) on the data voltage transition of the data lines (Dj, Dj+1) can be reduced.

[0197] FIG. 23 is a plan view showing a subpixel in detail according to another embodiment. FIG. 24 is a plan view showing region E of FIG. 23 in detail. FIG. 25 is a cross-sectional view showing an example of VII-VII' of FIG. 23.

[0198] The embodiments of FIGS. 23 to 25 differ from the embodiments of FIGS. 13 to 15 in that the shielding electrode (SHE) is not connected to the first sub-driving voltage wiring (SVDDL1) and is electrically floating.

[0199] Referring to FIGS. 23 through 25, the shielding electrode (SHE) can be electrically floating as it is not connected to wiring or electrodes. The shielding electrode (SHE) can overlap with at least a portion of the first transistor (ST1) in a third direction (Z-axis direction). The shielding electrode (SHE) can overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in a third direction (Z-axis direction).

[0200] The shielding electrode (SHE) may extend in a second direction (Y-axis direction). In the second direction (Y-axis direction), the shielding electrode (SHE) may be positioned between the second connecting electrode (VIE) and the k-th scan wiring (Sk). The shielding electrode (SHE) may not overlap with the second connecting electrode (VIE) and the k-th scan wiring (Sk) in a third direction (Z-axis direction).

[0201] The first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) may be formed on a buffer film (BF), and a shielding electrode (SHE) may be formed on a first interlayer insulating film (141). A first sub-drive voltage wiring (SVDDL1) and a data connection electrode (DCE) may be formed on a second interlayer insulating film (142), and a j+1 data wiring (Dj+1) may be formed on a first organic film (160).

[0202] According to the embodiments illustrated in FIGS. 23 to 25, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). For example, the shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). The shielding electrode (SHE) may be positioned between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1) and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1) to serve as a barrier. Therefore, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) can be reduced from being affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0203] FIG. 26 is a plan view showing a subpixel in detail according to another embodiment. FIG. 27 is a plan view showing region F of FIG. 26 in detail. FIG. 28 is a cross-sectional view showing an example of VIII-VIII' of FIG. 26.

[0204] The embodiments of FIGS. 26 to 28 differ from the embodiments of FIGS. 13 to 15 in that the shielding electrode (SHE) is connected to the second sub-drive voltage wiring (SVDDL2) rather than the first sub-drive voltage wiring (SVDDL1).

[0205] Referring to FIGS. 26 to 28, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). The shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction).

[0206] The shielding electrode (SHE) can be connected to the second sub-driving voltage wiring (SVDDL2) through the first contact hole (CNT1'). The shielding electrode (SHE) can be formed on the second interlayer insulating film (142), in which case the first contact hole (CNT1') may be a hole penetrating the second interlayer insulating film (142).

[0207] The shielding electrode (SHE) can be extended in a second direction (Y-axis direction). The shielding electrode (SHE) can intersect the k-th scan wiring (Sk).

[0208] The first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (S1-2) of the first-2 transistor (ST1-2) are formed on a buffer film (BF), the second sub-drive voltage wiring (SVDDL2) is formed on a first interlayer insulating film (141), the shielding electrode (SHE), the first sub-drive voltage wiring (SVDDL1), and the data connection electrode (DCE) are formed on a second interlayer insulating film (142), and the j+1 data wiring (Dj+1) can be formed on a first organic film (160).

[0209] According to the embodiment illustrated in FIGS. 26 to 28, the shielding electrode (SHE) may overlap with at least a portion of the first transistor (ST1) in the third direction (Z-axis direction). For example, the shielding electrode (SHE) may overlap with the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) in the third direction (Z-axis direction). The shielding electrode (SHE) may be positioned between the first electrode (S1-1) of the first-1 transistor (ST1-1) and the j+1 data line (Dj+1) and between the second electrode (S1-2) of the first-2 transistor (ST1-2) and the j+1 data line (Dj+1) to serve as a barrier. Therefore, the first electrode (S1-1) of the first-1 transistor (ST1-1) and the second electrode (D1-2) of the first-2 transistor (ST1-2) can be reduced from being affected by the data voltage change (transition) of the j+1 data wiring (Dj+1).

[0210] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0211] 10: Display device 100: Display panel 200: Display driving circuit 210: Timing control unit 220: Data driver 230: Power supply 300: Circuit board 410: Scan driver 420: Light emission signal output section

Claims

Claim 1 A display device comprising: a substrate; data lines disposed on the substrate to which data voltages are applied; scan lines disposed on the substrate to which scan signals are applied; and a pixel connected to one of the data lines and a first scan line and a second scan line among the scan lines, wherein the pixel comprises: a light-emitting element; a driving transistor that supplies a driving current flowing between a first electrode and a second electrode to the light-emitting element according to a data voltage of the data line applied to a gate electrode; a first transistor disposed between the gate electrode and the second electrode of the driving transistor; and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data lines, wherein the maximum length of the shielding electrode in a first direction in which the scan lines extend is longer than the maximum length in a second direction in which the data lines extend, and in the second direction, the shielding electrode is disposed between the first scan line and the second scan line. Claim 2 A display device according to claim 1, further comprising first driving voltage lines disposed on the substrate to which a first driving voltage is applied, wherein the pixel is connected to any one of the first driving voltage lines, and the shielding electrode is connected to the first driving voltage line. Claim 3 A display device according to claim 2, wherein the first transistor comprises a first-1 transistor having a gate electrode connected to any one of the at least one scan wiring and a second electrode connected to the gate electrode of the driving transistor; and a first-2 transistor having a gate electrode connected to the scan wiring and a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the first electrode of the first-1 transistor. Claim 4 In claim 3, the shielding electrode overlaps the first electrode of the first-1 transistor and the first-2 drain electrode of the first-2 transistor in the thickness direction of the substrate. Claim 5 In claim 3, the pixel further comprises: a second transistor that supplies the data voltage of the data wiring to the gate electrode of the driving transistor; and a third-1 transistor comprising a gate electrode connected to another scan wiring among the at least one scan wiring and a source electrode connected to the gate electrode of the driving transistor. Claim 6 A display device according to claim 5, wherein the shielding electrode comprises: a connection portion extending in one direction and connected to the first driving voltage wiring; a protrusion extending from the connection portion in another direction intersecting the one direction; and a shielding portion protruding from the protrusion and overlapping with the first electrode of the first-1 transistor and the second electrode of the first-2 transistor in the thickness direction of the substrate. Claim 7 In claim 6, the connection portion is positioned between the scan line and the other scan line in the one direction and does not overlap with the scan line and the other scan line in the thickness direction of the substrate. Claim 8 In claim 6, the protrusion is adjacent to a data line adjacent to the pixel among the data lines in the other direction and overlaps with a data line adjacent to the pixel in the thickness direction of the substrate. Claim 9 In claim 6, the shielding part is a display device extending in the above one direction. Claim 10 In claim 6, the protrusion is adjacent to the data line adjacent to the pixel among the data lines in the other direction and does not overlap with the data line adjacent to the pixel in the thickness direction of the substrate. Claim 11 In claim 6, the pixel further comprises a first connecting electrode that connects the gate electrode of the driving transistor and the second electrode of the first-1 transistor and is disposed on the same layer as the data wiring, and the first connecting electrode is adjacent to the connecting portion in one direction and adjacent to the protrusion in the other direction. Claim 12 In claim 2, the first driving voltage wiring comprises a first sub-driving voltage wiring extending in one direction; and a second sub-driving voltage wiring extending in another direction intersecting the one direction, and the shielding electrode is connected to the first sub-driving voltage wiring. Claim 13 A display device according to claim 12, wherein the scan wiring and the gate electrode of the driving transistor are disposed on a gate insulating film disposed on the substrate, the shielding electrode and the second sub-driving voltage wiring are disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first electrode and the second electrode of the driving transistor are disposed on a second interlayer insulating film disposed on the shielding electrode and the second sub-driving voltage wiring, and the data wiring is disposed on a first organic film disposed on the first sub-driving voltage wiring and the first electrode and the second electrode of the driving transistor. Claim 14 In claim 13, the first sub-driving voltage wiring is connected to the shielding electrode through a first contact hole penetrating the second interlayer insulating film. Claim 15 A display device according to claim 12, wherein the shielding electrode is disposed on the substrate, the scan wiring and the gate electrode of the driving transistor are disposed on a buffer film disposed on the shielding electrode, the second sub-driving voltage wiring is disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first and second electrodes of the driving transistor are disposed on a second interlayer insulating film disposed on the second sub-driving voltage wiring, and the data wiring is disposed on a first organic film disposed on the first sub-driving voltage wiring and the first and second electrodes of the driving transistor. Claim 16 In claim 15, the first sub-driving voltage wiring is connected to the shielding electrode through a first contact hole penetrating the buffer film, the buffer film, the first interlayer insulating film, and the second interlayer insulating film. Claim 17 In claim 1, the pixel further comprises: a second transistor that supplies the data voltage to the gate electrode of the driving transistor; and a data connection electrode that connects the data wiring and the first electrode of the second transistor, wherein the shielding electrode overlaps the data connection electrode in the thickness direction of the substrate. Claim 18 A substrate; data lines disposed on the substrate to which data voltages are applied; scan lines disposed on the substrate to which scan signals are applied; first driving voltage lines disposed on the substrate to which a first driving voltage is applied; and a pixel connected to any one of the data lines, at least one of the scan lines, and any one of the first driving voltage lines, wherein the pixel comprises: a light-emitting element; a driving transistor that supplies a driving current flowing between a first electrode and a second electrode to the light-emitting element according to the data voltage of the data lines applied to a gate electrode; a first transistor disposed between the gate electrode and the second electrode of the driving transistor; and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data lines, wherein the first driving voltage line comprises a first sub-driving voltage line extending in one direction; A display device comprising a second sub-driving voltage wiring extending in a different direction intersecting the first direction, wherein the shielding electrode comprises: a protrusion extending from the first sub-driving voltage wiring in a different direction intersecting the first direction; and a shielding portion extending from the protrusion and overlapping with at least a portion of the first transistor in the thickness direction of the substrate. Claim 19 In claim 1, the shielding electrode is an electrically floating display device. Claim 20 In claim 2, the shielding electrode is a display device positioned apart from the first driving voltage wiring. Claim 21 A substrate; data lines disposed on the substrate to which data voltages are applied; scan lines disposed on the substrate to which scan signals are applied; first driving voltage lines disposed on the substrate to which a first driving voltage is applied; and a pixel connected to any one of the data lines, at least one of the scan lines, and any one of the first driving voltage lines, wherein the pixel comprises: a light-emitting element; a driving transistor that supplies a driving current flowing between a first electrode and a second electrode to the light-emitting element according to the data voltage of the data lines applied to a gate electrode; a first transistor disposed between the gate electrode and the second electrode of the driving transistor; and a shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate and does not overlap with the data lines, wherein the first driving voltage line comprises a first sub-driving voltage line extending in one direction; A display device comprising a second sub-driving voltage wiring extending in a different direction intersecting the above one direction, wherein the shielding electrode protrudes from the second sub-driving voltage wiring. Claim 22 In claim 21, the shielding electrode is a display device extending in one direction. Claim 23 In claim 21, the shielding electrode is a display device that intersects with the at least one scan wiring. Claim 24 A display device according to claim 21, wherein the scan wiring and the gate electrode of the driving transistor are disposed on a gate insulating film disposed on the substrate, the second sub-driving voltage wiring is disposed on a first interlayer insulating film disposed on the scan wiring and the gate electrode of the driving transistor, the first sub-driving voltage wiring and the first and second electrodes of the driving transistor are disposed on a second interlayer insulating film disposed on the second sub-driving voltage wiring, and the data wiring and the shielding electrode are disposed on a first organic film disposed on the first sub-driving voltage wiring and the first and second electrodes of the driving transistor. Claim 25 In claim 24, the shielding electrode is a display device connected to the second sub-driving voltage wiring through a first contact hole penetrating the first organic film and the second interlayer insulating film. Claim 26 delete

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