Circuit having stacked MIM capacitors

Abstract

The present invention discloses a Metal-Insulator-Metal (MIM) capacitor circuit, wherein the said MIM capacitor circuit comprises at least two capacitor layers stacked sequentially between a lower conductive layer and an upper conductive layer, and forms an equivalent MIM capacitor connected in parallel by at least two capacitor layers.

Description

Technology Field

[0001] The present invention relates to a Metal-Insulator-Metal (MIM) capacitor circuit, and more specifically, to a stacked MIM capacitor circuit in which a multilayer MIM capacitor is formed between an upper conductive layer and a lower conductive layer to have improved integration density. Background Technology

[0002] Components such as image sensors, touch integrated circuits, and display driving circuits are manufactured as chips and mounted on substrates. The aforementioned components are equipped with a large number of terminals for the input and output of digital signals or analog signals, and multiple terminals for receiving and providing power.

[0003] In addition, the above-mentioned components have circuits for signal processing or power conversion mounted inside, and the above-mentioned circuits can be configured using capacitors.

[0004] Capacitors can be configured to have a large capacity depending on input or output characteristics, and large-capacity capacitors act as a cause for increasing chip size.

[0005] Therefore, capacitors within the chip need to be designed to have a reduced size and high integration density in order to reduce the size of components or secure design margins. The problem to be solved

[0006] The present invention aims to provide a stacked MIM capacitor circuit capable of implementing a plurality of MIM capacitors to have a small area, high integration density, and high capacitance between a single layer between a lower conductive layer and an upper conductive layer within a chip.

[0007] In addition, another objective of the present invention is to provide a stacked MIM capacitor circuit having good electrical characteristics by implementing a stacked MIM capacitor having a uniform capacitance by arranging a plurality of MIM capacitors between a lower conductive layer and an upper conductive layer.

[0008] In addition, another objective of the present invention is to provide a stacked MIM capacitor circuit having good electrical characteristics by implementing a plurality of MIM capacitors divided into a plurality of groups having the same capacitance between a lower conductive layer and an upper conductive layer.

[0009] In addition, another objective of the present invention is to provide a stacked MIM capacitor circuit that is advantageous in terms of chip size, can be manufactured with an efficient structure using a small number of layers, ensures process convenience, shortens the development period, and is economically advantageous. means of solving the problem

[0010] The stacked MIM capacitor circuit of the present invention comprises: a lower conductive layer; at least two capacitor layers stacked sequentially on top of the lower conductive layer; an interlayer insulating layer formed on top of the lower conductive layer and the at least two capacitor layers; a stacked upper conductive layer stacked on top of the interlayer insulating layer and having a plurality of electrode patterns separated to correspond to the lower conductive layer and the at least two capacitor layers, respectively; and a plurality of contact plugs penetrating the interlayer insulating layer and electrically connecting the lower conductive layer and the at least two capacitor layers and the plurality of electrode patterns corresponding thereto, respectively; wherein the at least two capacitor layers each have an overlapping region of the same area.

[0011] The stacked MIM capacitor circuit of the present invention comprises: a lower conductive layer; at least two capacitor layers stacked sequentially on top of the lower conductive layer; an interlayer insulating layer formed on top of the lower conductive layer and the at least two capacitor layers; a stacked upper conductive layer stacked on top of the interlayer insulating layer and having a plurality of electrode patterns separated to correspond to the lower conductive layer and the at least two capacitor layers, respectively; and a plurality of contact plugs penetrating the interlayer insulating layer and electrically connecting the lower conductive layer and the at least two capacitor layers and the plurality of electrode patterns corresponding thereto, respectively; wherein odd-numbered first capacitor layers are stacked to have a first overlapping area of ​​a lower portion and a first area, and even-numbered second capacitor layers are stacked to have a second overlapping area of ​​a lower portion and a second area. Effects of the invention

[0012] The stacked MIM capacitor circuit of the present invention implements a multilayer MIM capacitor stacked between a single layer between a lower conductive layer and an upper conductive layer within a chip. Therefore, the stacked MIM capacitor circuit of the present invention has the effect of achieving high integration density and securing high capacitance while having a planar area similar to that of a single-stage MIM capacitor.

[0013] Furthermore, in the stacked MIM capacitor circuit of the present invention, the MIM capacitors are formed to have a uniform area for each layer. Therefore, the capacitance of the stacked MIM capacitor circuit can be accurately designed, and as a result, it has the effect of having good electrical characteristics.

[0014] Furthermore, the stacked MIM capacitor circuit of the present invention comprises MIM capacitors stacked in multiple layers between a single layer between a lower conductive layer and an upper conductive layer within the chip, as described above. Therefore, the present invention offers advantages in chip size, enables the fabrication of an efficient structure with a small number of layers, ensures process convenience, shortens the development period, and provides economically advantageous effects. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional view showing a preferred embodiment of a stacked MIM capacitor circuit of the present invention. Figure 2 is an equivalent circuit diagram of Figure 1. FIG. 3 is a cross-sectional view showing another embodiment of the stacked MIM capacitor circuit of the present invention. Figure 4 is an equivalent circuit diagram of Figure 3. FIG. 5 is a cross-sectional view showing another embodiment of the stacked MIM capacitor circuit of the present invention. Figure 6 is an equivalent circuit diagram of Figure 5. Figure 7 is a modified equivalent circuit diagram of Figure 6. FIG. 8 is a cross-sectional view showing another embodiment of the stacked MIM capacitor circuit of the present invention. Figure 9 is an equivalent circuit diagram of Figure 8. Specific details for implementing the invention

[0016] The stacked MIM capacitor circuit of the present invention can be employed in image sensors, touch integrated circuits, display driving circuits, etc., which are fabricated as chips, and the above-mentioned components can be fabricated using a semiconductor substrate.

[0017] The above-described components include a device layer in which devices are formed on a semiconductor substrate and a plurality of metal layers above the device layer. The device layer refers to a layer in which devices, such as transistors, are formed on a semiconductor substrate, and the metal layer refers to a layer formed of a conductive material for forming wiring or electrodes. An interlayer insulating layer for insulation is formed between the plurality of metal layers and between the device layer and the upper metal layer.

[0018] The stacked MIM capacitor circuit of the present invention can be configured in a space comprising a pair of vertically adjacent metal layers and an interlayer insulating layer between them.

[0019] An embodiment of the present invention for this purpose can be described with reference to FIG. 1.

[0020] In FIG. 1, the stacked MIM capacitor circuit of the present invention is implemented to include MIM capacitors stacked in multiple layers between the lower conductive layer (10) and the upper conductive layer (60).

[0021] More specifically, in FIG. 1, the stacked MIM capacitor circuit includes a lower conductive layer (10), capacitor layers (20, 30), an interlayer insulating layer (50), an upper conductive layer (60), and contact plugs (70, 71, 72).

[0022] Among these, the lower conductive layer (10) and the upper conductive layer (60) are spaced apart vertically, and the interlayer insulating layer (50) is formed between the lower conductive layer (10) and the upper conductive layer (60).

[0023] And, the capacitor layers (20, 30) have a structure in which they are stacked sequentially on top of the lower conductive layer (10) and are located between the lower conductive layer (10) and the interlayer insulating layer (50).

[0024] As a result, a lower conductive layer (10) and capacitor layers (20, 30) are formed on the lower part of the interlayer insulating layer (50), and an upper conductive layer (60) is formed on the upper part of the interlayer insulating layer (50).

[0025] Among these, the lower conductive layer (10) is preferably formed to have a width sufficient for implementing the MIM capacitor circuit of the present invention, and can be formed to have a wider width than the upper capacitor layers (20, 30).

[0026] The lower conductive layer (10) can be understood as a layer formed by depositing a conductive metal material on the upper surface of the lower layer. The lower conductive layer (10) can be formed to have a pattern of width for forming an MIM capacitor circuit by etching, for example, dry etching or wet etching.

[0027] Here, the lower layer of the lower conductive layer (10) may include the aforementioned element layer. Additionally, the lower layer of the lower conductive layer (10) may include the aforementioned element layer and a metal layer and an insulating layer stacked on top thereof. In this case, the metal layer can be understood as being for forming wiring or pads that are electrically connected to the element layer. The insulating layer may be formed on the upper and lower parts of the metal layer, respectively, for insulation.

[0028] At least two capacitor layers stacked in sequence may be formed on the upper portion of the lower conductive layer (10). An embodiment of FIG. 1 is exemplified by two capacitor layers (20, 30).

[0029] That is, the capacitor layer (20) and the capacitor layer (30) are stacked sequentially on top of the lower conductive layer (10).

[0030] The capacitor layer (20) has a structure in which an insulating layer (21) and a metal layer (22) are stacked. Among these, the insulating layer (21) is stacked on top of the lower conductive layer (10), and the metal layer (22) is stacked on top of the insulating layer (21). Also, the capacitor layer (30) has a structure in which an insulating layer (31) and a metal layer (32) are stacked. Among these, the insulating layer (31) is stacked on top of the metal layer (22) of the capacitor layer (20), and the metal layer (32) is stacked on top of the insulating layer (31). Here, the insulating layers (21, 31) act as dielectrics for forming a capacitor.

[0031] In the embodiment of FIG. 1, the capacitor layer (20) is formed to have a wider width than the upper capacitor layer (30).

[0032] More specifically, the insulating layer (21) and the metal layer (22) of the capacitor layer (20) have the same width and have a structure aligned so that both ends of the width are formed at the same position. Also, the insulating layer (31) and the metal layer (32) of the capacitor layer (30) have the same width and have a structure aligned so that both ends of the width are formed at the same position. In FIG. 1, the insulating layer (21), the metal layer (22), the insulating layer (31), and the metal layer (32) are stacked sequentially and have a structure aligned so that one end of the width is formed at the same position. As a result, the capacitor layer (20) has a portion of non-overlapping areas that do not overlap with the capacitor layer (30) at the other end that is not aligned with one end of the capacitor layer (30).

[0033] As described above, the capacitor layer (20) can be formed by sequentially stacking an insulating layer (21) and a metal layer (22) on top of the lower conductive layer (10) by, for example, deposition, and then simultaneously etching the insulating layer (21) and the metal layer (22) to form a pattern of a preset width. Additionally, the capacitor layer (30) can be formed by sequentially stacking an insulating layer (31) and a metal layer (32) on top of the capacitor layer (20) by, for example, deposition, and then simultaneously etching the insulating layer (31) and the metal layer (32) to form a pattern of a preset width. As described above, the capacitor layer (20) and the capacitor layer (30) can each be formed by separate deposition and etching.

[0034] In contrast, the capacitor layer (20) and the capacitor layer (30) can be formed by sequentially stacking an insulating layer (21), a metal layer (22), an insulating layer (31), and a metal layer (32) according to the choice of the manufacturer, and then first performing an etching to form the capacitor layer (20) and then performing an etching to form the capacitor layer (30).

[0035] After the capacitor layer (20) and the capacitor layer (30) are formed, an interlayer insulating layer (50) is formed on the lower conductive layer (10) and the upper portion of the two capacitor layers (20, 30).

[0036] After that, an upper conductive layer (60) is laminated on top of the interlayer insulating layer (50), and the upper conductive layer (60) is formed to include a separated first electrode pattern (61) and a second electrode pattern (62).

[0037] The interlayer insulating layer (50) can be formed by the deposition of an insulating material and, for example, can be formed to have a pattern of width for forming an MIM capacitor circuit by etching such as dry etching or wet etching. And, the upper conductive layer (60) can be formed by the deposition of a conductive metal material and can be formed to have a first electrode pattern (61) and a second electrode pattern (62) separated by etching.

[0038] According to the above structure, the capacitor layer (20) has an overlapping region and a non-overlapping region with respect to the upper capacitor layer (30).

[0039] The non-overlapping region of the capacitor layer (20) faces the upper conductive layer (60) vertically through the interlayer insulating layer (50). That is, the first electrode pattern (61) is formed to face the non-overlapping region of the capacitor layer (20) vertically through the interlayer insulating layer (50).

[0040] And, the second electrode pattern (62) is formed such that a portion faces the capacitor layer (30) vertically through the interlayer insulating layer (50), and the remaining portion faces the lower conductive layer (10) vertically through the interlayer insulating layer (50). Here, the remaining portion of the second electrode pattern (62) can be understood as facing an extended area of ​​the lower conductive layer (10) that does not overlap with the two capacitor layers.

[0041] Here, the capacitor layer (20) can be understood as an odd-numbered stacked capacitor layer, and the capacitor layer (30) can be understood as an even-numbered stacked capacitor layer.

[0042] In the embodiment of FIG. 1, the contact plug (71) is configured to electrically connect the first electrode pattern (61) with the non-overlapping region of the capacitor layer (20) facing vertically, and for this purpose, at least one contact plug (71) may be formed to vertically penetrate the interlayer insulating layer (50). More specifically, the contact plug (71) is configured to electrically connect the first electrode pattern (61) with the metal layer (22) of the capacitor layer (20).

[0043] Additionally, the contact plug (72) is configured to electrically connect the capacitor layer (30) and the second electrode pattern (62) facing each other vertically, and for this purpose, at least one contact plug (72) may be formed to vertically penetrate the interlayer insulation layer (50). More specifically, the contact plug (72) is configured to electrically connect the second electrode pattern (62) and the metal layer (32) of the capacitor layer (30).

[0044] Additionally, the contact plug (70) is configured to electrically connect the lower conductive layer (10) and the second electrode pattern (62) facing each other vertically, and for this purpose, at least one contact plug (70) may be formed to vertically penetrate the interlayer insulating layer (50). More specifically, the contact plug (70) is configured to electrically connect the second electrode pattern (62) and an extended area of ​​the lower conductive layer (10) that does not overlap with the capacitor layers (20, 30) of the lower conductive layer (10).

[0045] In the embodiment of FIG. 1, the stacked capacitor layers (20, 30) may have different widths. That is, the capacitor layer (20) may have a larger area than the capacitor layer (30). The overlapping area between the capacitor layer (20) and the lower conductive layer (10) has a larger area than the overlapping area between the capacitor layer (30) and the capacitor layer (20). The capacitance of the capacitor layer (20) is determined by the area of ​​the overlapping area overlapping with the lower conductive layer (10), and the capacitance of the capacitor layer (30) is determined by the area of ​​the overlapping area overlapping with the capacitor layer (20). Therefore, the capacitor layer (20) may have a larger capacitance than the capacitor layer (30).

[0046] The embodiment of FIG. 1, which includes two layers of capacitor layers (20, 30) as described above, can be interpreted as including capacitors (C1) and (C2) formed in parallel equivalently as in FIG. 2.

[0047] In FIG. 2, node N2 can be understood to correspond to the first electrode pattern (61), contact plug (71), and metal layer (22) of the capacitor layer (20).

[0048] An equivalent capacitor (C1) is formed by a stacked structure between a metal layer (22), an insulating layer (21), and a lower conductive layer (10), and an equivalent capacitor (C2) is formed by a stacked structure between a metal layer (22), an insulating layer (31), and a metal layer (32). The above capacitors (C1, C2) can be understood as MIM capacitors having a metal-insulator-metal stacked structure.

[0049] And, in FIG. 2, the path for electrical connection with the first electrode pattern (61) can be understood as being provided by a contact plug (71) connected to the metal layer (22) of FIG. 1, and the path for electrical connection coupling capacitor (C1) and capacitor (C2) can be understood as being provided by a contact plug (72), a second electrode pattern (62), a contact plug (70), and a lower conductive layer (10).

[0050] According to the above structure, capacitors (C1, C2) can be understood to be formed in parallel between the first electrode pattern (61) and the second electrode pattern (62).

[0051] According to the embodiments of FIGS. 1 and 2, the stacked MIM capacitor circuit can have high-density MIM capacitors while having a planar area similar to a single-stage MIM capacitor generally formed between the lower conductive layer (10) and the upper conductive layer (60), and can secure high-capacitance capacitance.

[0052] In addition, the present invention may be modified as shown in FIG. 3 to increase integration density and capacitance according to the manufacturer's intent.

[0053] The embodiment of FIG. 3 is configured to include three stacked capacitor layers (20, 30, 40) in contrast to the embodiment of FIG. 1.

[0054] In the embodiment of FIG. 3, the lower conductive layer (10), capacitor layers (20, 30), and interlayer insulating film (50) can be understood by referring to the embodiment of FIG. 1, so a redundant description thereof is omitted.

[0055] In the embodiment of FIG. 3, the capacitor layer (40) is formed on top of the capacitor layer (30). The capacitor layer (40) has a structure in which an insulating layer (41) and a metal layer (42) are stacked. Among these, the insulating layer (41) is stacked on top of the metal layer (32) of the capacitor layer (30), and the metal layer (42) is stacked on top of the insulating layer (41). Here, the insulating layer (41) acts as a dielectric for forming a capacitor.

[0056] The capacitor layer (40) is formed to have a narrower width than the lower capacitor layer (30).

[0057] More specifically, the insulating layer (41) and the metal layer (42) of the capacitor layer (40) have the same width and have a structure aligned such that both ends of the width are formed at the same position. In FIG. 3, the insulating layer (31), the metal layer (32), the insulating layer (41), and the metal layer (42) are stacked sequentially. Among the two ends of the width of the insulating layer (31), the metal layer (32), the insulating layer (41), and the metal layer (42), the capacitor layer (20) has a structure aligned such that the other end opposite to the one end aligned with the capacitor layer (30) is formed at the same position. As a result, the capacitor layer (30) has a portion of non-overlapping region that does not overlap with the capacitor layer (40) at the end not aligned with the capacitor layer (40).

[0058] An interlayer insulating layer (50) is formed on the lower conductive layer (10) and the three capacitor layers (20, 30, 40) after the capacitor layer (40) is formed.

[0059] And, the upper conductive layer (60) is formed to include a separated first electrode pattern (63) and a second electrode pattern (64). Among these, the first electrode pattern (63) is formed to overlap with the non-overlapping region of the capacitor layer (20) and the capacitor layer (40), and to face each other vertically. And, the second electrode pattern (64) is formed to overlap with the non-overlapping region of the capacitor layer (30) and the extended region of the lower conductive layer (10) that does not overlap with the three capacitor layers (20, 30, 40), and to face each other vertically.

[0060] Here, the capacitor layers (20, 40) can be understood as odd-numbered stacked capacitor layers, and the capacitor layer (30) can be understood as even-numbered stacked capacitor layers.

[0061] In the embodiment of FIG. 1, the contact plug (74) is configured to electrically connect the first electrode pattern (63) and the non-overlapping region of the capacitor layer (20) facing each other vertically, and for this purpose, at least one contact plug (74) may be formed to vertically penetrate the interlayer insulating layer (50). More specifically, the contact plug (74) is configured to electrically connect the first electrode pattern (63) and the metal layer (22) of the capacitor layer (20).

[0062] Additionally, the contact plug (76) is configured to electrically connect the capacitor layer (40) and the first electrode pattern (63) facing each other vertically, and for this purpose, at least one contact plug (76) may be formed to vertically penetrate the interlayer insulation layer (50). More specifically, the contact plug (76) is configured to electrically connect the first electrode pattern (63) and the metal layer (42) of the capacitor layer (40).

[0063] Additionally, the contact plug (75) is configured to electrically connect the second electrode pattern (64) to the non-overlapping region of the capacitor layer (30) facing it vertically, and for this purpose, at least one contact plug (75) may be formed to vertically penetrate the interlayer insulation layer (50). More specifically, the contact plug (75) is configured to electrically connect the second electrode pattern (64) to the metal layer (32) of the capacitor layer (30).

[0064] Additionally, the contact plug (73) is configured to electrically connect the lower conductive layer (10) and the second electrode pattern (64) facing each other vertically, and for this purpose, at least one contact plug (73) may be formed to vertically penetrate the interlayer insulating layer (50). More specifically, the contact plug (73) is configured to electrically connect the second electrode pattern (64) and an extended area of ​​the lower conductive layer (10) that does not overlap with the capacitor layers (20, 30, 40).

[0065] In the embodiment of FIG. 3, the stacked capacitor layers (20, 30, 40) may have different widths. That is, the area where the capacitor layer (20) and the lower conductive layer (10) overlap is larger than the area where the capacitor layer (20) and the capacitor layer (30) overlap, and the area where the capacitor layer (20) and the capacitor layer (30) overlap is larger than the area where the capacitor layer (30) and the capacitor layer (40) overlap. As a result, the capacitor layer (20) may have a larger capacitance than the capacitor layer (30), and the capacitor layer (30) may have a larger capacitance than the capacitor layer (40).

[0066] The embodiment of FIG. 3, which includes three capacitor layers (20, 30, 40) as described above, can be interpreted as including capacitors (C3, C4, C5) formed in parallel equivalently as in FIG. 4.

[0067] In FIG. 4, node N4 can be understood as corresponding to the metal layer (22) of the capacitor layer (20), and node N6 can be understood as corresponding to the metal layer (32) of the capacitor layer (30).

[0068] An equivalent capacitor (C3) is formed by a stacked structure between a metal layer (22), an insulating layer (21), and a lower conductive layer (10), an equivalent capacitor (C4) is formed by a stacked structure between a metal layer (22), an insulating layer (31), and a metal layer (32), and an equivalent capacitor (C5) is formed by a stack between a metal layer (32), an insulating layer (41), and a metal layer (42).

[0069] In FIG. 4, it can be understood that the path for the electrical connection coupling the capacitor (C3) and the first electrode pattern (63) is provided by the contact plug (74) of FIG. 3, and the path for the electrical connection coupling the capacitor (C5) and the first electrode pattern (63) is provided by the contact plug (76). Also, it can be understood that the path for the electrical connection coupling the node N6 and the capacitor (C3) is provided by the contact plug (75), contact plug (73), the second electrode pattern (64), and the lower conductive layer (10) of FIG. 3.

[0070] According to the above structure, equivalent capacitors (C3, C4, C5) can be understood to be formed in parallel between the first electrode pattern (63) and the second electrode pattern (64).

[0071] The embodiments of FIGS. 1 to 4 have capacitor layers that do not have stacked regions of the same area, and accordingly, each capacitor layer has a different capacitance.

[0072] In contrast, the present invention may be implemented such that at least some capacitor layers have the same capacitance. An example thereof may be illustrated in FIGS. 5 and FIGS. 9.

[0073] First, the embodiment of FIG. 5 will be described.

[0074] The embodiment of FIG. 5 is configured to include a lower conductive layer (10), four capacitor layers, an interlayer insulating layer (50), an upper conductive layer (160) having a plurality of electrode patterns (161 to 165), and a plurality of contact plugs (170 to 174).

[0075] The embodiment of FIG. 5 further includes an upper capacitor layer (80) compared to the embodiment of FIG. 3. The capacitor layer (80) includes a lower insulating layer (83) and an upper metal layer (84). That is, the embodiment of FIG. 5 is configured to include four capacitor layers (20, 30, 40, 80) stacked sequentially on top of the lower conductive layer (10).

[0076] Also, in the embodiment of FIG. 5, the upper conductive layer (160) is configured differently from the embodiments of FIG. 1 and FIG. 3.

[0077] The upper conductive layer (160) is laminated on top of the interlayer insulating layer (50) and is formed to have a plurality of separated electrode patterns (161~165) corresponding to the lower conductive layer (10) and the at least four capacitor layers (20, 30, 40, 80), respectively.

[0078] The configuration of the upper conductive layer (160) described above is intended to correspond to the lower structure.

[0079] Specifically, the electrode pattern (161) is configured in an overlapping area corresponding to an extended area of ​​the lower conductive layer (10) that does not overlap with the four capacitor layers (20, 30, 40, 80), the electrode pattern (162) is configured in an overlapping area corresponding to a non-overlapping area of ​​the capacitor layer (20), the electrode pattern (163) is configured in an overlapping area corresponding to a non-overlapping area of ​​the capacitor layer (30), the electrode pattern (164) is configured in an overlapping area corresponding to a non-overlapping area of ​​the capacitor layer (40), and the electrode pattern (165) is configured in an overlapping area corresponding to the capacitor layer (80).

[0080] In addition, the embodiment of FIG. 5 includes a plurality of contact plugs (170 to 174) corresponding to the configuration of the upper conductive layer (160) described above, and the plurality of contact plugs (170 to 174) are configured to electrically connect the lower conductive layer (10), four capacitor layers (20, 30, 40, 80), and a plurality of electrode patterns (161 to 165) corresponding thereto, respectively.

[0081] In the above configuration, the method of forming the lower conductive layer (10), four capacitor layers, an interlayer insulating layer (50), an upper conductive layer (160) having a plurality of electrode patterns (161 to 165), and a plurality of contact plugs (170 to 174) can be understood by referring to the embodiments of FIGS. 1 and FIGS. 3, so a redundant description thereof is omitted.

[0082] The embodiment of FIG. 5 is configured such that four capacitor layers (20, 30, 40, 80) each have an overlapping area of ​​the same area, and the overlapping areas of the four capacitor layers (20, 30, 40, 80) are formed at the same location and are indicated as “L1”.

[0083] More specifically, a capacitor layer (20) is stacked on top of a lower conductive layer (10), and at this time, the front surface of the capacitor layer (20) overlaps with the lower conductive layer (10). At this time, the overlapping area between the capacitor layer (20) and the lower conductive layer (10) is indicated as “L2”. At this time, the overlapping area L2 is larger than the overlapping area L1 mentioned above.

[0084] A capacitor layer (30) is stacked on top of a capacitor layer (20), and at this time, the capacitor layer (30) is formed to overlap with a part of the capacitor layer (20) so that the capacitor layer (20) has a non-overlapping region.

[0085] Then, a capacitor layer (40) is stacked on top of the capacitor layer (30), and at this time, the capacitor layer (40) is formed to overlap with a part of the capacitor layer (30) so that the capacitor layer (30) has a non-overlapping region.

[0086] Then, a capacitor layer (80) is stacked on top of the capacitor layer (40), and at this time, the capacitor layer (80) is formed to overlap with a part of the capacitor layer (40) so that the capacitor layer (40) has a non-overlapping region.

[0087] The capacitor layer (80) can form an equivalent capacitor having a capacitance corresponding to the area of ​​the overlapping region L1 that overlaps with the lower capacitor layer (40), the capacitor layer (40) can form an equivalent capacitor having a capacitance corresponding to the area of ​​the overlapping region L1 that overlaps with the lower capacitor layer (30), the capacitor layer (30) can form an equivalent capacitor having a capacitance corresponding to the area of ​​the overlapping region L1 that overlaps with the lower capacitor layer (20), and the capacitor layer (20) can form an equivalent capacitor having a capacitance corresponding to the area of ​​the overlapping region L2 that overlaps with the lower conductive layer (10). The above-mentioned equivalent capacitors can be understood by referring to FIG. 6, which will be described later.

[0088] At this time, the lowest capacitor layer (20) has an overlapping area L2 of a first area with the lower conductive layer (10), and other capacitor layers (30, 40, 80) above the capacitor layer (20) have an overlapping area L1 of the same second area as described above. At this time, L2 and L1 can be understood as widths, but can be understood as values ​​representing the same or different areas.

[0089] According to the above structure, the capacitor layer (20) may have a capacitance corresponding to the overlapping region L2, the capacitor layers (30, 40, 80) may have the same capacitance corresponding to the overlapping region L1, and the capacitor layer (20) may have a larger capacitance than the capacitor layers (30, 40, 80).

[0090] And, the remaining capacitor layers (20, 30, 40), excluding the uppermost capacitor layer (80), each have a non-overlapping region in which at least a portion does not overlap with other capacitor layers, and the lower conductive layer (10) has a non-overlapping region in which it does not overlap with the four capacitor layers (20, 30, 40, 80).

[0091] Among the multiple contact plugs (170 to 174), the contact plugs (171, 172, 173) are electrically connected to the conductive layers (224, 34, 44) through the non-overlapping regions of the capacitor layers (20, 30, 40), and the contact plug (170) is electrically connected to the non-overlapping region of the lower conductive layer (10).

[0092] And, the non-overlapping regions of the capacitor layers (20, 30, 40) and the non-overlapping regions of the lower conductive layer (10) are formed in a staggered direction relative to the adjacent layers.

[0093] In the embodiment of FIG. 5, the remaining capacitor layers (20, 30), excluding the lowest capacitor layer (20), have the same capacitance corresponding to the same overlapping region.

[0094] Therefore, the embodiment of FIG. 5 can form a plurality of equivalent capacitors having some of the same capacitance between single layers by the above configuration.

[0095] Therefore, the MIM capacitor circuit of the present invention can secure sufficient capacitance in a small area, and can secure an accurately designed capacitance when using the same capacitance, thereby having good electrical characteristics.

[0096] Figure 5 can be explained by the equivalent circuit of Figure 6.

[0097] The capacitor (C11) can be understood as being formed by the capacitor layer (20). One end of the capacitor (C11) can be understood as being connected to the electrode pad (161) through the lower conductive layer (10) and the contact plug (170), and the other end of the capacitor (C11) can be understood as being connected to the node (N12). Here, the node (N12) can be understood as corresponding to the metal layer (24) of the capacitor layer (20) to which the electrode pad (162) is connected by the contact plug (171).

[0098] The capacitor (C12) can be understood as being formed by the capacitor layer (30). The two ends of the capacitor (C12) are connected to nodes (N12) and (N13). Here, node (N13) can be understood as corresponding to the metal layer (34) of the capacitor layer (30) to which the electrode pad (163) is connected by the contact plug (172).

[0099] The capacitor (C13) can be understood as being formed by the capacitor layer (40). The two ends of the capacitor (C13) are connected to nodes (N13) and (N14). Here, the node (N14) can be understood as corresponding to the metal layer (44) of the capacitor layer (40) to which the electrode pad (164) is connected by the contact plug (173).

[0100] It can be understood that the capacitor (C14) is formed by the capacitor layer (80). It can be understood that one end of the capacitor (C14) is connected to the node (N14), and the other end of the capacitor (C14) is connected to the electrode pad (165) through the contact plug (174).

[0101] In Fig. 6, the remaining capacitors (C12, C13, C14), excluding capacitor (C11), have the same capacitance.

[0102] If necessary, the electrode pad (161) may be electrically floated, and two selected of the remaining electrode pads (162, 163, 164, 165) may be activated. In this case, one capacitor or two or three capacitors connected in series may be configured between the two activated electrode pads.

[0103] Additionally, if necessary, the electrode pad (161) can be electrically activated. In this case, a capacitor (C11) can be used, and various equivalent circuits can be implemented by selectively activating two or more electrode pads (161 to 165).

[0104] In addition, the two selected electrode pads can be commonly connected through wiring (200) formed on different metal layers as shown in Fig. 7.

[0105] Meanwhile, the embodiment of Fig. 8 will be described.

[0106] The embodiment of FIG. 8 includes a plurality of electrode patterns (161–165) of an upper conductive layer (160), a lower conductive layer (10), four capacitor layers (20, 30, 40, 80), and a plurality of contact plugs (170–174), identical to FIG. 5. Therefore, a redundant description of the configuration identical to FIG. 5 in the embodiment of FIG. 8 is omitted.

[0107] The embodiment of FIG. 8 differs from FIG. 5 in that the stacking area of ​​the four capacitor layers (20, 30, 40, 80) is different.

[0108] In the embodiment of FIG. 8, the four capacitor layers (20, 30, 40, 80) can be divided into odd-numbered capacitor layers and even-numbered capacitor layers according to the order in which they are stacked on the lower conductive layer (10).

[0109] The capacitor layers (30, 80), which are the even-numbered capacitor layers, are stacked to have an overlapping area L1 of a second area with the lower capacitor layer (20) or capacitor layer (40). And, the capacitor layers (20, 40), which are the odd-numbered capacitor layers, are stacked to have an overlapping area L2 of a first area with the lower conductive layer (10) or capacitor layer (30).

[0110] At this time, the area of ​​the overlapping region L2 is larger than the area of ​​the overlapping region L1. Therefore, the capacitor layers (20, 40) of the odd number of layers have a larger capacitance than the capacitor layers (30, 80) of the even number of layers.

[0111] That is, the overlapping area L2 of the odd-numbered capacitor layers (20, 40) has the same location and area, and the overlapping area L1 of the even-numbered capacitor layers (30, 80) also has the same location and area.

[0112] In the embodiment of FIG. 8, the remaining capacitor layers (20, 30, 40), excluding the uppermost capacitor layer (80), each have a non-overlapping region in which at least a portion does not overlap with other capacitor layers, and the lower conductive layer (10) has a non-overlapping region in which it does not overlap with the four capacitor layers (20, 30, 40, 80).

[0113] And, a plurality of contact plugs (170 to 174) are electrically connected to the non-overlapping regions of the lower conductive layer (10) and capacitor layers (20, 30, 40) and the capacitor layer (80) in the same structure as in FIG. 5.

[0114] Here, the non-overlapping regions of the lower conductive layer (10) and the capacitor layers (20, 30, 40) can be formed in a staggered direction relative to adjacent layers.

[0115] The embodiment of FIG. 8 can be explained by the equivalent circuit of FIG. 9.

[0116] The capacitors (C21~C24) correspond to the capacitors (C11~C14) of FIG. 6. However, the capacitors (C21~C24) and the capacitors (C11~C14) have different capacitances due to the difference in the area of ​​the overlapping region. That is, the capacitors (C21, C23) have a capacitance corresponding to the area of ​​the overlapping region L2, and the capacitors (C22, C24) have a capacitance corresponding to the area of ​​the overlapping region L1.

[0117] If necessary, the electrode pad (165) may be electrically activated, and one of the remaining electrode pads (161–164) may be activated. In this case, one capacitor or two or three capacitors connected in series may be configured between the two activated electrode pads.

[0118] Additionally, if necessary, the electrode pads (161, 163, 165) can be electrically activated. In this case, a circuit can be obtained in which two series capacitors have the same capacitance and the two series capacitors are connected in parallel with respect to the electrode pad (163).

[0119] In addition, the embodiment of FIG. 8 can be implemented by the manufacturer as various equivalent circuits based on FIG. 9.

[0120] Although the embodiments of FIGS. 5 and 8 illustrate a 4-layer capacitor, it can be configured with various multilayer structures according to the manufacturer's intent and implemented with various equivalent circuits accordingly.

[0121] Embodiments of the present invention include MIM capacitors stacked in multiple layers between a single layer between a lower conductive layer and an upper conductive layer within a chip. Additionally, embodiments of the present invention may be configured to provide the capacitance required for the design by implementing various equivalent circuits.

[0122] Therefore, the present invention is advantageous in terms of chip size, allows for the fabrication of an efficient structure with a small number of layers, ensures process convenience, shortens the development period, and offers economically advantageous effects.

Claims

Claim 1 A lower conductive layer; at least two capacitor layers sequentially stacked on top of the lower conductive layer; an interlayer insulating layer formed on top of the lower conductive layer and the at least two capacitor layers; and a stacked upper conductive layer stacked on top of the interlayer insulating layer and having a plurality of separated electrode patterns corresponding to each of the lower conductive layer and the at least two capacitor layers. and a plurality of contact plugs penetrating the interlayer insulating layer and electrically connecting the lower conductive layer and the at least two capacitor layers and the plurality of electrode patterns corresponding thereto, respectively; wherein the at least two capacitor layers each have an overlapping region of the same area, and the at least two capacitor layers each include a lower insulating layer and an upper metal layer, wherein the lowest first capacitor layer has a first capacitance corresponding to a first area overlapping with the lower conductive layer, and the other capacitor layers above the first capacitor layer have a second capacitance corresponding to the same overlapping region, and among the other capacitor layers above the first capacitor layer, capacitor layers excluding the uppermost layer each have a non-overlapping region in which at least a portion does not overlap with an adjacent capacitor layer, and the non-overlapping regions are formed in a staggered direction between adjacent capacitor layers, and the plurality of contact plugs correspond to the upper metal layer of each capacitor layer through the non-overlapping region A stacked MI-M capacitor circuit configured such that electrode patterns are electrically connected independently to each different capacitor layer. Claim 2 delete Claim 3 delete Claim 4 A stacked MI-M capacitor circuit according to claim 1, wherein, among the at least two capacitor layers, the remaining capacitor layers excluding the uppermost second capacitor layer each have a first non-overlapping region in which at least a portion does not overlap with other capacitor layers, and the lower conductive layer has a second non-overlapping region in which it does not overlap with the at least two capacitor layers. Claim 5 delete Claim 6 A stacked MI-M capacitor circuit according to claim 1, wherein at least two capacitor layers form equivalent capacitors connected in series between a first electrode pattern connected to the lower conductive layer and a second electrode pattern connected to the uppermost second capacitor layer among the at least two capacitor layers, and the remaining electrode patterns excluding the first electrode pattern and the second electrode pattern form nodes between the capacitors. Claim 7 A lower conductive layer; at least two capacitor layers sequentially stacked on top of the lower conductive layer; an interlayer insulating layer formed on top of the lower conductive layer and the at least two capacitor layers; and a stacked upper conductive layer stacked on top of the interlayer insulating layer and having a plurality of separated electrode patterns corresponding to each of the lower conductive layer and the at least two capacitor layers. and a plurality of contact plugs penetrating the interlayer insulating layer and electrically connecting the lower conductive layer and the at least two capacitor layers and the plurality of electrode patterns corresponding thereto, respectively; wherein odd-numbered first capacitor layers are stacked to have a first overlapping region of a lower part and a first area, and the odd-numbered first capacitor layers have a first capacitance, and even-numbered second capacitor layers are stacked to have a second overlapping region of a lower part and a second area, and the even-numbered second capacitor layers have a second capacitance smaller than the first capacitance, and among the odd-numbered first capacitor layers and the even-numbered second capacitor layers, capacitor layers excluding the uppermost layer each have a non-overlapping region in which at least a portion does not overlap with an adjacent capacitor layer, and the non-overlapping regions are formed in a staggered direction between adjacent capacitor layers, and the plurality of contact plugs are connected to the upper part of each capacitor layer through the non-overlapping region A stacked MI-M capacitor circuit configured such that electrode patterns corresponding to metal layers are electrically connected independently to different capacitor layers. Claim 8 delete Claim 9 delete Claim 10 A stacked MI-M capacitor circuit according to claim 7, wherein the at least two capacitor layers each comprise a lower insulating layer and an upper metal layer, and each insulating layer is electrically connected to a corresponding contact plug. Claim 11 A stacked MI-M capacitor circuit according to claim 7, wherein, among the at least two capacitor layers, the remaining capacitor layers excluding the uppermost second capacitor layer each have a first non-overlapping region in which at least a portion does not overlap with other capacitor layers, and the lower conductive layer has a second non-overlapping region in which it does not overlap with the at least two capacitor layers. Claim 12 delete Claim 13 A stacked MI-M capacitor circuit according to claim 7, wherein at least two capacitor layers form equivalent capacitors connected in series between a first electrode pattern connected to the lower conductive layer and a second electrode pattern connected to the uppermost second capacitor layer among the at least two capacitor layers, and the remaining electrode patterns excluding the first electrode pattern and the second electrode pattern form nodes between the capacitors.

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