High density deep trench capacitor and manufacturing method thereof

Abstract

A high-density MIM deep trench capacitor and a method for manufacturing the same are provided. The high-density deep trench capacitor comprises a substrate, a plurality of trenches formed within the substrate by recessing from the surface of the substrate, and (MIM)n (n≥2) conformally formed within the trenches and filling the interior of the trenches, wherein (MIM)n (n≥2) consists of n+1 (n≥2) alternating electrode layers and n (n≥2) dielectric layers, and the uppermost and lowermost layers of (MIM)n (n≥2) are electrode layers, the capacitor comprises an insulating layer covering the capacitor, and at least three conductive contacts formed within the insulating layer and in contact with each of the electrode layers, wherein the thickness of the electrode layer in the contact portion in contact with each conductive contact is smaller than the thickness of the electrode layer in the non-contact portion.

Description

Technology Field

[0001] The present disclosure relates to a high-density deep trench capacitor and a method for manufacturing the same. Background Technology

[0002] Recently, high-performance SOCs (System On Chips) are being used in applications such as smartphones, artificial intelligence, autonomous vehicles, and the Internet of Things, and there is a demand for the development of technology to reduce power noise, switching noise, etc. in the high-frequency range (frequency band of several hundred MHz).

[0003] To solve these problems, a MIM Deep Trench Capacitor (DTC) with enhanced energy storage capacity can be used. The MIM DTC is formed by repeating the MIM layer at least twice to improve capacitance.

[0004] Therefore, MIM DTC must be patterned for each of the multiple electrode layers, and if polymer-based etching by-products generated during the dry etching process remain on the surface of the electrode layers, bridge formation or short circuits may occur between electrode patterns.

[0005] In addition, when forming metal contacts that contact each electrode layer, if the metal contact penetrates too deeply when landing on the electrode layer, the electrode is damaged, pinholes are induced in the capacitor film, or delamination or voids occur. As a result, there are problems such as increased leakage current or reduced reliability.

[0006] Therefore, a novel high-density deep trench capacitor and a method for manufacturing the same are required to solve problems that occur during electrode layer patterning or contact formation with the electrode layer. The problem to be solved

[0007] The embodiments are intended to provide a high-density deep trench capacitor and a method for manufacturing the same that can effectively block short circuits caused by etching by-products generated during an etching process for patterning an electrode layer.

[0008] The embodiments are intended to provide a high-density deep trench capacitor and a method for manufacturing the same that can prevent leakage current or reliability degradation caused by the metal contact landing of the electrode layer becoming too deep. means of solving the problem

[0009] A high-density deep trench capacitor according to the embodiments comprises a substrate, a plurality of trenches formed within the substrate by recessing from the surface of the substrate, and (MIM)n (n≥2) conformally formed within the trenches and filling the interior of the trenches, wherein (MIM)n (n≥2) is composed of n+1 (n≥2) alternating electrode layers and n (n≥2) dielectric layers, and the uppermost and lowermost layers of (MIM)n (n≥2) are electrode layers, a capacitor, an insulating layer covering the capacitor, and at least three conductive contacts formed within the insulating layer and in contact with each of the electrode layers, wherein the thickness of the electrode layer in the contact portion in contact with each conductive contact is smaller than the thickness of the electrode layer in the non-contact portion.

[0010] A method for manufacturing a high-density deep trench capacitor according to the embodiments comprises the step of forming a trench on a substrate according to a layout in which unit cells are configured as a matrix array,

[0011] The above unit cell is a unit cell formed by arranging a trench array in a pinwheel shape, the trench array comprising a plurality of trenches in four regions enclosed by a first space region and a second space region spaced repeatedly along a first axis on a substrate, and a third space region and a fourth space region spaced repeatedly along a second axis perpendicular to the first axis, wherein at least three of the first to fourth space regions have different widths, a trench formation step.

[0012] A step of conformally forming n+1 (n≥2) electrode layers and n (n≥2) dielectric layers within the above trench,

[0013] A step of forming different step-shaped electrode layer patterns in at least three of the first to fourth space regions, wherein when etching the n+1 (n≥2) electrode layer, the n (n≥2) dielectric layer is used as an etching stop layer for etching.

[0014] The step of forming an insulating layer on the above substrate, and

[0015] The method includes the step of forming at least three different conductive contacts disposed in the first to fourth space regions of the insulating layer and contacting each of the electrode layers, wherein the thickness of the electrode layer of the contact portion contacting each conductive contact is smaller than the thickness of the electrode layer of the non-contact portion. Effects of the invention

[0016] The high-density deep trench capacitor according to the embodiments utilizes the lower dielectric layer as an etch stop layer when etching the upper electrode, thereby preventing the lower electrode from being exposed. Therefore, short circuits between electrodes caused by etching byproducts (e.g., polymer residues) can be fundamentally prevented. In other words, by utilizing an MIM stack structure, short circuits can be effectively prevented without increasing process complexity.

[0017] The high-density deep trench capacitor according to the embodiments can improve the reliability of the high-density deep trench capacitor by preventing damage to the electrode and dielectric layer by controlling the landing depth of the metal contact, thereby reducing leakage current and preventing electrode detachment. Brief explanation of the drawing

[0018] FIGS. 1 and FIGS. 2 are plan views of a trench for forming a high-density deep trench capacitor (DTC) according to one embodiment. Figures 3 to 10 respectively show plan and cross-sectional views for each process to complete the DTC. Figure 11 is a STEM-EDS (Scanning Transmission Electron Microscopy - Energy Dispersive X-ray Spectroscopy) image of the third space region in which a third contact is formed in contact with the second electrode layer. FIG. 12 is a TEM (Transmission Electron Microscopy) image of a second space region in which a second contact in contact with a third electrode layer is formed, and a TEM image of a third space region in which a third contact in contact with a second electrode layer is formed. Specific details for implementing the invention

[0019] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0020] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0021] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0022] Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity.

[0023] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0024] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0025] The present invention will be explained in more detail below through examples and comparative examples. However, the following examples are merely illustrative of the present invention, and the scope of the present invention is not limited to the following examples.

[0026] FIGS. 1 and 2 are plan views of a trench for forming a high-density deep trench capacitor (DTC) according to one embodiment, and FIG. 3 is a cross-sectional view of a trench formed according to the plan view of FIG. 1 or 2.

[0027] Referring to FIGS. 1 and 2, the DTC is composed of a matrix array in which unit cells (UC) are repeatedly arranged in the first axis direction and the second axis direction, as exemplified in FIG. 1 or 2, in order to maximize the capacitance of (MIM)n (n≥2) capacitors conformally formed within the trench (T).

[0028] A first space area (S1) and a second space area (S2) are spaced apart and repeatedly arranged along a first axis. A third space area (S3) and a fourth space area (S4) are spaced apart and repeatedly arranged along a second axis that is orthogonal to the first axis. Accordingly, trench arrays (TA1, TA2, TA3, TA4) are arranged in a pinwheel shape in each of the four areas surrounded by the first to fourth space areas (S1, S2, S3, S4) to form a unit cell (UC).

[0029] Each of the trench arrays (TA1, TA2, TA3, TA4) consists of multiple trenches (T). For example, each trench array (TA1, TA2, TA3, TA4) may be designed to include 3 to 10 trenches.

[0030] In the (MIM)n formed in the unit cell (UC), when n is 2, it becomes a MIMIM structure, when n is 3, it becomes a MIMIMIM structure, and when n is 4, it becomes a MIMIMIMIM structure. Therefore, when n is 2, there are 3 different types of metal contacts, when n is 3, there are 4 different types of metal contacts, and when n is 4, there are 5 different types of metal contacts.

[0031] Since different metal contacts must each make contact with different electrode layers placed at different heights, the width of the space required in the area where each metal contact is formed also differs.

[0032] FIG. 1 illustrates the case where n is 3 (MIMIMIM). For four metal contacts that contact each of the four electrode layers, the first to fourth space regions (S1, S2, S3, S4) must all have different widths. Accordingly, in the first space region (S1), a metal contact with the fourth electrode layer is formed. Therefore, a space equal to the area where the contact pattern is to be formed is required. In the second space region (S2), for metal contact with the third electrode layer, the fourth electrode layer is patterned and open, and the area where the contact pattern is to be formed is included, so it must be wider than the first space region (S1). In the third space region (S3), for metal contact with the second electrode layer, the fourth electrode layer and the third electrode layer are patterned and open, and the area where the contact pattern is to be formed is included, so it must be wider than the second space region (S2). The fourth space area (S4) must be wider than the third space area (S4) because it includes an open area where the fourth electrode layer, the third electrode layer, and the second electrode layer are patterned for metal contact with the first electrode layer, as well as an area where a contact pattern is to be formed. This allows the formation of contact holes for signal connection to the first to fourth electrode layers, which are formed by overlapping in a single trench (T), to be carried out in a single process. This will be explained again in the contact hole formation step.

[0033] FIG. 2 illustrates the case where n is 2 (MIMIM). For three different metal contacts, at least three of the widths of the first to fourth space regions (S1, S2, S3, S4) need to have different widths. Thus, as shown in FIG. 2, the widths of two selected space regions (S2 and S4) may be the same. When n is 4 or greater, at least one selected space region among the first to fourth space regions (S1, S2, S3, S4) may be divided into different widths to provide n+1 different space regions. For example, when n is 4, five different metal contacts are required, so the fourth space region (S4) may be divided into different widths to define five different space regions.

[0034] In order to arrange at least three of the widths of the first to fourth space regions (S1, S2, S3, S4) to have different widths as in FIG. 1 or FIG. 2, it is desirable that the length and width of the trench array also be arranged differently. The length of each trench array is defined as the length of an individual trench constituting the trench array, and the width is defined as the distance between the two end trenches of the plurality of trenches constituting the trench array.

[0035] That is, the length (L1) of the first, second, and fourth trench arrays (TA1, TA2, TA4) is the same. The width (W1) of the first, second, and third trench arrays (TA1, TA2, TA3) is the same. The length (L2) of the third trench array (TA3) is longer than the length (L1) of the first, second, and fourth trenches (TA1, TA2, TA4). The width (W2) of the fourth trench array (TA4) is greater than the width (W1) of the first, second, and third trench arrays (TA1, TA2, TA3). Therefore, the fourth trench array (TA4) may include one or more additional trenches than the first, second, and third trench arrays (TA1, TA2, TA3).

[0036] With the arrangement described above, the unit cell (UC) has a rotational unsymmetry or rotationally staggered structure. In the case of a rotationally unsymmetry structure, the force resisting external forces or stresses applied in one direction can be strengthened, and accordingly, bending, twisting, and distortion can be significantly reduced.

[0037] Of course, although the structure is illustrated in FIG. 1 as a rotationally asymmetric structure, it is understood that the structure of the present invention can also be applied in cases where the four trench arrays (TA1, TA2, TA3, TA4) are mirror-symmetric (not shown) or rotationally symmetric (see US10276651).

[0038] Referring to FIG. 3, a trench (T) is formed in a semiconductor substrate (110). The semiconductor substrate (110) may be a silicon substrate. Specifically, it may be a P-type silicon substrate or an N-type silicon substrate.

[0039] According to the plan view shown in FIG. 1 or FIG. 2, an etching mask (not shown) is formed on a semiconductor substrate (110), and the semiconductor substrate (110) is etched using the etching mask to form a trench (T), and then the etching mask (not shown) is removed.

[0040] It is necessary to have a trench (T) with a depth (D) of 1 µm to 20 µm and a critical dimension of width (W, or line (L) of line and space) of 0.05 to 0.6 µm. If the depth (D) of the trench (T) is formed too deep for the purpose of increasing capacitance, mechanical stress on the substrate may increase. In particular, in high-density packages or thin-film chips, excessively deep trenches can cause chip wrap, cracking, and yield reduction. The reason the critical dimension must be 0.05 to 0.6 µm is to conformally form (MIM)n (n≥2) capacitors within the trench (T) in subsequent processes. Therefore, the aspect ratio (D:W) of the trench (T) is a deep trench formed with a high aspect ratio of 1.67:1 to 400:1.

[0041] In addition, the line (L) and space (S) ratio of the trench (T) is set to 1:0.3 to 1:5. If the space (S) is narrowed to increase capacitance, i.e., if it is 1:0.3 or less, the mechanical stability of the sidewall is reduced and the possibility of damage during the process increases. On the other hand, if the space (S) is made too wide, i.e., 1:5 or more, the contact process margin is reduced or the capacitance per unit area ((C / mm²)) decreases.

[0042] Trench (T) etching can be performed using dry etching. Specifically, it can be performed using deep reactive ion etching technology using the Bosch Cycle.

[0043] Next, a thermal oxide film liner (130) is formed on the semiconductor substrate (110) in which the trench (T) is formed. The thermal oxide film liner (130) is formed to heal defects formed on the sidewalls and bottom surface of the trench (T) and to increase stability. It also serves to improve the reliability of the capacitor by ensuring electrical insulation between the silicon substrate (110) and the (MIM)n (n≥2) electrode layer formed in a subsequent process.

[0044] The thermal oxide film liner (130) can be formed by applying dry oxidation carried out at 900 to 1100°C using O2 or a mixed gas of O2 and HCl, or wet oxidation carried out at 800 to 1000°C using H2O vapor.

[0045] The thickness of the thermal oxide film can be formed to be 150 to 500 Å. The thickness of the thermal oxide film liner (130) can vary depending on the design conditions.

[0046] For example, if the focus is on withstanding stress caused by (MIM)n (n≥2) to be formed on the thermal oxide film liner (130) in a subsequent process, the thickness of the thermal oxide film liner (130) can be formed to be greater than the thinnest thickness among the (MIM)n (n≥2) electrode layers.

[0047] On the other hand, the critical dimension of the trench can be formed within the range of 0.05 to 0.6 μm, and the thickness of the thermal oxide film liner (130) can be formed to be smaller than the thinnest thickness among the (MIM)n (n≥2) electrode layers, thereby sufficiently securing space for MIMn (n≥2) to be formed inside the trench. More preferably, the thickness of the thermal oxide film liner (130) can be formed to be thinner than half the thickness of the thinnest thickness among the electrode layers.

[0048] FIG. 4 is a cross-sectional view illustrating the process of forming (MIM)n (n=3) on a thermal oxide film liner (130). When n is 2, it becomes a MIMIM structure, when n is 3, it becomes a MIMIMIM structure, and when n is 4, it becomes a MIMIMIMIM structure. FIG. 4 illustrates the case where n is 3.

[0049] The first to fourth electrode layers (CEL1, CEL2, CEL3, CEL4) and the first to third dielectric layers (DL1, DL2, DL3) are alternately formed to form (MIM)n (n=3).

[0050] A first electrode layer (CEL1) is in contact with the thermal oxide film liner (130), and the uppermost layer of (MIM)n (n≥3) is composed of a fourth electrode layer (CEL4).

[0051] The first to fourth electrode layers (CEL1, CEL2, CEL3, CEL4) may be formed of a compound comprising at least one of tungsten, copper, titanium nitride, ruthenium, or aluminum, or composed of at least one of these.

[0052] The first to third dielectric layers (DL1, DL2, DL3) may each be formed by including, for example, at least one of titanium oxide, zirconium oxide, hafnium oxide, and aluminum oxide. (MIM)n (n=3) is conformally formed on the thermal oxide film liner (130). The top metal layer (CEL4) of (MIM)n (n=3) is uniformly lined into the trench from the upper surface of the substrate (110). In principle, the top metal layer (CEL4) can be completely bonded within the trench when the critical dimension of the trench, 0.05 to 0.6 μm, is equal to twice the total thickness of the electrode layers (CEL1, CEL2, CEL3, CEL4) and dielectric layers (DL1, DL2, DL3) of (MIM)n (n≥2). Alternatively, if the process margin is optionally allowed to be slightly more generous, a U-shaped or V-shaped linear or gap-shaped seam (not shown) may be formed in the space between the uppermost metal layers (CEL4) that meet each other. The seam may be continuous or discontinuous. Compared to voids, the seam is relatively significantly less likely to cause defects in subsequent processes. Additionally, the seam has the advantage of absorbing and minimizing stress caused by the deposition of (MIM)n film within the trench. The seam can be made to have a width of 1 to 100 nm. Additionally, the seam can be made to have a depth of 20 to 20,000 nm. By controlling the width and depth in this way, it is possible to prevent defects in subsequent processes caused by cavity formation during the process and to minimize stress caused by (MIM)n deposition.

[0053] An insulating film (e.g., PETEOS) (150) is formed on the (MIM) n. The insulating film is intended to prevent the photoresist formed for etching the electrode layer described below from entering the trench.

[0054] A process for completing the DTC will be described below with reference to FIGS. 5 to 9.

[0055] As shown in FIG. 5, the fourth electrode layer (CEL4) placed in the second to fourth space regions (S2, S3, S4), excluding the first space region (S1), is etched so that the fourth electrode layer (CEL4) is opened in the corresponding region.

[0056] At this time, the etching width (EW3) of the third space area (S3) is larger than the etching width (EW2) of the second space area (S2), and the etching width (EW4) of the fourth space area (S4) is larger than the etching width (EW3) of the third space area (S3).

[0057] When the fourth electrode layer (CEL4) is etched, the third dielectric layer (DL3) functions as an etch stop layer. Consequently, the third dielectric layer (DL3) is exposed by the patterned fourth electrode layer (CEL4), and the third electrode layer (CEL3) is not exposed. Therefore, the polymer-based etching byproduct generated during the etching of the fourth electrode layer (CEL4) is fundamentally prevented from coming into contact with the third electrode layer (CEL3). The byproduct generated during etching is easily removed by O2 plasma, etc., during the cleaning process after etching.

[0058] Because it is used as an etch stop layer, the exposed third etch stop dielectric layer (DL3') has a thickness greater than 0 and thinner than the third dielectric layer (DL3) sandwiched between the fourth electrode layer (CEL4) and the third electrode layer (CEL3). By controlling the process conditions, it is desirable that at least 10% of the thickness of the third dielectric layer (DL3) between the electrode layers (CEL4, CEL3) remains exposed in the third etch stop dielectric layer (DL3'). More preferably, it is desirable that about 30 to 70% remains.

[0059] Subsequently, as shown in FIG. 6, the third electrode layer (CEL3) placed in the third space region (S3) and the fourth space region (S4) is etched so that the third electrode layer (CEL3) is opened in the corresponding region.

[0060] At this time, the etching width (EW3', EW4') of the third electrode layer (CEL3) may have a width smaller than the etching width (EW2, EW3) of the fourth electrode layer (CEL4) described in FIG. 5. Accordingly, as shown in FIG. 6 (b), the cross-sectional shape in the third and fourth space regions (S3, S4) may have a stepped shape.

[0061] When the third electrode layer (CEL3) is etched, the second dielectric layer (DL2) functions as an etch stop layer. Consequently, the second dielectric layer (DL2) is exposed by the patterned third electrode layer (CEL3), and the second electrode layer (CEL2) is not exposed. Therefore, the polymer-based etching byproduct generated during the etching of the third electrode layer (CEL3) is fundamentally prevented from coming into contact with the second electrode layer (CEL2). The byproduct generated during etching is easily removed by O2 plasma, etc., during the cleaning process after etching.

[0062] Because it is used as an etch stop layer, the exposed second etch stop dielectric layer (DL2') has a thickness greater than 0 and thinner than the second dielectric layer (DL2) sandwiched between the third electrode layer (CEL3) and the second electrode layer (CEL3). By controlling the process conditions, it is desirable that at least 10% of the thickness of the second dielectric layer (DL2) between the electrode layers (CEL3, CEL2) remains exposed in the second etch stop dielectric layer (DL2'). More preferably, it is desirable that about 30 to 70% remains.

[0063] Subsequently, as shown in FIG. 7, the second electrode layer (CEL2) placed in the fourth space region (S4) is etched so that the second electrode layer (CEL2) is opened in that region. The etching width (EW4'') of the second electrode layer (CEL2) may be smaller than the etching width (EW4') of the third electrode layer (CEL3). Therefore, as shown in FIG. 7 (b), the cross-sectional shape in the fourth space region (S4) may have a stepped shape.

[0064] Accordingly, the electrode layer pattern formed in the second to fourth space regions (S2, S3, S4) is formed in a step shape, and the step heights in each space region are different from each other. That is, there is one step in the second space region (S2), two steps in the third space region (S3), and three steps in the fourth space region (S4). FIG. 7 illustrates the case where n is 3 in (MIM)n, so there are three different steps, but when n is 2, there are two different steps, and when n is 4, there are four different steps.

[0065] When the second electrode layer (CEL2) is etched, the first dielectric layer (DL1) functions as an etch stop layer. Consequently, the first dielectric layer (DL1) is exposed by the patterned second electrode layer (CEL2), and the first electrode layer (CEL1) is not exposed. Therefore, the polymer-based etching byproduct generated during the etching of the second electrode layer (CEL2) is fundamentally prevented from coming into contact with the first electrode layer (CEL1). The byproduct generated during etching is easily removed by O2 plasma, etc., during the cleaning process after etching.

[0066] Because it is used as an etch stop layer, the exposed first etch stop dielectric layer (DL1') has a thickness greater than 0 and thinner than the first dielectric layer (DL1) sandwiched between the second electrode layer (CEL2) and the first electrode layer (CEL1). By controlling the process conditions, it is preferable that at least 10% of the thickness of the first dielectric layer (DL1) between the electrode layers (CEL2, CEL1) remains exposed in the first etch stop dielectric layer (DL1'). More preferably, it is preferable that about 30 to 70% remains.

[0067] Accordingly, in the first space region (S1) on the substrate (110), the fourth electrode layer (CEL4) is exposed on the upper surface, in the second space region (S2), the third etching stop dielectric layer (DL3') is exposed, in the third space region (S3), the second etching stop dielectric layer (DL2') is exposed, and in the fourth space region (S4), the first etching stop dielectric layer (DL1') can be exposed. By forming such an exposed structure, the formation of contact holes of different depths (H1, H2, H3, H4 of FIG. 8), which will be described below, can be carried out simultaneously.

[0068] Subsequently, as shown in FIG. 8, a first insulating layer (160) is formed. The first insulating layer (160) may be made of an insulating material including a nitride or an oxide, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a diffusion process, or any combination thereof.

[0069] The first insulating layer (160) is flattened through a flattening process. Subsequently, the first insulating layer (160) and the first to third dielectric layers (DL1, DL2, DL3) in contact with the first insulating layer (160) are etched to simultaneously form a plurality of contact holes (H1, H2, H3, H4) that expose the fourth electrode layer (CEL4), the third electrode layer (CEL3), the second electrode layer (CEL2), and the first electrode layer (CEL1), respectively. At this time, the number of the plurality of contact holes (H1, H2, H3, H4) formed in the first insulating layer (160) may correspond to the number of electrode layers (CEL1, CEL2, CEL3, CEL4).

[0070] More specifically, a first contact hole (H1) is formed in the first insulating layer (160) corresponding to the first space area (S1) to expose the fourth electrode layer (CEL4), a second contact hole (H2) is formed in the first insulating layer (160) corresponding to the second space area (S2) to expose the third electrode layer (CEL3), a third contact hole (H3) is formed in the first insulating layer (160) corresponding to the third space area (S3) to expose the second electrode layer (CEL2), and a fourth contact hole (H4) is formed in the first insulating layer (160) corresponding to the fourth space area (S4) to expose the first electrode layer (CEL1).

[0071] When forming the first to fourth contact holes (H1, H2, H3, H4), over-etching is performed on each of the electrode layers (CEL4, CEL3, CEL2, CEL1) to be exposed, such that at least 10% of the thickness of each electrode layer (CEL4, CEL3, CEL2, CEL1) remains. Preferably, at least 2 / 3 of the thickness of each electrode layer (CEL4, CEL3, CEL2, CEL1) remains.

[0072] This effectively prevents an increase in leakage current caused by physical damage, delamination, or the induction of pinholes in the dielectric layer beneath the electrode layer when the metal contact formed in the subsequent process lands on the electrode layer (CEL4, CEL3, CEL2, CEL1), and can improve Time-Dependent Dielectric Breakdown (TDDB) characteristics.

[0073] Meanwhile, since the first to fourth contact holes (H1, H2, H3, H4) of different depths are etched simultaneously, the thicknesses of the electrode layers (CEL4, CEL3, CEL2, CEL1) exposed by the first to fourth contact holes (H1, H2, H3, H4) may differ depending on the degree of exposure to etching. For example, the fourth electrode layer (CEL4) exposed by the first contact hole (H1) is exposed to the etching process the most, and the first electrode layer (CEL1) exposed by the fourth contact hole (H4) is exposed to the etching process for the shortest amount of time. Accordingly, the thickness can be in the order of the fourth electrode layer (CEL4) exposed by the first contact hole (H1) < the third electrode layer (CEL3) exposed by the second contact hole (H2) < the second electrode layer (CEL2) exposed by the third contact hole (H3) < the first electrode layer (CEL1) exposed by the fourth contact hole (H4).

[0074] Afterward, as shown in FIG. 9a, the first to fourth contact holes (H1, H2, H3, H4) on the first insulating layer (160) are filled with a metallic material to form the first to fourth contacts (MC1, MC2, MC3, MC4). FIG. 9b is a schematic diagram showing the depth difference of each space area (S1, S2, S3, S4) in sequence enlarged to show the depth difference of the first to fourth contacts (MC1, MC2, MC3, MC4).

[0075] Referring to FIGS. 9a and 9b, each electrode layer (CEL1, CEL2, CEL3, CEL4) is divided into a contact portion that contacts the corresponding contact (MC4, MC3, MC2, MC1) and a non-contact portion that does not contact (in particular, a region in which at least one surface contacts the dielectric layer (DL3, DL2, DL1) to form capacitance). At this time, the thickness of the electrode layer in the contact portion that contacts each contact is smaller than the thickness of the electrode layer in the non-contact portion.

[0076] Specifically, the thickness (X1) of the first electrode layer (CEL1) of the contact portion contacted by the fourth contact (MC4) is smaller than the thickness (Y1) of the first electrode layer (CEL1) of the non-contact portion not contacted by the fourth contact (MC4). The difference in thickness of the electrode layers between the contact portion and the non-contact portion applies equally to the remaining contacts (MC3, MC2, MC1). The thickness of the second electrode layer (CEL2) of the contact portion contacted by the third contact (MC3) is smaller than the thickness of the second electrode layer (CEL2) of the non-contact portion. The thickness of the third electrode layer (CEL3) of the contact portion contacted by the second contact (MC2) is smaller than the thickness of the third electrode layer (CEL3) of the non-contact portion. The thickness of the fourth electrode layer (CEL4) of the contact portion contacted by the first contact (MC1) is smaller than the thickness of the fourth electrode layer (CEL4) of the non-contact portion. And, as explained in FIG. 8, due to the difference in time exposed to the etching process, the relationship can be established as follows: thickness (X4) of the fourth electrode layer (CEL4) in contact with the first contact (MC1) < thickness (X3) of the third electrode layer (CEL3) in contact with the second contact (MC2) < thickness (X2) of the second electrode layer (CEL2) in contact with the third contact (MC3) < thickness (X1) of the first electrode layer (CEL1) in contact with the fourth contact (MC4).

[0077] Additionally, as described in FIG. 7, the conductive contacts (MC2, MC3, MC4) that contact the first to nth electrode layers (CEL1, CEL2, CEL3 when n=3), excluding the uppermost electrode layer (i.e., the n+1th electrode layer, CEL4 when n=3), each include an etching stop dielectric layer (DL3', DL2' DL1') that surrounds them and extends to the dielectric layer (DL3, DL2, DL1) on the electrode layers (CEL1, CEL2, CEL3) that contact each conductive contact, and is thinner than the dielectric layer (DL3, DL2, DL1).

[0078] More specifically, the periphery of the fourth contact (MC4) in contact with the first electrode layer (CEL1) is surrounded by a first etching stop dielectric layer (DL1') that extends from the first dielectric layer (DL1) on the upper surface of the first electrode layer (CEL1) and has a thickness (x) thinner than the thickness (y) of the first dielectric layer (DL1). And, the fourth contact (MC4) is exposed by a fourth electrode pattern, a third electrode pattern, and a second electrode pattern formed in a stepped shape.

[0079] Around the third contact (MC3) that contacts the second electrode layer (CEL2), a second etching stop dielectric layer (DL2') extending from the second dielectric layer (DL2) on the upper surface of the second electrode layer (CEL2) and having a thickness (x2) thinner than the thickness (y2) of the second dielectric layer (DL1) surrounds it. And, the third contact (MC3) is exposed by a fourth electrode pattern and a third electrode pattern formed in a stepped shape.

[0080] Around the second contact (MC2) that contacts the third electrode layer (CEL3), a third etching stop dielectric layer (DL3') extending from the third dielectric layer (DL3) on the upper surface of the third electrode layer (CEL3) and having a thickness (x3) thinner than the thickness (y3) of the third dielectric layer (DL3) surrounds it. And, the second contact (MC2) has a structure in which it is surrounded by a fourth electrode pattern.

[0081] Next, a metal layer (M1) is formed on the first insulating layer (160) and then patterned to form a plurality of routing metal patterns electrically connected to each of the first to fourth electrode layers (CEL1, CEL2, CEL3, CEL4). At this time, the plurality of routing metal patterns may correspond to the number of the first to fourth electrode layers (CEL1, CEL2, CEL3, CEL4). More specifically, a first routing metal pattern (RM1) is formed on the first insulating layer (160) corresponding to the first space (S1) and electrically connected to the fourth electrode layer (CEL4) through a first contact (MC1). A second routing metal pattern (RM2) is formed on the first insulating layer (160) corresponding to the second space (S2) and electrically connected to the third electrode layer (CEL3) through a second contact (MC2). A third routing metal pattern (RM3) is formed on the first insulating layer (160) corresponding to the third space (S3) and is electrically connected to the second electrode layer (CEL2) through the third contact (MC3). A fourth routing metal pattern (RM4) is formed on the first insulating layer (160) corresponding to the fourth space (S4) and is electrically connected to the first electrode layer (CEL1) through the fourth contact (MC4).

[0082] Next, as illustrated in FIG. 10, a second insulating layer (170) is formed on a first insulating layer (160) on which first to fourth routing metal patterns (RM1, RM2, RM3, RM4) are formed. The second insulating layer (170) may be made of an insulating material including a nitride or an oxide, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a diffusion process, or any combination thereof.

[0083] Subsequently, the second insulating layer (170) forms fifth to eighth contacts (MC5, MC6, MC7, MC8) that contact each of the first to fourth routing metal patterns (RM1, RM2, RM3, RM4). Then, a plurality of metal pads (MP1, MP2) are formed that are electrically connected to each of the first to fourth routing metal patterns (RM1, RM2, RM3, RM4) through the fifth to eighth contacts (MC5, MC6, MC7, MC8).

[0084] Here, the metal pads (MP1, MP2), the first to fourth routing metal patterns (RM1, RM2, RM3, RM4), and the first to eighth contacts (MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8) may be collectively referred to as a metal contact (MC) or a conductive contact structure.

[0085] A ground voltage can be transmitted to the first pad (MP1), which is connected to the first electrode layer (CEL1) and the third electrode layer (CEL3) through the first and third routing metal patterns (RM1, RM3), and a source voltage can be transmitted to the second pad (MP2), which is connected to the second electrode layer (CEL2) and the fourth electrode layer (CEL4) through the second and fourth routing metal patterns (RM2, RM4). As shown in FIG. 10, the capacitance can be increased by connecting MIM capacitors in parallel.

[0086] FIG. 11 is a STEM-EDS (Scanning Transmission Electron Microscopy - Energy Dispersive X-ray Spectroscopy) image of a third space region (S3) in which a third contact (MC3) in contact with the second electrode layer (CEL2) is formed.

[0087] Referring to FIG. 11, the thickness of the second electrode layer (CEL2) in contact with the third contact (MC3) is smaller than the thickness of the second electrode layer (CEL2) sandwiched between the first dielectric layer (DL1) and the second dielectric layer (DL2). The thickness of the second electrode layer (CEL2) in contact with the metal contact (MC3) remains about 2 / 3 of the thickness of the second electrode layer (CEL2) sandwiched between the first dielectric layer (DL1) and the second dielectric layer (DL2).

[0088] Meanwhile, the cross-sectional shape around the metal contact (M3) exhibits a stepped shape due to the pattern of the fourth electrode layer (CEL4) and the pattern of the third electrode layer (CEL3). The third etching stop dielectric layer (DL3') is exposed by the pattern of the fourth electrode layer (CEL4), and the second etching stop dielectric layer (DL2') is exposed by the pattern of the third electrode layer (CEL3). The third etching stop dielectric layer (DL3') and the second etching stop dielectric layer (DL2') are formed in a structure that surrounds the periphery of the metal contact (MC).

[0089] Because it functions as an etching stop layer, the second etching stop dielectric layer (DL2') is thinner than the second dielectric layer (DL2) sandwiched between the second electrode layer (CEL2) and the third electrode layer (CEL3), and the third etching stop dielectric layer (DL3') is thinner than the third dielectric layer (DL3) sandwiched between the second electrode layer (CEL2) and the third electrode layer (CEL3).

[0090] FIG. 12 is a TEM (Transmission Electron Microscopy) image of a second space region (S2) in which a second contact (MC2) in contact with a third electrode layer (CEL3) is formed, and a TEM image of a third space region (S3) in which a third contact (MC3) in contact with the second electrode layer (CEL2) is formed.

[0091] As shown in FIG. 12, the third etching stop dielectric layer (DL3') surrounds the second contact (MC2) and the second etching stop dielectric layer (DL2') surrounds the third contact (MC3), forming a structure.

[0092] In addition, the thickness of the third electrode layer (CEL3) in contact with the third contact (MC3) is smaller than the thickness of the third electrode layer (CEL3) sandwiched between the third dielectric layer (DL3) and the second dielectric layer (DL2). Also, the thickness of the second electrode layer (CEL2) in contact with the second contact (MC2) is smaller than the thickness of the second electrode layer (CEL2) sandwiched between the second dielectric layer (DL2) and the first dielectric layer (DL1). Furthermore, it can be confirmed that the thickness of the electrode layer in the contact area with the contact has a thickness of at least 2 / 3 of the original electrode layer thickness. Moreover, it can be seen that the thickness of the third electrode layer (CEL3) in contact with the third contact (MC3) is smaller than the thickness of the second electrode layer (CEL2) in contact with the second contact (MC2).

[0093] Also, the third etching stop dielectric layer (DL3') is thinner than the second etching stop dielectric layer (DL2').

[0094] By adopting the etching stop dielectric layer structure and the electrode layer in contact with the contact described above, short circuits can be effectively prevented without increasing process complexity, and electrode damage can be prevented while maintaining electrical and mechanical reliability.

[0095] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also included within the scope of the present invention.

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 A step of forming trenches on a substrate according to a layout in which unit cells are configured as a matrix array, wherein the unit cells include four trench arrays and first to fourth space regions, the first and second space regions are spaced apart and repeatedly arranged along a first axis on the substrate, and the third and fourth space regions are spaced apart and repeatedly arranged along a second axis perpendicular to the first axis, so that the first to fourth space regions define quadrant regions, the four trench arrays are arranged in a pinwheel shape in the corresponding regions of the quadrants, and at least three of the first to fourth space regions have different widths, and the entire structure is divided into n+1 (n≥2) space regions having different widths, and the unit cells form trenches such that they have a rotationally asymmetric shape with respect to the center of the unit cells; A step of conformally forming first to n+1 (n≥2) electrode layers and first to n (n≥2) dielectric layers alternately within the trench; a step of forming different stepped electrode layer patterns in each of the n+1 (n≥2) space regions having different widths, wherein when etching the n+1 (n≥2)th electrode layer, the lower n (n≥2)th dielectric layer is used as an etching stop layer for etching; a step of forming an insulating layer on the substrate; and a step of simultaneously forming conductive contact holes that expose the first to n+1 electrode layers in the insulating layer, wherein each of the conductive contact holes is arranged according to the space regions of different widths, and the conductive contact holes are formed by performing over-etching such that at least 2 / 3 of the thickness of the corresponding first to n+1 electrode layers remains.A method for manufacturing a high-density deep trench capacitor, comprising the step of filling the conductive contact holes with a metallic material to form first to n+1 contacts that contact the first to n+1 electrode layers, wherein the thickness of the contact portion where each electrode layer contacts the corresponding conductive contact is smaller than the thickness of the remaining non-contact portion. Claim 17 delete Claim 18 delete Claim 19 A method for manufacturing a high-density deep trench capacitor according to claim 16, wherein, in the step of etching the n+1 (n≥2) electrode layer using the n (n≥2) dielectric layer as an etching stop layer, at least 10% of the thickness of the n (n≥2) dielectric layer remains. Claim 20 A method for manufacturing a high-density deep trench capacitor according to claim 16, wherein, in the step of etching the n+1 (n≥2) electrode layer using the n (n≥2) dielectric layer as an etching stop layer, at least 30 to 70% of the thickness of the n (n≥2) dielectric layer remains. Claim 21 In claim 16, the method for manufacturing a high-density deep trench capacitor in which (MIM)n (n≥2) are connected in parallel within the unit cell. Claim 22 A method for manufacturing a high-density deep trench capacitor according to claim 16, wherein the ratio of the line and space of the plurality of trenches is 1:0.3 to 1:

5. Claim 23 A method for manufacturing a high-density deep trench capacitor according to claim 16, wherein the critical dimension of the trench is 0.05 to 0.6 μm. Claim 24 A method for manufacturing a high-density deep trench capacitor according to claim 16, wherein the residual thickness of the first electrode layer is greater than the residual thickness of the n+1 electrode layer.

Images