Display apparatus

Abstract

The present invention provides a display device for a display device with improved resolution, comprising: a first transistor including a first semiconductor layer and a first electrode that overlaps at least partially with the first semiconductor layer; a first capacitor including the first electrode and a second electrode that overlaps at least partially with the first electrode; a second capacitor including the second electrode and a third electrode that overlaps at least partially with the second electrode; a first data line configured to transmit a data voltage; first and second scan lines configured to transmit first and second scan signals, respectively; a second transistor that connects the first data line to the second electrode in response to the first scan signal; and a third transistor that connects the first electrode to the drain of the first transistor in response to the second scan signal.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] A display device includes multiple pixels that receive electrical signals and emit light to display an image externally. Each pixel includes a display element; for example, in the case of an organic light-emitting display device, it includes an organic light-emitting diode (OLED) as the display element. Generally, an organic light-emitting display device forms thin-film transistors and organic light-emitting diodes on a substrate, and operates by the organic light-emitting diode emitting light on its own.

[0004] Recently, as the applications of display devices have become more diverse, various design attempts are being made to improve the quality of display devices. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device in which the resistance of the connecting line connecting the data line to the pad portion is reduced and the resolution is improved.

[0006] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description of the present invention. means of solving the problem

[0007] According to one aspect of the present invention, a display device is provided comprising: a first transistor including a first semiconductor layer and a first electrode that overlaps at least partially with the first semiconductor layer; a first capacitor including the first electrode and a second electrode that overlaps at least partially with the first electrode; a second capacitor including the second electrode and a third electrode that overlaps at least partially with the second electrode; a first data line configured to transmit a data voltage; first and second scan lines configured to transmit first and second scan signals, respectively; a second transistor that connects the first data line to the second electrode in response to the first scan signal; and a third transistor that connects the first electrode to the drain of the first transistor in response to the second scan signal.

[0008] According to one example, the third transistor is disposed on the first transistor and includes a second semiconductor layer and a fourth electrode that overlaps at least partially with the second semiconductor layer, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0009] According to one example, the display device further comprises a substrate having a display area and a peripheral area that partially surrounds the display area; second and third data lines disposed on the display area; a pad portion disposed on one side of the peripheral area and including first to third data pads; a first connecting line connecting the first data line disposed on the display area to the first data pad; a second connecting line connecting the second data line to the second data pad; and a third connecting line connecting the third data line to the third data pad, wherein the first to third connecting lines may be disposed on different layers.

[0010] According to one example, the first connecting line may be placed on the same layer as the first electrode, the second connecting line may be placed on the same layer as the fourth electrode, and the third connecting line may be placed on the same layer as the third electrode.

[0011] According to one example, the display device may further include a fifth electrode disposed below the second semiconductor layer, which overlaps at least partially with the second semiconductor layer and is electrically connected to the fourth electrode.

[0012] According to one example, the fifth electrode may be placed on the same layer as the second electrode or on the same layer as the third electrode.

[0013] According to one example, the conductivity type of the first transistor may be opposite to the conductivity type of the third transistor.

[0014] According to one example, the conductivity type of the second transistor may be the same as the conductivity type of the third transistor.

[0015] According to one example, the display device may further include a power line electrically connected to the third electrode and configured to transmit a driving voltage.

[0016] According to one example, the display device may further include: a display element having an anode and a cathode; a third scan line transmitting a third scan signal; a fourth scan line transmitting a fourth scan signal; a light emission control line transmitting a light emission control signal; a first voltage line configured to transmit an initialization voltage; a fourth transistor connecting the first voltage line to the first electrode in response to the third scan signal; a fifth transistor connecting the power line to the source of the first transistor in response to the light emission control signal; a sixth transistor connecting the drain of the first transistor to the anode of the display element in response to the light emission control signal; and a seventh transistor connecting the first voltage line to the anode of the display element in response to the fourth scan signal.

[0017] According to one example, the display device may further include a second voltage line configured to transmit a reference voltage; and an eighth transistor that connects the second voltage line to the second electrode in response to the second scan signal.

[0018] According to one example, the display device may further include a third voltage line configured to transmit a bias voltage; and a ninth transistor that connects the third voltage line to the source of the first transistor in response to the fourth scan signal.

[0019] According to another aspect of the present invention, a display device is provided comprising: a substrate having a display area and a peripheral area that at least partially surrounds the display area; a plurality of data lines arranged in a first direction on the display area; a pad portion disposed on one side of the peripheral area and including a plurality of data pads; a plurality of first connecting lines connecting a first data line, which is a part of the plurality of data lines, to a corresponding data pad among the plurality of data pads; a plurality of second connecting lines connecting a second data line, which is another part of the plurality of data lines, to a corresponding data pad among the plurality of data pads; and a plurality of third connecting lines connecting a third data line, which is yet another part of the plurality of data lines, to a corresponding data pad among the plurality of data pads, wherein the plurality of first connecting lines, the plurality of second connecting lines, and the plurality of third connecting lines are disposed on different layers.

[0020] According to one example, the plurality of first connecting lines and the plurality of second connecting lines are each placed between two third connecting lines adjacent in the first direction among the plurality of third connecting lines, and can be arranged alternately along the first direction.

[0021] According to one example, the plurality of second connecting lines may be placed on the plurality of first connecting lines, and the plurality of third connecting lines may be placed on the plurality of second connecting lines.

[0022] According to one example, the number of the plurality of third connecting lines per unit area is greater than the number of the plurality of first connecting lines per unit area, and the number of the plurality of third connecting lines per unit area may be greater than the number of the plurality of second connecting lines per unit area.

[0023] According to one example, the number of the plurality of first connecting lines per unit area may be the same as the number of the plurality of second connecting lines per unit area.

[0024] According to one example, the plurality of third connecting lines may have a multilayer structure.

[0025] According to one example, each of the plurality of third connecting lines may include a first layer, a third layer on the first layer, and a second layer interposed between the first layer and the third layer.

[0026] According to one example, the plurality of second connecting lines may have the same layer structure as the plurality of third connecting lines.

[0027] According to one example, the display device may further include: a first transistor disposed in the display area and comprising a first semiconductor layer and a first electrode that overlaps at least partially with the first semiconductor layer; a first capacitor disposed in the display area and comprising a first electrode and a second electrode that overlaps at least partially with the first electrode; a second capacitor disposed in the display area and comprising a second electrode and a third electrode that overlaps at least partially with the second electrode; and a second transistor disposed on the first transistor in the display area and comprising a second semiconductor layer and a fourth electrode that overlaps at least partially with the second semiconductor layer.

[0028] According to one example, the plurality of first connecting lines may be placed on the same layer as the first electrode, the plurality of second connecting lines may be placed on the same layer as the third electrode, and the plurality of third connecting lines may be placed on the same layer as the fourth electrode.

[0029] According to one example, the plurality of first connecting lines may be placed on the same layer as the first electrode, the plurality of second connecting lines may be placed on the same layer as the second electrode, and the plurality of third connecting lines may be placed on the same layer as the third electrode.

[0030] According to one example, the plurality of first connecting lines may be placed on the same layer as the first electrode, the plurality of second connecting lines may be placed on the same layer as the second electrode, and the plurality of third connecting lines may be placed on the same layer as the fourth electrode.

[0031] According to one example, the plurality of first connecting lines may be placed on the same layer as the second electrode, the plurality of second connecting lines may be placed on the same layer as the third electrode, and the plurality of third connecting lines may be placed on the same layer as the fourth electrode.

[0032] Other aspects, features, and advantages other than those described above will become clear from the specific details, claims, and drawings for implementing the invention below.

[0033] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0034] According to various embodiments of the present invention, the resistance of the connecting line connecting the data line to the pad portion can be reduced. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0035] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention. FIG. 2 is a plan view schematically illustrating a display device according to one embodiment of the present invention. FIG. 3 is an equivalent circuit diagram showing one pixel arranged in a display device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating a part of a pixel according to one embodiment of the present invention. FIG. 5 is a cross-sectional view schematically illustrating a part of a pixel according to one embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 7 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 8 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 9 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 10 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 11 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 12 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. FIG. 13 is a cross-sectional view schematically illustrating connecting lines according to one embodiment of the present invention. Specific details for implementing the invention

[0036] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0038] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0039] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0041] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of the other part, but also cases where another film, region, or component is interposed therein.

[0042] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0043] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0044] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0045] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0046] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0047] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0048] Referring to FIG. 1, the display device (1) includes a display area (DA) for displaying an image and a peripheral area (PA) placed around the display area (DA). The display device (1) can provide an image to the outside using light emitted from the display area (DA). Of course, since the display device (1) includes a substrate (100), it can be said that the substrate (100) has such a display area (DA) and a peripheral area (PA).

[0049] The substrate (100) may be composed of various materials such as glass, metal, or plastic. According to one embodiment, the substrate (100) may include a flexible material. Here, the flexible material may be a material that can be easily bent, folded, or rolled. The substrate (100) of such a flexible material may be composed of ultra-thin glass, metal, or plastic.

[0050] Pixels (PX) equipped with various display elements, such as organic light-emitting diodes (OLEDs), may be arranged in the display area (DA) of the substrate (100). The pixels (PX) may be composed of multiple pixels, and the multiple pixels (PX) may be arranged in various forms, such as a stripe array, a pentile array, or a mosaic array, to create an image.

[0051] In FIG. 1, the planar shape of the display area (DA) is shown as a rectangle, but in other embodiments, the display area (DA) may be provided in a polygonal shape such as a triangle, pentagon, or hexagon, or in a circular shape, elliptical shape, irregular shape, etc.

[0052] The peripheral area (PA) of the substrate (100) is an area placed around the display area (DA) and may be an area where no image is displayed. Various wirings that transmit electrical signals to be applied to the display area (DA), and pads to which printed circuit boards or driver IC chips are attached may be located in the peripheral area (PA).

[0053] FIG. 2 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0054] Referring to FIG. 2, the display device (1, see FIG. 1) may include a display panel (10), a printed circuit board (PCB), and a data driving circuit (150).

[0055] The display panel (10) may include a display area (DA) and a surrounding area (PA) that surrounds at least a portion of the display area (DA). The display area (DA) may be covered by a sealing member (not shown) to be protected from the outside air or moisture, etc.

[0056] The display panel (10) may include a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), a plurality of data lines (DL), and a plurality of power lines (PL) disposed in a display area (DA).

[0057] Each pixel (PX) may include a display element such as an organic light-emitting diode (OLED). Each pixel (PX) may emit light of, for example, red, green, blue, or white through the organic light-emitting diode (OLED). In the following specification, each pixel (PX) refers to a sub-pixel that emits a different color, and each pixel (PX) may be, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0058] Each scan line (SL) can be extended in a first direction (e.g., ±x direction) and connected to pixels (PX) located in the same row among a plurality of pixels (PX). The scan lines (SL) can be arranged in a second direction (e.g., ±y direction). In FIG. 2, the scan line (SL) is shown as a single wire, but in another embodiment, the scan line (SL) can be composed of a plurality of wires.

[0059] Each light emission control line (EL) can be extended in a first direction (e.g., ±x direction) and connected to pixels (PX) located in the same row among a plurality of pixels (PX). The light emission control lines (EL) can be arranged in a second direction (e.g., ±y direction). Although the light emission control line (EL) is shown as a single wire in FIG. 2, in another embodiment, the light emission control line (EL) can be composed of a plurality of wires.

[0060] Each data line (DL) can be extended in a second direction (e.g., ±y direction) and connected to pixels (PX) located in the same column among a plurality of pixels (PX). The data lines (DL) can be arranged in a first direction (e.g., ±x direction).

[0061] Each power line (PL) can be extended in a second direction (e.g., ±y direction) and connected to pixels (PX) located in the same column among a plurality of pixels (PX). The power lines (PL) can be arranged in a first direction (e.g., ±x direction).

[0062] The display panel (10) may include a first gate driving circuit (130), a second gate driving circuit (131), a first voltage supply wiring (160), a second voltage supply wiring (170), and a pad portion (140) disposed in a peripheral area (PA). Each pixel (PX) may be electrically connected to the peripheral circuits disposed in the peripheral area (PA).

[0063] The first gate driving circuit (130) and the second gate driving circuit (131) may each include a scan driving circuit and a light emission control driving circuit. The scan driving circuit may provide a scan signal to each pixel (PX) through a scan line (SL). The light emission control driving circuit may provide a light emission control signal to each pixel (PX) through a light emission control line (EL).

[0064] The second gate driving circuit (131) may be positioned parallel to the first gate driving circuit (130) with the display area (DA) in between. Some of the pixels (PX) placed in the display area (DA) may be electrically connected to the first gate driving circuit (130), and the rest may be connected to the second gate driving circuit (131). In another embodiment, the second gate driving circuit (131) may be omitted.

[0065] The first voltage supply wiring (160) may include a first sub-wiring (162) and a second sub-wiring (163) that extend parallel along a first direction (e.g., ±x direction) with the display area (DA) in between. The second voltage supply wiring (170) may partially surround the display area (DA) in a loop shape with one side open.

[0066] The pad portion (140) may be positioned on one side of the peripheral area (PA). The pad portion (140) may include a plurality of pads, such as data pads (DP). The pad portion (140) may be exposed without being covered by an insulating layer and may be electrically connected to a printed circuit board (PCB). The pads of the pad portion (140) may be electrically connected to terminal portions (PCB-P) of the printed circuit board (PCB). The printed circuit board (PCB) may transmit a signal or voltage from a control unit (not shown) to a display panel (10).

[0067] The control signal generated in the control unit can be transmitted to the first gate driving circuit (130) and the second gate driving circuit (131), respectively, through the printed circuit board (PCB) and the pad unit (140).

[0068] The first driving voltage (ELVDD, see FIG. 3) generated by the control unit can be transmitted to the first voltage supply wiring (160) through the first connection wiring (161) connected to the pad of the pad unit (140). The first driving voltage (ELVDD) can be provided to each pixel (PX) through a power line (PL) connected to the first voltage supply wiring (160).

[0069] The second driving voltage (ELVSS, see FIG. 3) generated by the control unit can be transmitted to the second voltage supply wiring (170) through the second connection wiring (171) connected to the pad of the pad unit (140). The second driving voltage (ELVSS) can be provided to the cathode (or, opposing electrode) of the display element connected to the second voltage supply wiring (170).

[0070] The data driving circuit (150) can be electrically connected to data lines (DL). The data signal (or data voltage) of the data driving circuit (150) can be provided to each pixel (PX) through a connection line (CL) connected to a data pad (DP) of the pad section (140), and a data line (DL) connected to the connection line (CL).

[0071] In FIG. 2, the data driving circuit (150) is shown as being placed on a printed circuit board (PCB), but in another embodiment, the data driving circuit (150) may be placed on a substrate (100). For example, the data driving circuit (150) may be placed between the pad portion (140) and the first voltage supply wire (160).

[0072] Meanwhile, as described above, a connection line (CL) can connect a data line (DL) to a data pad (DP). For example, a plurality of first connection lines (CL1) can connect a first data line (DL1), which is part of a plurality of data lines (DL), to a corresponding data pad (e.g., a first data pad (DP1)) among a plurality of data pads (DP). A plurality of second connection lines (CL2) can connect a second data line (DL2), which is another part of a plurality of data lines (DL), to a corresponding data pad (e.g., a second data pad (DP2)) among a plurality of data pads (DP). A plurality of third connection lines (CL3) can connect a third data line (DL3), which is yet another part of a plurality of data lines (DL), to a corresponding data pad (e.g., a third data pad (DP3)) among a plurality of data pads (DP).

[0073] In one embodiment, the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) may be placed on different layers as illustrated in FIGS. 6 to 13, which will be described later. When the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) are placed on different layers, the width of each of the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) can be freely adjusted compared to when the third connecting line (CL3) is placed on the same layer as the first connecting line (CL1) or the second connecting line (CL2). For example, the width of each of the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) may be increased. When the width of each of the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) increases, the resistance of each of the first connecting line (CL1), the second connecting line (CL2), and the third connecting line (CL3) may decrease. This is explained in more detail in FIGS. 6 to 13.

[0074] FIG. 3 is an equivalent circuit diagram showing one pixel arranged in a display device according to one embodiment of the present invention.

[0075] Referring to FIG. 3, a pixel (PX) may include a pixel circuit (PC) and a display element electrically connected to the pixel circuit (PC). The display element may be an organic light-emitting diode (OLED) having an anode (or pixel electrode) and a cathode (or counter electrode).

[0076] For example, the pixel circuit (PC) may include first to ninth transistors (T1 to T9), a first capacitor (C1), and a second capacitor (C2), as illustrated in FIG. 3. The first to ninth transistors (T1 to T9), the first capacitor (C1), and the second capacitor (C2) are connected to first to fourth scan lines (GWL, GCL, GIL, GBL) that respectively transmit first to fourth scan signals (GW, GC, GI, GB), a data line (DL) that transmits a data voltage (Dm), a light emission control line (EML) that transmits a light emission control signal (EM), a power line (PL) that transmits a first driving voltage (ELVDD), a first voltage line (VL1) that transmits an initialization voltage (Vint), a second voltage line (VL2) that transmits a reference voltage (Vref), a third voltage line (VL3) that transmits a bias voltage (Vbias), and a common electrode to which a second driving voltage (ELVSS) is applied.

[0077] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second to ninth transistors (T2 to T9) may be switching transistors that are turned on / off according to the gate-source voltage, substantially the gate voltage. The first to ninth transistors (T1 to T9) may be formed as thin-film transistors.

[0078] Some of the first to ninth transistors (T1 to T9) may be equipped with NMOS (n-channel MOSFETs), and the remainder may be equipped with PMOS (p-channel MOSFETs). For example, as shown in FIG. 3, among the first to ninth transistors (T1 to T9), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the eighth transistor (T8) may be equipped with NMOS (n-channel MOSFETs), and the remainder may be equipped with PMOS (p-channel MOSFETs). Alternatively, among the first to ninth transistors (T1 to T9), the third transistor (T3), the fourth transistor (T4), and the eighth transistor (T8) may be equipped with NMOS (n-channel MOSFETs), and the remainder may be equipped with PMOS (p-channel MOSFETs).

[0079] In another embodiment, only one of the first to ninth transistors (T1 to T9) may be provided as an NMOS and the others as PMOS. Alternatively, all of the first to ninth transistors (T1 to T9) may be provided as either NMOS or PMOS.

[0080] The first capacitor (C1) and the second capacitor (C2) are connected between the power line (PL) and the gate of the first transistor (T1). The first capacitor (C1) may have a first lower electrode (CE1) connected to the gate of the first transistor (T1), and a first upper electrode (CE2) connected to the second lower electrode (CE3) of the second capacitor (C2). The second capacitor (C2) may have a second lower electrode (CE3) connected to the first upper electrode (CE2) of the first capacitor (C1), and a second upper electrode (CE4) connected to the power line (PL).

[0081] Meanwhile, as illustrated in FIG. 4, which will be described later, the first capacitor (C1) and the second capacitor (C2) can overlap each other. For example, the first upper electrode (CE2) of the first capacitor (C1) can function as the second lower electrode (CE3) of the second capacitor (C2). In other words, the second lower electrode (CE3) of the second capacitor (C2) can function as the first upper electrode (CE2) of the first capacitor (C1).

[0082] Referring again to FIG. 3, the first transistor (T1) can control the magnitude of the driving current (Id) flowing from the power line (PL) to the organic light-emitting diode (OLED) according to the gate-source voltage. The first transistor (T1) may have a gate connected to the first lower electrode (CE1) of the first capacitor (C1), a source connected to the power line (PL) through the fifth transistor (T5), and a drain connected to the organic light-emitting diode (OLED) through the sixth transistor (T6).

[0083] The first transistor (T1) can output a driving current (Id) to an organic light-emitting diode (OLED) according to the gate-source voltage. The magnitude of the driving current (Id) is determined based on the difference between the gate-source voltage and the threshold voltage of the first transistor (T1). The organic light-emitting diode (OLED) receives the driving current (Id) from the first transistor (T1) and can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0084] The second transistor (T2) can connect a data line (DL) to the first upper electrode (CE2) of the first capacitor (C1) (or the second lower electrode (CE3) of the second capacitor (C2)) in response to the first scan signal (GW). The second transistor (T2) can transmit a data voltage (Dm) to the first upper electrode (CE2) of the first capacitor (C1) (or the second lower electrode (CE3) of the second capacitor (C2)) in response to the first scan signal (GW).

[0085] The third transistor (T3) can connect the drain and gate of the first transistor (T1) to each other in response to the second scan signal (GC). The third transistor (T3) can be connected in series between the drain and gate of the first transistor (T1).

[0086] The fourth transistor (T4) can connect the first voltage line (VL1) to the gate of the first transistor (T1) in response to the third scan signal (GI). The fourth transistor (T4) can apply an initialization voltage (Vint) to the gate of the first transistor (T1) in response to the third scan signal (GI).

[0087] The fifth transistor (T5) can connect the power line (PL) to the source of the first transistor (T1) in response to the light emission control signal (EM). The fifth transistor (T5) can connect the power line (PL) and the source of the first transistor (T1) to each other in response to the light emission control signal (EM).

[0088] The sixth transistor (T6) can connect the drain of the first transistor (T1) to the anode of the organic light-emitting diode (OLED) in response to the light emission control signal (EM). The sixth transistor (T6) can connect the drain of the first transistor (T1) and the anode of the organic light-emitting diode (OLED) to each other in response to the light emission control signal (EM).

[0089] In FIG. 3, the fifth transistor (T5) and the sixth transistor (T6) are shown operating in response to the same light emission control signal (EM), but in other embodiments, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to different light emission control signals. For example, the fifth transistor (T5) may have a gate connected to the first light emission control line and may connect the power line (PL) to the source of the first transistor (T1) in response to the first light emission control signal. The sixth transistor (T6) may have a gate connected to the second light emission control line and may connect the drain of the first transistor (T1) to the anode of the organic light-emitting diode (OLED) in response to the second light emission control signal.

[0090] The seventh transistor (T7) can connect the first voltage line (VL1) to the anode of the organic light-emitting diode (OLED) in response to the fourth scan signal (GB). The seventh transistor (T7) can apply an initialization voltage (Vint) to the anode of the organic light-emitting diode (OLED) in response to the fourth scan signal (GB).

[0091] The eighth transistor (T8) can connect the second voltage line (VL2) to the first upper electrode (CE2) of the first capacitor (C1) (or the second lower electrode (CE3) of the second capacitor (C2)) in response to the second scan signal (GC). The eighth transistor (T8) can apply a reference voltage (Vref) to the first upper electrode (CE2) of the first capacitor (C1) (or the second lower electrode (CE3) of the second capacitor (C2)) in response to the second scan signal (GC).

[0092] In FIG. 3, the third transistor (T3) and the eighth transistor (T8) are shown operating in response to the same second scan signal (GC), but in another embodiment, the third transistor (T3) and the eighth transistor (T8) may operate in response to different scan signals, respectively.

[0093] The ninth transistor (T9) can connect the third voltage line (VL3) to the source of the first transistor (T1) in response to the fourth scan signal (GB). The ninth transistor (T9) can apply a bias voltage (Vbias) to the source of the first transistor (T1) in response to the fourth scan signal (GB).

[0094] In FIG. 3, the 7th transistor (T7) and the 9th transistor (T9) are shown operating in response to the same 4th scan signal (GB), but in another embodiment, the 7th transistor (T7) and the 9th transistor (T9) may operate in response to different scan signals, respectively.

[0095] The second scan signal (GC) can be substantially synchronized with the first scan signal (GW). The third scan signal (GI) can be substantially synchronized with the first scan signal (GW) of the previous row. The fourth scan signal (GB) can be substantially synchronized with the first scan signal (GW). According to another example, the fourth scan signal (GB) can be substantially synchronized with the first scan signal (GW) of the next row or the third scan signal (GI) of the next row.

[0096] In one embodiment, the first to ninth transistors (T1 to T9) may include a semiconductor layer comprising silicon. As an example, the first to ninth transistors (T1 to T9) may include a semiconductor layer comprising low-temperature polysilicon (LTPS). Polysilicon material has high electron mobility (100 cm² / Vs or higher), low energy consumption, and excellent reliability.

[0097] As another example, the semiconductor layers of the first to ninth transistors (T1 to T9) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc.

[0098] As another example, some semiconductor layers of the first to ninth transistors (T1 to T9) may be formed of low-temperature polysilicon (LTPS), and other semiconductor layers may be formed of oxide semiconductors (IGZO, etc.).

[0099] FIG. 4 is a cross-sectional view schematically illustrating a portion of a pixel according to one embodiment of the present invention. Since FIG. 4 is an exemplary cross-sectional view of a portion of a pixel according to one embodiment, some components may be omitted.

[0100] Referring to FIG. 4, a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), a first capacitor (C1), and a second capacitor (C2) may be arranged in the display area (DA). The first thin-film transistor (TFT1) corresponds to the first transistor (T1) of FIG. 3, and the second thin-film transistor (TFT2) may correspond to the second transistor (T2), the third transistor (T3), the fourth transistor (T4), or the eighth transistor (T8) of FIG. 3.

[0101] The first thin-film transistor (TFT1) may include a first semiconductor layer (Act1) and a first electrode (E1) that overlaps at least partially with the first semiconductor layer (Act1). The first electrode (E1) corresponds to the gate (or gate electrode) of the first thin-film transistor (TFT1).

[0102] The second thin-film transistor (TFT2) may include a second semiconductor layer (Act2) and a fifth electrode (E5) that overlaps at least partially with the second semiconductor layer (Act2). The fifth electrode (E5) corresponds to the gate (or gate electrode) of the second thin-film transistor (TFT2). The second thin-film transistor (TFT2) may be placed on the first thin-film transistor (TFT1).

[0103] In one embodiment, the conductivity type of the first thin-film transistor (TFT1) may be opposite to the conductivity type of the second thin-film transistor (TFT2). For example, the first thin-film transistor (TFT1) may be provided as a PMOS (p-channel MOSFET) and the second thin-film transistor (TFT2) may be provided as an NMOS (n-channel MOSFET).

[0104] In one embodiment, the first semiconductor layer (Act1) of the first thin-film transistor (TFT1) and the second semiconductor layer (Act2) of the second thin-film transistor (TFT2) may comprise different materials. For example, the first semiconductor layer (Act1) may comprise a silicon semiconductor material, and the second semiconductor layer (Act2) may comprise an oxide semiconductor material.

[0105] The first capacitor (C1) may include a first electrode (E1) and a second electrode (E2) that overlaps at least partially with the first electrode (E1). The first capacitor (C1) may overlap with the first thin-film transistor (TFT1). For example, the first electrode (E1) may function as the first lower electrode (CE1) of the first capacitor (C1). In other words, the first electrode (E1) may correspond to the first lower electrode (CE1) of the first capacitor (C1).

[0106] The second capacitor (C2) may include a second electrode (E2) and a third electrode (E3) that overlaps at least partially with the second electrode (E2). The second capacitor (C2) may overlap with the first capacitor (C1). For example, the second electrode (E2) may function as the first upper electrode (CE2) of the first capacitor (C1) and as the second lower electrode (CE3) of the second capacitor (C2). In other words, the second electrode (E2) may correspond to the first upper electrode (CE2) of the first capacitor (C1) and to the second lower electrode (CE3) of the second capacitor (C2).

[0107] As in one embodiment of the present invention, when the first capacitor (C1) and the second capacitor (C2) overlap each other in the ±z direction, the number of pixels that can be placed in the xy plane can be increased compared to when the first capacitor (C1) and the second capacitor (C2) exist separately without overlapping each other. Since the number of pixels per unit area placed in the xy plane can be increased, the resolution of the display device can be increased. The resolution of the display device can be improved.

[0108] Meanwhile, in FIG. 4, the width of the first electrode (E1) and the width of the second electrode (E2) are shown as being the same, and the width of the second electrode (E2) and the width of the third electrode (E3) are different from each other, but this is merely an example and various variations are possible.

[0109] Hereinafter, with reference to FIG. 4, the configuration included in the display device will be described in more detail according to the stacked structure.

[0110] The substrate (100) may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. If the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0111] The substrate (100) may have a single-layer or multi-layer structure of the material, and in the case of a multi-layer structure, may further include an inorganic layer. In some embodiments, the substrate (100) may have an organic / inorganic / organic structure.

[0112] A barrier layer (not shown) may be further included between the substrate (100) and the buffer layer (110). The barrier layer may serve to prevent or minimize the penetration of impurities from the substrate (100), etc., into the first semiconductor layer (Act1) and the second semiconductor layer (Act2). The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0113] A lower metal layer (BML) may be interposed between the substrate (100) and the buffer layer (110). The lower metal layer (BML) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0114] The lower metal layer (BML) may overlap at least partially with the first semiconductor layer (Act1). The lower metal layer (BML) may serve to protect the first semiconductor layer (Act1). The lower metal layer (BML) may be configured to have an arbitrary (or preset) voltage applied. When driving a pixel circuit containing both an NMOS (n-channel MOSFET) and a PMOS (p-channel MOSFET) through the lower metal layer (BML) to which an arbitrary voltage is applied, the accumulation of unnecessary charge on the first semiconductor layer (Act1) can be prevented. As a result, the characteristics of the first thin-film transistor (TFT1) containing the first semiconductor layer (Act1) can be maintained stably.

[0115] A first semiconductor layer (Act1) may be disposed on the buffer layer (110). The first semiconductor layer (Act1) may include amorphous silicon or polysilicon. The first semiconductor layer (Act1) may include a channel region and source and drain regions disposed on both sides of the channel region. The source and drain regions may be regions doped by adding impurities (dopants). The first semiconductor layer (Act1) may be composed of a single layer or multiple layers.

[0116] A first insulating layer (111) and a second insulating layer (113) may be laminated and arranged on a substrate (100) to cover a first semiconductor layer (Act1). The first insulating layer (111) and the second insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0117] A first electrode (E1) may be disposed on the first insulating layer (111). The first electrode (E1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0118] A second electrode (E2) may be disposed on the second insulating layer (113). The second electrode (E2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0119] The first electrode (E1) and the second electrode (E2) overlap each other with the second insulating layer (113) in between, forming a capacitance. In this case, the second insulating layer (113) can function as the dielectric layer of the first capacitor (C1).

[0120] A third insulating layer (115) may be disposed on the second insulating layer (113) to cover the second electrode (E2). The third insulating layer (115) may be silicon oxide (SiO2) or silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0121] A third electrode (E3) and a fourth electrode (E4) may be disposed on the third insulating layer (115). The third electrode (E3) and the fourth electrode (E4) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0122] The second electrode (E2) and the third electrode (E3) overlap each other with the third insulating layer (115) in between, forming a capacitance. In this case, the third insulating layer (115) can function as the dielectric layer of the second capacitor (C2).

[0123] The fourth electrode (E4) may overlap at least partially with the second semiconductor layer (Act2). The fourth electrode (E4) may serve to protect the second semiconductor layer (Act2). The fourth electrode (E4) may be electrically connected to the fifth electrode (E5) through the second connecting electrode (CM2) to be described later.

[0124] In FIG. 4, the fourth electrode (E4) is shown as being placed on the same layer as the third electrode (E3), but in another embodiment, the fourth electrode (E4) may be placed on the same layer as the second electrode (E2). This will be described later in FIG. 5.

[0125] A fourth insulating layer (117) may be disposed on the third insulating layer (115) to cover the third electrode (E3) and the fourth electrode (E4). The fourth insulating layer (117) may be silicon oxide (SiO2) or silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0126] A second semiconductor layer (Act2) may be disposed on the fourth insulating layer (117). The second semiconductor layer (Act2) may include an oxide semiconductor material. The second semiconductor layer (Act2) may include, for example, an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0127] For example, the second semiconductor layer (Act2) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. Oxide semiconductors have a wide band gap (about 3.1 eV), high carrier mobility, and low leakage current, so even if the driving time is long, the voltage drop is not large, and thus there is an advantage that the change in brightness due to voltage drop is not large even when driving at low frequency.

[0128] The second semiconductor layer (Act2) may include a channel region and source and drain regions disposed on both sides of the channel region. The second semiconductor layer (Act2) may be composed of a single layer or multiple layers.

[0129] As described above, a fourth electrode (E4) may be disposed below the second semiconductor layer (Act2). Since the second semiconductor layer (Act2), which contains an oxide semiconductor material, has characteristics that are vulnerable to light, the second semiconductor layer (Act2) can be protected through the fourth electrode (E4). The fourth electrode (E4) can serve to prevent the device characteristics of the second thin-film transistor (TFT2), which contains an oxide semiconductor material, from changing due to photocurrents being induced in the second semiconductor layer (Act2) by external light incident from the substrate (100) side.

[0130] A fifth insulating layer (119) may be disposed on the second semiconductor layer (Act2). The fifth insulating layer (119) may be silicon oxide (SiO2) or silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0131] In FIG. 4, the fifth insulating layer (119) is shown placed over the entire surface of the substrate (100) to cover the second semiconductor layer (Act2), but in another embodiment, the fifth insulating layer (119) may be patterned to overlap with a part of the second semiconductor layer (Act2). For example, the fifth insulating layer (119) may be patterned to overlap with the channel region of the second semiconductor layer (Act2).

[0132] A fifth electrode (E5) may be disposed on the fifth insulating layer (119). The fifth electrode (E5) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0133] A sixth insulating layer (121) may be provided on the fifth insulating layer (119) to cover the fifth electrode (E5). The sixth insulating layer (121) may be silicon oxide (SiO2) or silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0134] A first connecting electrode (CM1), a second connecting electrode (CM2), and a third connecting electrode (CM3) may be disposed on the sixth insulating layer (121). The first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3) may be formed as a multilayer structure of Ti / Al / Ti.

[0135] The first connecting electrode (CM1) can be connected to the first semiconductor layer (Act1) through a first contact hole (CNT1) formed in the first to sixth insulating layers (111, 113, 115, 117, 119, 121). A portion of the first connecting electrode (CM1) can be embedded in the first contact hole (CNT1), and the first connecting electrode (CM1) and the first semiconductor layer (Act1) can be connected.

[0136] The second connecting electrode (CM2) can be connected to the fourth electrode (E4) through a second contact hole (CNT2) formed in the fourth to sixth insulating layers (117, 119, 121). A portion of the second connecting electrode (CM2) can be embedded in the second contact hole (CNT2), and the second connecting electrode (CM2) and the fourth electrode (E4) can be connected. The second connecting electrode (CM2) can be connected to the fifth electrode (E5) through a third contact hole (CNT3) formed in the sixth insulating layer (121). A portion of the second connecting electrode (CM2) can be embedded in the third contact hole (CNT3), and the third connecting electrode (CM3) and the fifth electrode (E5) can be connected. The second connecting electrode (CM2) can serve as a bridge connecting the fourth electrode (E4) and the fifth electrode (E5).

[0137] The third connecting electrode (CM3) can be connected to the third electrode (E3) through a fourth contact hole (CNT4) formed in the fourth to sixth insulating layers (117, 119, 121). A portion of the third connecting electrode (CM3) can be embedded in the fourth contact hole (CNT4), and the third connecting electrode (CM3) and the third electrode (E3) can be connected.

[0138] A first flattening layer (123) and a second flattening layer (125) may be laminated and disposed on the sixth insulating layer (121). The first flattening layer (123) and the second flattening layer (125) may be formed as a single layer or a multilayer film made of organic material and provide a flat upper surface. These first flattening layer (123) and the second flattening layer (125) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), or Polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0139] A fourth connecting electrode (CM4) and a power line (PL) may be disposed on the first flattening layer (123). The fourth connecting electrode (CM4) and the power line (PL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the fourth connecting electrode (CM4) and the power line (PL) may be formed as a multilayer structure of Ti / Al / Ti.

[0140] The fourth connecting electrode (CM4) can be connected to the first connecting electrode (CM1) through the fifth contact hole (CNT5) formed in the first planarization layer (123). A portion of the fourth connecting electrode (CM4) can be embedded in the fifth contact hole (CNT5), and the fourth connecting electrode (CM4) and the first connecting electrode (CM1) can be connected. The fourth connecting electrode (CM4) can be connected to the first semiconductor layer (Act1) through the first connecting electrode (CM1).

[0141] The power line (PL) can be connected to the third connecting electrode (CM3) through the sixth contact hole (CNT6) formed in the first flattening layer (123). A portion of the power line (PL) can be embedded in the sixth contact hole (CNT6), and the power line (PL) and the third connecting electrode (CM3) can be connected. The power line (PL) can be connected to the third electrode (E3) through the third connecting electrode (CM3).

[0142] A display element (200) may be disposed on the second flattening layer (125). The display element (200) may include a pixel electrode (210), an intermediate layer (220) including an organic light-emitting layer, and a counter electrode (230).

[0143] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode (210) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some embodiments, the pixel electrode (210) may be provided as ITO / Ag / ITO.

[0144] The pixel electrode (210) can be connected to the fourth connecting electrode (CM4) through the sixth contact hole (CNT6) formed in the second planarization layer (125). A portion of the pixel electrode (210) can be embedded in the sixth contact hole (CNT6), and the pixel electrode (210) and the fourth connecting electrode (CM4) can be connected. The pixel electrode (210) can be electrically connected to the first semiconductor layer (Act1) through the fourth connecting electrode (CM4) and the first connecting electrode (CM1).

[0145] A pixel defining film (127) may be disposed on the second flattening layer (125). Additionally, the pixel defining film (127) may serve to prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210).

[0146] The pixel defining film (127) may be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin. The pixel defining film (127) may include an organic insulating material. Alternatively, the pixel defining film (127) may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining film (127) may include both an organic insulating material and an inorganic insulating material. In some embodiments, the pixel defining film (127) may include a light-blocking material and may be provided in black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal particles such as nickel, aluminum, molybdenum and their alloys, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). If the pixel defining film (127) includes a light-blocking material, external light reflection by metal structures placed below the pixel defining film (127) can be reduced.

[0147] An intermediate layer (220) may be disposed within an opening formed by a pixel defining film (127). The intermediate layer (220) may include an organic light-emitting layer. The organic light-emitting layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be optionally disposed below and above the organic light-emitting layer.

[0148] The intermediate layer (220) may be disposed corresponding to each of the plurality of pixel electrodes (210). However, it is not limited thereto. Various variations are possible, such as the intermediate layer (220) including a layer that is integral across the plurality of pixel electrodes (210).

[0149] The counter electrode (230) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode (230) is disposed across the display area (DA) and may be disposed on top of the intermediate layer (220) and the pixel defining film (127). The counter electrode (230) may be formed integrally in a plurality of display elements (200) and may correspond to a plurality of pixel electrodes (210).

[0150] The display element (200) may be covered by a sealing layer (not shown). The sealing layer may include at least one organic sealing layer and at least one inorganic sealing layer. The at least one inorganic sealing layer may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The at least one inorganic sealing layer may be a single layer or a multilayer containing the aforementioned materials. The at least one organic sealing layer may include a polymer-based material. Polymer-based materials may include acrylic resins such as polymethyl methacrylate and polyacrylic acid, epoxy resins, polyimide, and polyethylene. In one embodiment, the at least one organic sealing layer may include an acrylate polymer.

[0151] Meanwhile, in FIG. 4, the thickness of each of the first to sixth insulating layers (111, 113, 115, 117, 119, 121) is shown as being the same, but this is merely an example and various variations are possible.

[0152] FIG. 5 is a cross-sectional view schematically illustrating a portion of a pixel according to an embodiment of the present invention. FIG. 5 is a modified embodiment of FIG. 4, differing in the structure of the fourth electrode. Hereinafter, overlapping content will be replaced by the description of FIG. 4, and the differences will be explained primarily.

[0153] Referring to FIG. 5, the fourth electrode (E4') can be placed on the second insulating layer (113). The fourth electrode (E4') can be placed on the same layer as the second electrode (E2).

[0154] The second connecting electrode (CM2) can be connected to the fourth electrode (E4') through a second contact hole (CNT2') formed in the third to sixth insulating layers (115, 117, 119, 121). A portion of the second connecting electrode (CM2) can be embedded in the second contact hole (CNT2'), and the second connecting electrode (CM2) and the fourth electrode (E4') can be connected.

[0155] In one embodiment, the first to fourth contact holes (CNT1, CNT2, CNT3, CNT4) may not be formed simultaneously. For example, the first contact hole (CNT1) and the second contact hole (CNT2') may be formed first, and then the third contact hole (CNT3) and the fourth contact hole (CNT4) may be formed. The depth of each of the first contact hole (CNT1) and the second contact hole (CNT2') may be greater than the depth of each of the third contact hole (CNT3) and the fourth contact hole (CNT4). If contact holes of different depths are formed simultaneously, the surface of the conductive layer exposed by the contact hole with a relatively smaller depth may be damaged. However, as in one embodiment of the present invention, if contact holes of different depths are not formed simultaneously but are formed separately, damage to the surface of the conductive layer exposed by the contact holes can be prevented.

[0156] FIG. 6 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. Specifically, FIG. 6 is an exemplary cross-sectional view of a portion of the display panel of FIG. 2 cut along X-X', and some components may be omitted. In FIG. 6, the same reference numerals as in FIG. 4 refer to the same components, and redundant descriptions thereof are omitted.

[0157] Referring to FIG. 6, a plurality of connecting lines (CL) and a first sub-wire (162) may be arranged in the surrounding area (PA).

[0158] As described above in FIG. 2, a plurality of connection lines (CL) can connect a plurality of data lines (DL) to a corresponding data pad (DP) among a plurality of data pads (DP) of the pad section (140). For example, the plurality of connection lines (CL) may include first connection lines (CL1), second connection lines (CL2), and third connection lines (CL3). The first connection lines (CL1) can connect the first data lines (DL1), which are part of the plurality of data lines (DL), to a corresponding data pad (e.g., first data pad (DP1)) among the plurality of data pads (DP). The second connection lines (CL2) can connect the second data lines (DL2), which are other part of the plurality of data lines (DL), to a corresponding data pad (e.g., second data pad (DP2)) among the plurality of data pads (DP). The third connection lines (CL3) can connect the third data lines (DL3), which are another part of the plurality of data lines (DL), to the corresponding data pad (e.g., the third data pad (DP3)) among the plurality of data pads (DP).

[0159] In one embodiment, a plurality of first connecting lines (CL1) and a plurality of second connecting lines (CL2) may each be arranged between two third connecting lines (CL3) adjacent in a first direction (e.g., ±x direction) among a plurality of third connecting lines (CL3). A plurality of first connecting lines (CL1) and a plurality of second connecting lines (CL2) may be arranged alternately along a first direction (e.g., ±x direction).

[0160] In one embodiment, the number of third connecting lines (CL3) per unit area may be greater than the number of first connecting lines (CL1) per unit area. The number of third connecting lines (CL3) per unit area may be greater than the number of second connecting lines (CL2) per unit area.

[0161] In one embodiment, the number of first connecting lines (CL1) per unit area may be equal to the number of second connecting lines (CL2) per unit area.

[0162] In one embodiment, the first connecting lines (CL1), the second connecting lines (CL2), and the third connecting lines (CL3) may be placed on different layers. For example, the second connecting lines (CL2) may be placed on the first connecting lines (CL1), and the third connecting lines (CL3) may be placed on the second connecting lines (CL2). As shown in FIG. 6, the first connecting lines (CL1) may be placed on the first insulating layer (111), the second connecting lines (CL2) may be placed on the third insulating layer (115), and the third connecting lines (CL3) may be placed on the fifth insulating layer (119). In other words, the first connecting lines (CL1) may be placed on the same layer as the first electrode (E1, see FIG. 4), the second connecting lines (CL2) may be placed on the same layer as the third electrode (E3, see FIG. 4), and the third connecting lines (CL3) may be placed on the same layer as the fourth electrode (E4, see FIG. 4).

[0163] In FIG. 6, the first connecting lines (CL1) are shown in the same layer as the first electrode (E1), the second connecting lines (CL2) are shown in the same layer as the third electrode (E3), and the third connecting lines (CL3) are shown in the same layer as the fourth electrode (E4); however, this is merely an example and various variations are possible. This will be described later in FIG. 9 to 13.

[0164] Additionally, although FIG. 6 illustrates that the second connecting line (CL2) and the third connecting line (CL3) overlap at least partially with each other, in another embodiment, the second connecting line (CL2) and the third connecting line (CL3) may not overlap with each other. In yet another embodiment, the first connecting line (CL1) and the third connecting line (CL3) may overlap at least partially with each other. In yet another embodiment, the first connecting line (CL1) and the third connecting line (CL3) may not overlap with each other.

[0165] As in one embodiment of the present invention, when the first connecting lines (CL1), the second connecting lines (CL2), and the third connecting lines (CL3) are placed on different layers, the number of connecting lines (CL) placed on each layer may be reduced compared to when the third connecting lines (CL3) are placed on the same layer as the first connecting lines (CL1) or the second connecting lines (CL2). When the connecting lines (CL) are separated and placed on three different layers, the number of connecting lines (CL) placed on each layer may be reduced. Since the number of connecting lines (CL) placed on each layer is reduced, the width of each connecting line (CL) can be changed more freely. For example, the width of each connecting line (CL) can be increased. If the first width (w1) of each of the first connecting lines (CL1) interposed between the first insulating layer (111) and the second insulating layer (113) is increased, the resistance of each of the first connecting lines (CL1) may be reduced. If the second width (w2) of each of the second connecting lines (CL2) interposed between the third insulating layer (115) and the fourth insulating layer (117) increases, the resistance of each of the second connecting lines (CL2) may decrease. If the third width (w3) of each of the third connecting lines (CL3) interposed between the fifth insulating layer (119) and the sixth insulating layer (121) increases, the resistance of each of the third connecting lines (CL3) may decrease.

[0166] The first sub-wiring (162) may include a first-1 sub-wiring (162a) and a first-2 sub-wiring (162b) separated by a first flattening layer (123). Although not shown in FIG. 6, the first-1 sub-wiring (162a) and the first-2 sub-wiring (162b) may be electrically connected.

[0167] In FIG. 6, the first flattening layer (123) is shown placed in the surrounding area (PA), but in another embodiment, at least a portion of the first flattening layer (123) may be omitted from the surrounding area (PA).

[0168] Additionally, in FIG. 6, the first sub-wire (162) is shown as including the first-1 sub-wire (162a) and the first-2 sub-wire (162b), but in another embodiment, either the first-1 sub-wire (162a) or the first-2 sub-wire (162b) may be omitted.

[0169] Since the third connecting line (CL3) and the first-1 sub-wiring (162a) are not connected to each other by the sixth insulating layer (121), a separate insulating layer may not be additionally placed as shown in FIG. 12, which will be described later. Therefore, a mask for placing a separate insulating layer may not be added.

[0170] FIG. 7 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 7 is a modified embodiment of FIG. 6, differing in the structure of the second connecting line and the third connecting line. Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0171] Referring to FIG. 7, the second connecting lines (CL2) and the third connecting lines (CL3) may have a multilayer structure. For example, each of the second connecting lines (CL2) may include a first layer (L1a), a third layer (L3a) on the first layer (L1a), and a second layer (L2a) interposed between the first layer (L1a) and the third layer (L3a). Each of the third connecting lines (CL3) may include a first layer (L1b), a third layer (L3b) on the first layer (L1b), and a second layer (L2b) interposed between the first layer (L1b) and the third layer (L3b).

[0172] The first layers (L1a, L1b), second layers (L2a, L2b), and third layers (L3a, L3b) may include a conductive material comprising molybdenum (Mo), aluminum (Al), aluminum alloy (Al-alloy), copper (Cu), titanium (Ti), titanium nitride (TiN), niobium (Nb), etc. For example, the first layers (L1a, L1b) may include titanium (Ti), the second layers (L2a, L2b) may include aluminum (Al), and the third layers (L3a, L3b) may include titanium (Ti). In this case, the resistance of each of the second connecting lines (CL2) and the third connecting lines (CL3) may be reduced.

[0173] In FIG. 7, the second connecting lines (CL2) and the third connecting lines (CL3) are each shown as comprising three layers, but in another embodiment, the first layers (L1a, L1b) may be omitted.

[0174] FIG. 8 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 8 is a modified embodiment of FIG. 6, differing in the structure of the third connecting line. Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0175] Referring to FIG. 8, the third connecting lines (CL3) may have a multilayer structure. For example, each of the third connecting lines (CL3) may include a first layer (L1b), a third layer (L3b) on the first layer (L1b), and a second layer (L2b) interposed between the first layer (L1b) and the third layer (L3b).

[0176] The first layer (L1b), the second layer (L2b), and the third layer (L3b) may include a conductive material including molybdenum (Mo), aluminum (Al), aluminum alloy (Al-alloy), copper (Cu), titanium (Ti), titanium nitride (TiN), niobium (Nb), etc. For example, the first layer (L1b) may include titanium (Ti), the second layer (L2b) may include aluminum (Al), and the third layer (L3b) may include titanium (Ti). In this case, the resistance of each of the third connecting lines (CL3) may be reduced.

[0177] In FIG. 8, each of the third connecting lines (CL3) is shown as comprising three layers, but in another embodiment, the first layer (L1b) may be omitted.

[0178] FIG. 9 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 9 is a modified embodiment of FIG. 6, differing in the structure of the connecting lines (CLa). Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0179] Referring to FIG. 9, the first connecting lines (CL1a), the second connecting lines (CL2a), and the third connecting lines (CL3a) may be placed on different layers. For example, the second connecting lines (CL2a) may be placed on the first connecting lines (CL1a), and the third connecting lines (CL3a) may be placed on the second connecting lines (CL2a). As shown in FIG. 9, the first connecting lines (CL1a) may be placed on the first insulating layer (111), the second connecting lines (CL2a) may be placed on the second insulating layer (113), and the third connecting lines (CL3a) may be placed on the third insulating layer (115). In other words, the first connecting lines (CL1a) may be placed on the same layer as the first electrode (E1, see FIG. 4), the second connecting lines (CL2a) may be placed on the same layer as the second electrode (E2, see FIG. 4), and the third connecting lines (CL3a) may be placed on the same layer as the third electrode (E3, see FIG. 4).

[0180] As in one embodiment of the present invention, when connecting lines (CLa) are separated and arranged into three different layers, the number of connecting lines (CLa) arranged in each layer can be reduced. Since the number of connecting lines (CLa) arranged in each layer is reduced, the width of each connecting line (CLa) can be increased. As the width of each connecting line (CLa) increases, the resistance of each connecting line (CLa) can be reduced.

[0181] FIG. 10 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 10 is a modified embodiment of FIG. 6, differing in the structure of the connecting lines (CLb). Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0182] Referring to FIG. 10, the first connecting lines (CL1b), the second connecting lines (CL2b), and the third connecting lines (CL3b) may be placed on different layers. For example, the second connecting lines (CL2b) may be placed on the first connecting lines (CL1b), and the third connecting lines (CL3b) may be placed on the second connecting lines (CL2b). As shown in FIG. 10, the first connecting lines (CL1b) may be placed on the first insulating layer (111), the second connecting lines (CL2b) may be placed on the second insulating layer (113), and the third connecting lines (CL3b) may be placed on the fifth insulating layer (119). In other words, the first connecting lines (CL1b) may be placed on the same layer as the first electrode (E1, see FIG. 4), the second connecting lines (CL2b) may be placed on the same layer as the second electrode (E2, see FIG. 4), and the third connecting lines (CL3b) may be placed on the same layer as the fourth electrode (E4, see FIG. 4).

[0183] As in one embodiment of the present invention, when connecting lines (CLb) are separated and arranged into three different layers, the number of connecting lines (CLb) arranged in each layer can be reduced. Since the number of connecting lines (CLb) arranged in each layer is reduced, the width of each connecting line (CLb) can be increased. As the width of each connecting line (CLb) increases, the resistance of each connecting line (CLb) can be reduced.

[0184] FIG. 11 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 11 is a modified embodiment of FIG. 6, differing in the structure of the connecting lines (CLc). Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0185] Referring to FIG. 11, the first connecting lines (CL1c), the second connecting lines (CL2c), and the third connecting lines (CL3c) may be placed on different layers. For example, the second connecting lines (CL2c) may be placed on the first connecting lines (CL1c), and the third connecting lines (CL3c) may be placed on the second connecting lines (CL2c). As shown in FIG. 11, the first connecting lines (CL1c) may be placed on the second insulating layer (113), the second connecting lines (CL2c) may be placed on the third insulating layer (115), and the third connecting lines (CL3c) may be placed on the fifth insulating layer (119). In other words, the first connecting lines (CL1c) may be placed on the same layer as the second electrode (E2, see FIG. 4), the second connecting lines (CL2c) may be placed on the same layer as the third electrode (E3, see FIG. 4), and the third connecting lines (CL3c) may be placed on the same layer as the fourth electrode (E4, see FIG. 4).

[0186] As in one embodiment of the present invention, when connecting lines (CLc) are separated and arranged into three different layers, the number of connecting lines (CLc) arranged in each layer may be reduced. Since the number of connecting lines (CLc) arranged in each layer is reduced, the width of each connecting line (CLc) may be increased. As the width of each connecting line (CLc) increases, the resistance of each connecting line (CLc) may be reduced.

[0187] FIG. 12 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 12 is a modified embodiment of FIG. 6, differing in the structure of the connecting lines (CLd). Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0188] Referring to FIG. 12, the first connecting lines (CL1d), the second connecting lines (CL2d), and the third connecting lines (CL3d) may be placed on different layers. For example, the second connecting lines (CL2d) may be placed on the first connecting lines (CL1d), and the third connecting lines (CL3d) may be placed on the second connecting lines (CL2d). As shown in FIG. 12, the first connecting lines (CL1d) may be placed on the first insulating layer (111), the second connecting lines (CL2d) may be placed on the second insulating layer (113), and the third connecting lines (CL3d) may be placed on the sixth insulating layer (121). In other words, the first connecting lines (CL1d) may be placed on the same layer as the first electrode (E1, see FIG. 4), the second connecting lines (CL2d) may be placed on the same layer as the second electrode (E2, see FIG. 4), and the third connecting lines (CL3d) may be placed on the same layer as the first connecting electrode (CM1, see FIG. 4).

[0189] As in one embodiment of the present invention, when connecting lines (CLd) are separated and arranged into three different layers, the number of connecting lines (CLd) arranged in each layer can be reduced. Since the number of connecting lines (CLd) arranged in each layer is reduced, the width of each connecting line (CLd) can be increased. As the width of each connecting line (CLd) increases, the resistance of each connecting line (CLd) can be reduced.

[0190] Meanwhile, the first sub-wiring (162) may be placed on the third connecting line (CL3d). To prevent the first sub-wiring (162) and the third connecting line (CL3d) from being connected to each other, a seventh insulating layer (122) may be placed between the first sub-wiring (162) and the third connecting line (CL3d). The seventh insulating layer (122) may be silicon oxide (SiO2) or silicon nitride (SiN2). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO X It may include ) etc. Zinc oxide (ZnO X ) may be zinc oxide (ZnO), and / or zinc peroxide (ZnO2).

[0191] FIG. 13 is a cross-sectional view schematically illustrating connecting lines according to an embodiment of the present invention. FIG. 13 is a modified embodiment of FIG. 12, differing in the structure of the connecting lines (CLe). Hereinafter, overlapping content will be replaced by the description of FIG. 12, and the differences will be explained primarily.

[0192] Referring to FIG. 13, the first connecting lines (CL1e), the second connecting lines (CL2e), and the third connecting lines (CL3e) may be placed on different layers. For example, the second connecting lines (CL2e) may be placed on the first connecting lines (CL1e), and the third connecting lines (CL3e) may be placed on the second connecting lines (CL2e). As shown in FIG. 13, the first connecting lines (CL1e) may be placed on the first insulating layer (111), the second connecting lines (CL2e) may be placed on the third insulating layer (115), and the third connecting lines (CL3e) may be placed on the sixth insulating layer (121). In other words, the first connecting lines (CL1e) may be placed on the same layer as the first electrode (E1, see FIG. 4), the second connecting lines (CL2e) may be placed on the same layer as the third electrode (E3, see FIG. 4), and the third connecting lines (CL3e) may be placed on the same layer as the first connecting electrode (CM1, see FIG. 4).

[0193] As in one embodiment of the present invention, when connecting lines (CLe) are separated and arranged into three different layers, the number of connecting lines (CLe) arranged in each layer can be reduced. Since the number of connecting lines (CLe) arranged in each layer is reduced, the width of each connecting line (CLe) can be increased. As the width of each connecting line (CLe) increases, the resistance of each connecting line (CLe) can be reduced.

[0194] Although the present invention has primarily described display devices so far, it is not limited thereto. For example, a method for manufacturing such a display device is also considered to fall within the scope of the present invention.

[0195] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0196] 1: Display device 10: Display panel 100: Substrate T1-T9: 1st to 9th transistors C1, C2: First and second capacitors Act1, Act2: First and second semiconductor layers E1, E2, E3: First to third electrodes DL: Data line SL: Scan line DP: Data pad CL: Connection line

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 A substrate having a display area and a peripheral area that partially surrounds the display area; a plurality of data lines arranged in a first direction on the display area; a pad portion disposed on one side of the peripheral area and including a plurality of data pads; a plurality of first connecting lines connecting a first data line, which is a part of the plurality of data lines, to a corresponding data pad among the plurality of data pads; a plurality of second connecting lines connecting a second data line, which is another part of the plurality of data lines, to a corresponding data pad among the plurality of data pads; A display device comprising a plurality of third connecting lines that connect a third data line, which is another part of the plurality of data lines, to a corresponding data pad among the plurality of data pads, wherein the plurality of first connecting lines, the plurality of second connecting lines, and the plurality of third connecting lines are arranged on different layers, and the plurality of first connecting lines and the plurality of second connecting lines are each arranged between two third connecting lines adjacent in the first direction among the plurality of third connecting lines, and are arranged alternately along the first direction, wherein the number of the plurality of third connecting lines per unit area is greater than the number of the plurality of first connecting lines per unit area, and the number of the plurality of third connecting lines per unit area is greater than the number of the plurality of second connecting lines per unit area. Claim 14 delete Claim 15 A display device according to claim 13, wherein the plurality of second connecting lines are disposed on the plurality of first connecting lines, and the plurality of third connecting lines are disposed on the plurality of second connecting lines. Claim 16 delete Claim 17 In claim 13, a display device in which the number of the plurality of first connecting lines per unit area is the same as the number of the plurality of second connecting lines per unit area. Claim 18 In claim 13, the plurality of third connecting lines are a display device having a multilayer structure. Claim 19 In claim 18, a display device comprising, wherein each of the plurality of third connecting lines comprises a first layer, a third layer on the first layer, and a second layer interposed between the first layer and the third layer. Claim 20 In claim 18, the plurality of second connecting lines are a display device having the same layer structure as the plurality of third connecting lines. Claim 21 A display device according to claim 13, further comprising: a first transistor disposed in the display area and comprising a first semiconductor layer and a first electrode that partially overlaps with the first semiconductor layer; a first capacitor disposed in the display area and comprising a first electrode and a second electrode that partially overlaps with the first electrode; a second capacitor disposed in the display area and comprising a second electrode and a third electrode that partially overlaps with the second electrode; and a second transistor disposed on the first transistor in the display area and comprising a second semiconductor layer and a fourth electrode that partially overlaps with the second semiconductor layer. Claim 22 A display device according to claim 21, wherein the plurality of first connecting lines are disposed on the same layer as the first electrode, the plurality of second connecting lines are disposed on the same layer as the third electrode, and the plurality of third connecting lines are disposed on the same layer as the fourth electrode. Claim 23 A display device according to claim 21, wherein the plurality of first connecting lines are disposed on the same layer as the first electrode, the plurality of second connecting lines are disposed on the same layer as the second electrode, and the plurality of third connecting lines are disposed on the same layer as the third electrode. Claim 24 A display device according to claim 21, wherein the plurality of first connecting lines are disposed on the same layer as the first electrode, the plurality of second connecting lines are disposed on the same layer as the second electrode, and the plurality of third connecting lines are disposed on the same layer as the fourth electrode. Claim 25 A display device according to claim 21, wherein the plurality of first connecting lines are disposed on the same layer as the second electrode, the plurality of second connecting lines are disposed on the same layer as the third electrode, and the plurality of third connecting lines are disposed on the same layer as the fourth electrode.

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