Booting method of computing system including memory module mounted processing unit

Abstract

A method for booting a computing system comprising a memory module in which a processing unit is installed is disclosed. After power-up, the computing system performs a first memory training for a plurality of memory devices by means of a processing unit in the memory module, generates a module ready signal indicating the completion of the first memory training, and transmits the module ready signal to a host device. The host device reads ID information for hardware components of the computing system and waits for the module ready signal to be received, and upon receipt of the module ready signal, performs a second memory training for a plurality of memory devices in the memory module.

Description

Technology Field

[0001] The present invention relates to computing systems, and more specifically, to a method for booting a computing system comprising a memory module in which a processing device is installed. Background Technology

[0002] Computing systems provide capabilities and functions according to their architectural configurations. Applications such as high-performance and / or graphics algorithms are data- and compute-intensive. Applications such as deep neural networks require computing systems with large computational and memory capabilities to train or learn different data sets more accurately. Considering the increase in training data sets, the increase in model parameters, and the increase in intermediate results of processing, such computing systems may include memory modules equipped with memory-intensive Dynamic Random Access Memory (DRAM) and processing units used for computationally heavy neural network or artificial intelligence training.

[0003] During the booting of a computing system, training and / or testing of the memory modules included in the system are performed manually as part of the Power On Self Test (POST). Unlike these conventional memory modules, memory modules containing processing units require interface tuning between the processing unit and the DRAMs within the memory module. Furthermore, it is necessary to notify the host device once the interface tuning between the processing unit and the DRAMs is completed. Accordingly, a computing system containing a memory module with an installed processing unit requires a new boot sequence during booting. The problem to be solved

[0004] The object of the present invention is to provide a memory module in which a processing device is mounted, a computing system including the memory module, and a method for booting the computing system. means of solving the problem

[0005] A memory module according to embodiments of the present invention comprises a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a processing device coupled to the printed circuit board and connected to the plurality of memory devices. When the memory module is powered up, the processing device performs memory training for the plurality of memory devices, generates a module ready signal after completing the memory training, and outputs the module ready signal to the outside of the memory module.

[0006] A computing system according to embodiments of the present invention comprises a board, a host device mounted on the board, a memory module mounted on the board and connected to the host device and including a plurality of memory devices and a processing device connected to the plurality of memory devices, and a BIOS memory storing BIOS code for booting the computing system. When the computing system is powered up, the processing device of the memory module performs memory training for the plurality of memory devices, generates a module ready signal after completing the memory training, and transmits the module ready signal to the host device.

[0007] A booting method for a computing system equipped with a memory module comprising a plurality of memory devices and a processing device connected to the plurality of memory devices according to embodiments of the present invention comprises: a step of powering up the computing system; a step of performing a first memory training for the plurality of memory devices by the processing device in the memory module after powering up and generating a module ready signal indicating the completion of the first memory training; a step of performing a first boot sequence by a host device executing BIOS code of a BIOS memory included in the computing system after powering up; a step of waiting for a module ready signal to be received from the memory module in the host device after performing the first boot sequence; and a step of receiving the module ready signal in the host device and performing a second boot sequence based on the module ready signal. Effects of the invention

[0008] A booting method for a computing system according to embodiments of the present invention can guarantee a minimum boot time by performing memory training primarily between a processing device and memory devices within a memory module and then notifying the host CPU of the module ready signal of the memory module. In addition, since memory training is performed twice—specifically, after the memory devices of the memory module undergo primary memory training by the processing device, secondary memory training by the host CPU is performed—the stability of the computing system can be guaranteed. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram conceptually illustrating a computing system including a memory module in which a processing device according to embodiments of the present invention is mounted. Figure 2 is a block diagram illustrating the memory module of Figure 1. FIG. 3 is a flowchart illustrating a booting method of a computing system according to embodiments of the present invention. FIG. 4 is a flowchart specifically explaining the first memory training by the processing device in the memory module of FIG. 3. FIG. 5 is a flowchart specifically describing the first boot sequence performed by the CPU of FIG. 3. FIG. 6 is a flowchart specifically describing the second boot sequence performed by the CPU of FIG. 3. Specific details for implementing the invention

[0010] FIG. 1 is a block diagram conceptually illustrating a computing system including a memory module in which a processing device according to embodiments of the present invention is mounted.

[0011] Referring to FIG. 1, a computing system (100) may include a host device (110) mounted on a board (101), a memory module (120), and a BIOS (Basic Input / Output System) memory (150). The host device (110) may be communicatively connected to the memory module (120) via a memory bus (140).

[0012] Some examples may be described using the expressions "connected" and / or "coupled" along with their derivatives. These terms are not necessarily intended to be synonyms for one another. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. Additionally, the terms "connected" and / or "coupled" may also imply that two or more elements are not in direct contact with each other but still cooperate or interact with one another.

[0013] The host device (110) may be, for example, a computing device, virtual machine, or its virtual computing device such as a laptop computer, desktop computer, server computer, workstation, portable communication terminal, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), smartphone, tablet PC, and other suitable computers. Alternatively, the host device (110) may be some of the components included in the computing system (100), such as a graphics card.

[0014] The host device (110) is a functional block that performs general computer operations within the computing system (100) and may correspond to a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or an Application Processor (AP). In this specification, the host device (110) may be referred to as a CPU (110).

[0015] The CPU (110) may be configured to execute one or more machine-executable instructions or pieces of software, firmware, or combinations thereof. The CPU (110) may include any number of processor cores. For example, the CPU (110) may include a single core or a multi-core such as a dual-core, quad-core, or hexa-core. Although FIG. 1 illustrates a computing system (100) including one CPU (110), according to the embodiment, the computing system (100) may include multiple CPUs. The CPU (110) may be connected to the BIOS memory (150) through various interfaces such as a Serial Peripheral Interface (SPI) or a Low Pin Count (LPC) bus.

[0016] The BIOS memory (150) can store BIOS code for booting the computing system (100). The BIOS memory (150) can be implemented as a non-volatile memory device. The non-volatile memory device can be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, RRAM (Resistive RAM), MRAM (Magnetic RAM), PRAM (Phase change RAM), FRAM (Ferroelectric RAM), NFGM (Nano Floating Gate Memory), PoRAM (Polymer RAM), or similar memory.

[0017] The BIOS code is a POST code and / or part of a POST code for detecting hardware of the computing system (100), such as the board (101), memory module (120), keyboard, disk drive, etc., and verifying whether they are operating normally. The BIOS code may include a Memory Reference Code (MRC) for initializing the memory module (120). The MRC may include various algorithms configured to enable the CPU (110) to interoperate normally with the memory module (120).

[0018] By means of an MRC executed by a CPU (110), SPD data stored in the Serial Presence Detect (SPD) memory device (104) of the memory module (120) is read out through the memory bus (140), and frequency, timing, driving, detailed operation parameters, etc. for controlling the memory module (120) using the SPD data can be set. The SPD data may include the type of the memory module (120), the type of memory device included in the memory module (120), operation timing information, manufacturing information, revision code, serial number, etc. BIST and / or memory training of the memory module (120) can be performed by means of an MRC code.

[0019] For the sake of brevity of the drawing, the memory bus (140) is depicted as being connected by a single signal line between the CPU (110) and the connecting pins (106) of the memory module (120), but in reality, it may be connected through multiple signal lines. The memory bus (140) may be implemented as a single channel including multiple signal lines, or as multiple channels. Additionally, one or more memory modules (120) may be connected to each channel.

[0020] The memory bus (140) may be composed of command / address signal lines that transmit commands / addresses and data lines that transmit data. Additionally, the memory bus (140) may include a module ready signal (RDY_DIMM, FIG. 2) line (250, FIG. 2) that is transmitted from the memory module (120) to the CPU (110). The module ready signal (RDY_DIMM) is a signal indicating that memory training by the processing unit (130) is completed after memory training is performed between the processing unit (130) and the memory devices (121-129) within the memory module (120) during the boot operation of the computing system (100). The module ready signal (RDY_DIMM) can serve as a basic signal indicating that the memory devices (121-129) of the memory module (120) are ready to perform secondary memory training by the CPU (110) after primary memory training by the processing device (130).

[0021] The memory module (120) is configured to perform processing functions and may include a processing device (130) coupled to a printed circuit board (102), a plurality of memory devices (121 to 129), and an SPD memory device (104). The memory module (120) may be implemented as any type of memory module. For example, the memory module (120) may be implemented as an RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM), FBDIMM (Fully Buffered DIMM), SODIMM (Small Outline DIMM), etc.

[0022] The processing unit (130) may operate as an accelerator or co-processor for the CPU (110). The processing unit (130) may be implemented as a System-on-Chip (SoC) in which various functional blocks and / or multiple IPs are integrated into a single semiconductor integrated circuit. IP refers to circuits, logic, or combinations thereof that can be integrated into the SoC.

[0023] The processing unit (130) is an accelerator that specializes in performing specific functions of the CPU (110) and may include a GPU (Graphic Processing Unit), which is a functional block that specializes in graphic data processing; an NPU (Neural Processing Unit), which is a block that specializes in AI calculation and inference; and / or a DPU (Data Processing Unit), which is a block that specializes in data transmission.

[0024] The processing unit (130) may include a memory controller (132) that controls the transmission and reception of data to and from memory devices (121–129). The memory controller (132) may access the memory devices (121–129) in response to a memory request from the processing unit (130). According to an embodiment, the memory controller (132) may access the memory devices (121–129) in response to a memory request from the CPU (110). In this case, the memory controller (132) may be configured so that access to the memory devices (121–129) controlled by the CPU (110) is performed transparently to the processing unit (130).

[0025] The memory controller (132) may include a memory physical layer interface (234, FIG. 2) for interfacing with memory devices (121–129), such as selecting rows and columns corresponding to memory locations, writing data to memory locations, or reading written data. Typically, the memory physical layer interface (234) is referred to as the memory PHY (234).

[0026] Memory devices (121–129) can write or read data under the control of a memory controller (132) within a processing device (130). For example, memory devices (121–129) may be DRAM devices. However, the scope of the present invention is not limited thereto, and memory devices (121–129) may be any one of volatile memory devices such as SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), GDDR SDRAM (Graphics Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, Wide I / O DRAM, HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), etc. Hereinafter, for convenience of explanation, memory devices (121–129) are collectively referred to as DRAMs (121–129).

[0027] Figure 2 is a block diagram illustrating the memory module of Figure 1.

[0028] Referring to FIG. 2, the memory module (120) may include a processing device (130) including a memory controller (132) and DRAMs (121-129). The memory controller (132) may include a Register Control Word (RCW, 230, hereinafter referred to as 'RCW'), a training circuit section (232), and a memory PHY (234).

[0029] The RCW (230) may be provided to control the initialization and / or operation characteristics of the memory module (120). The RCW (230) may include various algorithms for configuring the memory controller (132) so that the memory controller (132) can interact normally with the DRAMs (121-129). For example, codes indicating the frequency, timing, driving, and detailed operation parameters of the DRAMs (121-129) may be set in the RCW (230). Memory training of the DRAMs (121-129) may be performed according to the codes of the RCW (230).

[0030] The training circuit section (232) can perform memory core parameter training associated with the memory core of the DRAMs (121-129) and / or peripheral circuit parameter training for the remaining peripheral circuits excluding the memory core, under the control of the memory controller (132). The training circuit section (232) can determine optimal parameters for the memory core parameters and / or peripheral circuit parameters of the DRAMs (121-129). The training circuit section (232) can perform memory training of the DRAMs (121-129) with the memory controller (132) as the main entity.

[0031] The memory PHY (234) may include physical or electrical layers and logical layers provided for signals, frequencies, timings, drives, detailed operation parameters, and functionality required for efficient communication between the memory controller (132) and the DRAMs (121–129). The memory PHY (234) may support features of the DDR and / or LPDDR protocols of the JEDEC (Joint Electron Device Engineering Council) standard.

[0032] The memory PHY (234) can connect the memory controller (132) and the DRAMs (121–129) through the memory interface (240). For the sake of brevity in the drawing, the memory interface (240) is shown as being connected between the memory controller (132) and the DRAMs (121–129) via a single signal line, but in reality, it may be connected via multiple signal lines. The memory interface (240) may include connectors for connecting the memory controller (132) and the DRAMs (121–129). The connectors may be implemented as pins, balls, signal lines, or other hardware components. For example, clock, command, address, data, etc., may be transmitted and received between the memory controller (132) and the DRAMs (121–129) through the memory interface (240).

[0033] Each of the DRAMs (121 to 129) may include a Mode Register Set (MRS, 220, hereinafter referred to as 'MRS'), a memory core, and peripheral circuits excluding the memory core. The memory core may include a memory cell array, a row decoder, a column decoder, and a sense amplifier. The memory cell array may include a plurality of word lines and a plurality of bit lines, and a plurality of memory cells formed at the intersection of the word lines and bit lines. The row decoder enables a word line corresponding to a row address, the sense amplifier detects and amplifies data from memory cells connected to the enabled word line and transmits it to the bit lines, and the column decoder can progressively increase a column address received in burst mode and select bit lines corresponding to the progressively increased column address.

[0034] The MRS (220) can be programmed to set multiple operation options, various functions, characteristics, and modes of the DRAM. The MRS (220) can be programmed with appropriate bit values ​​provided to the address bus of the memory interface (240) when an MRS command is issued from the memory controller (132).

[0035] For example, MRS (220) may be used to control burst length (BL), CAS latency (CL), enable / disable write leveling, and data terminal reference voltage (VrefDQ) training. Burst length (BL) may be provided to set the maximum number of column locations accessible for read and / or write commands. CAS latency (CL) may be provided to define the clock cycle delay between a read command and the first bit of valid output data. Write leveling may be provided to enable or disable skew compensation between the clock signal and the data strobe signal during a write operation. VrefDQ training may be provided to set the reference voltage for reading data input or output to the data (DQ) terminals. VrefDQ training may be trained based on the power supply voltage (VDDQ) driving the input / output buffers connected to the DQ terminals.

[0036] Additionally, MRS (220) is associated with general functions, characteristics, and modes of DRAM, including DLL (Delay Locked Loop) reset, DLL enable / disable, output drive strength, additive latency, Termination Data Strobe (TDQS) enable / disable, I / O buffer enable / disable, CAS write latency, dynamic termination, write CRC (Cyclic Redundancy Check), MPR (Multi Purpose Register) location function, MPR operation function, gear down mode, MPR read format, power down mode, Vref monitoring, read preamble training mode, read preamble function, write preamble function, C / A (Command and Addresses) parity function, CRC error status, C / A parity error status, ODT (On Die Termination) function, data mask function, write DBI (Data Bus Inversion) function, read DBI function, EDC (Error Detection Code) hold It can be used to control patterns, etc.

[0037] When the computing system (100) is powered up, the memory module (120) can perform a first memory training for the DRAMs (121-129) by the processing unit (130) inside the memory module (120). At the same time, the computing system (100) can execute boot operations by executing a portion of the BIOS code by the CPU (110) upon power-up.

[0038] Meanwhile, among the boot operations in which the CPU (110) executes the BIOS code, a second memory training for the DRAMs (121-129) of the memory module (120) may be included. The second memory training for the DRAMs (121-129) by the CPU (110) may be performed after the first memory training for the DRAMs (121-129) by the processing unit (130) is completed, that is, after confirming that the memory module (120) is in a ready state, which may be beneficial for reducing the boot time of the computing system (100). Additionally, by informing the CPU (110) of the ready state of the memory module (120), a minimum boot time can be guaranteed.

[0039] The memory controller (132) of the memory module (120) can output a module ready signal (RDY_DIMM) after the first memory training for the DRAMs (121-129) by the processing device (130) is completed. The training circuit (232) can generate a module ready signal (RDY_DIMM) indicating the completion of memory training by performing the first memory training of the DRAMs (121-129). The memory module (120) can output the module ready signal (RDY_DIMM) to the outside of the memory module (120) through an unused pin among the connecting pins (106) of the memory module (120). According to an embodiment, the memory module (120) can output the module ready signal (RDY_DIMM) through a pin dedicated to the module ready signal among the connecting pins (106) of the memory module (120).

[0040] A module ready signal (DRY_DIMM) output from a memory module (120) can be transmitted to a CPU (110) via a dedicated signal line (250) formed on a board (101) of a computing system (100). The module ready signal (DRY_DIMM) line (250) can be included in a memory bus (140) and transmitted to the CPU (110).

[0041] According to an embodiment, a module ready signal (DRY_DIMM) may be transmitted to a CPU (110) via an interrupt signal line formed on a board (101) of a computing system (100). The CPU (110) includes a system management mode (SMM), which enables the CPU (110) to operate in an alternative environment used to monitor and manage system resources and power usage, and, for example, to execute specific system-level code. Typically, the SMM may be entered via a system management interrupt (SMI). The CPU (110) includes an SMI package pin, which may be connected to an interrupt signal line. The CPU (110) may receive the module ready signal (DRY_DIMM) via the interrupt signal line and the SMI package pin. Reusing existing interrupt signal lines within the board (101) can reduce the occupied space within the board (101) and avoid the cost of extending additional wires to the CPU (110). Additionally, avoiding additional wires can eliminate potential electromagnetic interference (EMI) that may arise from the presence of additional wires.

[0042] FIG. 3 is a flowchart illustrating a booting method of a computing system according to embodiments of the present invention.

[0043] Referring to FIG. 3 in conjunction with FIG. 1 and FIG. 2, power is supplied to the computing system (100) and the computing system (100) can be powered up (S100). Step S100 may include cases where the computing system (100) is reset or the power state of the computing system (100) is transitioned. According to an embodiment, when the computing system (100) is powered up, a Power-On-Reset (POR) operation may be performed on the hardware components of the computing system (100) for the proper operation of the computing system (100). For example, when the power voltage level provided to the memory module (120) is maintained stably and constantly, the processing unit (130) and DRAMs (121–129) may perform a POR operation for the proper operation of the memory module (120).

[0044] After the computing system (100) is powered up, the boot operation of the computing system (100) can be separated into first boot operations (S320, S322) executed by the processing unit (130) within the memory module (120) and second boot operations (S330, S332, S334, S336, S338) executed by the CPU (110) using BIOS code read from the BIOS memory (150). The first boot operations executed by the processing unit (130) can proceed simultaneously with some of the second boot operations executed by the CPU (110). The remainder of the second boot operations executed by the CPU (110) can proceed after checking the module ready status of the memory module (1220).

[0045] After the computing system (100) is powered up, the memory module (120) can perform first memory training by the processing unit (130) (S320). The training circuit section (232) of the memory controller (132) within the processing unit (130) can perform training for the DRAMs (121–129). For example, clock training, address training, write / read leveling, write / read re-center training, etc., can be performed. A detailed description of the first memory training by the processing unit (130) in step S320 will be described in FIG. 4.

[0046] The memory module (120) can generate a module ready signal (RDY_DIMM) when the first memory training (S320) by the processing device (130) is completed (S322). The module ready signal (RDY_DIMM) is a signal indicating that the first memory training is completed after the first memory training for the DRAMs (121~129) is completed in the training circuit section (232). The module ready signal (RDY_DIMM) can be transmitted to the CPU (110).

[0047] After the computing system (100) is powered up, the CPU (110) can perform a first boot sequence for the computing system (100) (S330). The first boot sequence may be configured to read stored ID information for the CPU (110), memory module (120), and computing system board (101). According to an embodiment, the stored ID information may be read from an SPD memory device (104) included in the memory module (120) or from a BIOS memory (150). The BIOS code included in the BIOS memory (150) may include instructions for reading stored ID information for the CPU (110), memory module (120), and computer system board. The CPU (110) can extract IDs, such as serial numbers, for the CPU (110), memory module (120), and computing system board (101) by executing the BIOS code. A detailed description of the first boot sequence of step S330 will be explained in Fig. 5.

[0048] After the CPU (110) performs the first boot sequence (S330), it can check whether a module ready signal (RDY_DIMM) has been received from the memory module (120) (S332). If the module ready signal (RDY_DIMM) has not been received (S332: No), that is, if the first memory training for the DRAMs (121-129) by the processing unit (130) within the memory module (120) has not been completed, the CPU (110) can wait, as indicated by the loops S332 and S334, until the first memory training by the processing unit (130) is completed and the module ready signal (RDY_DIMM) is received (S334).

[0049] When a module ready signal (RDY_DIMM) is received from the memory module (120) (S332: Yes), that is, when the first memory training for the DRAMs (121–129) by the processing unit (130) within the memory module (120) is completed, the CPU (110) may perform a second boot sequence for the computing system (100) (S336). The second boot sequence may be configured to perform initialization of the memory module (120) and second memory training for the DRAMs (121–129) by the CPU (110). The second memory training for the DRAMs (121–129) by the CPU (110) may be similar to the first memory training for the DRAMs (121–129) by the processing unit (130) performed in step S320. The second memory training for the DRAMs (121–129) by the CPU (110) may include, for example, clock training, address training, write / read leveling, write / read re-center training, etc. A detailed description of the second boot sequence of step S360 will be described in FIG. 6.

[0050] If the second boot sequence for the computing system (100) by the CPU (110) is successfully completed and no hardware malfunction is detected, the booted computing system (100) is operated. The computing system (100) can execute various computing functions.

[0051] The booting method of the computing system described above performs memory training primarily between the processing unit (130) in the memory module (120) and the DRAMs (121-129), and then performs memory training secondarily between the CPU (110) and the DRAMs (121-129). Since the memory training of the DRAMs (121-129) is performed twice, the stability of the computing system can be guaranteed.

[0052] FIG. 4 is a flowchart specifically describing the first memory training (S320) by the processing device in the memory module of FIG. 3.

[0053] Referring to FIGS. 2, FIGS. 3 and FIGS. 4, as the computing system (100) is powered up, the memory module (120) can be powered up (S310). After the memory module (120) is powered up, the memory controller (132) can set the RCW (230) to control the initialization and / or operation characteristics of the DRAMs (121-129) (S401). The memory controller (132) can store codes in the RCW (230) that indicate the frequency, timing, drive, detailed operation parameters, etc. of the DRAMs (121-129) so that they interact normally with the DRAMs (121-129).

[0054] DRAMs (121~129) can set an MRS (220) that sets multiple operation options, various functions, characteristics, and modes of DRAMs (121~129) (S402). The MRS (220) can be set with codes that set burst length (BL), CAS latency (CL), MPR operation function, MPR readout format, write leveling, VrefDQ training, readout / write DBI function, etc.

[0055] The training circuit section (232) of the memory controller (132) can perform clock training for control signals (CTL) through the memory interface (240) (S403). The control signals (CTL) may include a chip select signal (CS), a clock enable signal (CKE), a row address strobe signal (RAS), a column address strobe signal (CAS), a write enable signal (WE), etc. Clock training can be performed so that the control signals (CTL) transmitted from the memory controller (132) can be received by the DRAMs (121-129) in synchronization with the clock signal (CLK).

[0056] The training circuit section (232) of the memory controller (132) can perform clock training for commands (CMD) through the memory interface (240) (S404). The commands (CMD) may include precharge commands, active commands, read commands, write commands, etc. Clock training can be performed so that commands (CMD) transmitted from the memory controller (132) can be received by the DRAMs (121~129) synchronized with the clock signal (CLK).

[0057] The memory controller (132) can train a receive enable to recognize signals received by DRAMs (121–129) through the memory interface (240) (S405). The DRAMs (121–129) can provide a receive enable signal to the training circuit (232) to recognize the reception of signals transmitted from the memory controller (132). The training circuit (232) may include a buffering and timing circuit that maintains the assertion of the receive enable signal to coincide with the transmission of the signal from the memory controller (132). The timing of the assertion of the receive enable signal in the training circuit (232) may be determined during the receive enable training process.

[0058] The training circuit section (232) of the memory controller (132) can perform basic data strobe signal (DQS) training for data (DQ) output from DRAMs (121-129) through the memory interface (240) (S406). The training circuit section (232) can perform read-re-center training so that when the data strobe signal (DQS) of the DRAMs (121-129) is output to the memory controller (132) along with the data (DQ), the data strobe signal (DQS) edge is centered in the data (DQ) window.

[0059] Clock training for control signals (CTL) in step S403, clock training for commands (CMD) in step S404, receive enable training in step S405, and / or data strobe signal (DQS) training for data (DQ) in step S406 can be trained using the MPR operation function and MPR readout format of the MRS (220). Clock training for control signals (CTL), clock training for commands (CMD), and receive enable training can be trained by reading a timing calibration bit sequence preset in the MPR. And, data strobe signal (DQS) training for data (DQ) can be trained by reading a data pattern preset in the MPR. The trainings in steps S403 through S406 are parameter trainings in peripheral circuits using the MPR, without using the memory cores of the DRAMs (121 to 129).

[0060] The training circuit section (232) of the memory controller (132) receives a write leveling command associated with the write operation of the DRAMs (121-129) through the memory interface (240) and can perform write leveling to compensate for the skew between the received clock signal (CLK) and the data strobe signal (DQS) (S407). Write leveling is a function that samples the data strobe signal (DQS) output from the memory controller (132) as the clock signal (CLK), detects the phase relationship between the data strobe signal (DQS) and the clock signal (CLK), and adjusts the delay time of the data strobe signal (DQS).

[0061] The training circuit section (232) of the memory controller (132) can perform training of a data strobe signal (DQS) for data (DQ) input to the DRAMs (121-129) through the memory interface (240) (S408). The DRAMs (121-129) can perform write re-center training so that when the data strobe signal (DQS) is input along with the data (DQ) from the memory controller (132), the edge of the data strobe signal (DQS) is centered in the data (DQ) window.

[0062] The training circuit portion (232) of the memory controller (132) can perform a write / read data deskew operation to reduce the difference in data input / output time between data (DQ) input or output from / to DRAMs (121~129) through the memory interface (240) (S409). Since the DRAMs (121~129) reduce the effective data window when the skew between write data (DQ) increases in write mode, they can perform a write data deskew operation to compensate for data skew in order to secure an effective data margin. Since the DRAMs (121~129) reduce the effective data window when the skew between read data (DQ) increases in read mode, they can perform a read data deskew operation to compensate for data skew in order to secure an effective data margin.

[0063] The training circuit section (232) of the memory controller (132) can perform VrefDQ training to set a reference voltage (VrefDQ) level for reading data (DQ) input or output from / to DRAMs (121-129) through the memory interface (240) (S410). The DRAMs (121-129) can train the training value of the reference voltage (VrefDQ), the VrefDQ training range, etc. The DRAMs (121-129) can perform VREFDQ training so that the reference voltage (VrefDQ) level is in the middle of the data (DQ) eye diagram, which is shown as a superposition of multiple data (DQ) transitions.

[0064] In order for the memory controller (132) to properly identify data read from the DRAMs (121–129), it is important to determine the time during which the read data is valid. In order for the DRAMs (121–129) to properly identify write data received from the memory controller (132), it is also important to determine the time during which the write data is valid. To this end, a predetermined preamble time indicating whether the data (DQ) is valid before the input or output of the data (DQ) may be set in the data strobe signal (DQS). The training circuit section (232) of the memory controller (132) can perform advanced data strobe signal (DQS) training for the data (DQ) input or output from the DRAMs (121–129) through the memory interface (240) (S411).

[0065] The training circuit section (232) can enable training the data strobe signal (DQS) to have a preamble time of one clock cycle or two clock cycles before inputting data (DQ) according to a write command or before outputting data (DQ) according to a read command. Enable training for the data strobe signal (DQS) can perform an operation to adjust the delay of the DLL until the declaration of the enable signal matches the preamble indication in the data strobe signal (DQS).

[0066] The training steps S408 to S411 are core parameter training using the memory core of the DRAMs (121 to 129). The training circuit section (232) can complete peripheral circuit parameter training and core parameter training of the DRAMs (121 to 129) and store the optimized peripheral circuit parameters and core parameters in a parameter storage area. The parameter storage area may be, for example, an extended mode register set (EMRS), a separate parameter register section, or a non-volatile memory such as flash memory, EPROM, EEPROM, etc. The DRAMs (121 to 129) can write or read data in an environment set with the optimized peripheral circuit parameters and core parameters stored in the parameter storage area.

[0067] FIG. 5 is a flowchart specifically describing the first boot sequence (S330) performed by the CPU of FIG. 3.

[0068] Referring to FIGS. 1, FIGS. 3 and FIGS. 5, after the computing system (100) is powered up, the CPU (110) can detect the hardware configurations of the computing system (100). The CPU (110) can detect the configuration of the memory module (120) among the hardware configurations (S501). The CPU (110) can identify the type and / or memory attribute of the memory module (120). The type of the memory module (120) may be any one of RDIMM, LRDIMM, FBDIMM, and SODIMM. The memory attribute may consist of the number of ranks, data width, data bandwidth, etc. For example, it may consist of 1 Rank, x4, 1600MHz, etc.

[0069] The CPU (110) can check the power-on reset (POR) operation performed on the hardware components of the computing system (100) after power-up for the proper operation of the computing system (100) (S502). In particular, the CPU (110) can check the POR operation performed on the processing unit (130) and DRAMs (121~129) for the proper operation of the memory module (120).

[0070] The CPU (110) can initialize the DDR (Double-Data-Rate) clocks of the computing system (100) (S503). The CPU (110) can check the power voltage (VDD) of the computing system (100) and the rank of the memory module (120) (S504). The CPU (110) can obtain SPD data stored in the SPD memory device (104) included in the memory module (120) (S505). The SPD data may include the type of the memory module (120), the type of the memory device included in the memory module (120), operation timing information, manufacturing information, revision code, serial number, etc.

[0071] After powering up the computing system (100), the first boot sequence (S330) performed by the CPU may include the steps of detecting the configuration of the memory module (120) (S501), checking the POR operation (S502), initializing the DDR clocks (S503), checking the power voltage (VDD) and the rank of the memory module (120) (S504), and obtaining SPD data (S505). In this embodiment, the first boot sequence (S330) performed by the CPU is described as having five steps, but the scope of the invention is not limited thereto, and the first boot sequence (S330) may include various additional steps.

[0072] After the CPU (110) performs the first boot sequence (S330), it checks whether a module ready signal (RDY_DIMM) is received from the memory module (120) (S332), waits until the module ready signal (RDY_DIMM) is received (S334), and when the module ready signal (RDY_DIMM) is received, it can perform the second boot sequence (S336).

[0073] FIG. 6 is a flowchart specifically describing the second boot sequence (S336) performed by the CPU of FIG. 3.

[0074] Referring to FIGS. 1, FIGS. 3 and FIGS. 6, the CPU (110) confirms that a module ready signal (RDY_DIMM) has been received from the memory module (120) (S332: Yes) and can test the components of the computing system (100) (S601). For example, the CPU (110) can perform a coarse test on the clocks provided to the components of the computing system (100). The CPU (110) can perform a coarse test to synchronize the phases of the clock signals and maintain a constant operating frequency.

[0075] The CPU (110) can initialize the input / output interface of the DRAMs (121-129) of the memory module (120) (S602). At this time, the memory controller (132) of the memory module (120) can be configured so that the input / output interface of the DRAMs (121-129) controlled by the CPU (110) is transparent to the processing device (130) of the memory module (120).

[0076] After the input / output interface of the DRAMs (121-129) of the memory module (120) is initialized (S602), the CPU (110) can perform a second memory training for the DRAMs (121-129). The initialization of the input / output interface and the second memory training for the DRAMs (121-129) by the CPU (110) may be similar to the first memory training (S320) for the DRAMs (121-129) by the processing device (130) of the memory module (120) described in FIG. 4.

[0077] The step (S602) of initializing the input / output interface of the DRAMs (121~129) by the CPU (110) may include operations similar to the operation of the memory controller (132) in step S401 of FIG. 4 setting the RCW (230) to match the initialization and / or operation characteristics of the DRAMs (121~129) and the operation of setting the MRS (220) in step S402 to set multiple operation options, various functions, characteristics, and modes of the DRAMs (121~129).

[0078] After this, the CPU (110) can perform a second memory training for the DRAMs (121-129). The CPU (110) can perform clock training for the control signals (CTL) of the DRAMs (121-129) (S603). The step (S603) of performing clock training for the control signals (CTL) of the DRAMs (121-129) by the CPU (110) may be similar to the clock training operation performed so that the control signals (CTL) transmitted from the memory controller (132) in step S403 of FIG. 4 can be received by the DRAMs (121-129) synchronized with the clock signal (CLK).

[0079] The CPU (110) can perform clock training for commands (CMD) of DRAMs (121-129) (S604). The step (S604) of performing clock training for commands (CMD) of DRAMs (121-129) by the CPU (110) may be similar to the clock training operation performed so that commands (CMD) transmitted from the memory controller (132) in step S404 of FIG. 4 can be received by DRAMs (121-129) synchronized with the clock signal (CLK).

[0080] The CPU (110) can perform receive enable training to recognize signals received in DRAMs (121-129) (S605). The step (S605) of performing receive enable training to recognize signals received in DRAMs (121-129) by the CPU (110) may be similar to the receive enable training operation in which the declaration of a receive enable signal recognizing the reception of signals transmitted from the memory controller (132) in step S405 of FIG. 4 is performed to match the transmission of signals from the memory controller (132).

[0081] The CPU (110) can perform basic data strobe signal (DQS) training for data (DQ) output from DRAMs (121-129) (S606). The step (S606) of performing basic data strobe signal (DQS) training for data (DQ) output from DRAMs (121-129) by the CPU (110) may be similar to the read re-center training operation performed so that the data strobe signal (DQS) edge is centered in the data (DQ) window when the data strobe signal (DQS) of the DRAMs (121-129) of step S406 of FIG. 4 is output to the memory controller (132) along with the data (DQ).

[0082] The CPU (110) can perform write leveling in conjunction with the write operation of the DRAMs (121 to 129) (S607). The step (S607) of performing write leveling in conjunction with the write operation of the DRAMs (121 to 129) by the CPU (110) may be similar to the operation of sampling the data strobe signal (DQS) output from the memory controller (132) in step S407 of FIG. 4 into a clock signal (CLK), detecting the phase relationship between the data strobe signal (DQS) and the clock signal (CLK), and adjusting the delay time of the data strobe signal (DQS).

[0083] The CPU (110) can perform training of a data strobe signal (DQS) for data (DQ) input into DRAMs (121-129) (S608). The step (S608) of performing training of a data strobe signal (DQS) for data (DQ) input into DRAMs (121-129) by the CPU (110) may be similar to the operation of performing write re-center training so that the edge of the data strobe signal (DQS) is centered in the data (DQ) window when the data strobe signal (DQS) is input from the memory controller (132) to the DRAMs (121-129) in step S408 of FIG. 4.

[0084] The CPU (110) can perform a write / read data dequeue operation that can reduce the difference in data input / output time between data (DQ) input or output from / to / from DRAMs (121~129) (S609). The step (S609) of performing a write / read data dequeue operation by the CPU (110) that can reduce the difference in data input / output time between data (DQ) input or output from / to / from DRAMs (121~129) may be similar to the write data dequeue operation and the read data dequeue operation of step S409 of FIG. 4.

[0085] The CPU (110) may perform VrefDQ training to set a reference voltage (VrefDQ) level for reading data (DQ) input or output from / to DRAMs (121~129) (S610). The step (S610) of performing VrefDQ training to set a reference voltage (VrefDQ) level for reading data (DQ) input or output from / to DRAMs (121~129) by the CPU (110) may be similar to the operation of performing VREFDQ training such that the reference voltage (VrefDQ) level is in the middle of the data (DQ) eye diagram of step S410 of FIG. 4.

[0086] The CPU (110) can perform data strobe signal (DQS) training to set a predetermined preamble time indicating whether the data (DQ) is valid before inputting or outputting data (DQ) to the data strobe signal (DQS) of the DRAMs (121~129) (S611). The step (S611) of performing data strobe signal (DQS) training to set a predetermined preamble time indicating whether data (DQ) is valid before data (DQ) is input or output to the data strobe signal (DQS) of the DRAMs (121-129) by the CPU (110) may be similar to the operation of enabling training so that the data strobe signal (DQS) has a preamble time of 1 clock cycle or 2 clock cycles before data (DQ) input according to the write command or before data (DQ) output according to the read command of step S411 of FIG. 4, and adjusting the delay of the DLL until the declaration of the enable signal matches the preamble instruction in the data strobe signal (DQS).

[0087] The memory controller (132) can complete the second memory training of the DRAMs (121-129) by the CPU (110) and store the optimized peripheral circuit parameters and core parameters of the DRAMs (121-129) in the parameter storage area.

[0088] Although the present disclosure has been described with reference to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims

Claim 1 A computing system comprising: a board; a host device mounted on the board; a memory module mounted on the board and connected to the host device, and including a plurality of memory devices and a processing device connected to the plurality of memory devices; and a BIOS memory storing BIOS code for booting the computing system, wherein the processing device of the memory module performs primary memory training on the plurality of memory devices when the computing system is powered up, generates a module ready signal after completing the memory training, transmits the module ready signal to the host device, and the host device performs secondary memory training on the plurality of memory devices when it receives the module ready signal. Claim 2 A computing system according to claim 1, wherein the memory module outputs the module ready signal to the outside of the memory module through an unused pin among the connecting pins of the memory module. Claim 3 A computing system according to claim 1, wherein the memory module outputs the module ready signal to the outside of the memory module through a pin dedicated to the module ready signal among the connecting pins of the memory module. Claim 4 A computing system according to claim 1, characterized in that the module ready signal is transmitted to the host device through an interrupt signal line formed on the board. Claim 5 A computing system according to claim 1, characterized in that the module ready signal is transmitted to the host device through a module ready signal line formed on the board. Claim 6 A method for booting a computing system equipped with a memory module including a processing unit connected to a plurality of memory devices, comprising: a step of powering up the computing system; a step, after powering up, in which the memory module performs a first memory training for the plurality of memory devices by the processing unit and generates a module ready signal indicating the completion of the first memory training; a step, after powering up, in which a host device executing a BIOS code of a BIOS memory included in the computing system performs a first boot sequence; a step, after performing the first boot sequence, in which the host device waits for the module ready signal to be received from the memory module; and a step, in which the host device receives the module ready signal and performs a second boot sequence based on the module ready signal, wherein the second boot sequence includes a step of performing a second memory training for the plurality of memory devices. Claim 7 A booting method for a computing system according to claim 6, characterized in that the step of performing the first memory training and the step of performing the first boot sequence are performed simultaneously. Claim 8 A method for booting a computing system according to claim 6, wherein the first boot sequence is configured to read ID information for hardware components of the computing system, and the first boot sequence includes the step of checking the type and memory attributes of the memory module from the SPD memory of the memory module. Claim 9 A method for booting a computing system according to claim 8, characterized in that the memory module is of the DIMM type. Claim 10 A booting method for a computing system according to claim 6, wherein the second memory training performed by the host device is configured to be performed transparently to the processing device.

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