Bidirectional variable gain phase shifter

Abstract

A bidirectional active type phase shifter is disclosed that supports bidirectional operation to reduce the overall chip size. This phase shifter includes a first circuit, a second circuit, and a control circuit. The first circuit includes two differential signal terminals and four quadrature signal terminals, and operates as an I / Q generator during forward operation and as a vector synthesizer during reverse operation. The second circuit includes four quadrature signal terminals and two differential signal terminals, each connected to the quadrature signal terminals of the first circuit, and operates as a vector synthesizer during forward operation and as a variable gain differential amplifier during reverse operation. The control circuit controls the second circuit through four bias current sources, such that the current between the two differential terminals is maintained equal during forward operation and the current between the four quadrature terminals is maintained equal during reverse operation.

Description

Technology Field

[0001] The present invention relates to a bidirectional variable gain phase shifter, and more specifically, to a bidirectional variable gain phase shifter applicable to wireless radio frequency integrated circuits for beamforming systems. Background Technology

[0002] Phase shifters can be divided into passive and active types. There is a trade-off between gain (or loss) and DC power consumption between passive and active phase shifters. Passive phase shifters have zero DC power consumption, but active phase shifters exhibit better characteristics in terms of loss. Additionally, active phase shifters have the advantage of providing bit-independent gain.

[0003] As resolution increases, passive phase shifters suffer greater losses, whereas active phase shifters exhibit fewer such issues. In terms of input P1dB characteristics, passive phase shifters are clearly superior. Regarding gain control, configuring the system to use four sub-amplifiers simultaneously allows for the advantages of active phase shifters to be retained without additional insertion loss, while enabling high-resolution control of both phase and gain within a single block. Control is possible without additional blocks, whereas passive phase shifters require attenuators to control gain, which leads to greater losses. In terms of size, they are similar for approximately 4-bit phase control, but as resolution increases, active phase shifters become smaller than passive ones. Therefore, overall, active phase shifters are superior to passive types in high-resolution control, with the exception of P1dB.

[0004] However, since active-type phase shifters are unidirectional, two active-type phase shifters are required for each of the reception (Tx) and transmission (Rx) operations. In contrast, passive-type phase shifters possess bidirectional characteristics, requiring only a single one for the TRx chain. Consequently, even though active-type phase shifters are small, they are actually larger than passive-type phase shifters because two are required for TRx. Therefore, there is a demand for a phase shifter that reduces the overall chip size required for the system by making the active-type phase shifter bidirectional, while maintaining the low-loss, high-resolution independent gain and phase control of existing vector sum variable-gain phase shifters. The problem to be solved

[0005] The objective of the present invention, which aims to solve the aforementioned problems, is to provide a phase shifter that reduces the chip size required for the entire system by making the active type phase shifter bidirectional while maintaining low-loss, high-resolution independent gain and phase control. means of solving the problem

[0006] A bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure for solving such problems is a bidirectional variable gain phase shifter comprising: a first circuit configured to operate as an I / Q generator in the first direction and as a vector synthesizer in the second direction opposite to the first direction, comprising a pair of first differential signal terminals for receiving or outputting a differential signal and four first quadrature signal terminals for receiving or outputting a quadrature signal; a second circuit configured to operate as a vector synthesizer in the first direction and as a variable gain differential amplifier in the second direction, comprising four second quadrature signal terminals and a pair of second differential signal terminals each connected to the four first quadrature signal terminals, respectively; and a control circuit configured to control the second circuit through first, second, third, and fourth bias current sources, wherein the first direction is from the first circuit to the second circuit direction and the second direction is from the second circuit to the first circuit direction, and when operating in the first direction, the The current flowing through a pair of second differential signal terminals is maintained equal to each other, and during the second direction operation, the current flowing through four of the second quadrature signal terminals is maintained equal to each other.

[0007] Hereinafter, the first direction is referred to as the forward direction, and the second direction is referred to as the reverse direction.

[0008] In one embodiment, the second circuit includes a plurality of transistors, and the four second quadrature signal terminals may correspond to the output terminals of the plurality of transistors.

[0009] In one embodiment, during forward operation, the sum of the currents flowing through the second differential signal terminals may be the same as the sum of the currents flowing through the second quadrature signal terminals during reverse operation.

[0010] In one embodiment, the second circuit may be configured such that the gain of each path varies according to the phase information of the signal input or output through the four second quadrature signal terminals.

[0011] In one embodiment, the second circuit may include a first differential amplifier circuit group and a second differential amplifier circuit group. The first differential amplifier circuit group may include four second quadrature signal terminals and two second differential signal terminals. The second differential amplifier circuit group may share the second quadrature signal terminals and the second differential signal terminals of the first differential amplifier circuit group.

[0012] In one embodiment, the first differential amplifier circuit group and the second differential amplifier circuit group can output a first differential signal and a second differential signal generated based on a signal input through the first quadrature signal terminals through opposite second differential signal terminals.

[0013] In one embodiment, the control circuit may be configured to provide bias currents to each of the first differential amplifier circuit group and the second differential amplifier circuit group, and to maintain the total sum of the bias currents constant.

[0014] In one embodiment, the first differential amplifier circuit group may be controlled through the first and second bias current sources, and the second differential amplifier circuit group may be controlled through the third and fourth bias current sources.

[0015] In one embodiment, the control circuit includes a digital-to-analog converter (DAC), and the first, second, third, and fourth bias current sources can be set according to the output value of the DAC.

[0016] In one embodiment, during forward operation, the first quadrature signal terminals output a first phase signal (I+), a second phase signal (I-), a third phase signal (Q+), and a fourth phase signal (Q-), respectively, and during reverse operation, the second quadrature signal terminals output a fifth phase signal (I'(+)), a sixth phase signal (I'(-)), a seventh phase signal (Q'(+)), and an eighth phase signal (Q'(-)), respectively, and at this time, the relationship equations I'(+) = I+ + Q+, I'(-) = I- + Q-, Q'(+) = I- + Q+, and Q'(-) = I+ + Q- may be formed.

[0017] As one embodiment, this bidirectional variable gain phase shifter may further include a first transmission line transformer connected to first differential signal terminals.

[0018] As one embodiment, this bidirectional variable gain phase shifter may further include a second transmission line transformer connected to second differential signal terminals. Effects of the invention

[0019] According to the bidirectional variable gain phase shifter of the embodiments of the present disclosure, stable vector synthesis is possible by maintaining the currents flowing through the four second quadrature signal terminals equally even during reverse operation.

[0020] In addition, by sharing the DAC and passive network in both forward and reverse operations, circuit complexity can be significantly reduced and chip area minimized.

[0021] Furthermore, in the reverse direction, it has an advantage in terms of noise figures because it passes through a second circuit operating as a variable gain amplifier without going through an I / Q generator with large loss, and then a vector sum occurs in the first circuit (I / Q generator) operating as a vector synthesizer. Brief explanation of the drawing

[0022] FIG. 1 is a schematic diagram of a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure. FIGS. 2 and FIGS. 3 are conceptual diagrams illustrating the bidirectional variable gain phase shifter shown in FIGS. 1 when operating in the forward and reverse directions, respectively. FIGS. 4 and FIGS. 5 are conceptual diagrams illustrating how the first circuit shown in FIG. 1 operates as an I / Q generator when operating in the forward direction and as a vector synthesizer when operating in the reverse direction, respectively. FIG. 6 is a schematic diagram of a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure. FIG. 7 is a circuit diagram illustrating embodiments of the second circuit when operating in the forward direction. FIG. 8 is a circuit diagram illustrating a comparative example of the second circuit when operating in the reverse direction. FIG. 9 is a circuit diagram illustrating embodiments of the second circuit when operating in the reverse direction. FIGS. 10 and FIGS. 11 are drawings for explaining the operation of the circuit diagram illustrated in FIGS. 9. Specific details for implementing the invention

[0023] The present invention is susceptible to various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0024] Terms such as first, second, A, B, etc., may be used to describe various components, but said components shall not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0025] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0026] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0027] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0028] Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0029] FIG. 1 is a schematic diagram of a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure.

[0030] Referring to FIG. 1, a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure includes a first circuit (110), a second circuit (120), and a control circuit (150 in FIG. 6). The bidirectional variable gain phase shifter may further include at least one of a first transmission line transformer (130) and a second transmission line transformer (140).

[0031] The first circuit (110) includes two first differential signal terminals (DT1) and first quadrature signal terminals (QT1). The two first differential signal terminals (DT1) receive or output a differential signal. The four first quadrature signal terminals (QT1) receive or output a quadrature signal. The first circuit (110) is configured to operate as an I / Q generator in the forward direction and as a vector synthesizer in the reverse direction.

[0032] When operating in the forward direction, the first circuit (110) receives a differential signal from the first transmission line transformer (130) through the first differential signal terminals (DT1) and outputs a first phase signal (I+), a second phase signal (I-), a third phase signal (Q+), and a fourth phase signal (Q-) through the first quadrature signal terminals (QT1). The first phase signal (I+) and the second phase signal (I-) have a phase difference of 180 degrees from each other, and the third phase signal (Q+) and the fourth phase signal (Q-) have a phase difference of 180 degrees from each other. The first phase signal (I+) and the third phase signal (Q+) have a phase difference of 90 degrees from each other.

[0033] When operating in reverse, the first circuit (110) receives four phase signals from the second circuit (120) through the first quadrature signal terminals (QT1). At this time, among the four phase signals, the phase signals input to the terminal marked I+ and the terminal marked I- have a phase difference of 180 degrees from each other, the phase signals input to the terminal marked Q+ and the terminal marked Q- have a phase difference of 180 degrees from each other, and the terminal marked I+ and the terminal marked Q+ have the same phase from each other.

[0034] This first circuit (110) may be a hybrid coupler, an RC poly phase filter, an RC-RL poly phase filter, an RL poly phase filter, a quadrature all pass filter, etc.

[0035] The second circuit (120) includes four second quadrature signal terminals (QT2) and two second differential signal terminals (DT2). The second quadrature signal terminals (QT2) are each connected to the first quadrature signal terminals (QT1). The second circuit (120) is configured to operate as a vector synthesizer in the forward direction and as a variable gain differential amplifier in the reverse direction. In one embodiment, the second circuit (120) includes a plurality of transistors, and the four second quadrature signal terminals (QT2) may correspond to the output terminals of the transistors. The second circuit (120) may be configured so that the gain of each path varies according to the phase information of the signal input or output through the four second quadrature signal terminals (QT2). The configuration of the second circuit (120) will be described in detail later.

[0036] The above control circuit (150 in FIG. 6) controls the second circuit (120) through the first, second, third, and fourth bias current sources.

[0037] In the bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure, during forward operation, the currents flowing through the two second differential signal terminals (DT2) are kept equal to each other, and during reverse operation, the currents flowing through the four second quadrature signal terminals (QT2) are kept equal to each other.

[0038] The first transmission line transformer (130) is connected to the first differential signal terminals (DT1), and the second transmission line transformer (140) is connected to the second differential signal terminals (DT2). The first transmission line transformer (130) and the second transmission line transformer (140) perform impedance matching or power distribution through the difference in transmission line phase and length. The first transmission line transformer (130) and the second transmission line transformer (140) can be formed using a ferrite core (or bead) and multiple windings, or implemented using a coaxial cable. When the first transmission line transformer (130) and the second transmission line transformer (140) are formed using a ferrite core (or bead) and multiple windings, they are mainly used in relatively low-power circuits and low frequency bands, but they allow for easy impedance conversion of various values ​​and can be manufactured in a small size. When the first transmission line transformer (130) and the second transmission line transformer (140) are implemented via a coaxial cable, there is a disadvantage that they operate only at a fixed impedance ratio, but there is an advantage that they have excellent operation reproducibility and can be used with high-power circuits and up to a relatively high frequency range.

[0039] FIGS. 2 and FIGS. 3 are conceptual diagrams illustrating the bidirectional variable gain phase shifter shown in FIGS. 1 when operating in the forward and reverse directions, respectively.

[0040] Referring to FIG. 2, when operating in the forward direction, the RF signal (RF IN) is converted into a differential signal through a first transmission line transformer (130) that operates as a balun, and this differential signal is converted into a first phase signal (I+), a second phase signal (I-), a third phase signal (Q+), and a fourth phase signal (Q-) through a first circuit (110) that operates as an I / Q generator through first differential signal terminals (DT1), and is output through first quadrature signal terminals (QT1), respectively.

[0041] The signals output in this way are each adjusted in magnitude and combined through a second circuit (120) that operates as a vector synthesizer for the first phase signal (I+), the second phase signal (I-), the third phase signal (Q+), and the fourth phase signal (Q-), and then output as an RF signal (RF OUT) with adjusted magnitude and phase through a second transmission line transformer (140).

[0042] Referring to FIG. 3, when operating in reverse, the RF signal (RF IN) is converted into a differential signal through a second transmission line transformer (140) that operates as a balun, and the converted differential signal is separated into a fifth phase signal (I'(+)), a sixth phase signal (I'(-)), a seventh phase signal (Q'(+)) and an eighth phase signal (Q'(-)) through the second differential signal terminals (DT2) and a second circuit (120) that operates as a variable gain differential amplifier.

[0043] These phase signals are transmitted to a first circuit (110) that operates as a vector synthesizer, and each phase component is combined to perform vector synthesis, thereby combining into a differential RF signal. The combined differential signal is output through the first differential signal terminals (DT1), and is converted into a single RF signal (RF OUT) and output via the first transmission line transformer (130).

[0044] FIGS. 4 and FIGS. 5 are conceptual diagrams illustrating how the first circuit shown in FIG. 1 operates as an I / Q generator when operating in the forward direction and as a vector synthesizer when operating in the reverse direction, respectively.

[0045] Referring to FIGS. 1 and 4, the first circuit (110) according to the present embodiment operates as an I / Q generator during forward operation. More specifically, a single-phase RF signal (A1∠0°) input from an input terminal is separated through the first circuit (110) and converted into two signals having the same magnitude but a 90-degree phase difference. For example, as shown in FIG. 4, the input signal A1∠0° is separated into an I-axis direction signal (A1 / 2∠0°) and a Q-axis direction signal (A1 / 2∠-90°), respectively, which correspond to quadrature components in vector space.

[0046] These separated I / Q components are transmitted to the second circuit (120) at the rear, enabling independent amplification or phase control for each component, and finally enabling the synthesis and output of a phase-shifted RF signal.

[0047] On the other hand, referring to FIGS. 1 and FIGS. 5, the first circuit (110) acts as a vector combiner during reverse operation. In this case, two I / Q phase components (A1∠0°, A2∠0°) transmitted from the second circuit (120) or the preceding circuit are input to the vector combiner, which is the first circuit (110), and as shown in FIG. 5, the vector combiner combines the two input signals at a certain ratio to synthesize them into a single RF output signal.

[0048] Specifically, the signal output from the vector synthesizer takes the form of A1 / 2∠0° + A2 / 2∠-90°, representing the result of vector synthesis of orthogonal components. By physically and vectorially adding the two phase components within the combiner in this way, the phase and amplitude of the final RF output signal can be adjusted.

[0049] As a result, the first circuit (110) can operate as an I / Q generator during forward operation and as a vector synthesizer during reverse operation within the same hardware structure, so that bidirectional phase control circuits can be integrated into a single common structure. This enables chip area reduction at the overall system level while maintaining the function of the circuit, and is particularly suitable for phased array antenna systems or RF transceiver modules that require bidirectional phase control for transmission and reception.

[0050] Furthermore, by reusing the I / Q generator and vector synthesizer through a single combiner structure instead of implementing them as separate blocks, the complexity and power consumption of the passive network can be reduced, and insertion loss in the signal path can be minimized. In addition, this circuit configuration works in conjunction with a digital control-based DAC and a quadrant selector to support more precise variable gain control and phase vector synthesis.

[0051] Accordingly, the bidirectional variable-gain phase shifter according to the present disclosure can provide excellent technical effects in terms of circuit integration, phase accuracy, system miniaturization, and power efficiency.

[0052] FIG. 6 is a schematic diagram of a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure.

[0053] Referring to FIG. 6, a bidirectional variable gain phase shifter according to exemplary embodiments of the present disclosure is configured to enable bidirectional operation while precisely controlling the phase and magnitude of a high-frequency (RF) signal. In particular, by implementing forward and reverse signal paths within the same circuit, the embodiments enable the reuse of the DAC and passive network, and consequently allow for an efficient circuit configuration without redundancy of components. Accordingly, the bidirectional variable gain phase shifter is designed to effectively achieve improved system integration and size reduction.

[0054] In forward operation, the RF input signal (RF IN) is introduced through a first transmission line transformer (TLT: transmission line transformer, 130) that acts as a balun, and this performs the function of converting a single RF input into a differential RF signal. The converted differential signal is transmitted to a first circuit (110) that operates as an I / Q generator, and the first circuit (110) generates four signal components having a 90-degree phase difference with respect to the input signal, namely a first phase signal (I+), a second phase signal (I-), a third phase signal (Q+), and a fourth phase signal (Q-). For example, the first phase signal (I+) may have a phase of 0°, the second phase signal (I-) may have a phase of 180°, the third phase signal (Q+) may have a phase of 90°, and the fourth phase signal (Q-) may have a phase of 270°. These signals are transmitted to a subsequent circuit, the second circuit (120).

[0055] The second circuit (120) includes a plurality of variable-gain amplifiers capable of independently amplifying and controlling each of the four phase components. Each amplifier receives a corresponding phase component (I+, I-, Q+, Q-) as input, and its gain is individually adjusted according to the bias current supplied from a digital-to-analog converter (DAC) and a quadrant selection circuit. This configuration enables the realization of vector synthesis operations, which are important in a phase shifter, and allows for the generation of a composite RF signal having a desired phase and amplitude.

[0056] Meanwhile, by configuring the total bias current to be kept constant (Total current = K), the effect of improving the uniformity and linearity of power consumption is also achieved. This current synthesis method enables high-precision phase control and can minimize phase errors. Furthermore, by configuring the total bias current to be kept constant (Total current = K), the sum of the currents flowing through the second differential signal terminals (DT2) during forward operation can be equal to the sum of the currents flowing through the second quadrature signal terminals (QT2) during reverse operation.

[0057] For example, the second circuit (120) may include a first differential amplifier circuit group (121) and a second differential amplifier circuit group (122). The first differential amplifier circuit group (121) may include four second quadrature signal terminals (QT2) and two second differential signal terminals (DT2). The second differential amplifier circuit group (122) may share the second quadrature signal terminals (QT2) and the second differential signal terminals (DT2) of the first differential amplifier circuit group (121).

[0058] At this time, the first differential amplifier circuit group (121) and the second differential amplifier circuit group (122) can output a first differential signal and a second differential signal generated based on a signal input through the first quadrature signal terminals (QT1) through opposite second differential signal terminals (DT2).

[0059] More specifically, the first differential amplifier circuit group (121) receives first and second phase signals (I+, I-, Q+, Q-) through the first quadrature signal terminals (QT1), and the first and second differential signals of opposite phases output based on the first and second phase signals (I+, I-, Q+, Q-) are output through the signal terminals (DT2a, DT2b) located at the top and bottom in the drawing among the second differential signal terminals (DT2).

[0060] In contrast, the second differential amplifier circuit group (122) receives first and second phase signals (I+, I-, Q+, Q-) through the first quadrature signal terminals (QT1), and the first and second differential signals of opposite phases output based on the first and second phase signals (I+, I-, Q+, Q-) are output through the signal terminals (DT2b, DT2a) located at the bottom and top in the drawing among the second differential signal terminals (DT2).

[0061] In this way, the outputs of the first differential amplifier circuit group and the second differential amplifier circuit group are connected to opposite second differential signal terminals (DT2a, DT2b), so that the current flowing through the second quadrature signal terminals can be maintained at the same level even during reverse driving.

[0062] The synthesized RF signal is converted back into a single signal from a differential signal through an output transmission line transformer (output TLT) and transmitted to the RF output (RF OUT).

[0063] Meanwhile, the phase and gain of the second circuit (120) can be controlled through a control circuit (150). The control circuit (120) provides bias currents to each of the first differential amplifier circuit group (121) and the second differential amplifier circuit group (122), and can be configured so that the total sum of the bias currents is maintained constant.

[0064] For example, the first differential amplifier circuit group (121) may be controlled by a first bias current source (CA1) and a second bias current source (CA2), and the second differential amplifier circuit group (122) may be controlled through a third bias current source (CA3) and a fourth bias current source (CA4).

[0065] To control the amount of current flowing through the first to fourth bias current sources (CA1, CA2, CA3, CA4), the control circuit (150) may include a digital-to-analog converter (DAC). The digital-to-analog converter converts a digital signal input from the outside into an analog signal to control the amount of current flowing through the first to fourth bias current sources (CA1, CA2, CA3, CA4).

[0066] Meanwhile, as a result, the same circuit can receive RF input through the second transmission line transformer (140) in the reverse direction as well, separate I / Q components in the same manner, perform amplification control and synthesis, and then output through the first transmission line transformer (130). This bidirectional operation characteristic means that a single circuit block can accommodate both forward and reverse signal paths, and has the advantage of allowing components to be reused without additional circuit blocks.

[0067] Furthermore, by sharing the DAC and passive network in both forward and reverse operations, this phase shifter implements a structure that significantly reduces circuit complexity and minimizes chip area. Therefore, this embodiment provides superior circuit efficiency and integration compared to conventional unidirectional phase shifters, and can be very usefully applied in RF communication systems or phase array antennas.

[0068] FIG. 7 is a circuit diagram illustrating embodiments of the second circuit when operating in the forward direction.

[0069] Referring to FIG. 7, for example, the second circuit, which operates as a vector synthesizer when operating in the forward direction, may include, for example, a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8).

[0070] For example, the source terminal of the first transistor (T1) and the source terminal of the second transistor (T2) may be connected to each other to form a first bias current source (I_a). Additionally, the source terminal of the third transistor (T3) and the source terminal of the fourth transistor (T4) may be connected to each other to form a second bias current source (I_b). Furthermore, the source terminal of the fifth transistor (T5) and the source terminal of the sixth transistor (T6) may be connected to each other to form a third bias current source (I_c). Additionally, the source terminal of the seventh transistor (T7) and the source terminal of the eighth transistor (T8) may be connected to each other to form a fourth bias current source (I_d).

[0071] The gate terminal of the first transistor (T1) and the gate terminal of the fourth transistor (T4) are connected to each other and can be connected to the signal terminal that outputs the first phase signal (I+) among the first quadrature signal terminals of the first circuit operating as an I / Q generator. Additionally, the gate terminal of the second transistor (T2) and the gate terminal of the third transistor (T3) are connected to each other and can be connected to the signal terminal that outputs the second phase signal (I-) among the first quadrature signal terminals of the first circuit operating as an I / Q generator. Additionally, the gate terminal of the fifth transistor (T5) and the gate terminal of the eighth transistor (T8) are connected to each other and can be connected to the signal terminal that outputs the third phase signal (Q+) among the first quadrature signal terminals of the first circuit operating as an I / Q generator. In addition, the gate terminal of the sixth transistor (T6) and the gate terminal of the seventh transistor (T7) are connected to each other and can be connected to the signal terminal that outputs the fourth phase signal (Q-) among the first quadrature signal terminals of the first circuit operating as an I / Q generator.

[0072] The drain terminal of the first transistor (T1) and the drain terminal of the third transistor (T3) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the drain terminal of the second transistor (T2) and the drain terminal of the fourth transistor (T4) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6. Additionally, the drain terminal of the fifth transistor (T5) and the drain terminal of the seventh transistor (T7) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the drain terminal of the sixth transistor (T6) and the drain terminal of the eighth transistor (T4) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6.

[0073] In this connection, the sum of the total currents flowing through the first bias current source (I_a), the second bias current source (I_b), the third bias current source (I_c), and the fourth bias current source (I_b) is fixed (I_a + I_b + I_c + I_d = K), but by adjusting the individual magnitudes of each bias current source, a vector sum is generated.

[0074] To give a few examples of extreme cases, in the case where I_a = I_b = I_c = I_d = K / 4, the magnitudes of the first phase signal (I+) and the second phase signal (I-) having a phase difference of 180 degrees are equal, so the vector sum along the I-axis is 0, and the magnitudes of the third phase signal (Q+) and the fourth phase signal (Q-) having a phase difference of 180 degrees are equal, so the vector sum along the Q-axis is 0, and thus the total output becomes 0.

[0075] In addition, when I_a = K and I_b = I_c = I_d = 0, an output signal with the same phase as the first phase signal (I+) is generated, and when I_b = K and I_a = I_c = I_d = 0, an output signal with the same phase as the second phase signal (I-) is generated.

[0076] Likewise, when I_c = K and I_a = I_b = I_d = 0, an output signal with the same phase as the third phase signal (Q+) is generated, and when I_d = K and I_a = I_b = I_c = 0, an output signal with the same phase as the fourth phase signal (Q-) is generated.

[0077] As shown in FIG. 7, a variable gain phase shifter operating in the forward direction can operate normally even if any one of the first to fourth phase signals (I+, I-, Q+, Q-) is input, as the transistor connected to the second differential signal terminal (DT2a, DT2b), which is one of the two output signal terminals, is always turned on, and a constant DC current flows through the second differential signal terminal (DT2a, DT2b).

[0078] FIG. 8 is a circuit diagram illustrating a comparative example of the second circuit when operating in the reverse direction.

[0079] Referring to FIG. 8, for example, the second circuit according to the comparative example, which operates as a variable gain differential amplifier when operating in reverse direction, may include, for example, a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8).

[0080] For example, the source terminal of the first transistor (T1) and the source terminal of the second transistor (T2) may be connected to each other to form a first bias current source (I_a). Additionally, the source terminal of the third transistor (T3) and the source terminal of the fourth transistor (T4) may be connected to each other to form a second bias current source (I_b). Furthermore, the source terminal of the fifth transistor (T5) and the source terminal of the sixth transistor (T6) may be connected to each other to form a third bias current source (I_c). Additionally, the source terminal of the seventh transistor (T7) and the source terminal of the eighth transistor (T8) may be connected to each other to form a fourth bias current source (I_d).

[0081] The gate terminal of the first transistor (T1) and the gate terminal of the fourth transistor (T4) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the second transistor (T2) and the gate terminal of the third transistor (T3) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6. Additionally, the gate terminal of the fifth transistor (T5) and the gate terminal of the eighth transistor (T8) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the sixth transistor (T6) and the gate terminal of the seventh transistor (T7) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6.

[0082] The drain terminal of the first transistor (T1) and the drain terminal of the third transistor (T3) are connected to each other and can be connected to the signal terminal corresponding to the third phase signal (Q+) among the first quadrature signal terminals of the first circuit (110) shown in FIG. 6. Additionally, the drain terminal of the second transistor (T2) and the drain terminal of the fourth transistor (T4) are connected to each other and can be connected to the signal terminal corresponding to the fourth phase signal (Q-) among the first quadrature signal terminals of the first circuit (110) shown in FIG. 6. Additionally, the drain terminal of the fifth transistor (T5) and the drain terminal of the seventh transistor (T7) are connected to each other and can be connected to the signal terminal corresponding to the first phase signal (I+) among the first quadrature signal terminals of the first circuit (110) shown in FIG. 6. In addition, the drain terminal of the sixth transistor (T6) and the drain terminal of the eighth transistor (T4) are connected to each other and can be connected to the signal terminal corresponding to the second phase signal (I-) among the first quadrature signal terminals of the first circuit (110) shown in FIG. 6.

[0083] In this connection, the sum of the total currents flowing through the first bias current source (I_a), the second bias current source (I_b), the third bias current source (I_c), and the fourth bias current source (I_b) is fixed (I_a + I_b + I_c + I_d = K), but the variable gain is controlled by adjusting the individual magnitude of each bias current source.

[0084] However, in this case, the current at the first and second quadrature signal terminals corresponding to the first to fourth phase signals (I+, I-, Q+, Q-), which are each output node, changes over time, causing the impedance to change, and thus it cannot operate as a normal variable gain phase shifter.

[0085] FIG. 9 is a circuit diagram illustrating embodiments of the second circuit when operating in the reverse direction.

[0086] Referring to FIG. 9, for example, a second circuit operating as a variable gain differential amplifier may include, for example, a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a twelfth transistor (T12), a thirteenth transistor (T13), a fourteenth transistor (T14), a fifteenth transistor (T15), and a sixteenth transistor (T16).

[0087] For example, the source terminal of the first transistor (T1) and the source terminal of the second transistor (T2) may be connected to each other to form a first bias current source (I_a). Additionally, the source terminal of the third transistor (T3) and the source terminal of the fourth transistor (T4) may be connected to each other to form a second bias current source (I_b). Furthermore, the source terminal of the fifth transistor (T5) and the source terminal of the sixth transistor (T6) may be connected to each other to form a third bias current source (I_c). Additionally, the source terminal of the seventh transistor (T7) and the source terminal of the eighth transistor (T8) may be connected to each other to form a fourth bias current source (I_d). Furthermore, the source terminal of the ninth transistor (T9) and the source terminal of the tenth transistor (T10) may be connected to each other to form a first bias current source (I_a). Additionally, the source terminal of the 11th transistor (T11) and the source terminal of the 12th transistor (T12) can be connected to each other to form a second bias current source (I_b). Additionally, the source terminal of the 13th transistor (T13) and the source terminal of the 14th transistor (T14) can be connected to each other to form a third bias current source (I_c). Furthermore, the source terminal of the 15th transistor (T15) and the source terminal of the 16th transistor (T16) can be connected to each other to form a fourth bias current source (I_d).

[0088] The gate terminal of the first transistor (T1) and the gate terminal of the fourth transistor (T4) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the second transistor (T2) and the gate terminal of the third transistor (T3) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6. Additionally, the gate terminal of the fifth transistor (T5) and the gate terminal of the eighth transistor (T8) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the sixth transistor (T6) and the gate terminal of the seventh transistor (T7) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6. Additionally, the gate terminal of the ninth transistor (T9) and the gate terminal of the twelfth transistor (T12) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the tenth transistor (T10) and the gate terminal of the eleventh transistor (T11) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6. Additionally, the gate terminal of the thirteenth transistor (T13) and the gate terminal of the sixteenth transistor (T16) are connected to each other and can be connected to the upper second differential signal terminal (DT2a) shown in FIG. 6. Additionally, the gate terminal of the fourteenth transistor (T14) and the gate terminal of the fifteenth transistor (T15) are connected to each other and can be connected to the lower second differential signal terminal (DT2b) shown in FIG. 6.

[0089] The drain terminal of the first transistor (T1) and the drain terminal of the third transistor (T3) are connected to each other and can be connected to the signal terminal that outputs the first phase signal (I+) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the second transistor (T2) and the drain terminal of the fourth transistor (T4) are connected to each other and can be connected to the signal terminal that outputs the second phase signal (I-) among the first quadrature signal terminals of the first circuit. Furthermore, the drain terminal of the fifth transistor (T5) and the drain terminal of the seventh transistor (T7) are connected to each other and can be connected to the signal terminal that outputs the third phase signal (Q+) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the sixth transistor (T6) and the drain terminal of the eighth transistor (T4) are connected to each other and can be connected to the signal terminal that outputs the fourth phase signal (Q-) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the ninth transistor (T9) and the drain terminal of the eleventh transistor (T11) are connected to each other and can be connected to the signal terminal that outputs the third phase signal (Q+) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the tenth transistor (T10) and the drain terminal of the twelfth transistor (T12) are connected to each other and can be connected to the signal terminal that outputs the fourth phase signal (Q-) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the 13th transistor (T13) and the drain terminal of the 15th transistor (T15) are connected to each other and can be connected to the signal terminal that outputs the second phase signal (I-) among the first quadrature signal terminals of the first circuit. Additionally, the drain terminal of the 14th transistor (T14) and the drain terminal of the 16th transistor (T16) are connected to each other and can be connected to the signal terminal that outputs the first phase signal (I+) among the first quadrature signal terminals of the first circuit.

[0090] In the case of such a connection, unlike in Fig. 8 above, regardless of which of the two differential signals input from the second transmission line transformer is input, the transistors connected to the four second quadrature signal terminals always remain in a turned-on state, so that the same DC current flows through the second quadrature signal terminals, and accordingly, a stable variable gain phase shifter in the reverse direction can be implemented.

[0091] Meanwhile, the second circuit in the reverse direction shown in Fig. 9 and the second circuit in the forward direction shown in Fig. 7 may each be configured as separate circuits, and each circuit may be used during forward operation and reverse operation, or a switch may be configured in the circuit of Fig. 9 to switch as shown in Fig. 7.

[0092] FIGS. 10 and FIGS. 11 are drawings for explaining the operation of the circuit diagram illustrated in FIGS. 9.

[0093] Referring to FIG. 10, the sum of the total currents is fixed, and the current (i) for controlling the I-axis I,total ) and current (i) for controlling the Q-axis Q, total It is assumed that the ratio of ) is controlled to satisfy the following mathematical equation 1.

[0094]

[0095] In addition, current (i) for controlling the I-axis I,total Among ), the current (i) controlling the positive direction (I+) I,P Current (i) controlling the ) and negative direction (I-) I,M It is assumed that the ratio of ) is controlled to satisfy the following mathematical equation 2.

[0096]

[0097] In addition, current (i) for controlling the Q-axis Q,total Among ), the current (i) controlling the positive direction (I+) Q,P Current (i) controlling the ) and negative direction (I-) Q,MIt is assumed that the ratio of ) is controlled to satisfy the following mathematical equation 3.

[0098]

[0099] In this case, the reference vector is changed as shown in Fig. 11. That is, in the forward direction, the reference axes of I+, I-, Q+, and Q- are changed to I'(+), I'(-), Q'(+), and Q'(-) in the reverse direction.

[0100] In this case, the relationships I'(+) = I+ + Q+, I'(-) = I- + Q-, Q'(+) = I- + Q+, and Q'(-) = I+ + Q- are satisfied.

[0101] The simulation results of this bidirectional variable gain phase shifter are shown in Table 1 below.

[0102] Operation mode NF (Phase shifter only) NF(with 3dB NF, 15dB LNA) Forward (FW) 8.139dB 3.364dB Reverse direction (BW) 6.398dB 3.116dB

[0103] [Table 1] shows the Noise Figure (NF) values ​​in the forward and reverse directions. The Noise Figure is expressed as shown in Equation 4 below.

[0104]

[0105] That is, if the NF value is (0dB), it means that there is no additional noise in the ideal circuit, and if it is 0dB or higher, it means that the output signal contains more noise than the input signal, and in ordinary circuits, it appears as a value of 0dB or higher.

[0106] Simulation results show that the NF value in the forward direction was 8.139 dB, which is slightly higher than the NF value of 3.364 in the reverse direction. This can be attributed to the accumulation of losses as the signal passes through the I / Q generator (3 dB loss), the phase shifter, and the output path.

[0107] In other words, it can be seen that the path becomes simpler in the reverse direction, resulting in less loss. As such, in the case of the bidirectional variable gain phase shifter according to the embodiments of the present disclosure, in the reverse direction, it has an advantage in terms of noise figures because it passes through a second circuit operating as a variable gain amplifier without passing through an I / Q generator with large insertion loss, and then a vector sum occurs in the first circuit (I / Q generator) operating as a vector synthesizer.

[0108] In addition, it can be seen that the NF is further reduced when combined with a low-noise amplifier (LNA) with 3 dB NF and 15 dB Gain.

[0109] As described above, according to the bidirectional variable gain phase shifter of the embodiments of the present disclosure, stable vector synthesis is possible by maintaining the currents flowing through the four second quadrature signal terminals equally even during reverse operation.

[0110] In addition, by sharing the DAC and passive network in both forward and reverse operations, circuit complexity can be significantly reduced and chip area minimized.

[0111] Furthermore, in the reverse direction, it has an advantage in terms of noise figures because it passes through a second circuit operating as a variable gain amplifier without going through an I / Q generator with large loss, and then a vector sum occurs in the first circuit (I / Q generator) operating as a vector synthesizer.

[0112] The operation of the method according to an embodiment of the present invention can be implemented as a computer-readable program or code on a computer-readable recording medium. A computer-readable recording medium includes all types of recording devices in which information that can be read by a computer system is stored. Additionally, the computer-readable recording medium may be distributed across networked computer systems, allowing computer-readable programs or code to be stored and executed in a distributed manner.

[0113] In addition, computer-readable recording media may include hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Program instructions may include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0114] Some aspects of the invention have been described in the context of a device, but may also be described according to a corresponding method, wherein a block or device corresponds to a method step or a feature of a method step. Similarly, aspects described in the context of a method may also be described according to a corresponding block or item or a feature of a corresponding device. Some or all of the method steps may be performed by (or using) a hardware device, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, at least one of the most important method steps may be performed by such a device.

[0115] In the embodiments, a programmable logic device (e.g., a field-programmable gate array) may be used to perform some or all of the functions of the methods described herein. In the embodiments, the field-programmable gate array may operate with a microprocessor to perform one of the methods described herein. Generally, it is preferable that the methods be performed by some hardware device.

[0116] Although the present invention has been described with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A bidirectional variable gain phase shifter comprising a pair of first differential signal terminals that receive or output a differential signal and four first quadrature signal terminals that receive or output a quadrature signal, configured to operate as an I / Q generator in the first direction and as a vector synthesizer in the second direction opposite to the first direction; and a second circuit comprising four second quadrature signal terminals and a pair of second differential signal terminals each connected to the four first quadrature signal terminals, configured to operate as a vector synthesizer in the first direction and as a variable gain differential amplifier in the second direction. A bidirectional variable gain phase shifter comprising a control circuit configured to control the second circuit through first, second, third, and fourth bias current sources, wherein the first direction is from the first circuit to the second circuit direction and the second direction is from the second circuit to the first circuit direction, wherein when the first direction operation is performed, the currents flowing through the pair of second differential signal terminals are kept equal to each other, and when the second direction operation is performed, the currents flowing through the four second quadrature signal terminals are kept equal to each other. Claim 2 A bidirectional variable gain phase shifter according to claim 1, wherein the second circuit comprises a plurality of transistors, and the four second quadrature signal terminals correspond to the output terminals of the plurality of transistors. Claim 3 A bidirectional variable gain phase shifter according to claim 1, wherein, during forward operation, the sum of the currents flowing through the second differential signal terminals is the same as the sum of the currents flowing through the second quadrature signal terminals during reverse operation. Claim 4 A bidirectional variable gain phase shifter according to claim 1, wherein the second circuit is configured such that the gain of each path is varied according to the phase information of a signal input or output through the four second quadrature signal terminals. Claim 5 A bidirectional variable gain phase shifter according to claim 1, wherein the second circuit comprises: a first differential amplifier circuit group including four second quadrature signal terminals and two second differential signal terminals; and a second differential amplifier circuit group sharing the second quadrature signal terminals and the second differential signal terminals of the first differential amplifier circuit group. Claim 6 In claim 5, the first differential amplifier circuit group and the second differential amplifier circuit group output a first differential signal and a second differential signal generated based on a signal input through the first quadrature signal terminals through opposite second differential signal terminals, a bidirectional variable gain phase shifter. Claim 7 A bidirectional variable gain phase shifter according to claim 5, wherein the control circuit provides bias currents to each of the first differential amplifier circuit group and the second differential amplifier circuit group, and is configured such that the sum of the bias currents is maintained constant. Claim 8 A bidirectional variable gain phase shifter according to claim 5, wherein the first differential amplifier circuit group is controlled through the first and second bias current sources, and the second differential amplifier circuit group is controlled through the third and fourth bias current sources. Claim 9 In claim 8, the control circuit includes a digital-to-analog converter (DAC), and the first, second, third, and fourth bias current sources are set according to the output value of the DAC, a bidirectional variable gain phase shifter. Claim 10 A bidirectional variable gain phase shifter according to claim 1, wherein, during forward operation, the first quadrature signal terminals output a first phase signal (I+), a second phase signal (I-), a third phase signal (Q+), and a fourth phase signal (Q-), respectively, and during reverse operation, the second quadrature signal terminals output a fifth phase signal (I'(+)), a sixth phase signal (I'(-)), a seventh phase signal (Q'(+)), and an eighth phase signal (Q'(-)), respectively, and I'(+) = I+ + Q+, I'(-) = I- + Q-, Q'(+) = I- + Q+, and Q'(-) = I+ + Q-. Claim 11 A bidirectional variable gain phase shifter according to claim 1, further comprising a first transmission line transformer connected to first differential signal terminals. Claim 12 A bidirectional variable gain phase shifter according to claim 1, further comprising a second transmission line transformer connected to second differential signal terminals.

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