Manufacturing Method for SiC Power Semiconductor Devices

Abstract

The present invention relates to a method for flattening the surface of a SiC wafer by a thermal decomposition method, forming high-quality graphene on the surface, and continuously manufacturing a high-quality SiC wafer with an extremely flat surface on the graphene. A method for manufacturing a silicon carbide wafer according to the present invention comprises: (S1) a step of stacking graphene on a wafer containing a first silicon carbide (SiC); (S2) a step of stacking a wafer containing a second silicon carbide (SiC) on the graphene; and (S3) a step of peeling off the wafer containing the second silicon carbide to manufacture a silicon carbide wafer; wherein some or all of the carbon atoms contained in the graphene originate from the carbon contained in the first silicon carbide.

Description

Technology Field

[0001] The present invention relates to a method for flattening the surface of a SiC wafer by a thermal decomposition method, forming high-quality graphene on the surface, and continuously manufacturing a high-quality SiC wafer with an extremely flat surface on the graphene. Background Technology

[0002] SiC wafers have been manufactured using the physical vapor deposition (PVD) method. However, the aforementioned physical vapor deposition method can only be manufactured once within a batch deposition system, and it has disadvantages such as high process costs, slow production speed, and the need for additional etching and polishing processes to control wafer flatness, which leave numerous scratches on the wafer surface, thus hindering the commercialization of SiC wafers. Additionally, a method is currently being used in which bulk SiC is fabricated using the CVD epitaxial method on top of a SiC wafer formed by the physical vapor deposition method and then processed and cut into wafer shapes; however, this processing and cutting method has many problems regarding yield and economic feasibility, such as the original SiC wafer being damaged and discarded during the processing and cutting process. The problem to be solved

[0003] The object of the present invention is to provide a method for manufacturing a high-quality silicon carbide wafer having an extremely flat surface.

[0004] Another objective of the present invention is to provide a method for manufacturing high-quality silicon carbide wafers with an extremely flat surface at low cost.

[0005] Another objective of the present invention is to provide a method for continuously producing high-quality silicon carbide wafers with an extremely flat surface. means of solving the problem

[0006] The present invention provides a method for manufacturing a silicon carbide wafer, wherein the method for manufacturing a silicon carbide wafer comprises: (S1) a step of stacking graphene on a wafer containing a first silicon carbide (SiC); (S2) a step of stacking a wafer containing a second silicon carbide (SiC) on the graphene; and (S3) a step of peeling off the wafer containing the second silicon carbide to manufacture a silicon carbide wafer; wherein some or all of the carbon atoms contained in the graphene are derived from the carbon contained in the first silicon carbide.

[0007] In the method for manufacturing a silicon carbide wafer according to the present invention, the graphene in step (S1) can be produced by thermal decomposition of the first silicon carbide.

[0008] In the method for manufacturing a silicon carbide wafer according to the present invention, the step (S1) may be performed in at least one atmosphere among a carbon gas atmosphere and a silicon gas atmosphere.

[0009] In the method for manufacturing a silicon carbide wafer according to the present invention, the carbon gas atmosphere and the silicon gas atmosphere can each be formed independently by the thermal decomposition of the third silicon carbide.

[0010] In the method for manufacturing a silicon carbide wafer according to the present invention, the step (S1) may be performed under an atmosphere in which the ratio of silicon to carbon in the gas phase is 1:10 to 10:1.

[0011] In the method for manufacturing a silicon carbide wafer according to the present invention, the graphene may be simultaneously peeled off due to the peeling of the wafer containing the second silicon carbide in step (S3).

[0012] In the method for manufacturing a silicon carbide wafer according to the present invention, the graphene after step (S3) may be located on the wafer containing the second silicon carbide.

[0013] In the method for manufacturing a silicon carbide wafer according to the present invention, the deposition of the second silicon carbide in step (S2) can be performed by chemical vapor deposition (CVD).

[0014] In the method for manufacturing a silicon carbide wafer according to the present invention, the chemical vapor deposition may be performed using a gas containing a compound containing carbon atoms and silicon atoms in a 1:1 ratio.

[0015] In the method for manufacturing a silicon carbide wafer according to the present invention, the chemical vapor deposition may be performed using a gas containing methyltrichlorosilane (MTS).

[0016] In a method for manufacturing a silicon carbide wafer according to the present invention, the root mean square roughness (R) of the wafer containing the first silicon carbide after step (S1) measured by an atomic force microscope (AFM) q ) can be 1 to 200 nm.

[0017] In the method for manufacturing a silicon carbide wafer according to the present invention, the Raman spectrum obtained by analyzing the graphene by Raman spectroscopy has a 2D peak, and I d / I g It can be 0.01 to 0.5.

[0018] In the method for manufacturing a silicon carbide wafer according to the present invention, steps (S1) to (S3) may be performed repeatedly. Effects of the invention

[0019] The method for manufacturing a silicon carbide wafer according to the present invention can manufacture a high-quality silicon carbide wafer with an extremely flat surface at a low cost.

[0020] The method for manufacturing a silicon carbide wafer according to the present invention can produce a high-quality silicon carbide wafer with an extremely flat surface at a high yield, low cost, and in an environmentally friendly manner.

[0021] The method for manufacturing a silicon carbide wafer according to the present invention can mass-produce high-quality silicon carbide wafers with an extremely flat surface in a continuous process.

[0022] The method for manufacturing a silicon carbide wafer according to the present invention can transfer the manufactured silicon carbide wafer onto various substrates, thereby enabling a wide range of applications. Brief explanation of the drawing

[0023] FIG. 1 is a drawing illustrating a method for manufacturing silicon carbide according to one embodiment of the present invention and an optical image of silicon carbide manufactured by said method. FIG. 2 is a diagram illustrating the temperature profile of a method for manufacturing silicon carbide according to one embodiment of the present invention. Figure 3 is a drawing showing silicon carbide wafers according to Example 1 (with SiC powder) and Example 2 (without SiC powder) taken using a scanning electron microscope (SEM). Figure 4 is a diagram showing silicon carbide wafers according to Example 1 (right) and Example 2 (left) taken using an atomic force microscope (AFM). Figure 5 is a figure showing the Raman peaks of graphene prepared by the method of preparing silicon carbide wafers according to various temperature profiles, such as Example 1 (with SiC powder), Example 2 (without SiC powder), and Example 3, by Raman spectroscopy. Figure 6 is a diagram showing graphene according to Example 1 (with SiC powder) and Example 2 (without SiC powder) measured using a transmission electron microscope (TEM). Figure 7 is a drawing showing an image of the first silicon carbide wafer after peeling off the additionally deposited wafer using a scanning electron microscope. Figure 8 is a diagram showing an image of the 1 μm additionally deposited wafer taken using a transmission electron microscope. Figure 9 is a schematic diagram and optical image of a process for transferring a CVD SiC deposition layer deposited on graphene onto a SiO2 substrate using the aforementioned PMMA and TRT tapes. FIG. 10 is a schematic diagram illustrating a process for continuously producing silicon carbide wafers by reusing a first silicon carbide wafer. FIG. 11 is a drawing illustrating an optical image of a surface on which transfer has been completed in a method for manufacturing a silicon carbide wafer according to one embodiment of the present invention. Specific details for implementing the invention

[0024] The embodiments described in this specification may be modified in various different forms, and the technology according to one embodiment is not limited to the embodiments described below. Furthermore, the embodiments of one embodiment are provided to more fully explain the present disclosure to those with average knowledge in the relevant technical field. Unless otherwise defined, technical and scientific terms used herein have the meanings commonly understood by those with ordinary knowledge in the technical field to which this invention pertains, and descriptions of known functions and configurations that may unnecessarily obscure the essence of the present invention are omitted in the following description and accompanying drawings.

[0025] Additionally, the singular form used in this specification and the appended claims may be intended to include the plural form unless specifically indicated otherwise in the context.

[0026] Furthermore, in this specification and the appended claims, terms such as "first," "second," etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another.

[0027] Furthermore, in this specification and the appended claims, when a part such as a film (layer), region, or component is described as being located “on,” “on top,” “on the upper,” “under,” “on the lower,” or “on the lower” of another part, this includes not only cases where a part is in contact with another part, but also cases where another part exists between the two parts.

[0028] Furthermore, terms such as “approximately,” “substantially,” etc., as used in this specification and the appended claims, are used to mean at or near the stated value when inherent manufacturing and material tolerances are presented in the said sense, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure in which precise or absolute values ​​are mentioned to aid in understanding this specification and the appended claims.

[0029] Additionally, numeric ranges used in this specification include lower and upper limits and all values ​​within the range, increments logically derived from the shape and width of the defined range, all of which are limited values, and all possible combinations of upper and lower limits of numeric ranges limited in different forms.

[0030] Furthermore, terms such as "include" or "have" in this specification and the appended claims mean that the features or components described in the specification exist, and unless specifically limited, this does not preclude the possibility that one or more other features or components may be added.

[0031] Hereinafter, the method for manufacturing a silicon carbide wafer according to the present invention will be described in detail.

[0032] The present invention provides a method for manufacturing a silicon carbide wafer, wherein the method for manufacturing a silicon carbide wafer comprises: (S1) a step of stacking graphene on a wafer containing a first silicon carbide (SiC); (S2) a step of stacking a wafer containing a second silicon carbide (SiC) on the graphene; and (S3) a step of peeling off the wafer containing the second silicon carbide to manufacture a silicon carbide wafer; wherein some or all of the carbon atoms contained in the graphene are derived from the carbon contained in the first silicon carbide.

[0033] According to one embodiment, the graphene of step (S1) may be produced by thermal decomposition of the first silicon carbide. Specifically, the graphene of step (S1) may be formed on a wafer containing the first silicon carbide by thermal decomposition and removal of silicon atoms (Si) contained in the first silicon carbide (SiC) and recombination of the remaining carbon atoms (C).

[0034] According to one embodiment, step (S1) may be performed in at least one atmosphere among a carbon gas atmosphere and / or a silicon gas atmosphere. The graphene may be produced by thermal decomposition of the first silicon carbide as described above. At this time, silicon atoms are removed due to the thermal decomposition and the remaining carbon forms graphene; however, if the remaining carbon is present in excess, the excess remaining carbon may adhere to the surface in the form of graphite and / or graphite, which may hinder the smooth production of graphene with a uniform surface. Therefore, step (S1) may be a step in which the concentration of the gaseous silicon atmosphere and / or gaseous carbon atmosphere is controlled under sealed conditions and the graphene is stacked. The atmosphere under sealed conditions may refer to a gaseous silicon atmosphere, a gaseous carbon atmosphere, or a gaseous silicon and carbon atmosphere. The carbon gas and silicon gas mentioned above do not refer only to vaporized carbon and silicon, and may be controlled such that various phases, such as solid, liquid, gaseous, and / or plasma, are controlled to prevent the generation of excess residual carbon during the graphene formation process, thereby controlling the generation of excess residual carbon on the wafer containing the first silicon carbide.

[0035] According to one embodiment, the carbon gas atmosphere and / or the silicon gas atmosphere may each be formed independently by the thermal decomposition of the third silicon carbide. The carbon gas atmosphere and / or the silicon gas atmosphere may be generated by further introducing the third silicon carbide under the sealed conditions and thermally decomposing the third silicon carbide. In this case, to facilitate the thermal decomposition, the third silicon carbide may be introduced under the sealed conditions in the form of a plurality of solid particles and thermally decomposed.

[0036] According to one embodiment, the step (S1) may be performed under an atmosphere in which the ratio of silicon to carbon in the gaseous phase is between any two values ​​including 1:10 to 10:1 and the above range. The ratio of the silicon to carbon atmosphere in the step (S1) is selected from the above-described range so that the silicon (Si) in the gaseous phase generated by the thermal decomposition of the SiC powder during the thermal decomposition process is filled inside the crucible, thereby effectively controlling the thermal decomposition of Si of the first silicon carbide wafer.

[0037] According to one embodiment, the graphene may be simultaneously peeled off due to the peeling of the wafer containing the second silicon carbide in step (S3). After the wafer containing the second silicon carbide in step (S2) is stacked on the graphene, when the wafer containing the second silicon carbide is peeled off in step (S3), the bonding force or adhesion force between the wafer containing the second silicon carbide and the graphene is stronger than the bonding force or adhesion force between the wafer containing the first silicon carbide and the graphene, so that when the wafer containing the second silicon carbide is peeled off, the graphene may also be peeled off together with the wafer containing the second silicon carbide. Accordingly, the graphene after step (S3) may be located on the wafer containing the second silicon carbide, and the wafer containing the first silicon carbide may again be able to repeatedly perform steps (S1) through (S3).

[0038] According to one embodiment, the deposition of the second silicon carbide in step (S2) may be performed by chemical vapor deposition (CVD). The second silicon carbide may be deposited by a chemical vapor deposition method using a gas commonly used in the art for the deposition of silicon carbide.

[0039] According to one embodiment, the gas used for the chemical vapor deposition may be a gas comprising a compound containing carbon atoms and silicon atoms in a 1:1 ratio. By using such a gas, the reaction of the gas used for the chemical vapor deposition with the graphene during the performance of the chemical vapor deposition can be mitigated, and the graphene can be prevented from decomposing and / or being removed. Furthermore, by using such a gas, the graphene is not decomposed and / or removed even during the performance of the chemical vapor deposition, so that the second silicon carbide does not come into direct contact with and bond with the first silicon carbide. Therefore, during the peeling of step (S3), the wafer containing the second silicon carbide can be easily peeled off simultaneously with the graphene. Additionally, by using such a gas, the wafer containing the first silicon carbide can have an extremely flat surface after performing step (S1), as described below.

[0040] As a non-limiting example, the chemical vapor deposition may be performed using a gas containing methyltrichlorosilane (MTS).

[0041] According to one embodiment, the root mean square roughness (R) of the wafer containing the first silicon carbide after step (S1) measured by an atomic force microscope (AFM) q ) can be 1 to 200 nm.

[0042] The wafer containing the first silicon carbide performs step (S1), and the silicon atoms and carbon atoms located on the surface of the first silicon carbide are each thermally decomposed and simultaneously converted into graphene. Due to the thermal decomposition and the generation of graphene resulting from the performance of step (S1), the wafer containing the first silicon carbide may have surface irregularities removed and an extremely flat surface.

[0043] Root mean square roughness (R) of the wafer containing the first silicon carbide after step (S1) above, measured by an atomic force microscope (AFM). q ) may be 0.1 nm or more, 0.5 nm or more, 1 nm or more, 2 nm or more, or 5 nm or more, and as an upper limit, may be 200 nm or less, 100 nm or less, 50 nm or less, 20 nm or less, or 10 nm or less. Specifically, the root mean square roughness (R) of the wafer containing the first silicon carbide after step (S1) measured by an atomic force microscope (AFM) q ) may be 0.1 to 200 nm, 0.5 to 100 nm, 1 to 50 nm, 2 to 20 nm, or 5 to 10 nm. The wafer containing the first silicon carbide after step (S1) has the surface roughness described above, which improves the crystallinity and / or area of ​​the graphene, and can produce a wafer containing high-quality graphene and second silicon carbide with a flatter surface roughness than when step (S1) is performed again after step (S3).

[0044] According to one embodiment, the Raman spectrum obtained by analyzing the graphene by Raman spectroscopy has a 2D peak, and Id / I g The value may be between 0.01 and 0.5 or between any two values ​​listed herein. The graphene produced by the method for manufacturing a silicon carbide wafer of the present invention is a highly crystalline graphene with significantly fewer defects that satisfies the peak ratio described above, and at the same time, the wafer containing the first silicon carbide may be extremely flat and the peeling of step (S3) may be easy.

[0046] Examples and experimental examples are described below with specific examples. However, the examples and experimental examples described below are merely illustrative of some aspects, and the technology described in this specification is not limited thereto.

[0048] (Example 1)

[0049] As shown in Fig. 1, a 4H SiC wafer (first silicon carbide wafer) and SiC powder were placed inside a graphite crucible, and then the graphite crucible was sealed. The air inside the graphite crucible was removed using a vacuum pump to 10 -3 After forming a vacuum of Torr, argon (Ar) was purged three times to make the inside of the graphite crucible an argon atmosphere of 760 Torr.

[0050] Graphene was grown on the SiC wafer by thermal decomposition of the SiC wafer and SiC powder. The thermal decomposition was performed with a temperature profile as shown in Fig. 2.

[0051] A SiC wafer (second silicon carbide wafer) was deposited on the above graphene using the chemical vapor deposition (CVD) method.

[0052] Poly(methyl methacrylate) (PMMA, 4science, product name 950 PMMA A6) was applied to a thickness of 500 nm on the second silicon carbide wafer and then heated and cured at 100°C to deposit a PMMA layer. After attaching a thermal release tape (TRT) to the PMMA layer, the second silicon carbide wafer and the graphene were peeled together. Subsequently, the graphene was removed by oxygen plasma treatment, and the thermal release tape and PMMA layer were removed by heat treatment at 100°C and the application of acetone, respectively, to produce a silicon carbide wafer.

[0054] (Example 2)

[0055] In Example 1, a silicon carbide wafer was manufactured in the same manner as in Example 1, except that SiC powder was not introduced into the graphite crucible.

[0057] (Example 3)

[0058] In Example 1, a silicon carbide wafer was manufactured in the same manner as in Example 1, except that the temperature profile during the pyrolysis process was heated to 1400°C at a heating rate of 10°C, heat-treated at the highest temperature for 60 minutes, cooled to 1200°C at a rate of 20°C / min, and heated at 1200°C for 30 minutes to perform pyrolysis.

[0060] (Comparative Example 1)

[0061] Comparative example of depositing a second silicon carbide by performing CVD using silane instead of MTS

[0063] (Experimental Example 1)

[0064] Silicon carbide wafers according to Example 1 (Fig. 3 with SiC powder, right side of Fig. 4) and Example 2 (Fig. 3 without SiC powder, left side of Fig. 4) were photographed using a scanning electron microscope (SEM) and an atomic force microscope (AFM) and are shown in Figs. 3 and 4, respectively. R of the silicon carbide wafers according to Example 1 and Example 2 photographed by an atomic force microscope a The values ​​were confirmed to be 2.2 nm and 3.2 nm, respectively. In addition, the silicon carbide wafer according to Example 3, with a lowered pyrolysis temperature (1400℃), R a Graphene could be obtained on a very flat SiC wafer with a value of 1.04 nm.

[0065] Referring to FIGS. 3 and 4, it was confirmed that the surface roughness of the silicon carbide wafer manufactured by the method according to Example 1 is flatter. This is believed to be an effect resulting from the fact that the specific surface area of ​​the SiC powder introduced in Example 1 is higher than that of the first silicon carbide wafer, and the silicon (Si) in the gaseous phase generated by the thermal decomposition of the SiC powder during the thermal decomposition process is filled inside the graphite crucible, thereby effectively controlling the thermal decomposition of Si in the first silicon carbide wafer.

[0067] (Experimental Example 2)

[0068] Raman peaks of graphene according to the silicon carbide wafer manufacturing method of Example 1 (with SiC powder) and Example 2 (without SiC powder) were investigated using Raman spectroscopy and are shown in Fig. 5.

[0069] Referring to FIG. 5, the graphene according to Examples 1 and 2 had G peaks and 2D peaks, and at 1,350 cm⁻¹ -1Since there is no D peak generated in, it was confirmed that the graphene according to Examples 1 and 2 exhibits defect-free, high-quality crystallinity.

[0070] However, it was confirmed that the graphene produced by the method according to Example 3 did not have G-peaks or 2D peaks. It was confirmed that there is an appropriate temperature for the thermal decomposition of the first silicon carbide wafer and graphene nucleation, and that the temperature exceeds 1500℃.

[0071] The Raman peaks of graphene according to the manufacturing method of silicon carbide wafers performed at different heat treatment temperatures are shown in Figure 5. Referring to Figure 5, it can be seen that the critical temperature for graphene formation is 1400°C when SiC powder is not included, and it was confirmed that the critical temperature for graphene formation is 1650°C when SiC is added. This is interpreted to be because when SiC powder is added to the crucible, the Si / C ratio inside the crucible increases, thereby raising the temperature required for Si to thermally decompose and evaporate from the surface of the SiC wafer. As can be seen in Figure 5, it can be seen that graphene is not formed on the surface of the SiC wafer when thermal decomposition is performed with the addition of SiC powder at 1600°C, but it was confirmed that graphene is formed when the temperature is raised by 50°C for thermal decomposition.

[0073] (Experimental Example 3)

[0074] Graphene according to Example 1 (with SiC powder) and Example 2 (without SiC powder) was measured using a transmission electron microscope (TEM) and is shown in Fig. 6.

[0075] Referring to Fig. 6, it can be seen that graphene according to Example 2 has nearly 20 layers, and it was confirmed that graphene according to Example 1 has about 10 layers of graphene formed by controlling the number of layers of the graphene.

[0077] (Experimental Example 4)

[0078] In Example 1, after peeling off a silicon carbide wafer, a silicon carbide wafer (additional deposition wafer) was prepared on the first silicon carbide using the same method according to Example 1 and peeled off. At this time, the peeling pattern according to different thicknesses of the additional deposition wafer was investigated.

[0079] An image of the first silicon carbide wafer after peeling off the additional deposition wafer was taken using a scanning electron microscope and is shown in Fig. 7. The left image of Fig. 7 shows that the thickness of the additional deposition wafer was 5 μm, and the right image of Fig. 7 shows that the thickness of the additional deposition wafer was 1 μm. Referring to Fig. 7, it was confirmed that the shape of the peeling off of the deposited SiC layer differed depending on the thickness of the additional deposition wafer. It was confirmed that when the thickness of the additional deposition wafer was relatively thick, there were parts that were not peeled off, whereas when the thickness of the additional deposition wafer was controlled to within 1 μm, it was peeled off completely.

[0080] An image of the 1 μm additional deposition wafer was taken using a transmission electron microscope and is shown in Fig. 8. Referring to Fig. 8, it was confirmed that graphene was attached to the peeled additional deposition wafer and peeled off.

[0082] (Experimental Example 5)

[0083] Figure 9 shows a schematic diagram and optical image of the process of transferring a CVD SiC deposition layer deposited on graphene onto a SiO2 substrate using the previously mentioned PMMA and TRT tapes.

[0084] In addition, a schematic diagram of a process for continuously producing silicon carbide wafers by reusing the first silicon carbide wafer is shown in FIG. 10. The bottom image of FIG. 10 shows the cross-sectional shape of CVD SiC deposited on graphene. Also, the right side shows that the SiC layer deposited on graphene can be peeled off using only a simple tape.

[0086] (Experimental Example 6)

[0087] PMMA is applied onto CVD SiC and spin-coated (600–3,000 rpm, 60 seconds) to uniformly deposit the PMMA. Subsequently, the specimen is placed on a 200-degree hot plate to cure and solidify the PMMA. Afterward, when a thermal release tape (TRT) is attached to the cured PMMA, the TRT tape exhibits excellent contact with the PMMA surface. Furthermore, since the PMMA is initially applied to the CVD SiC layer in a liquid state, the contact between the PMMA and the CVD SiC is also excellent. In contrast, the contact at the heterogeneous interface between the CVD SiC layer and the graphene becomes relatively weak. Due to these characteristics, when the TRT tape is removed, the CVD SiC layer detaches along with the PMMA due to the graphene exfoliation properties. The detached TRT tape is then reattached to SiO2, and heat treatment is performed on a hot plate; this causes the TRT tape and PMMA to detach, and the remaining CVD SiC is successfully transferred onto the SiO2. An optical image of the surface after the transfer was completed is shown in Fig. 11.

[0089] As described above, the present invention has been explained in this specification by specific details and limited embodiments, but this is provided only to aid in a more comprehensive understanding of the invention, and the invention is not limited to the above embodiments. A person skilled in the art to which the invention pertains can make various modifications and variations from this description. Accordingly, the concept described in this specification should not be limited to the described embodiments, and all things equivalent to or having equivalent variations to the claims set forth below, as well as the claims themselves, shall be considered to fall within the scope of the concept described in this specification.

Claims

Claim 1 (S1) a step of stacking graphene on a wafer containing first silicon carbide (SiC); (S2) a step of stacking a wafer containing second silicon carbide (SiC) on the graphene; and (S3) a step of peeling off the wafer containing second silicon carbide to produce a silicon carbide wafer; wherein some or all of the carbon atoms contained in the graphene are derived from the carbon contained in the first silicon carbide, and the step (S1) is performed in a carbon gas atmosphere and a silicon gas atmosphere, and the carbon gas atmosphere and the silicon gas atmosphere are formed by the thermal decomposition of a third silicon carbide introduced in the form of a plurality of solid particles under sealed conditions. Claim 2 A method for manufacturing a silicon carbide wafer, wherein the graphene in step (S1) is produced by thermal decomposition of the first silicon carbide. Claim 3 delete Claim 4 delete Claim 5 A method for manufacturing a silicon carbide wafer according to claim 1, wherein the step (S1) is performed in an atmosphere in which the ratio of silicon to carbon in the gas phase is 1:10 to 10:

1. Claim 6 A method for manufacturing a silicon carbide wafer according to claim 1, wherein the graphene is simultaneously peeled off due to the peeling of the wafer containing the second silicon carbide in step (S3). Claim 7 A method for manufacturing a silicon carbide wafer according to claim 1, wherein the graphene after step (S3) is located on a wafer containing the second silicon carbide. Claim 8 A method for manufacturing a silicon carbide wafer according to claim 1, wherein the deposition of the second silicon carbide in step (S2) is performed by a chemical vapor deposition (CVD) method. Claim 9 A method for manufacturing a silicon carbide wafer according to claim 8, wherein the chemical vapor deposition is performed using a gas containing a compound containing carbon atoms and silicon atoms in a 1:1 ratio. Claim 10 A method for manufacturing a silicon carbide wafer according to claim 8, wherein the chemical vapor deposition is performed using a gas containing methyltrichlorosilane (MTS). Claim 11 In claim 1, the root mean square roughness (R) of the wafer containing the first silicon carbide after step (S1) measured by an atomic force microscope (AFM). q A method for manufacturing a silicon carbide wafer having a thickness of 1 to 200 nm. Claim 12 In claim 1, the Raman spectrum obtained by analyzing the graphene by Raman spectroscopy has a 2D peak, and I d / I g A method for manufacturing a silicon carbide wafer having a value of 0.01 to 0.

5. Claim 13 A method for manufacturing a silicon carbide wafer, wherein steps (S1) to (S3) can be repeated in claim 1. Claim 14 delete Claim 15 delete

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