Semiconductor Device, Apparatus and Method of Inspecting The Same

Abstract

The present invention relates to a semiconductor device capable of accurately detecting defects using a plurality of resistance circuits in an inspection process, and to an inspection device and method thereof. An inspection device of a semiconductor device according to one aspect may include each semiconductor chip having a plurality of external resistance circuits distributed along the outer region of the chip for crack inspection and an internal resistance circuit disposed in the inner region of the chip; and an inspection device that, in an inspection process, drives the plurality of external resistance circuits and the internal resistance circuits and detects whether a defect has occurred in each semiconductor chip by comparing the output of each of the plurality of external resistance circuits with the output of the internal resistance circuit.

Description

Technology Field

[0001] The present invention relates to a semiconductor device capable of electrically detecting defects in an inspection process, and to an inspection device and method thereof. Background Technology

[0002] Semiconductor chips are formed by performing a plurality of unit processes on a silicon wafer. The semiconductor chips formed in each semiconductor chip area on the silicon wafer are spaced apart at regular intervals with a scribe lane in between.

[0003] When the semiconductor chip manufacturing process is finished, a dicing process is carried out to separate the semiconductor chips by cutting the wafer along the centerline of the scribe lane in order to package the semiconductor chips individually.

[0004] However, during the dicing or handling process of cutting silicon wafers, crack defects may occur where cracks develop on the cut surface and outer edge of the semiconductor chip due to external physical forces and spread to the semiconductor chip area.

[0005] Since crack defects in semiconductor chips lead to operational failures and reliability issues, a method is required to accurately detect various chip defects, including crack defects, during the inspection process. The problem to be solved

[0006] The present invention provides a semiconductor device capable of accurately detecting defects using a plurality of resistance circuits in an inspection process, and a crack inspection device and method thereof. means of solving the problem

[0007] A semiconductor device according to one aspect of the present invention includes a plurality of external resistance circuits distributed along a chip outer region, each of the plurality of external resistance circuits may include an external resistance structure disposed within the chip outer region and comprising at least one of a diffusion layer, a polysilicon layer, and a wiring layer, an external transistor connected to the external resistance structure, and a first test pad disposed in a chip pad region and connected to the external transistor through the external resistance structure. In a test process, each of the plurality of external resistance circuits may reflect a change in the resistance value of the external resistance structure due to a defect in the current of the external transistor and output it through the first test pad.

[0008] A semiconductor device according to one aspect of the present invention may further include an internal resistance circuit disposed in an internal region of the chip. The internal resistance circuit may include an internal resistance structure disposed in an internal region of the chip and comprising at least one of a diffusion layer, a polysilicon layer, and a wiring layer, an internal transistor connected to the internal resistance structure, and a second test pad disposed in a chip pad region and connected to the internal transistor through the internal resistance structure.

[0009] An inspection device for a semiconductor device according to one aspect of the present invention may include each semiconductor chip having a plurality of external resistance circuits distributed along the outer region of the chip for crack inspection and an internal resistance circuit disposed in the inner region of the chip; and an inspection device that, in an inspection process, drives the plurality of external resistance circuits and the internal resistance circuits and detects whether a defect has occurred in each semiconductor chip by comparing the output of each of the plurality of external resistance circuits with the output of the internal resistance circuit.

[0010] An inspection device for a semiconductor device according to one aspect of the present invention may include each semiconductor chip having a plurality of external resistance circuits distributed along the outer region of the chip; and an inspection device that, in an inspection process, drives the plurality of external resistance circuits and compares the outputs of each of the plurality of external resistance circuits with one another or with a predetermined reference value to detect whether a defect has occurred in each semiconductor chip.

[0011] A method for inspecting a semiconductor device according to one aspect of the present invention may include the steps of: separating each of a plurality of semiconductor chips, each having a plurality of external resistance circuits distributed along the outer region of the chip and an internal resistance circuit disposed in the inner region of the chip, through a dicing process; driving the plurality of external resistance circuits and the internal resistance circuits of each semiconductor chip in the inspection process, and comparing the output of each of the plurality of external resistance circuits with the output of the internal resistance circuit; and determining that a crack has occurred in the semiconductor chip if an output among the outputs of the plurality of external resistance circuits is detected that is outside the allowable range relative to the output of the internal resistance circuit.

[0012] A method for inspecting a semiconductor device according to one aspect of the present invention may include the step of separating each of a plurality of semiconductor chips, each having a plurality of external resistance circuits distributed along the outer region of the chip, through a dicing process; the step of driving the plurality of external resistance circuits of each semiconductor chip in the inspection process and comparing the outputs of each of the plurality of external resistance circuits with one another or with a predetermined reference value; and the step of determining that a crack has occurred in the semiconductor chip if an output among the outputs of the plurality of external resistance circuits is detected that is outside the allowable range compared to other outputs or the reference value. Effects of the invention

[0013] A semiconductor device and its inspection device and method according to one aspect of the present invention can accurately detect the occurrence of a defect from an external resistance circuit having an output (performance) that deviates from an allowable range relative to a reference by comparing the outputs (performances) of a plurality of external resistance circuits distributed in the outer region of a semiconductor chip during an inspection process with each other, or by comparing the outputs (performances) of a plurality of external resistance circuits with a reference output (performance) of an internal resistance circuit or a predetermined reference value, and can also detect the location of the defect.

[0014] Accordingly, a semiconductor device and its inspection device and method according to one aspect of the present invention can improve the reliability of a semiconductor chip by accurately detecting defects and defect locations of the semiconductor chip during an inspection process and preventing quality accidents. Brief explanation of the drawing

[0015] FIGS. 1a and FIGS. 1b are drawings showing a semiconductor wafer on which semiconductor chips are arranged according to one embodiment. FIG. 2 is a schematic diagram showing a semiconductor chip having external and internal resistance circuits and an inspection device thereof according to one embodiment. FIG. 3 is a schematic diagram showing a semiconductor chip having an external resistance circuit according to one embodiment and an inspection device thereof. FIG. 4 is an equivalent circuit diagram showing a semiconductor chip inspection device according to one embodiment. FIG. 5 is a cross-sectional view showing the external resistance circuit structure of a semiconductor chip according to one embodiment. FIG. 6 is a cross-sectional view showing the external resistance circuit structure of a semiconductor chip according to one embodiment. FIG. 7 is a cross-sectional view showing the external resistance circuit structure of a semiconductor chip according to one embodiment. FIG. 8 is a cross-sectional view showing the external resistance circuit structure of a semiconductor chip according to one embodiment. FIG. 9 is a cross-sectional view showing the external resistance circuit structure of a semiconductor chip according to one embodiment. FIG. 10 is a cross-sectional view showing the structure of external resistance circuits of a semiconductor chip according to one embodiment. FIG. 11 is a cross-sectional view showing the structure of external resistance circuits of a semiconductor chip according to one embodiment. FIG. 12 is a cross-sectional view showing the structure of external resistance circuits of a semiconductor chip according to one embodiment. Specific details for implementing the invention

[0016] Throughout the specification, identical reference numbers denote substantially identical components. In the following description, detailed descriptions of components and functions known in the art may be omitted if they are not related to the core components of the invention. The meanings of the terms described in this specification should be understood as follows.

[0017] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0018] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0019] Where terms such as "includes," "has," "consists of," etc. are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise.

[0020] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0021] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using "after," "following," "next," "after," "before," etc., it may include cases where the sequence is not continuous unless "immediately" or "directly" is used.

[0022] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0023] In describing components in this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish a component from other components, and the nature, order, sequence, or number of such components are not limited by these terms. Where it is stated that a component is "connected," "combined," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may also be "interposed" between each component that may be indirectly connected or joined unless specifically stated otherwise.

[0024] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0025] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0026] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings.

[0027] FIG. 1a is a plan view showing a semiconductor wafer (1) on which semiconductor chips are formed according to one embodiment, and FIG. 1b is a plan view showing an enlarged portion (10) of the semiconductor wafer (1) shown in FIG. 1a.

[0028] Referring to FIGS. 1a and 1b, semiconductor chips (100) formed through a semiconductor manufacturing process are arranged in a matrix form on a semiconductor wafer (1). Each of the semiconductor chips (100) is formed in a semiconductor chip area on the semiconductor wafer (1) and is spaced apart at equal intervals with a Scribe Lane (30) of a certain width that extends in the horizontal and vertical directions and is orthogonal.

[0029] Each semiconductor chip (100) is provided with a circuit portion inside, and a plurality of pads connected to the internal circuit are arranged in an exposed structure for electrical connection with an external circuit in the outer region of each semiconductor chip (100).

[0030] When semiconductor chips (100) are completed on a semiconductor wafer (1) through a manufacturing process, a dicing process is performed to cut the semiconductor wafer (1) along the center lines (20) of the scribe lane (30), namely the horizontal center lines (20a) and the vertical center lines (20b), thereby separating the semiconductor chips (100) individually.

[0031] In the inspection process after dicing, the inspection equipment can electrically and accurately detect whether a chip defect has occurred and the location of the defect by using a plurality of resistance circuits distributed in the outer region of the semiconductor chip (100) according to one embodiment to detect a change in resistance caused by the occurrence of various defects including chip cracks.

[0032] FIG. 2 is a schematic diagram showing a semiconductor chip having external and internal resistance circuits according to one embodiment and an inspection device thereof, and FIG. 3 is a schematic diagram showing a semiconductor chip having an external resistance circuit according to one embodiment and an inspection device thereof.

[0033] Referring to FIG. 2, a semiconductor chip (100) according to one embodiment may include a plurality of external resistor circuits (120) distributed along the outer region of the chip for defect inspection, and an internal resistor circuit (110) disposed in the inner region of the chip. Since the internal resistor circuit (110) is intended to provide a reference to the external resistor circuits (120) during defect inspection, it may be defined as a reference resistor circuit. Each external resistor circuit (120) and the internal resistor circuit (110) may have equivalent or similar resistance values.

[0034] A plurality of external resistance circuits (120) may be distributed along the outer edge of the chip surrounding the pad area where the pads (130) connected to the internal circuit of the semiconductor chip (100) are located. In other words, on the semiconductor wafer (1, FIG. 1a), the external resistance circuits (120) of each semiconductor chip (100) may be placed between the pad area of ​​each semiconductor chip (100) and the scribe lane (30, FIG. 1b).

[0035] For example, 12 external resistor circuits (120) can be arranged in a structure separated from each other in four outer regions of a square semiconductor chip (100).

[0036] Each of the external resistance circuits (120) independently positioned within the outer region of the chip can be connected to any one of the pads (130) located in the pad region (first test pad). The internal resistance circuit (110) can be connected to another pad (second test pad) among the pads (130) located in the pad region.

[0037] In the inspection process after dicing, the inspection equipment (50) can detect whether a chip defect has occurred and the location of the defect by measuring and comparing the output of each of the external resistance circuits (120) of the semiconductor chip (100) shown in FIG. 2 with the reference output of the internal resistance circuit (110). When the inspection equipment (50) detects an external resistance circuit (120) having an abnormal output that is outside the allowable range relative to the reference output of the internal resistance circuit (100), it determines that a chip defect has occurred and can also detect the location where the external resistance circuit (12) is placed as the location of the defect.

[0038] Meanwhile, a semiconductor chip (100a) according to one embodiment includes a plurality of external resistance circuits (120) distributed along the outer region of the chip for inspection as shown in FIG. 3, and an internal resistance circuit (110) shown in FIG. 2 may be omitted.

[0039] In the inspection process after dicing, the inspection equipment (50) can detect whether a defect has occurred and the location of the defect by comparing the outputs of each of the external resistance circuits (120) of the semiconductor chip (100a) shown in FIG. 3. When the inspection equipment (50) detects an external resistance circuit (120) that has an abnormal output that is outside the allowable range compared to other outputs among the outputs of the external resistance circuits (120), it determines that a defect has occurred and can also detect the location where the external resistance circuit (120) is placed as the location of the defect.

[0040] In contrast, the inspection equipment (50) can detect whether a defect has occurred and the location of the defect by comparing the output of each external resistance circuit (120) of the semiconductor chip (100a) shown in FIG. 3 with a reference value. The reference value may be a simulation value determined during the chip design process or an output value measured from an undamaged external resistance circuit (120) prior to dicing. When the inspection equipment (50) detects an external resistance circuit (120) having an abnormal output that is outside the allowable range relative to the reference value among the outputs of the external resistance circuits (120), it determines that a defect has occurred and can also detect the location where the external resistance circuit (12) is placed as the location of the defect.

[0041] FIG. 4 is an equivalent circuit diagram showing a semiconductor chip inspection device according to one embodiment.

[0042] Referring to FIG. 4, each external resistance circuit (120) embedded in the semiconductor chip (100) includes an external resistance structure (R2) comprising at least one of a semiconductor diffusion layer, a polysilicon layer, and a metal layer disposed inside the outer region of the chip, and an external transistor (T2) connected to a first test pad (122) through the external resistance structure (R2). The external resistance structures (R2) of the external resistance circuits (120) may be formed to have the same or similar resistance values, and the external transistors (T2) may be formed to have the same or similar performance.

[0043] The gate electrode (G) of the external transistor (T2) receives a control signal (Vin) for the high potential power supply of the internal circuit of the semiconductor chip (100), the first source / drain electrode (SD1) is connected to the low potential power supply (Vss) of the internal circuit, and the second source / drain electrode (SD2) is connected to the first test pad (122) via the external resistor structure (R2). The first test pad (122) receives a high potential power supply voltage (Vdd) from the test equipment (50) and supplies it to the external transistor (T2) through the external resistor structure (R2), and the test equipment (50) is used as a terminal to measure the output of the external resistor circuit (120) which is proportional to the performance of the external transistor (T2).

[0044] An internal resistance circuit (110) embedded in a semiconductor chip (100) may be positioned in an internal region that is located inside the pad area of ​​the semiconductor chip (100) and is not subject to crack damage. The internal resistance circuit (110) includes an internal resistance structure (R1) comprising at least one of a semiconductor diffusion layer, a polysilicon layer, and a metal layer, and an internal transistor (T1) connected to a second test pad (112) via the internal resistance structure (R1). The internal resistance structure (R1) of the internal resistance circuit (110) may be formed to have a resistance value identical or similar to that of the external resistance structure (R2) of the external resistance circuit (120), and the internal transistor (T1) may be formed to have performance identical or similar to that of the external transistor (T2).

[0045] The gate electrode (G) of the internal transistor (T1) receives a control signal (Vin) for the high potential power supply of the internal circuit of the semiconductor chip (100), the first source / drain electrode (SD1) is connected to the low potential power supply (Vss) of the internal circuit, and the second source / drain electrode (SD2) is connected to the second test pad (112) via the internal resistance structure (R1). The second test pad (112) receives a high potential power supply voltage (Vdd) from the test equipment (50) and supplies it to the internal transistor (T1) through the internal resistance structure (R1), and the test equipment (50) is used as a terminal to measure the output of the internal resistance circuit (110) which is proportional to the performance of the internal transistor (T1).

[0046] In the inspection process after dicing, the inspection equipment (50) applies power to the semiconductor chip (100) to apply a gate-on voltage control signal (Vin) and a low-potential power supply (Vss) to the internal transistor (T1) and the external transistor (T2), and by applying a high-potential power supply (Vdd) to the first inspection pad (122) and the second inspection pad (112), the internal transistor (T1) and the external transistor (T2) are turned on. The inspection equipment (50) measures the output of each external resistance circuit (120) through the first inspection pad (122) and measures the output of the internal resistance circuit (110) through the second inspection pad (122). By comparing the output of each external resistance circuit (120) with the output of the internal resistance circuit (110), it is possible to detect whether a defect has occurred and the location of the defect.

[0047] For example, if a crack defect occurs in an external resistance structure (R2) comprising at least one of a semiconductor diffusion layer, a polysilicon layer, and a metal layer disposed within the outer region of a semiconductor chip (100) due to an external physical force, the resistance value of the external resistance structure (R2) increases during the inspection process, and the voltage drop of the high potential power supply (Vdd) increases, thereby reducing the amount of current flowing through the external transistor (T2) and degrading the performance of the external transistor (T2). As a result, the output signal (amount of current) of the external resistance circuit (120) measured through the first inspection pad (122) decreases.

[0048] The inspection equipment (50) compares the output signal of the external resistance circuit (120) with the output signal of the internal resistance circuit (110), and if the external resistance circuit (120) is detected to have an abnormal output below the allowable range relative to the output signal of the internal resistance circuit (100), it determines that a defect has occurred and can also detect the location where the external resistance circuit (12) is placed as the location where the defect occurred.

[0049] Meanwhile, in the case where only external resistance circuits (120) are provided without an internal resistance circuit, such as the semiconductor chip (100a) shown in FIG. 3, the inspection equipment (50) compares the outputs of each of the external resistance circuits (120) with one another and, if an external resistance circuit (120) having an abnormal output below the allowable range compared to other outputs is detected, determines that a defect has occurred and can also detect the location where the external resistance circuit (120) is placed as the location where the defect occurred.

[0050] In contrast, the inspection equipment (50) compares the output of each of the external resistance circuits (120) with a reference value, and if an external resistance circuit (120) having an abnormal output below the allowable range relative to the reference value is detected, it determines that a defect has occurred and also detects the location where the external resistance circuit (120) is placed as the location where the defect occurred.

[0051] Since the semiconductor chip (100) in which a defect is detected is determined to be a defective chip and discarded, quality accidents can be prevented.

[0052] FIGS. 5 to 12 are cross-sectional views showing various external resistance circuit structures of a semiconductor chip according to one embodiment.

[0053] Referring to FIG. 5, an external resistance circuit of a semiconductor chip according to one embodiment may include a transistor comprising a gate insulating film (204), a gate electrode (206), a source electrode (212), and a drain electrode (214) disposed on a semiconductor substrate (200), and a resistance structure comprising an impurity diffusion layer, a polysilicon layer (208), and a plurality of metal wiring layers (216, 222, 232, 242, 252) connected to the transistor.

[0054] Each device region of the semiconductor substrate (200) is electrically separated by an insulating structure (202). The gate electrode (206) overlaps with the channel region of the corresponding device region of the semiconductor substrate (200) with the gate insulating film (204) in between. The source electrode (212) and the drain electrode (214) on the interlayer insulating film (210) are each connected to the diffusion layer doped with impurities in the corresponding device region of the semiconductor substrate (200) through contact plugs (211, 213) formed within the contact holes of the interlayer insulating film (210).

[0055] Among the resistance structures, the polysilicon layer (208) is disposed on the insulating structure (203) of the semiconductor substrate (200) and is connected to the drain electrode (214) through one contact plug (215) formed within the interlayer insulating film (210), and is connected to the lowest metal wiring layer (216) on the interlayer insulating film (210) through another contact plug (217).

[0056] Among the resistance structures, a plurality of metal wiring layers (216, 222, 232, 242, 252) are each disposed on a plurality of interlayer insulating films (210, 220, 230, 240, 250) and can be connected to adjacent wiring layers above and below through contact plugs (221, 231, 241, 251) each formed in contact holes of the plurality of interlayer insulating films (220, 230, 240, 250). The plurality of metal wiring layers (216, 222, 232, 242, 252) can overlap each other and can be disposed to overlap at least a portion of the polysilicon layer (280). The uppermost metal wiring layer (252) can be exposed through a pad hole (262) penetrating the passivation layer (260) and used as an inspection pad.

[0057] Referring to FIG. 6, an external resistance circuit of a semiconductor chip according to one embodiment may include a transistor comprising a gate insulating film (204a), a gate electrode (206a), a source electrode (212a), and a drain electrode (214a) disposed on a semiconductor substrate (200), a diffusion layer connected to the transistor, and a resistance structure comprising a plurality of metal wiring layers (214a, 222a, 232a, 242a, 252a).

[0058] A gate electrode (206a) is disposed on the channel region of the corresponding device region separated by an insulating structure (202a) of the semiconductor substrate (200), with a gate insulating film (204a) in between. The source electrode (212a) and the drain electrode (214a) disposed on the interlayer insulating film (210) are each connected to the diffusion layer of the corresponding device region of the semiconductor substrate (200) through contact plugs (211a, 213a) formed within the contact holes of the interlayer insulating film (210).

[0059] Among the resistor structures, a plurality of metal wiring layers (214a, 222a, 232a, 242a, 252a) are each disposed on a plurality of interlayer insulating films (210, 220, 230, 240, 250) and can be connected to adjacent wiring layers above and below through contact plugs (221a, 231a, 241a, 251a) formed in contact holes of the plurality of interlayer insulating films (220, 230, 240, 250). The plurality of metal wiring layers (214a, 222a, 232a, 242a, 252a) can overlap each other and can be connected in series through contact plugs (221a, 231a, 241a, 251a). Multiple metal wiring layers (222a, 232a, 242a, 252a) may be arranged to overlap with the drain electrode (214a) of the transistor. The uppermost metal wiring layer (252a) may be exposed through a pad hole (262a) penetrating the passivation layer (260) and used as a test pad.

[0060] Referring to FIG. 7, an external resistance circuit of a semiconductor chip according to one embodiment may include a transistor comprising a gate insulating film (204b), a gate electrode (206b), a source electrode (212b), and a drain electrode (214b) disposed on a semiconductor substrate (200), and a resistance structure comprising a diffusion layer, a polysilicon layer (208b), and a plurality of metal wiring layers (216b, 222b, 232b, 242b, 252b) connected to the transistor.

[0061] A gate electrode (206b) is disposed on the channel region of the corresponding device region separated by an insulating structure (202b) of the semiconductor substrate (200), with a gate insulating film (204b) in between. The source electrode (212b) and the drain electrode (214b) disposed on the interlayer insulating film (210) are each connected to the diffusion layer of the corresponding device region of the semiconductor substrate (200) through contact plugs (211b, 213b) formed in the contact holes of the interlayer insulating film (210).

[0062] Among the resistance structures, the polysilicon layer (208b) is disposed on the insulating structure (203b) of the semiconductor substrate (200) and can be connected to the drain electrode (214b) through one contact plug (215b) formed within the interlayer insulating film (210), and can be connected to the lowest metal wiring layer (216b) on the interlayer insulating film (210) through another contact plug (217b).

[0063] Among the resistor structures, a plurality of metal wiring layers (216b, 222b, 232b, 242b, 252b) are each disposed on a plurality of interlayer insulating films (210, 220, 230, 240, 250) and can be connected to adjacent wiring layers above and below through contact plugs (221b, 231b, 241b, 251b) formed in contact holes of the plurality of interlayer insulating films (220, 230, 240, 250). The plurality of metal wiring layers (222b, 232b, 242b, 252b) can overlap each other and can be connected in series through contact plugs (231b, 241b, 251b). Multiple metal wiring layers (222b, 232b, 242b, 252b) are arranged to overlap with the transistor and polysilicon layer (208b) of the corresponding resistor circuit, thereby increasing the arrangement area of ​​the resistor structure and thus increasing the defect detection area. The uppermost metal wiring layer (252a) can be exposed through a pad hole (262a) penetrating the passivation layer (260) and used as an inspection pad.

[0064] Referring to FIG. 8, an external resistance circuit of a semiconductor chip according to one embodiment may include a transistor comprising a gate insulating film (204d), a gate electrode (206d), a source electrode (212d), and a drain electrode (214d) disposed on a semiconductor substrate (200), and a resistance structure comprising a diffusion layer connected to the transistor and a plurality of metal wiring layers (222d, 232d, 242d, 272, 252d). The resistance structure may be disposed to overlap with the transistor of the resistance circuit and also overlap with another adjacent resistance circuit.

[0065] A gate electrode (206d) is disposed on the channel region of the corresponding device region separated by an insulating structure (202d) of the semiconductor substrate (200), with a gate insulating film (204d) in between. The source electrode (212d) and the drain electrode (214d) disposed on the interlayer insulating film (210) are each connected to the diffusion layer of the corresponding device region of the semiconductor substrate (200) through contact plugs (211d, 213d) formed in the contact holes of the interlayer insulating film (210).

[0066] Among the resistor structure, a plurality of metal wiring layers (222d, 232d, 242d, 272, 252d) are each disposed on a plurality of interlayer insulating films (220, 230, 240, 250, 270) and can be connected to adjacent wiring layers above and below through a contact plug (221d, 231d, 241d, 251d, 273) formed in a contact hole of the plurality of interlayer insulating films (220, 230, 240, 250, 270). The lowest metal wiring layer (222d) among the plurality of metal wiring layers (222d, 232d, 242d, 272, 252d) can overlap with a drain electrode (214d) connected through the contact plug (221d). A plurality of metal wiring layers (222d, 232d, 242d, 272) can be connected in series through contact plugs (231d, 241d, 251d). Each of the metal wiring layers (222d, 232d, 242d, 272) includes a first end and a second end, and the first end of the metal wiring layer is connected through a lower contact plug while overlapping with the second end of the lower metal wiring layer, and the second end of the metal wiring layer is connected through an upper contact plug while overlapping with the first end of the upper metal wiring layer. The uppermost metal wiring layer (252a) is connected in parallel with the lower wiring layer (272) through a plurality of contact plugs (273) and can be exposed through a pad hole (262d) penetrating the passivation layer (260) to be used as an inspection pad.

[0067] Among the plurality of metal wiring layers (222d, 232d, 242d, 272, 252d) constituting the resistor structure, the lowest wiring layer (222d) can be arranged to overlap with the drain electrode (214d) of the transistor, and the remaining metal wiring layers (232d, 242d, 272, 252d) can be arranged to overlap with other adjacent resistor circuits, thereby further increasing the placement area of ​​the resistor structure and the defect detection area proportional thereto. The metal wiring layers (232d, 242d, 272, 252d) can be arranged to overlap with the transistor and polysilicon layer (208c) of other adjacent resistor circuits. The transistor of another resistance circuit includes a gate insulating film (206c), a gate electrode (204c), a source electrode (212c), and a drain electrode (214c) on the interlayer insulating film (210) on the corresponding device region separated by an insulating structure (202c) of the semiconductor substrate (200). The source electrode (212c) and the drain electrode (214d) are connected to the diffusion layer of the semiconductor substrate (200) through contact plugs (211c, 213c). The polysilicon layer (208c) constituting the resistance structure of the other resistance circuit is placed on the insulating structure (203c) of the semiconductor substrate (200) and can be connected to the drain electrode (214c) through a contact plug (215c) and to the metal wiring layer (216c) through another contact plug (217c).

[0068] Referring to FIG. 9, an external resistance circuit of a semiconductor chip according to one embodiment may include a transistor comprising a gate insulating film (204e), a gate electrode (206e), a source electrode (212e), and a drain electrode (214e) disposed on a semiconductor substrate (200), and a resistance structure comprising a diffusion layer connected to the transistor and a plurality of metal wiring layers (222e, 232e, 242e, 272e, 252e). The resistance structure may be disposed to overlap with the transistor of the resistance circuit and to overlap with the resistance structure of an adjacent resistance circuit.

[0069] A gate insulating film (204e) and a gate electrode (206e) are disposed on the channel region of the corresponding device region separated by an insulating structure (202e) of the semiconductor substrate (200), and a source electrode (212e) and a drain electrode (214e) disposed on the interlayer insulating film (210) are each connected to the diffusion layer of the corresponding device region of the semiconductor substrate (200) through contact plugs (211e, 213e).

[0070] Among the resistance structures, a plurality of metal wiring layers (222e, 232e, 242e, 272e, 252e) are each disposed on a plurality of interlayer insulating films (220, 230, 240, 250, 270) and can be connected to adjacent wiring layers above and below through contact plugs (221e, 231e, 241e, 251e, 273e). The lowest metal wiring layer (222e) can overlap with a drain electrode (214e) connected through a contact plug (221e). The plurality of metal wiring layers (222e, 232e, 242e, 272e) can be connected in series through contact plugs (231e, 241e, 251e). Each of the metal wiring layers (222e, 232e, 242e, 272e) includes a first end and a second end, and the first end of the metal wiring layer overlaps with the second end of the lower metal wiring layer and is connected through a lower contact plug, and the second end of the metal wiring layer overlaps with the first end of the upper metal wiring layer and is connected through an upper contact plug. The uppermost metal wiring layer (252e) is connected in parallel with the lower wiring layer (272e) through a plurality of contact plugs (273e) and is exposed through a pad hole (262e) penetrating the passivation layer (260) and can be used as an inspection pad.

[0071] Among the plurality of metal wiring layers (222e, 232e, 242e, 272e, 252e) constituting the resistor structure, some of the lower wiring layers (222e, 232e) may be arranged to overlap with the corresponding transistor, and the remaining metal wiring layers (242e, 272e, 252e) may be arranged to overlap with the polysilicon layer (208f) constituting the resistor structure of an adjacent resistor circuit. The polysilicon layer (208f) constituting the resistor structure of the other resistor circuit may be placed on the insulating structure (203f) of the semiconductor substrate (200), connected to the drain electrode (214f) through a contact plug (215f), and connected to the metal wiring layer (216f) through another contact plug (217f). The polysilicon layer (208f) is formed to be long enough to overlap with a plurality of metal wiring layers (242e, 272e, 252e) of an adjacent resistance circuit, thereby further increasing the defect detection area of ​​the polysilicon layer (208f).

[0072] Multiple external resistance circuits may have the same structure or different structures.

[0073] Referring to FIG. 10, one of the plurality of external resistor circuits may include a resistor structure composed of a diffusion layer, a polysilicon layer (208), and metal wiring layers (216, 222, 232, 242, 252), as in the resistor circuit shown in FIG. 5, and a transistor connected to the resistor structure, and the other may include a resistor structure composed of a diffusion layer, a metal wiring layer (214a, 222a, 232a, 242a, 252a), as in the resistor circuit shown in FIG. 6, and a transistor connected to the resistor structure.

[0074] Referring to FIG. 11, one of the plurality of external resistor circuits may include a resistor structure composed of a diffusion layer and metal wiring layers (214a, 222a, 232a, 242a, 252a) and a transistor connected to the resistor structure, as in the resistor circuit shown in FIG. 6, and the other may include a resistor structure composed of a diffusion layer, a polysilicon layer (298b), and metal wiring layers (216b, 222b, 232b, 242b, 252b) and a transistor connected to the resistor structure, as in the resistor circuit shown in FIG. 7.

[0075] Referring to FIG. 12, one of the plurality of external resistor circuits may include a resistor structure composed of a diffusion layer and a metal wiring layer (214a, 222a, 232a, 242a, 252a), as in the resistor circuit shown in FIG. 6, and a transistor connected to the resistor structure, and the other may include a resistor structure composed of at least a diffusion layer of a semiconductor substrate (200) and a transistor connected to the resistor structure. In this transistor, a gate insulating film (204h) and a gate electrode (206h) are disposed on the channel region of the corresponding device region separated by an insulating structure (202h) of the semiconductor substrate (200), and a source electrode (212h) and a drain electrode (214h) disposed on the interlayer insulating film (210) may be connected to the diffusion layer of the corresponding device region of the semiconductor substrate (200) through contact plugs (211h, 213h), respectively. The drain electrode (214h) can be connected to another diffusion layer of the semiconductor substrate (200), which is a resistive structure, through another contact plug (217h).

[0076] As described above, a semiconductor device and its inspection device and method according to one aspect of the present invention can accurately detect the occurrence of a defect from an external resistance circuit having an output (performance) that deviates from an allowable range relative to a reference by comparing the outputs (performances) of a plurality of external resistance circuits distributed in the outer region of a semiconductor chip during an inspection process with each other, or by comparing the outputs (performances) of a plurality of external resistance circuits with a reference output (performance) of an internal resistance circuit or a predetermined reference value, and can also detect the location of the defect.

[0077] Accordingly, a semiconductor device and its inspection device and method according to one aspect of the present invention can improve the reliability of a semiconductor chip by accurately detecting defects and defect locations of the semiconductor chip during an inspection process and preventing quality accidents.

[0078] Those skilled in the art to which the present invention pertains will understand that the above-described invention may be implemented in other specific forms without altering its technical concept or essential features.

[0079] Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of the invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the invention. Explanation of the symbols

[0080] 1: Semiconductor wafer 10: Partial area 20: Centerline of the scribe lane 30: Scrib lane 100, 100a: Semiconductor chip 110: Internal resistance circuit 120: External resistor circuit 130, 112, 122: Pads 200: Semiconductor substrate 210, 220, 230, 240, 250: Interlayer insulating film 260: Passivation layer 204~204h: Gate insulating film 202~202h, 203~203f: Insulating structures 206~206h: Gate electrodes 212~212h: Source electrode 214~214h: Drain electrode 208~208f: Polysilicon layer 262~262e: Pad hole 211~211h, 213~213h, 215~215f, 217~217h, 221~221e, 231~231e, 241~241e, 251~252e, 273, 273e: Contact plug 216, 216b, 222~222e, 232~232e, 242~242e, 252~252e, 272, 272e: Metal wiring layer

Claims

Claim 1 A semiconductor device comprising a plurality of external resistance circuits separated along a chip outer region and distributed within the chip outer region, wherein each of the plurality of external resistance circuits comprises an external resistance structure including at least one of a diffusion layer, a polysilicon layer, and a wiring layer formed on a semiconductor substrate, an external transistor connected to the external resistance structure, and a first test pad disposed in a chip pad region and connected to the external transistor through the external resistance structure, wherein in a test process, each of the plurality of external resistance circuits reflects a change in the resistance value of the external resistance structure to the current of the external transistor and outputs it through the first test pad. Claim 2 A semiconductor device according to claim 1, further comprising an internal resistance circuit disposed in an internal region of a chip, wherein the internal resistance circuit comprises an internal resistance structure disposed in the internal region of the chip and including at least one of a diffusion layer, a polysilicon layer, and a wiring layer formed on the semiconductor substrate, an internal transistor connected to the internal resistance structure, and a second test pad disposed in the chip pad region and connected to the internal transistor through the internal resistance structure. Claim 3 A semiconductor device according to claim 2, wherein in the inspection process, the internal resistance circuit outputs a reference signal to be compared with the output of each of the plurality of external resistance circuits. Claim 4 delete Claim 5 delete Claim 6 A semiconductor device according to claim 1, wherein the polysilicon layer of the external resistance structure is disposed on an insulating structure of the semiconductor substrate, the polysilicon layer of the external resistance structure is disposed on an insulating structure of the semiconductor substrate, and the wiring layer of the external resistance structure is disposed on a plurality of interlayer insulating films and comprises a plurality of wiring layers connected to each other through contact plugs of each interlayer insulating film, and the uppermost wiring layer of the plurality of wiring layers is exposed to the first inspection pad. Claim 7 A semiconductor device according to claim 6, wherein the plurality of wiring layers among the external resistance structures are connected to the external transistor or connected to the external transistor via the polysilicon layer, and are arranged to overlap with at least a portion of the external transistor and the polysilicon layer. Claim 8 A semiconductor device according to claim 6, wherein one of the plurality of external resistance circuits is arranged to partially overlap with another adjacent external resistance circuit. Claim 9 A semiconductor device according to claim 8, wherein the plurality of wiring layers among the external resistance structures constituting any one of the external resistance circuits are arranged to overlap with at least one of the external transistor and polysilicon layer of the other external resistance circuit. Claim 10 A semiconductor device according to claim 6, wherein the plurality of external resistance circuits each have the same resistance value and the same external resistance structure, or have the same resistance value but different external resistance structure. Claim 11 Each semiconductor chip comprising: a plurality of external resistance circuits formed on a semiconductor substrate and disposed separately along the outer region of the chip, and an internal resistance circuit formed on the semiconductor substrate and disposed in the inner region of the chip; and an inspection device comprising, in an inspection process, driving the plurality of external resistance circuits and the internal resistance circuits, and detecting the location of defect occurrence in each semiconductor chip by detecting an external resistance circuit having an abnormal output that deviates from an allowable range relative to a reference value by comparing the output of each of the plurality of external resistance circuits with the output of the internal resistance circuit. Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 A semiconductor device inspection device comprising: each semiconductor chip having a plurality of external resistance circuits formed on a semiconductor substrate and separated and distributed along the outer region of the chip; and, in an inspection process, an inspection device that drives the plurality of external resistance circuits and compares the outputs of each of the plurality of external resistance circuits with one another or with a predetermined reference value to detect an external resistance circuit having an abnormal output that deviates from an allowable range relative to the reference value, thereby detecting the location of a defect in each semiconductor chip. Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete

Images