Semiconductor device and method of disposing electrical components over side surfaces of interconnect substrate

Abstract

A semiconductor device has an interconnect substrate having conductive vias. A first electrical component is disposed on the main surface of the interconnect substrate. An electrical interconnect compound is disposed on the conductive vias exposed from the side surface of the interconnect substrate. The electrical interconnect compound may be applied with a nozzle oriented obliquely at a certain angle. A second electrical component is disposed on the electrical interconnect compound on the conductive vias exposed from the side surface of the interconnect substrate. A plurality of second electrical components may be disposed on two or more side surfaces of the interconnect substrate. The interconnect substrate may have a plurality of stacked conductive vias, and the second electrical components are disposed on the stacked conductive vias. An encapsulant is deposited on the first electrical component and the interconnect substrate. A shielding layer may be formed on the encapsulant.

Description

Technology Field

[0001] The present invention generally relates to a semiconductor device, and more specifically, to a semiconductor device having a plurality of electrical components disposed on one or more side surfaces of an interconnection substrate and a method for manufacturing the same. Background Technology

[0003] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, electromagnetic signal transmission and reception, electronic device control, photoelectricity, and the generation of visual images for television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0005] In particular, semiconductor devices for high-frequency applications, such as radio frequency (RF) communication, often contain one or more integrated passive devices (IPDs) to perform necessary electrical functions. By integrating multiple semiconductor dies, IPDs, and other electrical components into a System-in-Package (SIP) module or other wafer-level package (WLP), higher density can be achieved in a small space and electrical functions can be expanded. Within a SIP module, electrical components are mounted on a substrate for structural support and electrical interconnection. Encapsulant is deposited on the electrical components and the substrate. The problem to be solved

[0007] Most, though not all, SIP modules and WLPs place electrical components on the main surface of the substrate. As SIP module functionality continues to expand, an increasing number of electrical components are placed on the main surface of the substrate, and the surface area of ​​the SIP module increases. However, the preferred trend is to make SIP modules smaller while simultaneously enhancing their functionality. Brief explanation of the drawing

[0009] Figures 1a-1c illustrate a semiconductor wafer having a plurality of semiconductor dies separated by top street. FIGS. 2a-2h illustrate a process of placing electrical components on one or more sides of an interconnection board to form a SIP module. FIGS. 3a-3h illustrate additional details regarding the placement of electrical components on one or more sides of an interconnection substrate. FIGS. 4a-4g illustrate the use of a carrier for placing electrical components on the side of an interconnection board. FIGS. 5a-5b illustrates placing electrical components on multiple sides of an interconnection board. FIG. 6 illustrates a shielding layer on a SIP module having electrical components disposed on one or more sides of an interconnection board. And FIG. 7 illustrates a printed circuit board (PCB) having different types of packages mounted on the surface of the printed circuit board (PCB). Specific details for implementing the invention

[0010] The present invention is described in the following description by one or more embodiments with reference to drawings in which the same or similar elements are represented. Although the present invention is described in the best form for achieving the purpose of the invention, those skilled in the art will understand that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalents supported by the following detailed description and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and multiple semiconductor devices.

[0011] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function.

[0012] Back-end manufacturing refers to the process of cutting or singulating a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scored and cut along non-functional areas of the wafer known as saw streets or scribes. The wafer is individualized using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components.

[0013] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102), such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials, for structural support. A plurality of semiconductor dies or components (104) are formed on the wafer (100) separated by a wafer area between inactive dies or a saw street (106). The saw street (106) provides a cutting area for singulating the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0014] FIG. 1b illustrates a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has a back surface or inactive surface (108) and an active surface (110) comprising an analog or digital circuit implemented as an active element, a passive element, a conductive layer, and a dielectric layer formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (210) to implement an analog or digital circuit, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a memory, or other signal processing circuit. The semiconductor die (104) may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0015] An electrically conductive layer (112) is formed on an active surface (110) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit on the active surface (110).

[0016] An electrically conductive bump material is deposited onto a conductive layer (112) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, combinations thereof, or other suitable conductive materials having an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (112) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a conductive ball or bump (114). In one embodiment, the bump (114) is formed on a lower bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump (114) may also be compression bonded or thermally compressed to the conductive layer (112). The bump (114) represents a type of interconnect structure that can be formed on the conductive layer (112). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0017] In FIG. 1c, a semiconductor wafer (100) is singulated into individual semiconductor dies (104) through a saw street (106) using a saw blade or laser cutting tool (118). After singulation, the individual semiconductor dies (104) can be inspected and electrically tested to identify known good dies or units (KGD / KGU).

[0018] FIGS. 2a-2h illustrate a process of placing electrical components on the side surfaces of an interconnect substrate to form a SIP module. FIG. 2a illustrates a cross-sectional view of a multilayer interconnect substrate (120) comprising a conductive layer (122) and an insulating layer (123). The conductive layer (122) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (122) provides horizontal electrical interconnection across the substrate (120) and vertical electrical interconnection vias (124) between the upper main surface (126) and the lower main surface (128) of the substrate (120). Parts of the conductive layer (122) may be electrically common or electrically isolated depending on the design and function of the semiconductor die and other electrical components. The insulating layer (123) comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon nitride oxide (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The insulating layer (123) provides isolation between the conductive layers (122).

[0019] In FIG. 2b, a plurality of electrical components (130a-130c) are mounted on the surface (126) of an interconnection substrate (120) and electrically and mechanically connected to a conductive layer (122). Each of the electrical components (130a-130c) is positioned on the die attachment locations (129a-129c) of the substrate (120) and uses a pick-and-place operation. For example, the electrical component (130a) may be similar to the semiconductor die (104) of FIG. 1c, with the active surface (110) and bump (114) oriented toward the surface (126) of the substrate (120). The electrical components (130b and 130c) may be similar to the semiconductor die (104), but may differ in shape and function, with the active surface (110) and bump (114) oriented toward the surface (126) of the substrate (120). Alternatively, the electrical components (130a-130c) may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or IPDs such as resistors, capacitors, and inductors. FIG. 2c illustrates electrical components (130a-130c) electrically and mechanically connected to the conductive layer (122) and vertical interconnect vias (124) of the substrate (120).

[0020] In FIG. 2d, an encapsulant or molding compound (136) is deposited on and around electrical components (130a-130c) on a substrate (120) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant (136) may be a polymer composite material such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant (136) is non-conductive and provides structural support and environmentally protects the semiconductor device from external elements and contaminants. The electrical components (130a-130c) are mounted on an interconnect substrate (120) and covered by the encapsulant (136), forming a SIP module or WLP (138).

[0021] In FIG. 2e, electrical components (140a and 140b) are positioned on the side surface (141) of the interconnection substrate (120) using a pick-and-place operation. The side surface (141) is the surface of the interconnection substrate (120) between the main surface (126) and the main surface (128) and perpendicular to these surfaces. The electrical components (140a, 140b) may be semiconductor dies (similar to semiconductor die (104)), semiconductor packages, surface mount devices, RF components, discrete electrical devices, or IPDs, such as resistors, capacitors, and inductors. The external connection terminals (142a, 142b) of the electrical components (140a, 140b) are aligned with an electrical interconnection compound (144), such as solder or electrically conductive paste. The electrical interconnect compound (144) creates an electrical connection between the external connection terminals (142a, 142b) and the vertical interconnect vias (124) of the conductive layer (122) and the interconnect substrate (120).

[0022] FIG. 2f illustrates electrical components (140a-140b) electrically and mechanically connected to the side surface (141), conductive layer (122), and vertical interconnect via (124) of the interconnection substrate (120). In the prior art, electrical components such as the electrical components (140a-140b) are located on the main surface of the interconnection substrate, creating a need for a large surface area to accommodate the components. Instead, the electrical components (140a, 140b) are placed on the side surface (141) of the interconnection substrate (120), thereby reducing the surface area of ​​the surface (126) of the component-dedicated SIP module (138).

[0023] In another embodiment, continuing from FIG. 2d, the electric components (148a, 148b) are positioned on the side surface (141) of the interconnection substrate (120) using a pick-and-place operation as in FIG. 2g. For example, although FIG. 1c has a different form and function and the contact pads (149a and 149b) are oriented toward the side surface (141) of the substrate (120), the electric components (148a and 148b) may be similar to the semiconductor die (104) of FIG. 1c. The side surface (141) is a surface of the interconnection substrate (120) perpendicular between the main surface (126) and the main surface (128). Optionally, the electric components (148a-148b) may be other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electric devices, or IPDs such as resistors, capacitors, and inductors. The external connection terminals (149a, 149b) of the electrical components (148a, 148b) are aligned with an electrical interconnection compound (144), such as solder or electrically conductive paste. The electrical interconnection compound (144) creates an electrical connection between the external connection terminals (142a, 142b) and the conductive layer (122) and vertical interconnection vias (124) of the interconnection substrate (120). Components having similar functions in the drawing are given the same reference number.

[0024] FIG. 2h illustrates electrical components (148a, 148b) electrically and mechanically connected to the side surface (141), conductive layer (122), and vertical interconnect via (124) of the interconnection substrate (120). In the prior art, the electrical components (148a, 148b) are positioned on the main surface of the interconnection substrate, creating a need for a large surface area to accommodate the components. Instead, the electrical components (148a, 148b) are positioned on the side surface (141) of the interconnection substrate (120), thereby reducing the surface area of ​​the surface (126) of the component-dedicated SIP module (138).

[0025] FIG. 3a illustrates a SIP module (138) having an encapsulant (136) deposited on an electrical component (130a-130c) and an interconnection substrate (120). FIG. 3b is a side view of the SIP module (138) from FIG. 3a, showing an insulating layer (123), a conductive layer (122), and vertical interconnection vias (124) exposed from a side surface (141). In another embodiment, FIG. 3c is a side view of the SIP module (138) showing stacked vertical interconnection vias (124) exposed from an insulating layer (123), a conductive layer (122), and a side surface (141). In another embodiment, FIG. 3d is a side view of a SIP module (138) showing an insulating layer (123), a copper clad laminate (CCL) layer (150), a conductive layer (122), and an offset stacked vertical interconnect via (124) exposed from a side surface (141).

[0026] FIG. 3e illustrates a SIP module (138) with an encapsulant (136) deposited on electrical components (130a-130c) and an interconnect substrate (120). An electrical interconnect compound (144), such as solder or electrically conductive paste, is deposited on exposed vertical interconnect vias (124). FIG. 3f is a side view of the SIP module (138) from FIG. 3e, illustrating an insulating layer (123), a conductive layer (122), and an electrical interconnect compound (144) deposited on exposed vertical interconnect vias (124) on a side surface (141). The electrical interconnect compound (144) may be positioned horizontally or vertically, and electrical components (140a-140b) are aligned with the electrical interconnect compound.

[0027] FIG. 3g illustrates a SIP module (138) with an encapsulant (136) deposited on an electrical component (130a-130c) and an interconnection substrate (120). The electrical components (140a-140b) are electrically and mechanically connected to a conductive layer (122), and an electrical interconnection compound (144) is deposited on exposed vertical interconnection vias (124) of the substrate (120). FIG. 3h is a side view of the SIP module (138) from FIG. 3g, illustrating an insulating layer (123) and electrical interconnection components (140a-140b) electrically and mechanically connected to a conductive layer (122) and an electrical interconnection compound (144) deposited on exposed vertical interconnection vias (124) on a side surface (141) of the substrate (120).

[0028] To perform the steps of FIGS. 2a-2h and 3a-3h, a plurality of SIP modules (138) are mounted vertically on a carrier (160) as shown in FIG. 4a. The carrier (160) may be a film having an adhesive layer. The SIP modules (138) are bonded to the adhesive layer of the carrier (160). Alternatively, the carrier (162) may be a rigid support such as metal or plastic having a plurality of slots (164) sized to accommodate the SIP modules (138) as shown in FIG. 4b. The plurality of SIP modules (138) are positioned within the slots (164) in a vertical orientation.

[0029] In FIG. 4c, an electrical interconnect compound (144), such as solder or electrically conductive paste, is deposited on an exposed vertical interconnect via (124) on a side surface (141) of a SIP module (138) on a carrier (160). In particular, as shown in FIG. 4d, the electrical interconnect compound (144) is deposited using a nozzle (166). The nozzle (166) is tilted at an angle (q) of about 25 degrees to ensure and accurately deliver the electrical interconnect compound (144) to a smaller area on the vertical interconnect via (124). Dispensing at an angle with the nozzle (166) allows for precise dispensing of the electrical interconnect compound (144) to a pad on a vertically oriented substrate. The angled nozzle (166) can move to a target location for accurate delivery. Accordingly, the nozzle (166) deposits an electrical interconnect compound (144) on the pads of the vertical interconnect vias (124). Alternatively, the electrical interconnect compound (144) may be deposited by paste printing or other paste dispensing techniques.

[0030] In FIG. 4e, the electrical components (140a-140b) are placed on the electrical interconnect compound (144) on the side surface (141) using a pick-and-place tool (168). In FIG. 4f, the electrical components (140a-140b) are electrically and mechanically connected to the electrical interconnect compound (144) and the conductive layer (122) deposited on the exposed vertical interconnect vias (124) on the side surface (141) of the substrate (120) using a laser (170). Laser-assisted bonding using a laser (170) enables component mounting and prevents package warping compared to other mass reflows. An underfill material (172), such as epoxy resin, can be deposited between the electrical components (140a-140b) and the interconnect substrate (120) as shown in FIG. 4g.

[0031] In another embodiment, the SIP module (180) may have electrical components (174) similar to the electrical components (140a-140b) disposed on one, two, three, or four side surfaces (141). FIG. 5a illustrates electrical components (174) electrically and mechanically connected to a conductive layer (122) and an electrical interconnection compound (176) deposited on exposed vertical interconnection vias (124) on multiple side surfaces (141) of the substrate (120). FIG. 5b is a top view of the SIP module (180) showing electrical components (174) electrically and mechanically connected to an electrical interconnection compound (176) and a conductive layer (122) deposited on exposed vertical interconnection vias (124) on all four side surfaces (141) of the substrate (120). An underfill material, such as epoxy resin, can be deposited between the electrical component (174) and the interconnection substrate (120).

[0032] As illustrated in FIGS. 2f, 3h, 4f and 5b, an SIP module (138 or 180) in which electrical components (140a-140b or 174) are placed on one or more side surfaces (141) of an interconnection substrate (120) reduces package size and increases space utilization.

[0033] The electrical components (130a-130c) may include IPDs that generate or are sensitive to EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included within the electrical components (130a-130c) provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components (130a-130b) include digital circuits that switch at high frequencies that can interfere with the operation of the IPDs in the SIP module.

[0034] The SIP module (138) includes high-speed digital and RF electrical components (130a-130c) that are highly integrated for small size and low height and operate at high clock frequencies. As shown in FIG. 6, an electromagnetic shielding layer (190) is formed or placed over a portion of the encapsulant (136) and interconnection substrate (120) by conformal application of a shielding material. The shielding layer (190) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the shielding layer (190) may be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon iron, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing EMI, RFI, and other inter-device interference effects. Additionally, the shielding layer (190) covers one or more side surfaces of the substrate (120) as well as the side surface of the encapsulant (136). The electromagnetic shielding layer (190) reduces or prevents EMI, RFI, and other inter-device interference emitted by the high-speed digital device from adjacent devices affecting the SIP module (138) or adjacent to it.

[0035] FIG. 7 illustrates an electronic device (300) having a chip carrier substrate or PCB (302) having a plurality of semiconductor packages mounted on the surface of the PCB (302), including SIP modules (138, 180). Depending on the application, the electronic device (300) may have one type of semiconductor package or multiple types of semiconductor packages.

[0036] The electronic device (300) may be a standalone system using a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device (300) may be a sub-component of a larger system. For example, the electronic device (300) may be part of a tablet, mobile phone, digital camera, communication system, or other electronic device. Optionally, the electronic device (300) may be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete discrete device, or other semiconductor die or electrical component. Miniaturization and lightweighting are essential for the product to be accepted in the market. To achieve high density, the distance between semiconductor devices can be reduced.

[0037] In FIG. 7, the PCB (302) provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces (304) are formed on the surface of or within a layer of the PCB (302) using deposition, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (304) provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. The traces (304) also provide power and ground connections to each of the semiconductor packages.

[0038] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging includes mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level packaging in which the die is directly mechanically and electrically mounted to a PCB.

[0039] For example, several types of first-stage packaging, including bond wire packages (306) and flip chips (308), are shown on the PCB (302). Additionally, several types of second-stage packaging, including ball grid arrays (BGA) (310), bump chip carriers (BCC) (312), land grid arrays (LGA) (316), multichip modules (MCM) (318) or SIP modules (318), quad flat lead-free packages (QFN) (320), quad flat packages (322), embedded wafer-level ball grid arrays (eWLB) (324), and wafer-level chip scale packages (WLCSP) (326), are shown mounted on the PCB (302). In one embodiment, eWLB (324) is a fan-out wafer-level package (Fo-WLP) and WLCSP (326) is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages composed of any combination of first and second-stage packaging styles and other electronic components may be connected to the PCB (302). In some embodiments, the electronic device (300) comprises a single attached semiconductor package, whereas other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic devices and systems. Because the semiconductor packages contain sophisticated functions, electronic devices can be manufactured using inexpensive components and simplified manufacturing processes. As a result, the devices are less likely to fail and have lower manufacturing costs, leading to reduced consumer costs.

[0040] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and changes to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 An interconnection substrate - the interconnection substrate comprises a conductive layer within, wherein the conductive layer comprises a first conductive via exposed at a side surface of the interconnection substrate and extending from a first main surface of the interconnection substrate to a second main surface of the interconnection substrate opposite to the first main surface of the interconnection substrate, and a second conductive via exposed at the side surface of the interconnection substrate and extending from the first main surface of the interconnection substrate to the second main surface of the interconnection substrate - a first active electrical component disposed on the first main surface of the interconnection substrate; and a second active electrical component disposed on the side surface of the interconnection substrate in contact with the first conductive via and the second conductive via. Claim 2 A semiconductor device according to claim 1, further comprising an electrical interconnection compound disposed on the first conductive via exposed on the side surface of the interconnection substrate. Claim 3 A semiconductor device according to claim 1, further comprising a plurality of second electrical components disposed on two or more side surfaces of the interconnection substrate. Claim 4 A semiconductor device according to claim 1, wherein the first conductive via comprises a plurality of stacked conductive vias, and the second active electrical component is disposed in contact with the stacked conductive vias. Claim 5 An interconnection substrate - the interconnection substrate comprises a first conductive via exposed at a side surface of the interconnection substrate and extending from a first main surface of the interconnection substrate to a second main surface of the interconnection substrate opposite to the first main surface of the interconnection substrate, and a second conductive via exposed at the side surface of the interconnection substrate and extending from the first main surface of the interconnection substrate to the second main surface of the interconnection substrate - a first electrical component disposed on the first main surface of the interconnection substrate; and a second electrical component disposed on the first conductive via and the second conductive via on the side surface of the interconnection substrate, a semiconductor device. Claim 6 A semiconductor device according to claim 5, further comprising an electrical interconnection compound disposed on a side surface of the interconnection substrate. Claim 7 A semiconductor device according to claim 5, further comprising a plurality of second electrical components disposed on two or more side surfaces of the interconnection substrate. Claim 8 A semiconductor device according to claim 5, further comprising an encapsulant deposited on the first electrical component and the interconnection substrate. Claim 9 A semiconductor device according to claim 5, wherein the first conductive via comprises a plurality of stacked conductive vias, and the second electrical component is disposed on the stacked conductive vias. Claim 10 A method for manufacturing a semiconductor device, comprising the steps of: providing an interconnection substrate—the interconnection substrate comprising a first conductive via exposed at a side surface of the interconnection substrate and extending from a first main surface of the interconnection substrate to a second main surface of the interconnection substrate opposite to the first main surface of the interconnection substrate, and a second conductive via exposed at the side surface of the interconnection substrate and extending from the first main surface of the interconnection substrate to the second main surface of the interconnection substrate—, placing a first electrical component on the first main surface of the interconnection substrate, and placing a second electrical component on the first conductive via and the second conductive via on the side surface of the interconnection substrate. Claim 11 A method for manufacturing a semiconductor device according to claim 10, further comprising the step of placing an electrical interconnection compound on a side surface of the interconnection substrate. Claim 12 A method for manufacturing a semiconductor device according to claim 10, further comprising the step of placing a plurality of second electrical components on two or more side surfaces of the interconnection substrate. Claim 13 A method for manufacturing a semiconductor device according to claim 10, wherein the first conductive via extends from a first surface of an interconnection substrate to a second surface of a substrate opposite to the first surface of the substrate. Claim 14 A method for manufacturing a semiconductor device according to claim 10, further comprising the step of depositing an encapsulant on the first electrical component and the interconnection substrate. Claim 15 A method for manufacturing a semiconductor device according to claim 14, further comprising the step of forming a shielding layer on the above-mentioned encapsulant.

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