Display device

Abstract

A display device according to an embodiment of the present invention comprises a display area and a non-display area, a stretchable lower substrate, a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first line patterns formed in the display area, a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area, a plurality of pixels formed on a plurality of first plate patterns, a plurality of first connecting lines connecting a plurality of pixels, a gate driver formed on a plurality of second plate patterns, a power supply formed on a plurality of second plate patterns, a plurality of second connecting lines disposed in the non-display area, and a stretchable upper substrate covering the gate driver, the power supply, and the plurality of pixels. The non-display area includes a first area located outside the display area, a second area located outside the first area where a plurality of gate drivers are disposed, and a third area located outside the second area where a plurality of power supplies are disposed. A plurality of second connecting lines disposed in the first area are connected to a different layer from the plurality of second connecting lines through an anchor hole. It comes into contact with the placed metal pattern.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically, to a stretchable display device. Background Technology

[0002] Display devices used in computer monitors, TVs, mobile phones, etc., include Organic Light Emitting Displays (OLEDs) that emit light on their own, and Liquid Crystal Displays (LCDs) that require a separate light source.

[0003] The application range of display devices is expanding to include not only computer monitors and TVs but also personal portable devices, and research is underway on display devices that have a large display area while possessing reduced volume and weight.

[0004] In addition, recently, display devices manufactured by forming display parts, wiring, etc. on a flexible substrate such as plastic, which is a flexible material, and being able to be stretched in a specific direction and changed into various shapes are attracting attention as next-generation display devices. The problem to be solved

[0005] The problem to be solved by the present invention is to provide a display device in which the wiring is not damaged even under repeated stretching.

[0006] Another problem that the present invention aims to solve is to provide a display device capable of biaxially stretching all areas of the display device.

[0007] Another problem that the present invention aims to solve is to provide a display device that can prevent wiring tearing during the lift-off process.

[0008] Another problem that the present invention aims to solve is to provide a display device capable of preventing a drop in driving voltage.

[0009] The problems of the present invention are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0010] To solve the problem described above, a display device according to one embodiment of the present invention comprises a display area and a non-display area, a stretchable lower substrate, a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first line patterns formed in the display area, a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area, a plurality of pixels formed on a plurality of first plate patterns, a plurality of first connecting lines connecting a plurality of pixels, a gate driver formed on a plurality of second plate patterns, a power supply formed on a plurality of second plate patterns, a plurality of second connecting lines disposed in the non-display area, and a stretchable upper substrate covering the gate driver, the power supply, and the plurality of pixels, wherein the non-display area includes a first area located outside the display area, a second area located outside the first area where a plurality of gate drivers are disposed, and a third area located outside the second area where a plurality of power supplies are disposed, and the plurality of second connecting lines disposed in the first area through an anchor hole It comes into contact with a plurality of second connecting wires and a metal pattern placed on a different layer.

[0011] A display device according to another embodiment of the present invention comprises a flexible substrate, a plurality of rigid patterns formed on the flexible substrate, a plurality of pixels formed on a plurality of first plate patterns spaced apart from each other among the plurality of rigid patterns, and a power supply formed on a portion of a plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, wherein the power supply supplies a driving voltage to the plurality of pixels and is composed of power blocks spaced apart from each other in a first direction and a second direction.

[0012] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0013] The present invention allows the stretching reliability of a display device to be stably secured by forming an anchor hole in the buffer wiring.

[0014] The present invention secures the buffer wiring through an anchor hole, thereby preventing damage to the display device when lifted off.

[0015] In the present invention, the non-display area is stretched in a biaxial direction, which can improve the usability of the display device.

[0016] In the present invention, the power supply includes additional power blocks electrically connected between power blocks, thereby minimizing the drop in driving voltage.

[0017] The effects according to the present invention are not limited to those exemplified above, and a wider variety of effects are included within the present invention. Brief explanation of the drawing

[0018] FIG. 1 is a plan view of a display device according to one embodiment of the present invention. FIG. 2 is an enlarged plan view of the display area of ​​a display device according to one embodiment of the present invention. Figure 3 is a cross-sectional view taken along the cutting line III-III' shown in Figure 2. Figure 4 is a cross-sectional view taken along the cutting line Ⅳ-Ⅳ' shown in Figure 2. FIG. 5 is a cross-sectional view taken along the cutting line V-V' shown in FIG. 2. FIG. 6 is a circuit diagram of a subpixel of a display device according to one embodiment of the present invention. FIG. 7 is an enlarged plan view of a non-display area of ​​a display device according to one embodiment of the present invention. FIG. 8 is an enlarged plan view of a first area of ​​a display device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view taken along the cutting line IX-IX' shown in FIG. 8. FIG. 10 is an enlarged plan view of a third region of a display device according to one embodiment of the present invention. FIG. 11 is a cross-sectional view taken along the cutting line XI-XI' shown in FIG. 10. FIG. 12 is an enlarged plan view of a third area of ​​a display device according to another embodiment of the present invention. FIG. 13 is a cross-sectional view taken along the cutting line XIII-XIII' shown in FIG. 12. Specific details for implementing the invention

[0019] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0020] Shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in the present invention, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0023] When an element or layer is referred to as "on" another element or layer, it includes cases where another layer or element is placed directly on top of or in between.

[0024] Additionally, terms such as first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0025] In addition, when terms such as 'connect' or 'contact' mentioned in the present invention are used, unless expressions such as 'immediately' or 'directly' are used, one or more other parts may be located between the two parts to be connected or contacted.

[0026] Throughout the specification, the same reference numerals refer to the same components.

[0027] The area and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the illustrated components.

[0028] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0029] Various embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0030] A display device according to one embodiment of the present invention is a display device capable of displaying images even when bent or stretched, and may also be referred to as a stretchable display device, an elastic display device, or a stretchable display device. Compared to conventional general display devices, the display device not only possesses high flexibility but also stretchability. Accordingly, a user can bend or stretch the display device, and the shape of the display device can be freely changed according to the user's operation. For example, if a user grasps and pulls the end of the display device, the display device can stretch in the direction in which the user pulls. Alternatively, if a user places the display device on an uneven outer surface, the display device can be positioned to bend along the shape of the outer surface of the wall. Furthermore, when the force applied by the user is removed, the display device can be restored to its original shape.

[0031] <스트레쳐블 기판 및 패턴층>

[0032] FIG. 1 is a plan view of a display device according to one embodiment of the present invention.

[0033] FIG. 2 is an enlarged plan view of a display area of ​​a display device according to an embodiment of the present invention. Specifically, FIG. 2 is an enlarged plan view of area A shown in FIG. 1.

[0035] Figure 3 is a cross-sectional view taken along the cutting line III-III' shown in Figure 2.

[0036] Referring to FIG. 1, a display device (100) according to one embodiment of the present invention may include a lower substrate (111), a pattern layer (120), a plurality of pixels (PX), a gate driver (GD), a data driver (DD), and a power supply (PS). Also, referring to FIG. 3, a display device (100) according to one embodiment of the present invention may further include a filling layer (190) and an upper substrate (112).

[0037] The lower substrate (111) is a substrate for supporting and protecting various components of the display device (100). And, the upper substrate (112) is a substrate for covering and protecting various components of the display device (100). That is, the lower substrate (111) is a substrate that supports a pattern layer (120) on which a pixel (PX), a gate driver (GD), and a power supply (PS) are formed. And, the upper substrate (112) is a substrate that covers the pixel (PX), the gate driver (GD), and the power supply (PS).

[0038] Each of the lower substrate (111) and the upper substrate (112) may be composed of an insulating material that can be bent or stretched as a flexible substrate. For example, each of the lower substrate (111) and the upper substrate (112) may be made of an elastomer such as silicone rubber (polydimethylsiloxane; PDMS), polyurethane (PU), or PTFE (polytetrafluoroethylene), and thus may have flexible properties. Furthermore, the materials of the lower substrate (111) and the upper substrate (112) may be the same, but are not limited thereto and may be modified in various ways.

[0039] Each of the lower substrate (111) and the upper substrate (112) is a flexible substrate and can be reversibly expanded and contracted. Accordingly, the lower substrate (111) may also be referred to as a lower stretchable substrate, a lower elastic substrate, a lower elongated substrate, a lower flexible substrate, a lower flexible substrate, a first stretchable substrate, a first elastic substrate, a first elongated substrate, a first flexible substrate, or a first flexible substrate, and the upper substrate (112) may also be referred to as an upper stretchable substrate, an upper elastic substrate, an upper elongated substrate, an upper flexible substrate, an upper flexible substrate, a second stretchable substrate, a second elastic substrate, a second elongated substrate, a second flexible substrate, or a second flexible substrate. Additionally, the modulus of elasticity of the lower substrate (111) and the upper substrate (112) may be several MPa to several hundred MPa. In addition, the ductile breaking rate of the lower substrate (111) and the upper substrate (112) may be 100% or more. Here, the ductile breaking rate refers to the elongation rate at the point when the elongated object is broken or cracked. The thickness of the lower substrate may be 10 µm to 1 mm, but is not limited thereto.

[0040] The lower substrate (111) may have an active area (AA) and a non-active area (NA) surrounding the active area (AA).

[0041] The display area (AA) is an area where an image is displayed in the display device (100). A plurality of pixels (PX) are arranged in the display area (AA). Each pixel (PX) may include a display element and various driving elements for driving the display element. The various driving elements may include at least one thin film transistor (TFT) and a capacitor, but are not limited thereto. Additionally, each of the plurality of pixels (PX) may be connected to various wiring. For example, each of the plurality of pixels (PX) may be connected to various wiring such as gate wiring, data wiring, high potential power wiring, low potential power wiring, reference voltage wiring, etc.

[0042] The non-display area (NA) is an area where no image is displayed. The non-display area (NA) may be an area adjacent to and surrounding the display area (AA). However, it is not limited to this, and the non-display area (NA) corresponds to an area of ​​the lower substrate (111) excluding the display area (AA), and this can be modified and separated into various shapes. Components for driving a plurality of pixels (PX) placed in the display area (AA) are disposed in the non-display area (NA). A gate driver (GD) and a power supply (PS) may be disposed in the non-display area (NA). Additionally, a plurality of pads connected to the gate driver (GD) and the data driver (DD) may be disposed in the non-display area (NA), and each pad may be connected to each of the plurality of pixels (PX) of the display area (AA).

[0043] A pattern layer (120) made of a plastic material having lower flexibility than the lower substrate (111) may be disposed on the lower substrate (111). For example, the pattern layer (120) may be made of polyimide (PI), polyacrylate, polyacetate, etc.

[0044] And, the pattern layer (120) may include a plurality of first plate patterns (121) and a plurality of first line patterns (122) disposed in a display area (AA), and a plurality of second plate patterns (123) and a plurality of second line patterns (124) disposed in a non-display area (NA).

[0045] A plurality of first plate patterns (121) are placed in the display area (AA) of the lower substrate (111), and a plurality of pixels (PX) are formed on the plurality of first plate patterns (121). Then, a plurality of second plate patterns (123) are placed in the non-display area (NA) of the lower substrate (111), and a gate driver (GD) and a power supply (PS) are formed on the plurality of second plate patterns (123).

[0046] As described above, a plurality of first plate patterns (121) and a plurality of second plate patterns (123) are arranged in an island shape spaced apart from each other, so that each of the plurality of first plate patterns (121) and the plurality of second plate patterns (123) can be separated individually. Accordingly, the plurality of first plate patterns (121) and the plurality of second plate patterns (123) may be referred to as a first island pattern and a second island pattern, or a first individual pattern and a second individual pattern. The first plate patterns (121) spaced apart from each other can be connected by a first wiring pattern (122). And, in a non-display area (NA), the second plate patterns (123) spaced apart from each other can be connected by a second wiring pattern (124).

[0047] Specifically, a plurality of second plate patterns (123) disposed in a non-display area (NA) include a plurality of first sub-plate patterns (123a) in which an anchor hole is disposed, a plurality of second sub-plate patterns (123b) in which a gate driver (GD) is disposed, and a plurality of third sub-plate patterns (123c) in which a power supply (PS) is disposed.

[0048] More specifically, as illustrated in FIG. 1, a plurality of first sub-plate patterns (123a) may be arranged adjacent to the display area (AA) in the first direction (X) and spaced apart in the second direction (Y). That is, with respect to the first direction (X), the first sub-plate patterns (123a) may be arranged on both sides of the display area (AA). However, this is not limited thereto, and the first sub-plate patterns (123a) may be arranged only on one side of the display area (AA) with respect to the first direction (X). Additionally, anchor holes for connecting a plurality of connecting wires may be arranged on the plurality of first sub-plate patterns (123a).

[0049] Additionally, a plurality of second sub-plate patterns (123b) may be arranged adjacent to a plurality of first sub-plate patterns (123a) in a first direction (X) and spaced apart in a second direction (Y). That is, with respect to the first direction (X), a plurality of second sub-plate patterns (123b) may be arranged on both sides of a plurality of first sub-plate patterns (123a). However, this is not limited thereto, and a second sub-plate pattern (123b) may be arranged on only one side of a plurality of first sub-plate patterns (123a).

[0050] Additionally, a gate driver (GD) may be mounted on a plurality of second sub-plate patterns (123b). The gate driver (GD) may be formed on the second sub-plate pattern (123b) using a Gate In Panel (GIP) method during the manufacturing of various components on the first plate pattern (121). Accordingly, various circuit configurations constituting the gate driver (GD), such as various transistors, capacitors, and wiring, may be arranged on the plurality of second sub-plate patterns (123b). However, the gate driver (GD) may also be mounted using a Chip on Film (COF) method, without being limited thereto.

[0051] Additionally, a plurality of third sub-plate patterns (123c) may be arranged adjacent to a plurality of second sub-plate patterns (123b) in the first direction (X) and spaced apart in the second direction (Y). That is, a plurality of third sub-plate patterns (123c) may be arranged on both sides of the plurality of second sub-plate patterns (123b) in the first direction (X). However, this is not limited thereto, and a third sub-plate pattern (123c) may be arranged only on one side of the plurality of second sub-plate patterns (123b) in the first direction (X). Furthermore, a power supply (PS) may be mounted on the plurality of third sub-plate patterns (123c). The power supply (PS) may be formed on the third sub-plate pattern (123c) as a plurality of power blocks that are patterned during the manufacturing of various components on the first plate pattern (121). Accordingly, power blocks that are placed on different layers can be placed on the third sub-plate pattern (123c).

[0052] Referring to FIG. 1, the size of a plurality of first sub-plate patterns (123a) may be smaller than the size of a plurality of first plate patterns (121). Specifically, the size of each of the plurality of first sub-plate patterns (123a) may be smaller than the size of each of the plurality of first plate patterns (121). As described above, an anchor hole (AH) is disposed in each of the plurality of first sub-plate patterns (123a), and since the area occupied by the anchor hole (AH) is smaller than the area occupied by the pixel (PX), the size of each of the plurality of first sub-plate patterns (123a) may be smaller than the size of each of the plurality of first plate patterns (121).

[0053] Additionally, the size of the plurality of second sub-plate patterns (123b) may be larger than the size of the plurality of first plate patterns (121). Specifically, the size of each of the plurality of second sub-plate patterns (123b) may be larger than the size of each of the plurality of first plate patterns (121). As described above, a gate driver (GD) may be disposed in each of the plurality of second sub-plate patterns (123b), and a stage of the gate driver (GD) may be disposed in each of the plurality of second sub-plate patterns (123b). Accordingly, since the area occupied by the various circuit configurations constituting a stage of the gate driver (GD) is relatively larger than the area occupied by the pixel (PX), the size of each of the plurality of second sub-plate patterns (123b) may be larger than the size of each of the plurality of first plate patterns (121).

[0054] In FIG. 1, a plurality of second plate patterns (123) are shown arranged on both sides of the first direction (X) in the non-display area (NA), but are not limited thereto and may be arranged in any area of ​​the non-display area (NA). Additionally, a plurality of first plate patterns (121) and a plurality of second plate patterns (123) are shown in a rectangular shape, but are not limited thereto and the plurality of first plate patterns (121) and a plurality of second plate patterns (123) can be modified into various shapes.

[0055] Referring to FIGS. 1 and FIGS. 3, the pattern layer (120) may further include a plurality of first line patterns (122) placed in a display area (AA) and a plurality of second line patterns (124) placed in a non-display area (NA).

[0056] A plurality of first wiring patterns (122) may be placed in the display area (AA). Additionally, the plurality of first wiring patterns (122) may be referred to as first connection patterns as patterns that connect adjacent first plate patterns (121). That is, a plurality of first wiring patterns (122) are placed between the plurality of first plate patterns (121).

[0057] A plurality of second wiring patterns (124) may be placed in a non-display area (NA). Additionally, a plurality of second wiring patterns (124) may connect adjacent first plate patterns (121) and second plate patterns (123). For example, a first plate pattern (121) located at the edge of a display area (AA) may be connected to a second plate pattern (123) placed in an area adjacent to the first plate pattern (121) in the non-display area (NA). Furthermore, a plurality of second wiring patterns (124) may be patterns that connect adjacent second plate patterns (123). Thus, a plurality of second wiring patterns (124) may be referred to as second connection patterns. That is, a plurality of second wiring patterns (124) are placed between adjacent first plate patterns (121) and second plate patterns (123), and between adjacent second plate patterns (123).

[0058] Referring to FIG. 1, a plurality of first wiring patterns (122) and second wiring patterns (124) have a curved shape. For example, a plurality of first wiring patterns (122) and second wiring patterns (124) may have a sinusoidal shape. However, the shape of the plurality of first wiring patterns (122) and second wiring patterns (124) is not limited thereto. For example, the plurality of first wiring patterns (122) and second wiring patterns (124) may extend in a zigzag shape, or may have various shapes such as a plurality of rhombus-shaped substrates connected at vertices and extended. Furthermore, the number and shape of the plurality of first wiring patterns (122) and second wiring patterns (124) shown in FIG. 1 are exemplary, and the number and shape of the plurality of first wiring patterns (122) and second wiring patterns (124) may be varied according to the design.

[0059] Additionally, the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) are rigid patterns. That is, the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) may be rigid compared to the lower substrate (111) and the upper substrate (112). That is, the modulus of elasticity of the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) may be higher than the modulus of elasticity of the lower substrate (111). The modulus of elasticity is a parameter representing the ratio of deformation to stress applied to the substrate, and if the modulus of elasticity is relatively high, the hardness may be relatively high. Accordingly, each of the plurality of first plate patterns (121), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) may be referred to as the plurality of first rigidity patterns, the plurality of second rigidity patterns, the plurality of third rigidity patterns, and the plurality of fourth rigidity patterns. The elastic modulus of the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) may be 1,000 times higher than the elastic modulus of the lower substrate (111) and the upper substrate (112), but is not limited thereto.

[0060] The plurality of rigid substrates, the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124), may be made of a plastic material having lower flexibility than the lower substrate (111) and the upper substrate (112), and may be made of, for example, polyimide (PI), polyacrylate, polyacetate, etc. At this time, the plurality of first plate patterns (121), the plurality of first wiring patterns (122), the plurality of second plate patterns (123), and the plurality of second wiring patterns (124) may be made of the same material, but are not limited thereto and may be made of different materials.

[0061] In some embodiments, the lower substrate (111) may be defined as including a plurality of first lower patterns and a plurality of second lower patterns. The plurality of first lower patterns are disposed in an area of ​​the lower substrate (111) that overlaps with a plurality of first plate patterns (121) and a plurality of second plate patterns (123), and the second lower pattern may be disposed in an area excluding the area where the plurality of first plate patterns (121) and a plurality of second plate patterns (123) are disposed, or may be disposed in the entire area of ​​the display device (100).

[0062] Additionally, the upper substrate (111) may be defined as including a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns are placed in an area overlapping with a plurality of first plate patterns (121) and a plurality of second plate patterns (123) among the upper substrate (111), and the second upper pattern may be placed in an area excluding the area where the plurality of first plate patterns (121) and a plurality of second plate patterns (123) are placed, or may be placed in the entire area of ​​the display device (100).

[0063] At this time, the elastic modulus of the plurality of first lower patterns and first upper substrates may be greater than the elastic modulus of the second lower pattern and second upper pattern. For example, the plurality of first lower patterns and first upper patterns may be made of the same material as the plurality of first plate patterns (121) and the plurality of second plate patterns (123), and the second lower pattern and second upper pattern may be made of a material having a lower elastic modulus than the plurality of first plate patterns (121) and the plurality of second plate patterns (123).

[0064] That is, the first lower pattern and the first upper pattern may be made of polyimide (PI), polyacrylate, polyacetate, etc., and the second lower pattern and the second upper pattern may be made of silicone rubber such as polydimethylsiloxane (PDMS), polyurethane (PU), PTFE (polytetrafluoroethylene), etc., elastomers such as polytetrafluoroethylene.

[0065] <비표시 영역 구동 소자>

[0066] A gate driver (GD) is a component that supplies gate voltage to a plurality of pixels (PX) placed in a display area (AA). The gate driver (GD) includes a plurality of stages formed on a second sub-plate pattern (123b) among a plurality of second plate patterns (123), and each stage of the gate driver (GD) can be electrically connected to one another through a plurality of gate connection wires. Thus, a gate voltage output from one stage can be transmitted to another stage. Additionally, each stage can sequentially supply gate voltage to a plurality of pixels (PX) connected to each stage.

[0067] The power supply (PS) is connected to the gate driver (GD) and can supply gate driving voltage and gate clock voltage. Additionally, the power supply (PS) is connected to a plurality of pixels (PX) and can supply pixel driving voltage to each of the plurality of pixels (PX). Furthermore, the power supply (PS) can be formed on the third sub-plate pattern (123c) among the plurality of second plate patterns (123). That is, the power supply (PS) can be formed adjacent to the gate driver (GD) on the second plate pattern (123). And each of the power supplies (PS) formed on the plurality of third sub-plate patterns (123c) can be electrically connected to the gate driver (GD) and the plurality of pixels (PX). That is, the plurality of power supplies (PS) formed on the plurality of third sub-plate patterns (123c) can be connected by gate power connection wiring and pixel power connection wiring. Accordingly, each of the multiple power supplies (PS) can supply a gate driving voltage, a gate clock voltage, and a pixel driving voltage.

[0068] A printed circuit board (PCB) is configured to transmit signals and voltages from a control unit to a display element for driving the display element. Accordingly, the printed circuit board (PCB) may also be referred to as a driving board. A control unit, such as an IC chip or a circuit unit, may be mounted on the printed circuit board (PCB). Additionally, a memory or processor may be mounted on the printed circuit board (PCB). Furthermore, the printed circuit board (PCB) provided in the display device (100) may include a stretchable area and a non-stretchable area to ensure stretchability. An IC chip, a circuit unit, a memory, a processor, etc., may be mounted in the non-stretchable area, and wiring electrically connected to the IC chip, circuit unit, memory, and processor may be arranged in the stretchable area.

[0069] A data driver (DD) is a component that supplies data voltage to multiple pixels (PX) placed in a display area (AA). The data driver (DD) can be configured in the form of an IC chip and may also be referred to as a data integrated circuit (D-IC). Additionally, the data driver (DD) can be mounted in the non-stretched area of ​​a printed circuit board (PCB). That is, the data driver (DD) can be mounted on the printed circuit board (PCB) in the form of a Chip On Board (COB). However, although FIG. 1 illustrates the data driver (DD) being mounted in the Chip On Board (COB) manner, it is not limited thereto, and the data driver (DD) may be mounted in the form of a Chip On Film (COF), Chip On Glass (COG), Tape Carrier Package (TCP), etc.

[0070] Additionally, in FIG. 1, it is shown that one data driver (DD) is positioned to correspond to a row of first plate patterns (121) placed in the display area (AA), but it is not limited thereto. That is, one data driver (DD) can be positioned to correspond to a plurality of rows of first plate patterns (121).

[0071] Hereinafter, for a more detailed explanation of the display area (AA) of the display device (100) according to one embodiment of the present invention, reference is made to FIG. 4 and FIG. 5 together.

[0072] <표시 영역의 평면 및 단면 구조>

[0073] Figure 4 is a cross-sectional view taken along the cutting line Ⅳ-Ⅳ' shown in Figure 2.

[0074] FIG. 5 is a cross-sectional view taken along the cutting line V-V' shown in FIG. 2.

[0075] For the convenience of explanation, the following description will be made with reference to FIGS. 1 to 3.

[0076] Referring to FIGS. 1 and 2, a plurality of first plate patterns (121) are arranged on a lower substrate (111) in a display area (AA). The plurality of first plate patterns (121) are spaced apart from each other and arranged on the lower substrate (111). For example, the plurality of first plate patterns (121) may be arranged in a matrix form on the lower substrate (111) as shown in FIG. 1, but are not limited thereto.

[0077] Referring to FIGS. 2 and 3, a pixel (PX) including a plurality of subpixels (SPX) is arranged on a first plate pattern (121). Each subpixel (SPX) may include a light-emitting element (170) which is a display element, a driving transistor (160) for driving the light-emitting element (170), and a switching transistor (150). However, the display element in the subpixel (SPX) is not limited to a light-emitting element but may be changed to an organic light-emitting diode. Also, the plurality of subpixels (SPX) may include a red subpixel, a green subpixel, and a blue subpixel, but are not limited thereto, and the colors of the plurality of subpixels (SPX) may be varied as needed.

[0078] A plurality of subpixels (SPX) can be connected to a plurality of pixel connection wires (181, 182). That is, a plurality of subpixels (SPX) can be electrically connected to a first pixel connection wire (181) extending in a first direction (X). And, a plurality of subpixels (SPX) can be electrically connected to a second pixel connection wire (182) extending in a second direction (Y).

[0079] Meanwhile, a plurality of pixel connection lines (181, 182) placed in the display area (AA) may be referred to as the first connection lines, and a buffer line, gate connection line, or power line placed in the non-display area (NA) may be referred to as the second connection lines.

[0080] Below, the cross-sectional structure of the display area (AA) will be described in detail with reference to FIG. 3.

[0081] Referring to FIG. 3, a plurality of inorganic insulating layers are disposed on a plurality of first plate patterns (121). For example, the plurality of inorganic insulating layers may include a buffer layer (141), a gate insulating layer (142), a first interlayer insulating layer (143), a second interlayer insulating layer (144), and a passivation layer (145), but are not limited thereto. Various inorganic insulating layers may be additionally disposed on the plurality of first plate patterns (121), or one or more of the inorganic insulating layers, such as the buffer layer (141), the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145), may be omitted.

[0082] Specifically, a buffer layer (141) is disposed on a plurality of first plate patterns (121). The buffer layer (141) is formed on the plurality of first plate patterns (121) to protect various components of the display device (100) from the penetration of moisture (H2O) and oxygen (O2), etc., from outside the lower substrate (111) and the plurality of first plate patterns (121). The buffer layer (141) may be composed of an insulating material. For example, the buffer layer (141) may be composed of a single layer or a multilayer made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). However, the buffer layer (141) may be omitted depending on the structure or characteristics of the display device (100).

[0083] In the display area (AA), the buffer layer (141) may be formed only in the area where the lower substrate (111) overlaps with the plurality of first plate patterns (121). As described above, since the buffer layer (141) may be made of an inorganic material, it may be easily damaged, such as by cracking, during the process of stretching the display device (100). Accordingly, in the display area (AA), the buffer layer (141) may not be formed in the area between the plurality of first plate patterns (121), but may be formed only on the upper part of the plurality of first plate patterns (121) by being patterned in the shape of the plurality of first plate patterns (121).

[0084] Additionally, in the non-display area (NA), the buffer layer (141) may be formed only in the area where the lower substrate (111) overlaps with the plurality of second plate patterns (123). As described above, since the buffer layer (141) may be made of an inorganic material, it may be easily damaged, such as by cracking, during the process of stretching the display device (100). Accordingly, in the non-display area (NA), the buffer layer (141) may not be formed in the area between the plurality of second plate patterns (123), but may be patterned in the shape of the plurality of second plate patterns (123) and formed only on the upper part of the plurality of second plate patterns (123).

[0085] In this way, the buffer layer (141) may be formed only in the area where the lower substrate (111) overlaps with the plurality of first plate patterns (121) and the plurality of second plate patterns (123). As described above, since the buffer layer (141) may be made of an inorganic material, it may be easily damaged, such as by cracking, during the process of stretching the display device (100). Accordingly, the buffer layer (141) may not be formed in the area between the plurality of first plate patterns (121) and the plurality of second plate patterns (123), but may be formed only on the upper part of the plurality of first plate patterns (121) and the plurality of second plate patterns (123) by patterning it in the shape of the plurality of first plate patterns (121) and the plurality of second plate patterns (123). Accordingly, a display device (100) according to one embodiment of the present invention forms a buffer layer (141) only in the area overlapping with a plurality of first plate patterns (121) and a plurality of second plate patterns (123), which are rigid patterns, thereby preventing damage to various components of the display device (100) even when the display device (100) is deformed, such as by bending or stretching. In addition, the buffer layer (141)

[0086] Referring to FIG. 3, a switching transistor (150) including a gate electrode (151), an active layer (152), a source electrode (153), and a drain electrode (154) and a driving transistor (160) including a gate electrode (161), an active layer (162), a source electrode, and a drain electrode (164) are formed on the buffer layer (141).

[0087] First, referring to FIG. 3, an active layer (152) of a switching transistor (150) and an active layer (162) of a driving transistor (160) are disposed on a buffer layer (141). For example, each of the active layer (152) of the switching transistor (150) and the active layer (162) of the driving transistor (160) may be formed of an oxide semiconductor, or the active layer (152) of the switching transistor (150) and the active layer (162) of the driving transistor (160) may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor, etc.

[0088] A gate insulating layer (142) is disposed on the active layer (152) of the switching transistor (150) and the active layer (162) of the driving transistor (160). The gate insulating layer (142) is a layer for electrically insulating the gate electrode (151) of the switching transistor (150) from the active layer (152) of the switching transistor (150), and for electrically insulating the gate electrode (161) of the driving transistor (160) from the active layer (162) of the driving transistor (160). Additionally, the gate insulating layer (142) may be made of an insulating material. For example, the gate insulating layer (142) may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0089] On the gate insulating layer (142), the gate electrode (151) of the switching transistor (150) and the gate electrode (161) of the driving transistor (160) are disposed. The gate electrode (151) of the switching transistor (150) and the gate electrode (161) of the driving transistor (160) are disposed spaced apart from each other on the gate insulating layer (142). Then, the gate electrode (151) of the switching transistor (150) overlaps with the active layer (152) of the switching transistor (150), and the gate electrode (161) of the driving transistor (160) overlaps with the active layer (162) of the driving transistor (160).

[0090] Each of the gate electrode (151) of the switching transistor (150) and the gate electrode (161) of the driving transistor (160) may be any one of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these, or a multilayer thereof, but is not limited thereto.

[0091] A first interlayer insulating layer (143) is disposed on the gate electrode (151) of the switching transistor (150) and the gate electrode (161) of the driving transistor (160). The first interlayer insulating layer (143) insulates the gate electrode (161) of the driving transistor (160) from the intermediate metal layer (IM). The first interlayer insulating layer (143) may be made of an inorganic material, just like the buffer layer (141). For example, the first interlayer insulating layer (143) may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0092] An intermediate metal layer (IM) is disposed on the first interlayer insulating layer (143). The intermediate metal layer (IM) overlaps with the gate electrode (161) of the driving transistor (160). Accordingly, a storage capacitor is formed in the overlapping region between the intermediate metal layer (IM) and the gate electrode (161) of the driving transistor (160). Specifically, the gate electrode (161) of the driving transistor (160), the first interlayer insulating layer (143), and the intermediate metal layer (IM) form a storage capacitor. However, the placement region of the intermediate metal layer (IM) is not limited thereto, and the intermediate metal layer (IM) can overlap with other electrodes to form various storage capacitors.

[0093] The intermediate metal layer (IM) may be any one of various metallic materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these, or a multilayer thereof, but is not limited thereto.

[0094] A second interlayer insulating layer (144) is disposed on the intermediate metal layer (IM). The second interlayer insulating layer (144) insulates the gate electrode (151) of the switching transistor (150) from the source electrode (153) and drain electrode (154) of the switching transistor (150). Additionally, the second interlayer insulating layer (144) insulates the intermediate metal layer (IM) from the source electrode and drain electrode (164) of the driving transistor (160). The second interlayer insulating layer (144) may be made of an inorganic material, just like the buffer layer (141). For example, the first interlayer insulating layer (143) may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0095] The source electrode (153) and drain electrode (154) of the switching transistor (150) are disposed on the second interlayer insulating layer (144). Then, the source electrode and drain electrode (164) of the driving transistor (160) are disposed on the second interlayer insulating layer (144). The source electrode (153) and drain electrode (154) of the switching transistor (150) are disposed spaced apart from each other on the same layer. Also, although the source electrode of the driving transistor (160) is omitted in FIG. 3, the source electrode of the driving transistor (160) is also disposed spaced apart from the drain electrode (164) on the same layer. In the switching transistor (150), the source electrode (153) and drain electrode (154) can be electrically connected to the active layer (152) in a manner that contacts the active layer (152). In addition, in the driving transistor (160), the source electrode and the drain electrode (164) can be electrically connected to the active layer (162) in a manner that contacts the active layer (162). In addition, the drain electrode (154) of the switching transistor (150) can be electrically connected to the gate electrode (161) of the driving transistor (160) in a manner that contacts the gate electrode (161) of the driving transistor (160) through a contact hole.

[0096] The source electrode (153) and drain electrode (154, 164) may be any one of various metallic materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these, or a multilayer thereof, but are not limited thereto.

[0097] Additionally, although the driving transistor (160) is described in this specification as having a coplanar structure, various transistors such as a staggered structure may also be used.

[0098] A gate pad (GP) and a data pad (DP) can be placed on the second interlayer insulation layer (144).

[0099] Specifically, referring to FIG. 4, the gate pad (GP) is a pad for transmitting a gate voltage to a plurality of subpixels (SPX). The gate pad (GP) is connected to the first pixel connection wiring (181) through a contact hole. Then, the gate voltage supplied from the first pixel connection wiring (181) can be transmitted from the gate pad (GP) to the gate electrode (151) of the switching transistor (150) through wiring formed on the first plate pattern (121).

[0100] And, the data pad (DP) is a pad for transmitting data voltage to a plurality of subpixels (SPX). The data pad (DP) is connected to the second pixel connection wiring (182) through a contact hole. And, the data voltage supplied from the second pixel connection wiring (182) can be transmitted from the data pad (DP) to the source electrode (153) of the switching transistor (150) through the wiring formed on the first plate pattern (121).

[0101] The gate pad (GP) and data pad (DP) may be made of the same material as the source electrode (153) and drain electrode (154, 164), but are not limited thereto.

[0102] Referring to FIG. 3, a passivation layer (145) is formed on a switching transistor (150) and a driving transistor (160). That is, the passivation layer (145) covers the switching transistor (150) and the driving transistor (160) to protect them from the penetration of moisture and oxygen. The passivation layer (145) may be made of an inorganic material and may be a single layer or a multilayer, but is not limited thereto.

[0103] Additionally, the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145) may be formed only in the area that overlaps with the plurality of first plate patterns (121) by patterning. Since the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145) may also be made of inorganic material, just like the buffer layer (141), they may be easily damaged, such as by cracks, during the process of stretching the display device (100). Accordingly, the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145) may not be formed in the area between the plurality of first plate patterns (121), but may be formed only on the upper part of the plurality of first plate patterns (121) by patterning in the shape of the plurality of first plate patterns (121).

[0104] A flattening layer (146) is formed on the passivation layer (145). The flattening layer (146) flattens the upper portion of the switching transistor (150) and the driving transistor (160). The flattening layer (146) may be composed of a single layer or multiple layers and may be made of an organic material. Accordingly, the flattening layer (146) may be referred to as an organic insulating layer. For example, the flattening layer (146) may be made of an acrylic-based organic material, but is not limited thereto.

[0105] Referring to FIG. 3, the flattening layer (146) may be arranged to cover the upper and side surfaces of the buffer layer (141), gate insulating layer (142), first interlayer insulating layer (143), second interlayer insulating layer (144), and passivation layer (145) on a plurality of first plate patterns (121). Additionally, the flattening layer (146) surrounds the buffer layer (141), gate insulating layer (142), first interlayer insulating layer (143), second interlayer insulating layer (144), and passivation layer (145) together with the plurality of first plate patterns (121). Specifically, the flattening layer (146) may be positioned to cover the upper and side surfaces of the passivation layer (145), the side surface of the first interlayer insulating layer (143), the side surface of the second interlayer insulating layer (144), the side surface of the gate insulating layer (142), the side surface of the buffer layer (141), and a portion of the upper surface of a plurality of first plate patterns (121). Accordingly, the flattening layer (146) can compensate for the step difference on the side surfaces of the buffer layer (141), the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145), and can increase the adhesive strength of the pixel connection wiring (181, 182) positioned on the side surfaces of the flattening layer (146) and the flattening layer (146).

[0106] Referring to FIG. 3, the angle of inclination of the side of the flattening layer (146) may be smaller than the angle of inclination formed by the sides of the buffer layer (141), the gate insulating layer (142), the first interlayer insulating layer (143), the second interlayer insulating layer (144), and the passivation layer (145). For example, the side of the flattening layer (146) may have a gentler slope than the slope formed by the side of the passivation layer (145), the side of the first interlayer insulating layer (143), the side of the second interlayer insulating layer (144), the side of the gate insulating layer (142), and the side of the buffer layer (141). Accordingly, the pixel connection wiring (181, 182) arranged in contact with the side of the flattening layer (146) is arranged with a gentle slope, so that when the display device (100) is stretched, the stress generated in the pixel connection wiring (181, 182) is reduced, and the phenomenon of the pixel connection wiring (181, 182) cracking or peeling off from the side of the flattening layer (146) can be suppressed.

[0107] Referring to FIGS. 2 to 4, pixel connection wiring (181, 182) refers to wiring that electrically connects pads on a plurality of first plate patterns (121). Pixel connection wiring (181, 182) is placed on a plurality of first wiring patterns (122). Additionally, pixel connection wiring (181, 182) may extend onto a plurality of first plate patterns (121) to be electrically connected to gate pads (GP) and data pads (DP) on a plurality of first plate patterns (121). Referring to FIG. 5, in the area between the plurality of first plate patterns (121) where pixel connection wiring (181, 182) is not placed, the first wiring pattern (122) is not placed.

[0108] The pixel connection wiring (181, 182) includes a first pixel connection wiring (181) and a second pixel connection wiring (182). The first pixel connection wiring (181) and the second pixel connection wiring (182) are arranged between a plurality of first plate patterns (121). Specifically, the first pixel connection wiring (181) refers to a wiring that extends in the X-axis direction between a plurality of first plate patterns (121) among the pixel connection wirings (181, 182), and the second pixel connection wiring (182) refers to a wiring that extends in the Y-axis direction between a plurality of first plate patterns (121) among the pixel connection wirings (181, 182).

[0109] The pixel connection wiring (181, 182) may be made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or a stacked structure of a metal material such as copper / molybdenum-titanium (Cu / Moti) or titanium / aluminum / titanium (Ti / Al / Ti), but is not limited thereto.

[0110] In the case of a typical display device, various wirings such as multiple gate wirings and multiple data wirings are arranged to extend in a straight line between multiple subpixels, and multiple subpixels are connected to a single signal wiring. Accordingly, in the case of a typical display device, various wirings such as gate wirings, data wirings, high-potential power wirings, and reference voltage wirings extend from one side to the other of an organic light-emitting display device without interruption on a substrate.

[0111] In contrast, in the case of a display device (100) according to one embodiment of the present invention, various wirings such as straight-shaped gate wiring, data wiring, high-potential power wiring, and reference voltage wiring, which can be seen as used in general organic light-emitting display devices, are placed only on a plurality of first plate patterns (121) and a plurality of second plate patterns (123). That is, in the display device (100) according to one embodiment of the present invention, straight-shaped wiring can be placed only on a plurality of first plate patterns (121) and a plurality of second plate patterns (123).

[0112] In a display device (100) according to one embodiment of the present invention, in order to connect discontinuous wiring on a first plate pattern (121) or a second plate pattern (123), pads on two adjacent first plate patterns (121) or two adjacent second plate patterns (123) may be connected by pixel connection wiring (181, 182). That is, the pixel connection wiring (181, 182) electrically connects a gate pad (GP) or a data pad (DP) on two adjacent first plate patterns (121). Accordingly, a display device (100) according to one embodiment of the present invention may include a plurality of pixel connection wirings (181, 182) to electrically connect various wirings, such as gate wiring, data wiring, high potential power wiring, reference voltage wiring, etc., between a plurality of first plate patterns (121) and a plurality of second plate patterns (123). For example, gate wiring may be disposed on a plurality of first plate patterns (121) arranged adjacently in the first direction (X), and gate pads (GP) may be disposed at both ends of the gate wiring. At this time, each of the plurality of gate pads (GP) on the plurality of first plate patterns (121) arranged adjacently in the first direction (X) may be connected to one another by a first pixel connection wiring (181) that functions as gate wiring. Accordingly, the gate wiring disposed on the plurality of first plate patterns (121) and the first pixel connection wiring (181) disposed on the second plate pattern (123) may function as a single gate wiring. In addition, among all the various wirings that may be included in the display device (100), wiring extending in the first direction (X), for example, light emission signal wiring, low potential power wiring, and high potential power wiring, may also be electrically connected by the first pixel connection wiring (181) as described above.

[0113] Referring to FIGS. 2 and 4, the first pixel connection wiring (181) can connect two gate pads (GP) on a first plate pattern (121) that are arranged side by side among a plurality of gate pads (GP) on a plurality of first plate patterns (121) arranged adjacently in the first direction (X). The first pixel connection wiring (181) can function as a gate wiring, a light emission signal wiring, a high potential power supply wiring, or a low potential power supply wiring, but is not limited thereto. For example, the first pixel connection wiring (181) can function as a gate wiring and can electrically connect two gate pads (GP) on a first plate pattern (121) arranged side by side in the first direction (X). Accordingly, as previously described, gate pads (GP) on a plurality of first plate patterns (121) arranged in the first direction (X) can be connected by the first pixel connection wiring (181) that functions as a gate wiring, and a gate voltage can be transmitted.

[0114] And, referring to FIG. 3, the second pixel connection wiring (182) can connect two data pads (DPs) on a first plate pattern (121) that are arranged side by side among the data pads (DPs) on a plurality of first plate patterns (121) arranged adjacently in the second direction (Y). The second pixel connection wiring (182) can function as a data wiring, a high-potential power wiring, a low-potential power wiring, or a reference voltage wiring, but is not limited thereto. For example, the second pixel connection wiring (182) can function as a data wiring and can electrically connect the data wirings on two first plate patterns (121) arranged side by side in the second direction (Y). Accordingly, as previously described, the internal wiring on a plurality of first plate patterns (121) arranged in the second direction (Y) can be connected by a plurality of second pixel connection wirings (182) that function as data wiring, and a single data voltage can be transmitted.

[0115] As shown in FIG. 4, the first pixel connection wiring (181) may be formed by extending to the upper surface of the first wiring pattern (122) while in contact with the upper and side surfaces of the flattening layer (146) placed on the first plate pattern (121). Additionally, as shown in FIG. 3, the second pixel connection wiring (182) may be formed by extending to the upper surface of the first wiring pattern (122) while in contact with the upper and side surfaces of the flattening layer (146) placed on the first plate pattern (121).

[0116] However, as shown in FIG. 5, since there is no need to place a rigid pattern in the area where the first pixel connection wiring (181) and the second pixel connection wiring (182) are not placed, the first wiring pattern (122), which is a rigid pattern, is not placed below the first pixel connection wiring (181) and the second pixel connection wiring (182).

[0117] Meanwhile, referring to FIG. 3, a bank (147) is formed on a connection pad (CNT), pixel connection wiring (181, 182), and a flattening layer (146). The bank (147) is a component that separates adjacent subpixels (SPX). The bank (147) is positioned to cover at least a portion of the pad (PD), pixel connection wiring (181, 182), and the flattening layer (146). The bank (147) may be made of an insulating material. Additionally, the bank (147) may be made of a black material. By including a black material, the bank (147) serves to obscure wiring that can be seen through the display area (AA). The bank (147) may be made of, for example, a transparent carbon-based mixture, and specifically may include carbon black. However, it is not limited thereto, and the bank (147) may also be made of a transparent insulating material. Also, in FIG. 3, the height of the bank (147) is shown to be lower than the height of the light-emitting element (170), but is not limited thereto, and the height of the bank (147) may be equal to the height of the light-emitting element (170).

[0118] Referring to FIG. 3, a light-emitting element (170) is disposed on a connection pad (CNT) and a first pixel connection wiring (181). The light-emitting element (170) includes an n-type layer (171), an active layer (172), a p-type layer (173), an n-electrode (174), and a p-electrode (175). The light-emitting element (170) of a display device (100) according to one embodiment of the present invention has a flip-chip structure in which an n-electrode (174) and a p-electrode (175) are formed on one side.

[0119] The n-type layer (171) can be formed by injecting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer (171) may also be placed on a separate base substrate made of a material capable of emitting light.

[0120] An active layer (172) is disposed on the n-type layer (171). The active layer (172) is a light-emitting layer that emits light from the light-emitting element (170) and may be made of a nitride semiconductor, for example, indium gallium nitride (InGaN). A p-type layer (173) is disposed on the active layer (172). The p-type layer (173) may be formed by injecting p-type impurities into gallium nitride (GaN).

[0121] A light-emitting element (170) according to one embodiment of the present invention is manufactured by sequentially stacking an n-type layer (171), an active layer (172), and a p-type layer (173) as described above, and then etching a predetermined portion to form an n-electrode (174) and a p-electrode (175). At this time, the predetermined portion is a space to separate the n-electrode (174) and the p-electrode (175), and the predetermined portion is etched so that a part of the n-type layer (171) is exposed. In other words, the surface of the light-emitting element (170) on which the n-electrode (174) and the p-electrode (175) are placed may have different height levels rather than being a flattened surface.

[0122] In this way, an n-electrode (174) is disposed in the etched region, and the n-electrode (174) may be made of a conductive material. And, a p-electrode (175) is disposed in the unetched region, and the p-electrode (175) may also be made of a conductive material. For example, an n-electrode (174) is disposed on the n-type layer (171) exposed by the etching process, and a p-electrode (175) is disposed on the p-type layer (173). The p-electrode (175) may be made of the same material as the n-electrode (174).

[0123] An adhesive layer (AD) is disposed between the upper surface of the connection pad (CNT) and the first pixel connection wiring (181) and the connection pad (CNT) and the first pixel connection wiring (181), so that a light-emitting element (170) can be adhered to the connection pad (CNT) and the first pixel connection wiring (181). At this time, the n-electrode (174) can be disposed on the first pixel connection wiring (181), and the p-electrode (175) can be disposed on the connection pad (CNT).

[0124] The adhesive layer (AD) may be a conductive adhesive layer in which conductive balls are dispersed on an insulating base member. Accordingly, when heat or pressure is applied to the adhesive layer (AD), the conductive balls in the area where heat or pressure is applied may be electrically connected to possess conductive properties, while the area where no pressure is applied may possess insulating properties. For example, the n-electrode (174) is electrically connected to the first pixel connection wiring (181) through the adhesive layer (AD), and the p-electrode (175) is electrically connected to the connection pad (CNT) through the adhesive layer (AD). After applying the adhesive layer (AD) to the upper surface of the first pixel connection wiring (181) and the connection pad (CNT) by means such as inkjet, the light-emitting element (170) is transferred onto the adhesive layer (AD), and the connection pad (CNT) and the p-electrode (175) and the first pixel connection wiring (181) and the n-electrode (174) can be electrically connected by applying pressure and heat to the light-emitting element (170). However, other parts of the adhesive layer (AD), excluding the part of the adhesive layer (AD) disposed between the n-electrode (174) and the first pixel connection wiring (181) and the part of the adhesive layer (AD) disposed between the p-electrode (175) and the connection pad (CNT), have insulating properties. Meanwhile, the adhesive layer (AD) may be disposed in a separated form on the connection pad (CNT) and the first pixel connection wiring (181), respectively.

[0125] Then, the connection pad (CNT) is electrically connected to the drain electrode (164) of the driving transistor (160) and receives a driving voltage for driving the light-emitting element (170) from the driving transistor (160). Then, a low-potential driving voltage for driving the light-emitting element (170) is applied to the first pixel connection wiring (181). Accordingly, when the display device (100) is turned on, different voltage levels applied to the connection pad (CNT) and the first pixel connection wiring (181) are transmitted to the n-electrode (174) and the p-electrode (175), respectively, causing the light-emitting element (170) to emit light.

[0126] The upper substrate (112) is a substrate that supports various components placed below the upper substrate (112). Specifically, the upper substrate (112) can be formed by coating a material constituting the upper substrate (112) onto the lower substrate (111) and the first plate pattern (121) and then curing it, so as to be placed in contact with the lower substrate (111), the first plate pattern (121), the first wiring pattern (122), and the pixel connection wiring (181, 182).

[0127] The upper substrate (112) may be made of the same material as the lower substrate (111). For example, the upper substrate (112) may be made of silicone rubber such as polydimethylsiloxane (PDMS), polyurethane (PU), or an elastomer such as PTFE (polytetrafluoroethylene), and thus may have flexible properties. However, the material of the upper substrate (112) is not limited thereto.

[0128] Meanwhile, although not shown in FIG. 3, a polarizing layer may be disposed on the upper substrate (112). The polarizing layer may function to reduce external light reflection by polarizing light incident from outside the display device (100). Additionally, an optical film other than the polarizing layer may be disposed on the upper substrate (112).

[0129] Additionally, a filling layer (190) may be disposed on the front surface of the lower substrate (111) to fill the space between the upper substrate (112) and the components disposed on the lower substrate (111). The filling layer (190) may be composed of a curable adhesive. Specifically, the filling layer (190) may be disposed between the components disposed on the upper substrate (112) and the lower substrate (111) by forming the material constituting the filling layer (190) by coating it on the front surface of the lower substrate (111) and then curing it. For example, the filling layer (190) may be an OCA (optically clear adhesive) and may be composed of acrylic adhesives, silicone adhesives, urethane adhesives, etc.

[0130] <표시 영역의 회로 구조>

[0131] FIG. 6 is a circuit diagram of a subpixel of a display device according to one embodiment of the present invention.

[0132] For convenience of explanation, the structure and operation thereof when the subpixel (SPX) of a display device according to one embodiment of the present invention is a pixel circuit of 2T (Transistor) 1C (Capacitor) are described below, but the present invention is not limited thereto.

[0133] Referring to FIGS. 3 and FIGS. 6, a subpixel (SPX) of a display device according to one embodiment of the present invention may be configured to include a switching transistor (150), a driving transistor (160), a storage capacitor (C), and a light-emitting element (170).

[0134] The switching transistor (150) applies a data signal (DATA) supplied through the second pixel connection wire (182) to the driving transistor (160) and the storage capacitor (C) according to the gate signal (SCAN) supplied through the first pixel connection wire (181).

[0135] And, the gate electrode (151) of the switching transistor (150) is electrically connected to the first pixel connection wire (181), the source electrode (153) of the switching transistor (150) is connected to the second pixel connection wire (182), and the drain electrode (154) of the switching transistor (150) is connected to the gate electrode (161) of the driving transistor (160).

[0136] The driving transistor (160) can operate to allow a driving current to flow according to the high potential power supply (VDD) supplied through the first pixel connection wiring (181) and the data voltage (DATA) in response to the data voltage (DATA) stored in the storage capacitor (C).

[0137] And, the gate electrode (161) of the driving transistor (160) is electrically connected to the drain electrode (154) of the switching transistor (150), the source electrode of the driving transistor (160) is connected to the first pixel connection wiring (181), and the drain electrode (164) of the driving transistor (160) is connected to the light-emitting element (170).

[0138] The light-emitting element (170) can be operated to emit light according to the driving current formed by the driving transistor (160). And, as described above, the n-electrode (174) of the light-emitting element (170) is connected to the first pixel connection wiring (181) so that a low potential power supply (VSS) is applied, and the p-electrode (174) of the light-emitting element (170) is connected to the drain electrode (164) of the driving transistor (160) so that a driving voltage corresponding to the driving current is applied.

[0139] A subpixel (SPX) of a display device according to one embodiment of the present invention is configured as a 2T1C structure including a switching transistor (150), a driving transistor (160), a storage capacitor (C), and a light-emitting element (170), but can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc. when a compensation circuit is added.

[0140] As described above, a display device according to one embodiment of the present invention may include a plurality of subpixels on a first substrate which is a rigid substrate, and each of the plurality of subpixels (SPX) may be configured to include a switching transistor, a driving transistor storage capacitor, and a light-emitting element.

[0141] Accordingly, a display device according to one embodiment of the present invention can be stretched by a lower substrate, and each first substrate is provided with a pixel circuit of a 2T1C structure, so that light can be emitted according to the data voltage in accordance with each gate timing.

[0142] <비표시 영역의 패턴층>

[0143] FIG. 7 is an enlarged plan view of a non-display area of ​​a display device according to one embodiment of the present invention.

[0144] Specifically, FIG. 7 is an enlarged plan view of area B shown in FIG. 1. For reference, in FIG. 7, a thin wavy line indicates that only the second wiring pattern is placed, and a thick wavy line indicates that the second connecting wiring, such as buffer wiring, gate connecting wiring, or power wiring, is placed on the second wiring pattern.

[0145] As illustrated in FIG. 7, the non-display area (NA) includes a first area (A1) located outside the display area (AA), a second area (A2) located outside the first area (A1), and a third area (A3) located outside the second area (A2). For example, the non-display area (NA) includes a first area (A1) positioned adjacent to the display area (AA), a second area (A2) positioned adjacent to the first area (A1), and a third area (A3) positioned adjacent to the second area (A2). The second area (A2) may be positioned between the first area (A1) and the third area (A3).

[0146] And, an anchor hole (AH) is placed in the first area (A1), a gate driver (GD) is placed in the second area (A2), and a power block (PB) constituting a power supply (PS) is placed in the third area (A3).

[0147] That is, based on the first direction (X), the first area (A1), the second area (A2), and the third area (A3) are sequentially located outside the display area (AA). Accordingly, based on the first direction (X), the anchor hole (AH), the gate driver (GD), and the power supply (PS) are sequentially arranged in the area adjacent to the display area (AA).

[0148] In the non-display area (NA), a plurality of second plate patterns (123) in which a gate driver (GD) and a power supply (PS) are formed may be arranged. Additionally, a second wiring pattern (124) is arranged to connect the adjacent first plate pattern (121) and the second plate pattern (123), and to connect the adjacent plurality of second plate patterns (123). The second wiring pattern (124) may be referred to as a second connection pattern. For example, the second wiring pattern (124) may be arranged between the adjacent first plate pattern (121) and the second plate pattern (123), and the second wiring pattern (124) may be arranged between the adjacent plurality of second plate patterns (123).

[0149] Specifically, a plurality of second plate patterns (123) disposed in a non-display area (NA) include a plurality of first sub-plate patterns (123a) disposed in a first area (A1) and having an anchor hole (AH), a plurality of second sub-plate patterns (123b) disposed in a second area (A2) and having a gate driver (GD), and a plurality of third sub-plate patterns (123c) disposed in a third area (A3) and having a power supply (PS).

[0150] More specifically, on one side of the non-display area (NA), a plurality of first sub-plate patterns (123a) are arranged in a row along the second direction (Y) in the first area (A1), a plurality of second sub-plate patterns (123b) are arranged in a row along the second direction (Y) in the second area (A2), and a plurality of third sub-plate patterns (123c) are arranged in a row along the second direction (Y) in the third area (A3).

[0151] For example, a plurality of first sub-plate patterns (123a) may be placed in a first area (A1) and spaced apart from each other only in a second direction (Y), a plurality of second sub-plate patterns (123b) may be placed in a second area (A2) and spaced apart from each other only in a second direction (Y), and a plurality of third sub-plate patterns (123c) may be placed in a third area (A3) and spaced apart from each other in a first direction (X) and a second direction (Y).

[0152] Additionally, the size of the plurality of first sub-plate patterns (123a) may be smaller than the size of the plurality of second sub-plate patterns (123b). Specifically, the size of each of the plurality of first sub-plate patterns (123a) may be smaller than the size of each of the plurality of second sub-plate patterns (123b). As described above, an anchor hole (AH) may be placed in each of the plurality of first sub-plate patterns (123a). Furthermore, the area of ​​the anchor hole (AH) placed in the plurality of first sub-plate patterns (123a) may be smaller than the area of ​​the gate driver (GD) placed in the plurality of second sub-plate patterns (123b).

[0153] And, a plurality of second wiring patterns (124) placed in a non-display area (NA) include a first sub-wiring pattern (124a) located in a first area (A1), a second sub-wiring pattern (124b) located in a second area (A2), and a third sub-wiring pattern (124c) located in a third area (A3).

[0154] The first sub-wiring pattern (124a) can connect the first plate pattern (121) placed in the display area (AA) and the first sub-plate pattern (123a) of the second plate pattern (123) placed in the non-display area (NA). Additionally, the first sub-wiring pattern (124a) connects the first sub-plate pattern (123a) placed in the non-display area (NA) and the second sub-plate pattern (123b).

[0155] More specifically, the first sub-wiring pattern (124a) may include a first-1 sub-wiring pattern (124a-1) and a first-2 sub-wiring pattern (124a-2). The first-1 sub-wiring pattern (124a-1) extends in a first direction (X) and may connect the first plate pattern (121) and the first sub-plate pattern (123a), and may connect the first sub-plate pattern (123a) and the second sub-plate pattern (123b). Additionally, the first-2 sub-wiring pattern (124a-2) extends in a second direction (Y) and may connect a plurality of first sub-plate patterns (123a).

[0156] The second sub-wiring pattern (124b) extends in the second direction (Y) and connects a plurality of second sub-plate patterns (123b).

[0157] Additionally, the third sub-wiring pattern (124c) includes a third-1 sub-wiring pattern (124c-1) and a third-2 sub-wiring pattern (124c-2). The third-1 sub-wiring pattern (124c-1) extends in a first direction (X) and can connect a third sub-plate pattern (123c) spaced apart in the first direction (X). Additionally, the third-2 sub-wiring pattern (124c-2) extends in a second direction (Y) and can connect a plurality of third sub-plate patterns (123c) spaced apart in the second direction (Y).

[0158] Meanwhile, a plurality of gate connection wires (184) are arranged on the second sub-wiring pattern (124b) arranged in the second region (A2) so that a plurality of gate drivers (GD) can be electrically connected. That is, a gate driving voltage and a gate clock voltage are applied to the plurality of gate connection wires (184) arranged on the second sub-wiring pattern (124b) so that each of the plurality of gate drivers (GD) can output a gate voltage. However, although FIG. 7 is illustrated as having gate connection wires (184) arranged only on some of the plurality of second sub-wiring patterns (124b), it is not limited thereto, and gate connection wires (184) can be arranged on all of the plurality of second sub-wiring patterns (124b).

[0159] Additionally, the gate connection wiring (184) formed on the second sub-wiring pattern (124b) may have the same shape as the second sub-wiring pattern (124b). Specifically, each of the plurality of gate connection wirings (184) may have a curved shape. For example, each of the plurality of gate connection wirings (184) may have a sinusoidal shape. However, the shape of each of the plurality of gate connection wirings (184) is not limited thereto; for example, each of the plurality of gate connection wirings (184) may extend in a zigzag shape, or may have various shapes such as multiple rhombus-shaped substrates being connected at vertices and extended. Furthermore, the number and shape of each of the plurality of gate connection wirings (184) shown in FIG. 8 are exemplary, and the number and shape of each of the plurality of gate connection wirings (184) may be varied according to the design.

[0160] However, in FIG. 7, gate connection wiring (184) is not placed on all second sub-wiring patterns (124b), and there may also be second sub-wiring patterns (124b) on which gate connection wiring (184) is not placed. The second sub-wiring patterns (124b) on which gate connection wiring (184) is not placed, as described above, may be structures additionally placed to secure rigidity for elongation in the second direction (Y).

[0161] <제1 영역의 구성>

[0162] FIG. 8 is an enlarged plan view of a first area of ​​a display device according to one embodiment of the present invention.

[0163] FIG. 9 is a cross-sectional view taken along the cutting line IX-IX' shown in FIG. 8.

[0164] As illustrated in FIG. 8, a buffer wiring (183), which is wiring connecting a gate driver (GD) and a plurality of pixels (PX), is disposed in the first region (A1). Additionally, an anchor hole (AH) for fixing the buffer wiring (183) may be disposed in the first region (A1). For example, the buffer wiring (183) may be formed on a first sub-wiring pattern (124a) connecting a first plate pattern (121) and a first sub-plate pattern (123a), thereby connecting a gate driver (GD) disposed on the first sub-plate pattern (123a) and a pixel (PX) disposed on the first plate pattern (121).

[0165] Also, referring to FIG. 8, the width of both ends of the first-1 sub-wiring pattern (124a-1) located between the first plate pattern (121) and the first sub-plate pattern (123a) may be greater than the width of the central area of ​​the first-1 sub-wiring pattern (124a-1). Additionally, the width of both ends of the first-1 sub-wiring pattern (124a-1) formed between the first sub-plate pattern (123a) and the second sub-plate pattern (123b) may also be greater than the width of the central area.

[0166] Accordingly, in the buffer wiring (183) formed on the first-1 sub-wiring pattern (124a-1), the width of the buffer wiring (183) placed in the area overlapping with the first plate pattern (121), the first sub-plate pattern (123a), or the second sub-plate pattern (123b) may be greater than the width of the buffer wiring (183) placed in the area overlapping with the first-1 sub-wiring pattern (124a-1).

[0167] That is, since the width of the central region of the buffer wiring (183) is relatively thin, the buffer wiring (183) can be stretched with less force. Accordingly, the elongation rate of the buffer wiring (183) can be improved. Also, since the width of both ends of the buffer wiring (183) is relatively thick, the area where the buffer wiring (183) can be fixed by contacting the first plate pattern (121), the first sub-plate pattern (123a), or the second sub-plate pattern (123b) is increased. Accordingly, even if the buffer wiring (183) is repeatedly stretched, it may not be separated from the first plate pattern (121), the first sub-plate pattern (123a), or the second sub-plate pattern (123b). Accordingly, the elongation reliability of the buffer wiring (183) can be improved.

[0168] Each buffer wire (183) is extended in a first direction (X) to connect a gate driver (GD) and a plurality of pixels (PX), and the plurality of buffer wires (183) are arranged in a second direction (Y).

[0169] And a plurality of buffer wirings (183) are arranged across the first sub-plate pattern (123a) and the first sub-wiring pattern (124a). Specifically, the first sub-wiring pattern (124a) is composed of a first-1 sub-wiring pattern (124a-1) extending in the first direction (X) and a first-2 sub-wiring pattern (124a-2) extending in the second direction (Y), but the buffer wiring (183) extends only in the first direction (X). Accordingly, the buffer wiring (183) can be formed on the first sub-plate pattern (123a) and the first-1 sub-wiring pattern (124a-1). And, the buffer wiring (183) may not be formed on the first-2 sub-wiring pattern (124a-2). Additionally, the buffer wiring (183) formed on the first-1 sub-wiring pattern (124a-1) may have the same shape as the first-1 sub-wiring pattern (124a-1). Specifically, each of the plurality of buffer wirings (183) has a curved shape. For example, each of the plurality of buffer wirings (183) may have a sinusoidal shape. However, the shape of each of the plurality of buffer wirings (183) is not limited thereto; for example, each of the plurality of buffer wirings (183) may extend in a zigzag shape, or may have various shapes such as multiple rhombus-shaped substrates connected at vertices and extended. Furthermore, the number and shape of each of the plurality of buffer wirings (183) shown in FIG. 8 are exemplary, and the number and shape of each of the plurality of buffer wirings (183) may be varied according to the design.

[0170] Additionally, the buffer wiring (183) formed on the first sub-plate pattern (123a) may be in the form of a straight line extending in the first direction (X). However, the shape of the buffer wiring (183) formed on the first sub-plate pattern (123a) is not limited thereto and may be a curved shape as described above. The width of the buffer wiring (183) formed on the first sub-plate pattern (123a) may be greater than the width of the buffer wiring (183) formed on the first-1 sub-wiring pattern (124a-1). Referring to FIG. 8, the width of the first-1 sub-wiring pattern (124a-1) may be formed differently. For example, the width of the first-1 sub-wiring pattern (124a-1) placed in an area adjacent to the first sub-plate pattern (123a) or the first plate pattern (121) may be greater than the width of the curved area of ​​the first-1 sub-wiring pattern (124a-1).

[0171] Accordingly, since a portion of the plurality of buffer wires (183) has a curved shape, the first region (A1) of the non-display area (NA) can be extended in the first direction (X). Also, since another portion of the plurality of buffer wires (183) has a straight shape, the resistance of the buffer wires (183) can be reduced. Accordingly, the delay of the gate voltage transmitted by the plurality of buffer wires (183) can be minimized.

[0172] And, a plurality of anchor holes (AH) are formed on the first sub-plate pattern (123a) to contact a plurality of buffer wirings (183) and a metal pattern (MT) placed on a different layer.

[0173] As illustrated in FIG. 8, a plurality of anchor holes (AH) can be formed to overlap with buffer wiring (183) formed on the first sub-plate pattern (123a). Specifically, since the buffer wiring (183) formed on the first sub-plate pattern (123a) extends in a first direction (X), a plurality of anchor holes (AH) can be arranged in the first direction (X) according to the buffer wiring (183) formed on the first sub-plate pattern (123a).

[0174] For example, on the first sub-plate pattern (123a), a plurality of buffer wires (183) extending in the first direction (X) are arranged in the second direction (Y), so a plurality of anchor holes (AH) arranged in the first direction (X) can be arranged in the second direction (Y).

[0175] And with reference to FIG. 9, through each of the plurality of anchor holes (AH), the plurality of buffer wirings (183) can be in direct contact with other metal patterns (MT).

[0176] On the first sub-plate pattern (123a) disposed on the lower substrate (111), a buffer layer (141) which is an inorganic insulating layer, a gate insulating layer (142), a first interlayer insulating layer (143), a second interlayer insulating layer (144) and a passivation layer (145), and a flattening layer (146) which is an organic insulating layer may be disposed.

[0177] And, the buffer wiring (183) is placed on the flattening layer (146), and the metal pattern (MT) can be placed between the buffer layer (141), gate insulating layer (142), first interlayer insulating layer (143), second interlayer insulating layer (144), and passivation layer (145), which are inorganic insulating layers.

[0178] For example, in FIG. 9, the metal pattern (MT) can be formed of the same material as the source electrode and drain electrode of the transistor disposed between the second interlayer insulating layer (144) and the passivation layer (145). That is, the metal pattern (MT) can be formed of the same material in the same layer as the source electrode and drain electrode of the transistor.

[0179] However, the metal pattern (MT) is not limited thereto, and the metal pattern (MT) may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer (143) and the second interlayer insulating layer (144), or the metal pattern (MT) may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer (142) and the first interlayer insulating layer (143).

[0180] And, a filling layer (190) and an upper substrate (112) can be sequentially arranged on the buffer wiring (183) and the flattening layer.

[0181] As described above, a display device according to one embodiment of the present invention may include an anchor hole (AH) for fixing a buffer wiring. Accordingly, even if the display device is repeatedly stretched, the buffer wiring (183) may not be separated from the lower component. In addition, since the buffer wiring (183) is fixed on the first sub-plate pattern (123a) through the anchor hole (AH), the area in which the buffer wiring (183) can move flexibly is reduced. Accordingly, the stretching stress received by the buffer wiring (183) can be significantly reduced. Ultimately, by forming an anchor hole (AH) in the display device according to one embodiment of the present invention, the stretching reliability of the display device can be stably secured.

[0182] In addition, when manufacturing a display device, components are placed on a lower substrate and lifted off to separate them, after which a filling layer and an upper substrate are attached. As described above, when components placed on the lower substrate are lifted off, a problem occurs in which components such as buffer wiring placed on the lower substrate are torn off. Accordingly, in a display device according to an embodiment of the present invention, by fixing the buffer wiring through an anchor hole, the display device may not be damaged when lifted off. Consequently, the display device according to an embodiment of the present invention can also ensure process stability.

[0183] <제3 영역의 구성>

[0184] FIG. 10 is an enlarged plan view of a third region of a display device according to one embodiment of the present invention.

[0185] FIG. 11 is a cross-sectional view taken along the cutting line XI-XI' shown in FIG. 10.

[0186] As illustrated in FIG. 10, a plurality of power blocks (PB) constituting a power supply (PS) and power wiring (185) connecting the plurality of power blocks (PB) are arranged in the third area (A3).

[0187] A plurality of power blocks (PB) are each formed on a plurality of third sub-plate patterns (123c) spaced apart from each other. As described above, since the third sub-plate patterns (123c) can be arranged in an island shape spaced apart from each other in the first direction (X) and the second direction (Y), a plurality of power blocks (PB) can also be arranged in an island shape spaced apart from each other in the first direction (X) and the second direction (Y).

[0188] FIG. 10 illustrates a plurality of power blocks (PB) arranged in a 4 x 2 matrix form, each placed in a plurality of third sub-plate patterns (123c) arranged in a 4 x 2 matrix form, but is not limited thereto and the arrangement of the plurality of power blocks (PB) can be varied in many ways. For example, instead of only one power block (PB) being placed in a single third sub-plate pattern (123c), a plurality of power blocks (PB) may be arranged in a matrix form.

[0189] And as illustrated in FIG. 11, each of the plurality of power blocks (PB) may include a plurality of power patterns (PP) disposed on different layers. Specifically, the plurality of power blocks (PB) may include a first power pattern (PP1) and a second power pattern (PP2) disposed on different layers.

[0190] On the third sub-plate pattern (123c) disposed on the lower substrate (111), a buffer layer (141), a gate insulating layer (142), a first interlayer insulating layer (143), a second interlayer insulating layer (144), and a passivation layer (145), and a flattening layer (146), which is an organic insulating layer, may be disposed.

[0191] And, the first power pattern (PP1) can be placed between the buffer layer (141), gate insulating layer (142), first interlayer insulating layer (143), second interlayer insulating layer (144), and passivation layer (145), which are inorganic insulating layers. And, the second power pattern (PP2) can be placed on the flattening layer (146).

[0192] For example, in FIG. 11, the first power pattern (PP1) can be formed of the same material as the source electrode and drain electrode of the transistor disposed between the second interlayer insulating layer (144) and the passivation layer (145). That is, the first power pattern (PP1) can be formed of the same material in the same layer as the source electrode and drain electrode of the transistor.

[0193] However, the first power pattern (PP1) is not limited thereto, and the first power pattern (PP1) may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer (143) and the second interlayer insulating layer (144), or the first power pattern (PP1) may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer (142) and the first interlayer insulating layer (143).

[0194] However, although FIG. 11 illustrates that the power block (PB) is composed of only two power pattern layers (PP1, PP2), it is not limited thereto and may be composed of three or more multiple power pattern layers arranged on different layers of the power block (PB).

[0195] And, a filling layer (190) and an upper substrate (112) can be sequentially disposed on the second power pattern (PP2) and the flattening layer.

[0196] Meanwhile, a plurality of power wires (185) connect a plurality of power blocks (PB) arranged in an island shape. Accordingly, the plurality of power wires (185) include a first power wire (185a) extended in a first direction (X) and a second power wire (185b) extended in a second direction (Y).

[0197] And, a plurality of first power wires (185a) extending in the first direction (X) are placed on a third-1 sub-wiring pattern (124c-1) extending in the first direction (X), and a plurality of second power wires (185b) extending in the second direction (Y) are placed on a third-2 sub-wiring pattern (124c-2) extending in the second direction (Y).

[0198] Additionally, the first power wiring (185a) formed on the third-1 sub-wiring pattern (124c-1) may have the same shape as the third-1 sub-wiring pattern (124c-1), and the second power wiring (185b) formed on the third-2 sub-wiring pattern (124c-2) may have the same shape as the third-2 sub-wiring pattern (124c-2). Specifically, each of the plurality of first power wirings (185a) and the plurality of second power wirings (185b) has a curved shape. For example, each of the plurality of first power wirings (185a) and the plurality of second power wirings (185b) may have a sinusoidal shape. However, the shape of each of the plurality of first power wires (185a) and the plurality of second power wires (185b) is not limited thereto, and for example, each of the plurality of first power wires (185a) and the plurality of second power wires (185b) may have various shapes, such as being extended in a zigzag shape or having multiple rhombus-shaped substrates connected at vertices and extended. Additionally, in FIG. 10, six first power wires (185a) are shown as forming a group and electrically connecting a plurality of power blocks (PB) adjacent in the first direction (X), and three second power wires (185b) are shown as forming a group and electrically connecting a plurality of power blocks (PB) adjacent in the second direction (Y). However, the number and shape of each of the illustrated first power wires (185a) and second power wires (185b) are exemplary, and the number and shape of each of the first power wires (185a) and second power wires (185b) may vary depending on the design.

[0199] And as illustrated in FIG. 11, each of the plurality of first power lines (185a) and the plurality of second power lines (185b) may include a plurality of power lines arranged on different layers. Specifically, the plurality of first power lines (185a) may include a first-1 power line and a first-2 power line arranged on different layers. And, the plurality of second power lines (185b) may include a second-1 power line (185b-1) and a second-2 power line (185b-2) arranged on different layers.

[0200] Figure 11 is a cross-sectional view of the second power wiring (185b), so the interlayer structure of the second power wiring (185b) is explained.

[0201] A second-1 power wiring (185b-1) may be disposed on a third-2 sub-wiring pattern (124c-2) disposed on a lower substrate (111). Additionally, a passivation layer (145) and a flattening layer (146) are disposed on the second-1 power wiring (185b-1), and the second-2 power wiring (185b-2) may be disposed on the flattening layer (146).

[0202] And, the 2-1 power wiring (185b-1) can be composed of the same material as the 1 power pattern (PP1), and the 2-2 power wiring (185b-2) can be composed of the same material as the 2 power pattern (PP2).

[0203] For example, in FIG. 11, the second-1 power wiring (185b-1) may be formed of the same material as the source electrode and drain electrode of the transistor. However, the second-1 power wiring (185b-1) is not limited thereto, and the second-1 power wiring (185b-1) may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer (143) and the second interlayer insulating layer (144), or the second-1 power wiring (185b-1) may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer (142) and the first interlayer insulating layer (143).

[0204] However, although FIG. 11 shows the second power wiring (185b) composed only of two power wiring layers (185b-1, 185b-2), it is not limited thereto and may be composed of three or more power wiring layers arranged in different layers of the second power wiring (185b).

[0205] The interlayer structure of the first power wiring (185a) is the same as the interlayer structure of the second power wiring (185b).

[0206] Specifically, a first-1 power wiring may be disposed on a third-1 sub-wiring pattern (124c-1) disposed on a lower substrate (111). Additionally, a passivation layer (145) and a flattening layer (146) are disposed on the first-1 power wiring, and a first-2 power wiring may be disposed on the flattening layer (146).

[0207] In addition, the 1-1 power wiring can be composed of the same material as the 1 power pattern (PP1), and the 1-2 power wiring can be composed of the same material as the 2 power pattern (PP2).

[0208] However, although the first power wiring (185a) is depicted as being composed of only two power wiring layers, it is not limited thereto and may be composed of three or more power wiring layers arranged in different layers of the first power wiring (185a).

[0209] As described above, the first-1 power wiring and the second-1 power wiring (185b-1) are composed of the same material as the first power pattern (PP1), so that the first-1 power wiring, the second-1 power wiring (185b-1), and the first power pattern (PP1) can be electrically connected to each other. Accordingly, a low-potential driving voltage can be applied to a plurality of first power patterns (PP1) placed on one side through the link wiring. Then, the low-potential driving voltage is stored in the first power pattern (PP1) placed on the other side through the first-1 power wiring and the second-1 power wiring (185b-1), and the low-potential driving voltage can be supplied to a plurality of pixels through the first-1 power wiring and the second-1 power wiring (185b-1).

[0210] In addition, the first-2 power wiring and the second-2 power wiring (185b-2) are composed of the same material as the second power pattern (PP2), so that the first-2 power wiring, the second-2 power wiring (185b-2), and the second power pattern (PP2) can be electrically connected to each other. Accordingly, a high-potential driving voltage can be applied to a plurality of second power patterns (PP2) placed on one side through the link wiring. In addition, a high-potential driving voltage is stored in the second power pattern (PP2) placed on the other side through the first-2 power wiring and the second-2 power wiring (185b-2), and the high-potential driving voltage can be supplied to a plurality of pixels through the first-2 power wiring and the second-2 power wiring (185b-2).

[0211] That is, as described above, a high potential driving voltage is supplied to the pixel through the first-2 power wiring, the second-2 power wiring (185b-2) and the second power pattern (PP2), which are components placed in the relatively upper layer of the power supply (PS), and a low potential driving voltage is supplied to the pixel through the first-1 power wiring, the second-1 power wiring (185b-1) and the first power pattern (PP1), which are components placed in the relatively lower layer of the power supply (PS).

[0212] However, not limited thereto, a high potential driving voltage may be applied through a link wire to a component located in one area among the first-2 power wiring, the second-2 power wiring (185b-2) and the second power pattern (PP2), which are components located in a relatively upper layer of the power supply (PS), and a low potential driving voltage may be applied through a link wire to a component located in another area among the first-2 power wiring, the second-2 power wiring (185b-2) and the second power pattern (PP2). Additionally, the second power pattern (PP2) located in the other area is electrically connected to the first power pattern (PP1) located in a relatively lower layer through a contact hole. Accordingly, a low-potential driving voltage is stored in the first-1 power wiring, the second-1 power wiring (185b-1), and the first power pattern (PP1), so that the low-potential driving voltage can be supplied to the pixel through the first-1 power wiring, the second-1 power wiring (185b-1), and the first power pattern (PP1).

[0213] For example, as illustrated in FIG. 10, when a power block (PB) in the form of a 4x2 matrix is ​​arranged, the second power pattern (PP2) of the power block (PB) in the form of a 2x2 matrix arranged relatively inside the third area (A3) receives a high potential driving voltage from the link wiring and can apply a high potential driving voltage to the pixel through the power wiring (185).

[0214] Meanwhile, the second power pattern (PP2) of the 2x2 matrix power block (PB) positioned relatively outside the third region (A3) receives a low-potential driving voltage from the link wiring. Then, the low-potential driving voltage is transmitted through the contact hole to the first power pattern (PP1) of the 4x2 matrix power block (PB) positioned across the third region (A3). Then, the low-potential driving voltage can be applied to the pixel through the power wiring (185) connected to the first power pattern (PP1).

[0215] In the above-described case, a high-potential driving voltage is applied to the 2x2 matrix-shaped power block (PB) placed inside the third area (A3), and a low-potential driving voltage is applied to the 2x2 matrix-shaped power block (PB) placed outside the third area (A3). Therefore, the 2x2 matrix-shaped power block (PB) placed inside the third area (A3) and the 2x2 matrix-shaped power block (PB) placed outside the third area (A3) must not be electrically connected. Accordingly, power wiring (185) may not be placed between the 2x2 matrix-shaped power block (PB) placed inside the third area (A3) and the 2x2 matrix-shaped power block (PB) placed outside the third area (A3).

[0216] As described above, in a display device according to one embodiment of the present invention, a power supply (PS) may be formed on a plurality of third sub-plate patterns (123c) spaced apart in an island shape. That is, the power supply (PS) itself may be stretched in a first direction (X) as well as in a second direction (Y) by including power blocks (PB) spaced apart from each other in the biaxial direction of the power supply (PS). Accordingly, in one embodiment of the present invention, the non-display area (NA) of the display device may also be stretched in the biaxial direction. Thus, the application range of the stretchable display device is expanded, and the potential for utilizing the stretchable display device may be improved. Furthermore, as the stretching direction of the stretchable display device is expanded, the stretching stress received in one direction may be significantly reduced. Accordingly, the stretching rate of the display device according to one embodiment of the present invention may be improved. Also, by applying different voltages to the upper and lower layers of the power supply of the display device, various types of driving voltages can be applied even in a limited space. In addition, multiple power wires of the power supply are connected in parallel to minimize the drop in the driving voltage to be delivered.

[0217] <본 발명의 다른 실시예-추가 파워 블록>

[0218] Hereinafter, a display device (200) according to another embodiment of the present invention will be described in detail. Compared to the display device (100) according to one embodiment of the present invention, the display device (200) according to another embodiment of the present invention has a difference regarding an additional power block placed in a third area. Accordingly, details where the display device according to another embodiment of the present invention and the display device according to one embodiment of the present invention overlap are omitted, and the aforementioned difference is described in detail.

[0219] FIG. 12 is an enlarged plan view of a third area of ​​a display device according to another embodiment of the present invention.

[0220] FIG. 13 is a cross-sectional view taken along the cutting line XIII-XIII' shown in FIG. 12.

[0221] A display device (200) according to another embodiment of the present invention may further include a plurality of additional power blocks (APB) disposed on a fourth sub-plate pattern (123d) and additional power wiring (186) connecting the additional power blocks (APB) and the additional power blocks (APB).

[0222] As illustrated in FIG. 12, in the third area of ​​the non-display area of ​​the display device (200) according to another embodiment of the present invention, not only are a plurality of power blocks (PB) constituting a power supply (PS) and a power wiring (185) connecting the plurality of power blocks (PB) arranged, but a plurality of additional power blocks (APB) and an additional power wiring (186) connecting the additional power blocks (APB) and the additional power blocks (APB) may also be arranged.

[0223] A plurality of additional power blocks (APBs) are each formed on a plurality of spaced-apart fourth sub-plate patterns (123d). As described above, the fourth sub-plate patterns (123d) may be arranged between a plurality of third sub-plate patterns (123c) arranged in the third direction (Z, Z'). Additionally, the fourth sub-plate patterns (123d) may also be arranged in an island shape spaced apart from each other in the first direction (X) and the second direction (Y). Accordingly, a plurality of additional power blocks (APBs) may also be arranged in an island shape spaced apart from each other in the first direction (X) and the second direction (Y).

[0224] In other words, referring to FIG. 12, a plurality of additional power blocks (APB) may be placed between a plurality of power blocks (PB) arranged in a third direction (Z, Z'), between a plurality of first power wires (185a), or between a plurality of second power wires (185b).

[0225] Since the aforementioned fourth sub-plate pattern (123d) is a component of the second plate pattern, the fourth sub-plate pattern (123d) may also be a square-shaped rigid pattern.

[0226] Also, in FIG. 12, each fourth sub-plate pattern (123d) is illustrated with one additional power block (APB), but this is not limited to this and the arrangement of the additional power blocks (APB) can be varied in many ways. For example, instead of having only one additional power block (APB) arranged in one fourth sub-plate pattern (123d), multiple additional power blocks (APB) can be arranged in a matrix form.

[0227] And with reference to FIG. 13, each of the plurality of additional power blocks (APB) may include a plurality of additional power patterns (APP1, APP2) disposed on different layers. Specifically, the plurality of additional power blocks (APB) may include a first additional power pattern (APP1) and a second additional power pattern (APP2) disposed on different layers.

[0228] Also, the first additional power pattern (APP1) can be formed with the same material on the same layer as the first power pattern (PP1), and the second additional power pattern (APP2) can be formed with the same material on the same layer as the second power pattern (PP2).

[0229] That is, the first additional power pattern (APP1) is disposed between the buffer layer (141), gate insulating layer (142), first interlayer insulating layer (143), second interlayer insulating layer (144), and passivation layer (145), which are inorganic insulating layers, and the second additional power pattern (APP2) can be disposed on the flattening layer (146).

[0230] For example, the first additional power pattern (APP1) may be formed of the same material as the source electrode and drain electrode of the transistor disposed between the second interlayer insulating layer (144) and the passivation layer (145). That is, the first additional power pattern (APP1) may be formed of the same material in the same layer as the source electrode and drain electrode of the transistor.

[0231] However, the first additional power pattern (APP1) is not limited thereto and may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer (143) and the second interlayer insulating layer (144), or the first additional power pattern (APP1) may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer (142) and the first interlayer insulating layer (143).

[0232] However, although FIG. 13 illustrates that the additional power block (APB) is composed only of two additional power pattern layers (PP1, PP2), it is not limited thereto and may be composed of three or more additional power pattern layers arranged in different layers of the additional power block (APB).

[0233] Meanwhile, a plurality of additional power wires (186) connect the power block (PB) and the additional power block (APB). Since the power block (PB) and the additional power block (APB) are spaced apart from each other in a third direction (Z, Z'), the plurality of additional power wires (186) connecting the power block (PB) and the additional power block (APB) can also be extended in the third direction (Z, Z').

[0234] And, each of the multiple additional power wires (186) extending in the third direction (Z, Z') can be placed on the multiple fourth sub-wire patterns (124d) extending in the third direction (Z, Z').

[0235] Additionally, the shape of the plurality of additional power lines (186) may be the same as the shape of the plurality of fourth sub-wire patterns (124d). Specifically, each of the plurality of fourth sub-wire patterns (124d) and the plurality of additional power lines (186) has a curved shape. For example, each of the plurality of fourth sub-wire patterns (124d) and the plurality of additional power lines (186) may have a sinusoidal shape. However, the shape of each of the plurality of fourth sub-wire patterns (124d) and the plurality of additional power lines (186) is not limited thereto; for example, each of the plurality of fourth sub-wire patterns (124d) and the plurality of additional power lines (186) may have various shapes, such as extending in a zigzag shape or extending by connecting multiple rhombus-shaped substrates at the vertices.

[0236] And as illustrated in FIG. 13, each of the plurality of additional power wirings (186) may include a plurality of power wiring layers disposed on different layers. Specifically, the plurality of additional power wirings (186) may include a first additional power wiring (186-1) and a second additional power wiring (186-2) disposed on different layers.

[0237] A first additional power wiring (186-1) is disposed on a fourth sub-wiring pattern (124d) disposed on a lower substrate (111), and a passivation layer (145) and a flattening layer (146) are disposed on the first additional power wiring (186-1), and a second additional power wiring (186-2) can be disposed on the flattening layer (146).

[0238] And, the first additional power wiring (186-1) may be composed of the same material as the first additional power pattern (APP1) and the first power pattern (PP1), and the second additional power wiring (186-2) may be composed of the same material as the first additional power pattern (APP1) and the second power pattern (PP2).

[0239] For example, in FIG. 13, the first additional power wiring (186-1) may be formed of the same material as the source electrode and drain electrode of the transistor. However, the first additional power wiring (186-1) is not limited thereto, and the first additional power wiring (186-1) may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer (143) and the second interlayer insulating layer (144), or the first additional power wiring (186-1) may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer (142) and the first interlayer insulating layer (143).

[0240] However, although FIG. 13 shows that the additional power wiring (186) is composed of only two additional power wiring layers (186-1, 186-2), it is not limited thereto and the additional power wiring (186) may be composed of three or more power wiring layers arranged in different layers.

[0241] In a display device according to another embodiment of the present invention, a component placed in a relatively upper layer of the power supply (PS) may include not only a first-2 power wiring, a second-2 power wiring (185b-2), and a second power pattern (PP2), but may also include a second additional power pattern (APP2) and a second additional power wiring (186-2). That is, in another embodiment of the present invention, by further including a second additional power pattern (APP2) and a second additional power wiring (186-2), the area of ​​the component storing the high potential voltage may be increased. That is, in another embodiment of the present invention, the power supply may minimize the resistance of the component storing the high potential voltage, thereby minimizing the voltage drop of the high potential voltage.

[0242] In addition, the component placed in the relatively lower layer of the power supply (PS) may include not only the first-1 power wiring, the second-1 power wiring (185b-1), and the first power pattern (PP1), but also the first additional power pattern (APP1) and the first additional power wiring (186-1). That is, in another embodiment of the present invention, by further including the first additional power pattern (APP1) and the second additional power wiring (186-1), the area of ​​the component storing the low potential voltage may be expanded. That is, in another embodiment of the present invention, the power supply may minimize the resistance of the component storing the low potential voltage, thereby minimizing the voltage drop of the low potential voltage.

[0243] That is, in a display device according to another embodiment of the present invention, the power supply may include an additional power block to minimize the drop in driving voltage. Accordingly, a uniform voltage is applied to all pixels of the display device according to another embodiment of the present invention, thereby enabling uniformity of image quality.

[0244] A display device according to various embodiments of the present invention can be described as follows.

[0245] To solve the problem described above, a display device according to one embodiment of the present invention comprises a display area and a non-display area, a stretchable lower substrate, a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first line patterns formed in the display area, a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area, a plurality of pixels formed on a plurality of first plate patterns, a plurality of first connecting lines connecting a plurality of pixels, a gate driver formed on a plurality of second plate patterns, a power supply formed on a plurality of second plate patterns, a plurality of second connecting lines disposed in the non-display area, and a stretchable upper substrate covering the gate driver, the power supply, and the plurality of pixels, wherein the non-display area includes a first area located outside the display area, a second area located outside the first area where a plurality of gate drivers are disposed, and a third area located outside the second area where a plurality of power supplies are disposed, and the plurality of second connecting lines disposed in the first area through an anchor hole It comes into contact with a plurality of second connecting wires and a metal pattern placed on a different layer.

[0246] According to another feature of the present invention, a plurality of second plate patterns include a plurality of first sub-plate patterns disposed in a first area, a plurality of second sub-plate patterns disposed in a second area, and a plurality of third sub-plate patterns disposed in a third area, and a plurality of second wiring patterns include a plurality of first sub-wiring patterns disposed in a first area, a plurality of second sub-wiring patterns disposed in a second area, and a plurality of third sub-wiring patterns disposed in a third area, and anchor holes may be formed on a plurality of first sub-plate patterns.

[0247] According to another feature of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, and a metal pattern may be formed on the same layer as the source electrode and the drain electrode.

[0248] According to another feature of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, and a metal pattern may be formed on the same layer as the gate electrode.

[0249] According to another feature of the present invention, a plurality of second sub-plate patterns may be spaced apart from each other only in a second direction, and a plurality of third sub-plate patterns may be spaced apart from each other in a first direction and a second direction.

[0250] According to another feature of the present invention, a plurality of stages constituting a gate driver may be arranged on a plurality of second sub-plate patterns, and a plurality of power blocks constituting a power supply may be arranged on a plurality of third sub-plate patterns.

[0251] According to another feature of the present invention, a plurality of power blocks may include a first power pattern and a second power pattern disposed on different layers.

[0252] According to another feature of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, and the first power pattern may be formed of the same material as the source electrode and the drain electrode, and the second power pattern may be formed of the same material as the second connecting wire.

[0253] According to another feature of the present invention, a plurality of third sub-wiring patterns may include a third-1 sub-wiring pattern connecting a plurality of third sub-plate patterns spaced apart in a first direction and a third-2 sub-wiring pattern connecting a plurality of third sub-plate patterns spaced apart in a second direction.

[0254] According to another feature of the present invention, a plurality of second connecting wires disposed in a third area connect a plurality of power blocks, and the plurality of second connecting wires disposed in the third area may include a first power wire disposed on a third-1 sub-wiring pattern and a second power wire disposed on a third-2 sub-wiring pattern.

[0255] According to another feature of the present invention, the first power wiring may include a first-1 power wiring and a first-2 power wiring disposed on different layers, and the second power wiring may include a second-1 power wiring and a second-2 power wiring disposed on different layers.

[0256] According to another feature of the present invention, the first-1 power wiring and the second-1 power wiring are composed of the same material as the first power pattern, and the first-2 power wiring and the second-2 power wiring may be composed of the same material as the second power pattern.

[0257] According to another feature of the present invention, the display device may further include a plurality of additional power blocks disposed between a plurality of power blocks spaced apart in a third direction.

[0258] According to another feature of the present invention, a plurality of additional power blocks may include a first additional power pattern and a second additional power pattern disposed on different layers.

[0259] According to another feature of the present invention, a first additional power pattern may be electrically connected to the first power pattern, and a second additional power pattern may be electrically connected to the second power pattern.

[0260] To solve the problem described above, a display device according to another embodiment of the present invention comprises a flexible substrate, a plurality of rigid patterns formed on the flexible substrate, a plurality of pixels formed on a plurality of first plate patterns spaced apart from each other among the plurality of rigid patterns, and a power supply formed on a portion of a plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, wherein the power supply supplies a driving voltage to the plurality of pixels and may be composed of power blocks spaced apart from each other in a first direction and a second direction.

[0261] According to another feature of the present invention, a plurality of power blocks may include a first power pattern and a second power pattern disposed on different layers.

[0262] According to another feature of the present invention, different driving voltages may be applied to the first power pattern and the second power pattern.

[0263] According to another feature of the present invention, a plurality of power blocks may be connected by a plurality of first power wires extended in a first direction and a plurality of second power wires extended in a second direction.

[0264] According to another feature of the present invention, the first power wiring may include a first-1 power wiring and a first-2 power wiring disposed on different layers, and the second power wiring may include a second-1 power wiring and a second-2 power wiring disposed on different layers.

[0265] According to another feature of the present invention, the first-1 power wiring and the second-1 power wiring are electrically connected to the first power pattern, and the first-2 power wiring and the second-2 power wiring can be electrically connected to the second power pattern.

[0266] According to another feature of the present invention, a plurality of additional power blocks may be further included, which are disposed between a plurality of first power lines and between a plurality of second power lines.

[0267] According to another feature of the present invention, a plurality of additional power blocks may include a first additional power pattern and a second additional power pattern disposed on different layers.

[0268] According to another feature of the present invention, a first additional power pattern may be electrically connected to the first power pattern, and a second additional power pattern may be electrically connected to the second power pattern.

[0269] According to another feature of the present invention, the display device further includes a gate driver between a power supply and a plurality of pixels, and the gate driver and the plurality of pixels are connected by a plurality of buffer wires, and the plurality of buffer wires can be fixed to a metal layer formed on a different layer from the plurality of buffer wires through anchor holes.

[0270] According to another feature of the present invention, an anchor hole may be formed on the upper part of another portion of a plurality of second plate patterns that are spaced apart from each other among a plurality of rigid patterns.

[0271] Although embodiments of the present invention have been described in more detail, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims below, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0273] 100, 200: Display device 111: Lower substrate 112: Upper substrate 120: Pattern layer 121: First Edition Pattern 122: First wiring pattern 123: 2nd Edition Pattern 123a: First sub-plate pattern 123b: Second sub-plate pattern 123c: Third sub-plate pattern 123d: Third sub-plate pattern 124: Second wiring pattern 124a: 1st sub-wiring pattern 124b: Second sub-wiring pattern 124c: 3rd sub-wiring pattern 124d: 4th sub-wiring pattern 141: Buffer layer 142: Gate insulation layer 143: First interlayer insulation layer 144: Second interlayer insulation layer 145: Passivation layer 146: Leveling layer 147: Bank 150: Switching transistor 160: Driving transistor 151, 161: Gate electrode 152, 162: Active layer 153: Source electrode 154, 164: Drain electrode 170: Light-emitting element 171: n-type layer 172: Active layer 173: p-type layer 174: p-electrode 175: n-electrode 181: 1st pixel connection wiring 182: Second pixel connection wiring 183: Buffer Wiring 184: Gate connection wiring 185: Power Wiring 185a: 1st Power Wiring 185b: Second power wiring 186: Additional Power Wiring 190: Packing layer PX: Pixel SPX: Subpixel GD: Gate Driver DD: Data driver GP: Gate Pad DP: Data pad PCB: Printed Circuit Board PS: Power supply PB: Power Block AA: Display area NA: Non-display area A1: Area 1 A2: Area 2 A3: Third Area AH: Anchor hole CNT: Connection pad MT: Metal pattern PP1: 1st Power Pattern PP2: 2nd Power Pattern APB: Additional Power Block APP1: 1st Additional Power Pattern APP2: 2nd Additional Power Pattern

Claims

Claim 1 A lower substrate that is stretchable and includes a display area and a non-display area; a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first line patterns formed in the display area, and a plurality of second plate patterns and a plurality of second line patterns formed in the non-display area; a plurality of pixels formed on the plurality of first plate patterns; a plurality of first connecting lines connecting the plurality of pixels; a gate driver formed on the plurality of second plate patterns; a power supply formed on the plurality of second plate patterns; and a plurality of second connecting lines disposed in the non-display area. A display device comprising a gate driver, a power supply, and a plurality of pixels, and an extendable upper substrate covering the gate driver, the power supply, and the plurality of pixels, wherein the non-display area includes a first area located outside the display area, a second area located outside the first area where the gate driver is disposed, and a third area located outside the second area where the power supply is disposed, wherein a plurality of second connecting wires disposed in the first area of ​​the non-display area contact a metal pattern disposed on a different layer from the plurality of second connecting wires through an anchor hole. Claim 2 A display device according to claim 1, wherein the plurality of second plate patterns comprises a plurality of first sub-plate patterns disposed in the first area, a plurality of second sub-plate patterns disposed in the second area, and a plurality of third sub-plate patterns disposed in the third area, and the plurality of second wiring patterns comprises a plurality of first sub-wiring patterns disposed in the first area, a plurality of second sub-wiring patterns disposed in the second area, and a plurality of third sub-wiring patterns disposed in the third area, and the anchor hole is formed on the plurality of first sub-plate patterns. Claim 3 A display device according to claim 2, wherein the plurality of second sub-plate patterns are spaced apart from each other only in the second direction, and the plurality of third sub-plate patterns are spaced apart from each other in the first direction and the second direction. Claim 4 A display device according to claim 3, wherein a plurality of stages constituting the gate driver are disposed on the plurality of second sub-plate patterns, and a plurality of power blocks constituting the power supply are disposed on the plurality of third sub-plate patterns. Claim 5 In claim 4, the plurality of power blocks comprises a first power pattern and a second power pattern disposed on different layers, a display device. Claim 6 A display device according to claim 5, wherein a plurality of third sub-wiring patterns comprises a third-1 sub-wiring pattern connecting a plurality of third sub-plate patterns spaced apart in a first direction and a third-2 sub-wiring pattern connecting a plurality of third sub-plate patterns spaced apart in a second direction. Claim 7 A display device according to claim 6, wherein a plurality of second connecting wires disposed in the third area connect the plurality of power blocks, and the plurality of second connecting wires disposed in the third area include a first power wire disposed on the third-1 sub-wiring pattern and a second power wire disposed on the third-2 sub-wiring pattern. Claim 8 A display device according to claim 7, wherein the first power wiring comprises a first-1 power wiring and a first-2 power wiring disposed on different layers, and the second power wiring comprises a second-1 power wiring and a second-2 power wiring disposed on different layers. Claim 9 A display device according to claim 5, further comprising a plurality of additional power blocks disposed between a plurality of power blocks spaced apart in a third direction. Claim 10 In claim 9, the plurality of additional power blocks comprises a first additional power pattern and a second additional power pattern disposed on different layers, a display device. Claim 11 A display device according to claim 10, wherein the first additional power pattern is electrically connected to the first power pattern and the second additional power pattern is electrically connected to the second power pattern. Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete

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