Multi-level cache coherence protocol for cache line evicting

Abstract

Examples of a system and method for communicating cache line evicting data from a CPU subsystem to a home node through a prioritized channel and for releasing the cache subsystem initially to process other transactions are disclosed.

Description

Technology Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 083,810 filed on September 25, 2020, the full text of which is incorporated herein by reference. Background Technology

[0002] Modern computing systems typically include multiple caches in a cache hierarchy and have multiple central processing units (CPUs) that rely on them to improve processor and memory performance. A cache is a smaller and faster memory device compared to main memory that stores data expected to be frequently accessed or used in the near future, allowing that data to be accessed with low latency. These cache devices are often implemented in static random access memory (SRAM) and are typically located between the processing unit issuing memory requests and the main memory device. A memory-side cache is a dedicated cache attached to a specific memory device or partition that caches data written to and read from the memory device by other devices.

[0003] Cache subsystems in computing systems include high-speed cache memories configured to store blocks of data. As used herein, a “block” is a set of bytes stored in contiguous memory locations treated as a unit for coherency purposes. As used herein, the terms “cache block,” “block,” “cache line,” and “line” are interchangeable. In some embodiments, a block may also be a unit of allocation and deallocation within the cache. The number of bytes in a block may vary depending on design choice and may vary in size.

[0004] In multi-node computer systems, special care must be taken to maintain data coherence among different processing nodes. For example, when a processor attempts to access data at a specific memory address, it must first determine whether the memory is stored in another cache and has been modified. To implement such cache coherency protocols, caches typically include multiple status bits that indicate the status of cache lines to maintain data coherence across the system. One coherency protocol is, for example, the "MOESI" protocol, where each character represents the status of a cache line. These statuses are as follows: the cache line has been modified (M), the cache line is exclusive (E) or shared (S), or the cache line is invalid (I). The ownership (O) status indicates that the line has been modified in one cache, that a shared copy may exist in another cache, and that the data in memory is stale. Each cache line contains a status bit in the cache directory, which tracks the cache line currently in use by the system to indicate which MOESI state the line is in. Prior art: U.S. Patent Application Publication US 2019 / 0266091 (Publication date: August 29, 2019). Brief explanation of the drawing

[0005] The embodiments illustrated in the drawings of the accompanying drawings of this specification are examples, not limitations. In the drawings, Figure 1 is a block diagram of an embodiment of a computing system. FIG. 2 is a block diagram of one embodiment of a core complex. Figure 3 is a block diagram of an embodiment of a multi-CPU processor system. Figure 4 is a flowchart illustrating a process for performing dirty cache line eviction. FIG. 5 is a flowchart illustrating an example of a process for reducing occupancy pressure and bottlenecks in a processor system. FIG. 6 is a flowchart illustrating one embodiment of a process for reducing occupancy pressure in a processor system when there is no overlap between evicting for the same address and other transactions. FIG. 7a is a flowchart illustrating a process for reducing occupancy pressure in a processor system when a probe is received from a coherent master before a dirty cache line evicting transaction to the same address according to one embodiment is completed. FIG. 7b is a flowchart illustrating a process for reducing occupancy pressure in a processor system when a probe is received from a coherent master before a dirty cache line evicting transaction to the same address is completed according to one embodiment. Specific details for implementing the invention

[0006] The following description explains numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of the embodiments. However, it will be obvious to those skilled in the art that at least some embodiments may be practiced without these specific details. In other examples, well-known components or methods are not described in detail or are presented in the form of simple block diagrams to avoid unnecessarily obscuring the embodiments. Accordingly, the specific details presented are merely illustrative. Specific embodiments may differ from these illustrative details and may still be considered to be within the scope of the embodiments.

[0007] Data stored in the cache subsystem is no longer regularly accessed, and the cache line of data may be marked for eviction. This means that the cache line, sometimes referred to as the "victim," is cleared from the cache subsystem to make space for a new cache line. The cache line or victim being evictioned can be "dirty" or "clean." If the victim cache line is dirty, it means that the data within the victim has been modified and that memory must be updated to the most recent copy before purging the victim from the cache and associated buffers.

[0008] Executing dirty or clean cache line eviction from a cache involves multiple operations competing with other transactions. The operations for each transaction are typically performed serially and are held in a prioritized queue as data and signals interact between various interface blocks within the system. The execution method for an eviction transaction occupies resources in both the cache subsystem and other computer system interface blocks to preserve cache coherence. Consequently, the lifetime or occupancy of a transaction increases significantly with the distance between the cache subsystem and other computer system interface blocks. This occupancy can create a bottleneck in large systems with multiple CPU clusters, where each cluster has associated system interface blocks spread across multiple sockets and its own cache subsystem. For simplicity, the embodiments described herein will refer to dirty cache line evictions. However, processes and systems are also applicable to clean cache line evictions.

[0009] FIG. 1 is a block diagram of a computing system (100) according to one embodiment for performing more efficient cache line transactions, such as dirty or clean cache line evictions. In one embodiment, the computing system (100) includes a plurality of CPU subsystems (105A-N), input / output (I / O) interfaces (120), a data fabric / bus (125), a plurality of home nodes (130A-N), and a network interface (135). In other embodiments, the computing system (100) may include other components and / or may be arranged in other configurations. For clarity, as used herein, "core complex" may also be referred to as "CPU".

[0010] In one embodiment, each CPU subsystem (105A-N) may include various components such as one or more processor core masters (e.g., core(s) (308A) of FIG. 3) or other specialized processing components, such as a coherent master (e.g., coherent master (315A) of FIG. 3) for managing cache coherence and processing components. Each processor core within the CPU subsystem (105A-N) includes a cache subsystem having one or more levels of cache connected to the coherent master. In one embodiment, the cache subsystem includes a shared cache (e.g., L3 cache (230) of FIG. 2) connected to each CPU subsystem (105A-N). In some embodiments, one or more CPU subsystems (105A-N) may include data parallel processors having a highly parallel architecture, such as one or more of a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC). As used herein, "core complex" may also be referred to as a "processing node" or "CPU".

[0011] In one embodiment, the home node(s) (130) may include one or more of a coherent slave, a cache directory, and a memory controller coupled to any number and type of memory device (not shown). For example, the memory device(s) coupled to the home node(s) (130) may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0012] In various embodiments, each home node (130A-N) and each CPU subsystem (105A-N) includes logic for communicating with each other to send probes and acknowledgments, and to move data, such as cache lines or cache area data, particularly to request locations and memory. For example, the CPU subsystem (105A) may exchange signals with the home node (130N) to handle dirty cache line evicting.

[0013] The I / O interfaces (120) represent any number and type of I / O interfaces, including, but not limited to, various types of PCI (peripheral component interconnect) buses, GBE (gigabit ethernet) buses, USB (universal serial bus), special processors (e.g., platform security processors, graphics processors), and system management logic. Various types of peripheral devices may be coupled to the I / O interfaces (120). These peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0014] In various embodiments, the computing system (100) may be any of a server, a desktop computer, a laptop, a mobile device, a game console, a streaming device, a wearable device, or various other types of computing systems or devices. The number, orientation, and type of components exemplified in the computing system (100) are merely examples and may vary from embodiment to embodiment based on the application and system architecture.

[0015] FIG. 2 is a block diagram of an embodiment of a CPU complex (200) that may be found, for example, within the CPU subsystems (105A-N) of FIG. 1. The CPU complex (200) may include four processor cores (210A-D) and a cache subsystem comprising an L1 cache (215A-D), an L2 cache (220A-D), and an L3 cache (230). In one embodiment of the CPU complex (200), the cache subsystem includes high-speed cache memories (e.g., L1 cache (215A-D), L2 cache (220A-D), and L3 cache (230)) configured to store data blocks (not shown). As used herein, a “block” is a set of bytes stored in adjacent memory locations within the cache memories, which is treated as a unit for coherence purposes. Additionally, the terms “cache block,” “block,” “cache line,” and “line” are interchangeable in this specification. In some embodiments, a block may also be a unit of allocation and deallocation within a cache. A block may be retrieved from other caches within the system, for example, from other core complexes (e.g., CPU subsystems (105A-N) of FIG. 1), or from main memory which can be retrieved, for example, through the home node (130A) of FIG. 1.

[0016] Additionally, in one embodiment, the L3 cache (230) is shared by each of the processor cores (210A-D). The L3 cache (230) is coupled to a coherent master (not shown) for access to the data fabric (e.g., the data fabric / bus (125) of FIG. 1) and the memory subsystem. In another embodiment, the CPU complex (200) may include fewer or more processor cores (e.g., processor core (210A)) and corresponding L2 caches (e.g., L2 cache (220A)). In yet other embodiments, the CPU complex (200) may include other types of addressable cache subsystems that may include cache memories of different numbers, types, and levels without departing from the novelty of the present disclosure.

[0017] In one embodiment, an L2 or L3 cache (e.g., L2 cache (220A) or L3 cache (230)) exchanges signaling with a coherent master (not shown) to evict a dirty cache line (victim) from the cache. During this process, the cache forwards the victim to the coherent master, and after confirming that each of their respective tasks is completed (e.g., see FIG. 5), the cache then purges the victim from its memory and is ready to receive a new cache line entry while the coherent master and the home node complete the evicting process.

[0018] FIG. 3 is a block diagram of one embodiment of a processor system (300). In one embodiment, the processor system (300) includes a plurality of core complexes as exemplified by CPUs (305A-N). In various embodiments, the number of CPUs (e.g., CPU complex (305A)) and the number of cores per CPU (e.g., cores (308A-N)) may vary depending on design choice. Each CPU (305A-N) also includes a corresponding cache subsystem (310A-N). In various embodiments, the size and structure of the cache subsystem (310A-N) may vary as described above with reference to FIG. 2.

[0019] In one embodiment, each CPU (305A-N) is connected to a corresponding coherent master (315A-N) that is additionally connected to the data fabric / bus (318). As used herein, a “coherent master” is defined as an agent that handles traffic flowing through an interconnect (e.g., data fabric / bus (318)) and manages cache coherency, and includes each coherent master (e.g., coherent masters (315A-N)) that works in cooperation to generate, receive, and process coherency-related messages and probes for synchronizing copies of shared cache line data within the processor system (300).

[0020] In various embodiments, each CPU (305A-N) may be connected to one or more coherent slaves by a corresponding coherent master (315A-N) and a data fabric / bus (318). A coherent slave (320A) is connected to a memory controller (MC) (330A) and a cache directory (CD) (325A), while a coherent slave (321A) is connected to a memory controller (331A) and a cache directory (326A). Each memory controller (330A-N and 331A-N) is connected to one of the memory devices (340A-N and 341A-N). One of the functions of each memory controller, such as the memory controller (330A), is to provide access to the memory devices (340A-N and 341A-N) to elements of the processor system (300). In various embodiments, although illustrated as a single block, each of the memory devices (340A-N and 341A-N) may be composed of one or more physical memories and may be any type suitable for storing data, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0021] In various embodiments, a coherent slave (e.g., coherent slave (320A-N)) is responsible for reading memory (e.g., memory (340A-N)) through an attached memory controller (e.g., memory controller (330A-N)) and managing cache coherence through a cache directory (e.g., cache directory (325A-N)).

[0022] In one embodiment, similar to the cache subsystem (310A), the coherent master (315A) sends the victim to the coherent slave (320A) via a non-blocking virtual channel within the data fabric / bus (318). The coherent slave (320A) prioritizes the execution of the victim based on the use of the non-blocking virtual channel and sends the victim to the memory controller (330A) to be written to memory (340A) while simultaneously sending another globally visible response back to the coherent master (315A) to indicate that the transaction is complete (see, for example, FIG. 5). This indicates that the coherent master (315A) can purge the victim data from its buffer while retaining the victim command. Similarly, once the victim is sent to the memory controller (330A), in the case of a dirty cache line victim, the coherent slave (320A) Victims can be purged from the buffer and moved to other transactions to the same addresses. In addition to the prioritized channel(s), the timing and order of signaling reduce the buffer occupancy and transaction resources of data and commands in the cache subsystem (310A) and coherent slave (320A), which results in increased system speed and efficiency. For convenience, the components described herein, such as cache subsystems, coherent masters, and coherent slaves, are discussed as having a single buffer for command data and cache data. However, in other embodiments, each component may have two or more buffers shared with or dedicated to different types of data, such as command data and cache data (e.g., victim data).

[0023] In other embodiments, asynchronous eviction transactions using a non-blocking virtual channel utilize system-wide hazard checks (e.g., race conditions) to ensure other data coherence. For example, before executing an eviction transaction, a coherent slave (e.g., coherent slave (320A-N)) must perform hazard checks on address-matching transactions, such as memory reads or coherence probes associated with the same cache line data, to ensure that these transactions obtain the most up-to-date data. Hazard check transactions are discussed in more detail below in relation to Figures 7a and 7b.

[0024] Although not illustrated in FIG. 3, in other embodiments, to avoid obscuring the drawings, there may be other connections from the data fabric / bus (318) to other components not illustrated. For example, in another embodiment, the data fabric / bus (318) includes one or more I / O interfaces and connections to one or more I / O devices illustrated in FIG. 1.

[0025] FIG. 4 is a flowchart illustrating a process (400) for performing dirty cache line eviction. The process (400) begins in block (402) when a lower-level cache (LLC) of a cache subsystem (e.g., cache subsystem (310A) in FIG. 3 and L2 cache (220A) and L3 cache (230) in FIG. 2) initiates dirty cache line eviction, and for clarity, the dirty cache line data is referred to as the victim in this figure. The victim is forwarded to a coherent master (CM) (e.g., coherent master (315A) in FIG. 3), which then sends it to a coherent slave (CS) (e.g., coherent slave (320A) in FIG. 3) in block (404). Although the coherent slave may need to process other transactions for the same address, the victim transaction will eventually become the oldest transaction for that address corresponding to the victim data. Then, in block (406), the coherent slave will indicate to the coherent master that this transaction is now globally visible (GV) as a GV response. When the coherent master receives the GV response, it sends the GV response to the cache subsystem in block (408). In block (410), until the GV response is received, the victim retains and occupies space within the cache subsystem, and then the victim is removed, and a cache completion response packet can be sent to the coherent master, which provides an indication that the coherent master no longer needs to maintain the coherency state. Then, the coherent master converts the cache completion response into a CM completion response packet and, in block (412), sends it to the coherent slave. When this packet reaches the coherent slave, in block (414), the coherent slave then sinks the victim to the memory controller, deletes the buffer, and the transaction is completed.Finally, in block (416), the memory controller receives victim data and updates the memory address location accordingly.

[0026] The process of the transaction exemplified in FIG. 4 occupies resources in both the cache subsystem and the coherent slave to preserve the accuracy of the cache coherence. The lifetime of this transaction increases significantly based on the distance between the cache subsystem and the coherent slave, and the way the system prioritizes data. Thus, in a processor system having, for example, multiple cache subsystems, coherent masters and coherent slaves and multiple sockets (e.g., the processor system (300) in FIG. 3), transactions may have to pass through several switches to move from the cache subsystem to the coherent slave and back (e.g., see each component AN in FIG. 3), and may be blocked behind other transactions. As the system becomes larger, these components may hold a portion of the evicted transaction for a longer period, thus increasing the pressure on these components to occupy buffers and commands, which causes bottlenecks affecting performance.

[0027] FIG. 5 is a flowchart of a process (500) illustrating an embodiment of a method for reducing occupancy pressure and bottlenecks in a processor system (e.g., the processor system (300) of FIG. 3). In block (502), cache line ejection begins when the lower-level cache (LLC) of the cache subsystem (e.g., the cache subsystem (310A) of FIG. 3 and the L2 cache (220A) and L3 cache (230) of FIG. 2) initiates cache line ejection and sends the cache line (victim) to the coherent master (CM) (e.g., the coherent master (315A) of FIG. 3). At the moment this victim arrives, in block (504), the coherent master immediately sends an initial GV response transferring ownership of the victim transaction from the cache subsystem (LLC) to the coherent master. After receiving the initial GV response, the cache subsystem, in block (506), returns a "cache done" response to the coherent master, deletes the victim data and command from the LLC buffer, and is released to process the next transaction. In block (508), the coherent master sends the victim to the coherent slave via the priority channel (509) and deletes the victim data from the coherent master buffer.

[0028] In one embodiment, the priority channel (509) is a non-blocking virtual channel. For example, a priority channel such as a non-blocking virtual channel is used because the victim may not be the oldest transaction for a specific address of the victim, which means that the victim may be backed up behind other transactions for the same address or somewhere in between within the processor system.

[0029] In one embodiment, when the coherent slave receives data on the prioritized channel (509), it ensures forward progress for the victim relative to other transactions, which means that the coherent slave does not delay the victim based on other functions, such as address comparison, address matching checks, or any other processing that could delay the victim's progress. In block (510), the coherent slave prioritizes cache line ejection data and updates the memory for the victim in block (512) by sending or sinking it to the memory controller (e.g., the memory controller (330A) of FIG. 3). Returning to block (510), the coherent slave also completes the transaction in the coherent slave by sending the GV response backward to the coherent master and clearing the buffer. In block (514), the coherent slave clears the victim command and victim data from the buffer. In block (516), the coherent master receives a GV response indicating that the coherent slave has completed the transaction, and removes the victim command from the buffer.

[0030] FIG. 6 is a flowchart illustrating an example of a process for reducing occupancy pressure in a processor system (e.g., processor system (300) of FIG. 3) when there is no overlap between the eviction and other transactions for the same address. In this exemplary embodiment, while the eviction of a cache line (victim) to be completed exists in the first CPU complex and the first coherent master (e.g., CPU complex (305A) and coherent master (315A) of FIG. 3), substantially simultaneously, the second CPU complex and the second coherent master (e.g., CPU complex (305N) and coherent master (315N) of FIG. 3) want to read the same cache line. This process begins in block (602), where the second coherent master (CM2) sends a read data request to a coherent slave (CS) (e.g., coherent slave (321A) of FIG. 3) corresponding to an address associated with a set of cache lines for ejection. In block (604), the coherent slave sends a memory read request to a memory controller (MC) (e.g., memory controller (331A) of FIG. 3), and in response, in block (606), the memory controller sends the memory data in reverse. In block (608), the coherent slave forwards the received memory data to the second coherent master that performed the initial request in block (602).

[0031] Returning to block (604), the coherent slave sends a memory read request and simultaneously sends one or more probes to find cache line data corresponding to the memory address. In this example, only one probe is sent to the first coherent master (CM1) which receives the probe in block (610) and forwards it to the first cache subsystem (LLC1) (e.g., the cache subsystem (310A) of FIG. 3 and the L2 cache (220A) and L3 cache (230) of FIG. 2). The probe is a hit, and the first cache subsystem responds to the probe with the LLC1 data back to the first coherent master in block (612). The first coherent master in block (614) forwards the LLC1 data to the second coherent master that initiated the probe via a request to the coherent slave in block (602).

[0032] The second coherent master receives LLC1 data from the first coherent master and memory data from the coherent slave in block (616). In block (618), the coherent master prioritizes the retention of the LLC1 data for memory data determined to be older than the cache line data and sends the LLC1 data to its associated second cache subsystem (LLC2) (not shown). In various embodiments, the prioritization may be based on a byte-by-byte comparison of the data, flags (e.g., status bit(s)), etc. In block (620), the second coherent master sends a CM2 completion message to the coherent slave, and the coherent slave receives the CM2 completion message in block (622) and completes the transaction.

[0033] When the probe transaction for the cache line is completed, the process (600) can continue to process the eviction of the cache line as in the process (500) of FIG. 5. Cache line eviction begins in block (624) when the cache subsystem initiates cache line eviction and sends the victim (cache line eviction data) to the first coherent master. Then, in block (626), the coherent master sends an initial GV response transferring ownership of the victim transaction from the first cache subsystem to the first coherent master. After receiving the initial GV response, the first cache subsystem returns a cache completion response to the first coherent master in block (628), deletes the victim data and command from the LLC buffer, and is released to process the next transaction. In block (630), the first coherent master sends the victim to the coherent slave through the priority channel (631) and deletes the victim data from the coherent master buffer.

[0034] In one embodiment, the priority channel (631) is a non-blocking virtual channel. For example, a priority channel such as a non-blocking virtual channel is used because the victim may not be the oldest transaction for a specific address of the victim, which means that the victim may be backed up behind other transactions for the same address or somewhere in between within the processor system.

[0035] In one embodiment, when the coherent slave receives data on the prioritized channel (631), it ensures forward progress for the victim over other transactions, which means that the coherent slave does not delay the victim based on other functions, such as address comparison, address matching checks, or any other processing that could delay the progress of the victim. In block (632), the coherent slave prioritizes the victim transaction and sends or sinks it to the memory controller to update the memory to the victim in block (634). Returning to block (632), the coherent slave also sends a GV response back to the first coherent master and deletes the buffer that completed the transaction in the coherent slave in block (634). In block (636), the first coherent master receives a GV response indicating that the coherent slave has completed the transaction and deletes the victim command from the buffer. In block (638), the coherent slave deletes the victim command and victim data from the buffer.

[0036] FIG. 7a is a flowchart of a process (700) illustrating an embodiment of a method for reducing occupancy pressure in a processor system (e.g., processor system (300) of FIG. 3) when a probe is received from a coherent master before a dirty cache line evicting transaction to the same address is completed. In this exemplary embodiment, similar to the process (600) of FIG. 6, while a dirty cache line evicting of a cache line (victim) to be completed at the first CPU complex and the first coherent master (e.g., CPU complex (305A) and coherent master (315A) of FIG. 3) exists, substantially simultaneously, the second CPU complex and the second coherent master (e.g., CPU complex (305N) and coherent master (315N) of FIG. 3) want to read the same cache line. However, in this example, the probe reaches the first coherent master before the dirty cache line evicting transaction is completed.

[0037] The process (700) begins in block (702) when the cache subsystem initiates the dirty cache line evicting and sends the victim to the first coherent master. Then, in block (704), the coherent master sends an initial GV response indicating that ownership and transactions of the victim have been transferred from the first cache subsystem to the first coherent master. After receiving the initial GV response, the first cache subsystem returns a cache completion response to the first coherent master in block (706), deletes the victim data and commands from the LLC buffer, and is released to process the next transaction. In block (708), the first coherent master sends the victim to the coherent slave via the priority channel (709) and deletes the victim data from the coherent master buffer.

[0038] However, before sending the victim to the coherent slave, the second coherent master (CM2) sends a read data request in block (710) to the coherent slave (CS) (e.g., the coherent slave (321A) of FIG. 3) corresponding to the address associated with the dirty cache line extraction. The coherent slave sends a memory read request in block (712) to the memory controller (MC) (e.g., the memory controller (331A) of FIG. 3), and in response, in block (714), the memory controller sends the memory data in reverse.

[0039] Returning to block (712), the coherent slave sends a memory read request and simultaneously sends one or more probes to find cache line data corresponding to the memory address. In this example, there is only one probe for the first coherent master (CM1) that received the probe in block (715). In one embodiment, because there was an initial GV response previously, in block (704), the first coherent master is aware of the priority channel eviction transaction and will block the probe response until the eviction transaction is completed. In other embodiments, there may be other signaling or flags set to indicate the probe block. In another embodiment, if the first coherent master receives an address matching probe before the initial GV response in block (704), the first coherent master allows the victim to use the normal flow of execution and does not perform any initial GV responses.

[0040] In block (716), the coherent slave receives the victim through the prioritized channel (709), and the coherent slave prioritizes the victim transaction and sends or syncs it to the memory controller to update the memory to the victim in block (718). In block (720), the coherent slave ignores the memory data received from the memory controller because the coherent slave also holds the victim for the same address, which is the latest data corresponding to that address by definition. The coherent slave also sends the GV response backward to the first coherent master. In block (722), the first coherent master receives a GV response indicating that the coherent slave has completed the victim transaction, and releases a probe miss response to the second coherent master (the original data requester in block (710)) because the victim is no longer available after being sent to the coherent slave in block (708).

[0041] Simultaneously, in block (726), the coherent slave sends a second memory read request to the memory controller, and in response, in block (728), the memory controller sends the updated memory data backward, which is received by the coherent slave in block (730). In block (732), the first coherent master sends a read data request to the coherent slave indicating that the second coherent master needs to receive the updated data from the memory. In block (734), the coherent slave sends the updated data from the memory to the second coherent master, and the second coherent master receives the updated data in block (736), sends a CM2 completion response backward to the coherent slave, and deletes the victim command from the buffer. In block (738), the coherent slave deletes the victim command and victim data from the buffer. In another embodiment, the coherent slave directly forwards data from the victim in block (734) in response to a read request in block (732), thereby avoiding the second memory read process in blocks (726-730).

[0042] FIG. 7b is a flowchart of a process (750) illustrating an embodiment of a method for reducing occupancy pressure in a processor system of a second scenario (e.g., processor system (300) of FIG. 3) when a probe is received from a coherent master before a dirty cache line evicting transaction to the same address is completed. In this exemplary embodiment, while a dirty cache line evicting of a cache line (victim) to be completed exists at the first CPU complex and the first coherent master (e.g., CPU complex (305A) and coherent master (315A) of FIG. 3), substantially simultaneously, the second CPU complex and the second coherent master (e.g., CPU complex (305N) and coherent master (315N) of FIG. 3) want to read the same cache line. However, in this example, before the dirty cache line evicting transaction is completed, the probe reaches the first coherent master and the first read memory reaches the second coherent master.

[0043] The process (750) begins in block (752) when the cache subsystem initiates dirty cache line ejection and sends the victim (cache line ejection data) to the first coherent master. Then, in block (754), the coherent master sends an initial GV response indicating that ownership and transactions of the victim have been transferred from the first cache subsystem to the first coherent master. After receiving the initial GV response, the first cache subsystem returns a cache completion response to the first coherent master in block (756), deletes the victim data and commands from the LLC buffer, and is released for processing. In block (758), the first coherent master sends the victim to the coherent slave via the priority channel (759) and deletes the victim data from the coherent master buffer.

[0044] However, before sending the victim to the coherent slave, the second coherent master (CM2) sends a read data request in block (760) to the coherent slave (CS) (e.g., the coherent slave (321A) of FIG. 3) corresponding to the address associated with the dirty cache line extraction. The coherent slave sends a memory read request in block (762) to the memory controller (MC) (e.g., the memory controller (331A) of FIG. 3), and in response, in block (764), the memory controller sends the memory data in reverse.

[0045] Returning to block (762), the coherent slave sends a memory read request and simultaneously sends one or more probes to find cache line data corresponding to the memory address. In this example, in block (765), only one probe is sent to the first coherent master (CM1) receiving the probe. In one embodiment, because there was an initial GV response previously in block (754), the first coherent master is aware of the priority channel evicting transaction and will block the probe until the evicting transaction is completed. In other embodiments, other signaling or flags set to indicate the probe block may exist.

[0046] In block (766), the coherent slave sends the memory data received from the memory controller to the second coherent master, which is received in block (768). However, the victim with updated data has not yet been received by the coherent slave, causing the second coherent master to receive stale data, which must be resolved in process (750) by the first coherent master that owns the victim transaction.

[0047] In block (770), the coherent slave receives the victim through the prioritized channel (759), prioritizes the victim transaction, and sends or syncs it to the memory controller to update the memory to the victim in block (772). Additionally, in block (770), the coherent slave sends a GV response to the first coherent master indicating that the coherent slave has completed the victim transaction. The first coherent master receives the GV response in block (774), releases its probe miss response to the second coherent master (the original data requester in block (760)), which is received in block (776).

[0048] Simultaneously, in block (778), the coherent slave sends a second memory read request to the memory controller, and in response, in block (780), the memory controller sends the updated memory data backward, which is received by the coherent slave in block (782). In block (784), the first coherent master sends a read data request to the coherent slave indicating that the second coherent master needs to receive the updated data from memory. In block (786), the coherent slave sends the updated data from memory to the second coherent master, and the second coherent master receives the updated data in block (788), sends a CM2 completion response backward to the coherent slave, and deletes the victim command from the buffer. In block (790), the coherent slave deletes the victim command and victim data from its buffer.

[0049] There may be other hazards occurring in the signaling between a coherent slave (e.g., the coherent slave (320A) in FIG. 3) and one or more coherent masters (e.g., the coherent masters (315A and 315B) in FIG. 3) during dirty cache line evicting. Even in the event of such hazards, various embodiments utilize priority channels and initial GV responses, as described in detail above, to ensure that the most recent copy of the cache line is provided to the requester with minimal bottlenecks.

[0050] For each failure, the coherent master(s) and coherent slave use interlocks to ensure that the most recent copy of the cache line is delivered and that the process is not interrupted. For example, a probe may be seen after the victim has been processed into memory (e.g., memory (340A) in FIG. 3) via the coherent slave. In this scenario, the cache subsystem (e.g., cache subsystem (310A) in FIG. 3)) has already completed the victim transaction, and the first coherent master has pushed the victim to the coherent slave. However, before the victim arrives, the coherent slave receives a read for the same address from the second coherent master and sends coherence probes to the first coherent master that sent the victim. If this race is not handled correctly, the cache subsystem requesting the read data will obtain stale data from memory. To resolve this, according to one embodiment, a coherent slave detects a race condition and indicates the fault by notifying a first coherent master that a race condition has been detected. The first coherent master responds by holding the victim and waiting until a coherence probe is received. When the probe is received, the first coherent master notifies the coherent slave that the coherence probe is missing and requests another read from memory to be sent to a second coherent master.

[0051] Another possible failure occurs when the Coherent Slave receives a read for the same address from the Second Coherent Master and sends Coherence Probes to the First Coherent Master, but the Coherence Probes are received by the First Coherent Master and completed with a probe response before the Victim is received and processed by the Coherent Slave. This can cause false contention detection in the Coherent Slave. In this case, according to one embodiment, the Coherent Slave releases the hold on the Victim upon receiving an indication that the Second Coherent Master has completed, instead of waiting for a request for another memory read to be sent to the Second Coherent Master.

[0052] A method for processing a cache line ejection transaction may include the step of receiving cache line ejection data from a cache subsystem and the step of processing the cache line ejection data received through a prioritized channel.

[0053] The method may also include a releasing step of the cache subsystem to process other transactions after receiving the cache line ejection data, before processing the cache line ejection data.

[0054] In the above method, the step of processing cache line eviction data may include the step of processing cache line eviction data before processing lower priority transactions and the step of updating the memory by writing the cache line eviction data to the memory at a memory address associated with the cache line eviction data.

[0055] The method may also include the step of processing a coherency probe for cache line data corresponding to a memory address associated with the cache line ejection data before processing the cache line ejection data—the coherency probe originates from a request for cache line data from a coherent master—; and the step of delaying the dispatch of the coherency probe response until after processing the cache line ejection data.

[0056] The method may also include the step of requesting data from memory to provide updated cache line data to the coherent master after sending the coherence probe response.

[0057] The method may also include the step of forwarding cache line ejection data to the coherent master after sending the coherence probe response.

[0058] The method may also include the steps of: holding a cache line eviction transaction based on an indication of a hazard condition after processing the cache line eviction data; processing a coherence probe for cache line data corresponding to a memory address associated with the cache line eviction data after processing the cache line eviction data—the coherence probe originates from a request for cache line data from a coherent master—and requesting data from memory to provide updated cache line data to the coherent master based on a probe miss response.

[0059] The method may also include, prior to the step of receiving cache line ejection data from a cache subsystem, the step of processing a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data—the coherence probe originates from a request for cache line data from a coherent master—the step of receiving a probe response having cache line data from a coherent master, and after processing the cache line ejection data from a coherent slave, the step of holding the cache line ejection data until the coherent master receives the cache line ejection data and releasing the hold on the cache line ejection data to complete a cache line ejection transaction.

[0060] A device for processing a cache line extraction transaction may include a first coherent master that receives cache line extraction data from a cache subsystem corresponding to a first coherent master and communicates the cache line extraction data to a coherent slave through a prioritized channel, and a coherent slave that processes the cache line extraction data based on the reception of the cache line extraction data through the prioritized channel.

[0061] In the above device, the first coherent master may be configured to release the cache subsystem of the cache line ejection transaction by communicating a response indicating ownership of the cache line ejection transaction to the cache subsystem after receiving the cache line ejection data and before communicating the cache line ejection data to the coherent slave.

[0062] In the above device, the coherent slave can process the cache line ejection data by communicating the cache line ejection data to a memory controller to update the memory address location corresponding to the cache line ejection data, and can communicate a response to the first coherent master indicating that the cache line ejection transaction has been completed to release the first coherent master of the cache line ejection transaction.

[0063] In the above device, the first coherent master may receive a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data before communicating cache line ejection data to the coherent slave, and the coherence probe originates from a request for cache line data from the second coherent master. In the above device, the first coherent master may delay the coherence probe response until after the coherent slave has processed the cache line ejection data in response to the reception of the coherence probe and the cache line ejection data.

[0064] In the above device, the first coherent master can communicate a probe miss to the second coherent master, and the first coherent master can communicate a read data request to the coherent slave to provide updated cache line data corresponding to the cache line extraction data to the second coherent master.

[0065] In the above device, the first coherent master may receive a command to hold a cache line ejection transaction based on an indication of a failure state after the coherent slave has processed the cache line ejection data, and may receive a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data, the coherence probe originates from a request for cache line data from the second coherent master. The coherent master may communicate a probe miss to the second coherent master and may communicate a read data request to the coherent slave to provide updated cache line data corresponding to the cache line ejection data to the second coherent master.

[0066] In the above device, before receiving cache line ejection data from the cache subsystem, the first coherent master may receive a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data, and the coherence probe originates from a request for cache line data from the second coherent master. The first coherent master may communicate a probe response containing the cache line data to the second coherent master, and after processing the cache line ejection data at the coherent slave, the first coherent master may receive a hold regarding the cache line ejection data. The second coherent master may receive cache line ejection data from the coherent slave, and the first coherent master may release the hold regarding the cache line ejection data based on a transaction completed at the coherent slave.

[0067] In the above device, the first coherent master receives a command to hold a cache line ejection transaction based on an indication of a fault state after the coherent slave has processed the cache line ejection data, determines that the fault state is false, and can release the hold on the transaction.

[0068] A method for processing a cache line ejection transaction may include receiving a request for cache line data associated with a memory address from a first CPU subsystem; communicating cache line ejection data corresponding to the memory address of the requested cache line data from a second CPU subsystem to a home node via a prioritized channel; processing the cache line ejection data received via the prioritized channel; detecting a fault state between the requested cache line data and the cache line ejection data; retaining the cache line ejection data until the fault state is resolved; and communicating the cache line ejection data to the first CPU subsystem to complete the cache line ejection transaction.

[0069] In the above method, the step of detecting the fault state may include the step of detecting the fault state in the second CPU subsystem based on receiving a probe requesting the cache line data before communicating the cache line ejection data to the home node, and the step of sending a request to the home node in the second CPU subsystem to provide updated cache line data corresponding to the cache line ejection data to the first core complex before communicating the cache line ejection data.

[0070] In the above method, the step of detecting the fault state may also include the step of detecting the fault state at the home node based on the fact that the second CPU subsystem receives a probe requesting the cache line data after processing the cache line ejection data, and the step of sending a request to the home node to provide updated cache line data corresponding to the cache line ejection data to the first core complex before communicating the cache line ejection data at the second CPU subsystem.

[0071] In the above method, the step of detecting the fault state may further include the step of detecting the fault state at the home node based on the second CPU subsystem having the cache line data and responding to a probe request for the cache line data before processing the cache line ejection data. The step of holding the cache line ejection data until the fault state is resolved may include the step of holding the cache line ejection data in the second CPU subsystem until the head node communicates the completion of the cache line ejection transaction.

[0072] As used herein, the term “combined to” may mean directly or indirectly coupled through one or more interposed components. Any signals provided across the various buses described herein may be time-multiplexed with other signals and provided through one or more common buses. Additionally, interconnections between circuit components or blocks may be illustrated as buses or as single signal lines. Each bus may alternatively be one or more single signal lines, and each single signal line may alternatively be a bus.

[0073] Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transient computer-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A computer-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer) (e.g., software, processing applications). A non-transient computer-readable storage medium may include, but is not limited to: magnetic storage media (e.g., floppy diskettes); optical storage media (e.g., CD-ROM); magneto-optical storage media; read-only memory (ROM); random access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory, or other types of media suitable for storing electronic instructions.

[0074] Additionally, some embodiments may be implemented in a distributed computing environment where a computer-readable medium is stored in and / or executed by one or more computer systems. Additionally, information transmitted between computer systems may be pulled or pushed through a transmission medium connecting the computer systems.

[0075] Generally, a data structure representing a computing system (100) and / or a part thereof carried on a computer-readable storage medium may be a database or other data structure that can be read by a program and used directly or indirectly to manufacture hardware including the computing system (100). For example, the data structure may be a behavioral-level description of hardware functions in a high-level design language (HDL) such as Verilog or VHDL, or a register-transfer-level (RTL) description. The description may be read by a synthesis tool capable of synthesizing the description to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates representing the functions of the hardware including the computing system (100). The netlist may then be arranged and routed to generate a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor manufacturing steps to create semiconductor circuits or circuits corresponding to the computing system (100). Alternatively, a database on a computer-readable storage medium may be, as desired, a netlist (with or without a synthetic library), a dataset, or Graphics Data System (GDS) II data.

[0076] Although the operations of the methods(s) of this specification have been illustrated and described in a specific order, the order of the operations of each method may be changed so that specific operations may be performed in reverse order, or specific operations may be performed simultaneously with other operations, at least partially. In other embodiments, instructions or sub-operations of separate operations may be intermittent and / or alternating.

[0077] In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made without departing from the broader scope of the embodiments as described in the appended claims. Accordingly, the specification and drawings should be regarded as exemplary rather than restrictive.

Claims

Claim 1 A method performed by a computing system to process a cache line eviction transaction, the method comprising: receiving cache line eviction data evoked from a cache subsystem; releasing the cache subsystem by clearing the cache line eviction data from a buffer of the cache subsystem, wherein the cache subsystem is released before the cache line eviction data is sent through a prioritized channel; and processing the cache line eviction data received through the prioritized channel by updating a memory with the cache line eviction data. Claim 2 A method according to claim 1, wherein, after receiving the cache line extraction data, the cache subsystem is released to process other transactions. Claim 3 The method according to claim 1, wherein the step of processing the cache line extraction data further comprises: processing the cache line extraction data before processing lower priority transactions; and updating the memory by writing the cache line extraction data to the memory at a memory address associated with the cache line extraction data. Claim 4 In paragraph 3, the method further comprises the step of processing a coherency probe for cache line data corresponding to the memory address associated with the cache line ejection data prior to processing the cache line ejection data, wherein the coherency probe originates from a request for the cache line data from a coherent master; and the step of delaying the sending of the coherency probe response until after processing the cache line ejection data. Claim 5 A method according to claim 4, further comprising the step of requesting data from the memory to provide updated cache line extraction data to the coherent master after sending the coherence probe response. Claim 6 In claim 4: a method further comprising the step of forwarding the cache line extraction data to the coherent master after sending the coherence probe response. Claim 7 In claim 3, the method further comprises the steps of: holding the cache line extraction transaction based on an indication of a hazard condition after processing the cache line extraction data; processing a coherence probe for the cache line data corresponding to the memory address associated with the cache line extraction data, wherein the coherence probe originates from a request for the cache line data from the coherent master; and requesting data from the memory to provide the updated cache line extraction data to the coherent master based on a probe miss response. Claim 8 In claim 3, the method further comprises the steps of: processing a coherence probe for cache line data corresponding to the memory address associated with the cache line data before receiving the cache line ejection data ejected by the cache subsystem, wherein the coherence probe originates from a request for the cache line data from a coherent master; receiving a probe response having the cache line data from the coherent master; and retaining the cache line ejection data after processing the cache line ejection data in the coherent slave until the coherent master receives the cache line ejection data; and releasing the retention of the cache line ejection data to complete the cache line ejection transaction. Claim 9 A device for processing a cache line extraction transaction, the device comprises a coherent master that is a coherent master, receives cache line extraction data extracted from a cache subsystem corresponding to the coherent master, and communicates said cache line extraction data to a coherent slave through a prioritized channel, wherein the cache subsystem deletes said cache line extraction data from a buffer in connection with releasing said cache subsystem, said cache subsystem is released before communication of said cache line extraction data through the prioritized channel, and said coherent slave processes said cache line extraction data based on receiving said cache line extraction data through the prioritized channel by updating memory with said cache line extraction data. Claim 10 A device configured such that, in claim 9, the coherent master, after receiving the cache line ejection data and before communicating the cache line ejection data to the coherent slave, communicates a response indicating ownership of the cache line ejection transaction to the cache subsystem to release the cache subsystem of the cache line ejection transaction. Claim 11 A device configured in claim 9, wherein the coherent slave processes the cache line ejection data by the steps of: communicating the cache line ejection data to a memory controller to update a memory location corresponding to the cache line ejection data; and communicating to the coherent master a response indicating that the cache line ejection transaction is completed to release the coherent master of the cache line ejection transaction. Claim 12 In claim 9, the device is configured such that, before communicating the cache line extraction data to the coherent slave, the coherent master is configured to receive a coherence probe for cache line data corresponding to a memory address associated with the cache line extraction data, the coherence probe originates from a request for the cache line data from an additional coherent master; and the coherent master is configured to delay the coherence probe response until after the coherent slave has processed the cache line extraction data, in response to the reception of the coherence probe and the cache line extraction data. Claim 13 A device according to claim 12, wherein the coherent master is configured to communicate a probe miss to the additional coherent master; and the coherent master is configured to communicate a read data request to the coherent slave to provide the additional coherent master with updated cache line data corresponding to the cache line extraction data. Claim 14 A device according to claim 9, wherein after the coherent slave processes the cache line ejection data, the coherent master receives a command to hold the cache line ejection transaction based on an indication of a failure state; receives a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data, the coherence probe originates from a request for the cache line data from an additional coherent master; communicates a probe miss to the additional coherent master; and communicates a read data request to the coherent slave to provide the additional coherent master with updated cache line data corresponding to the cache line ejection data. Claim 15 In claim 9, before receiving the cache line ejection data from the cache subsystem, the coherent master receives a coherence probe for cache line data corresponding to a memory address associated with the cache line ejection data, the coherence probe originates from a request for the cache line data from an additional coherent master; is configured to communicate a probe response having the cache line data to the additional coherent master; after processing the cache line ejection data at the coherent slave, the coherent master is configured to receive a hold on the cache line ejection data; the additional coherent master is configured to receive the cache line ejection data from the coherent slave; and the coherent master is configured to release the hold on the cache line ejection data based on the fact that the cache line ejection transaction has been completed at the coherent slave. Claim 16 A device configured in claim 9, wherein the coherent master receives a command to hold the cache line ejection transaction based on an indication of a fault state after the coherent slave has processed the cache line ejection data; determines that the fault state is false; and releases the hold on the cache line ejection transaction. Claim 17 A method performed by a computing system to process a cache line ejection transaction comprises: receiving a request for cache line data associated with a memory address from a first CPU subsystem; communicating cache line ejection data corresponding to the memory address of the requested cache line data from a second CPU subsystem to a home node via a prioritized channel, wherein the cache line ejection data is ejected from a cache subsystem, and the cache subsystem is released prior to the communication of the cache line ejection data via the prioritized channel; processing the cache line ejection data received via the prioritized channel by updating memory with the cache line ejection data; detecting a hazard condition between the requested cache line data and the cache line ejection data; retaining the cache line ejection data until the hazard condition is resolved; and communicating the cache line ejection data to the first CPU subsystem to complete the cache line ejection transaction. Claim 18 In claim 17, the step of detecting the fault state further comprises: detecting the fault state in the second CPU subsystem based on receiving a probe requesting the cache line data before communicating the cache line ejection data to the home node; and sending a request to the home node in the second CPU subsystem and before communicating the cache line ejection data to provide the first core complex with updated cache line data corresponding to the cache line ejection data. Claim 19 The method according to claim 17, wherein the step of detecting the fault state further comprises: detecting the fault state at the home node based on the fact that the second CPU subsystem receives a probe requesting the cache line data after processing the cache line ejection data; and sending a request to the home node to provide updated cache line data corresponding to the cache line ejection data to the first core complex before communicating the cache line ejection data at the second CPU subsystem. Claim 20 In claim 17, the step of detecting the fault state comprises: detecting the fault state at the home node based on the second CPU subsystem having the cache line data and responding to a probe request for the cache line data before processing the cache line ejection data; and the step of retaining the cache line ejection data until the fault state is resolved further comprises the step of retaining the cache line ejection data at the second CPU subsystem until the home node communicates the completion of the cache line ejection transaction.

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