Semiconductor package

Abstract

A semiconductor package according to an embodiment of the present invention comprises a substrate, at least one semiconductor chip mounted on the upper surface of the substrate, a molding portion covering a portion of the sidewall of the semiconductor chip, and a heat dissipation member having a trench formed at the bottom that contacts the upper surface and the remaining portion of the sidewall of the semiconductor chip.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] Semiconductor packaging is the process of packaging a semiconductor chip (or semiconductor die) to electrically connect it to an electronic device.

[0003] Recently, as the implementation of high-performance devices is required, semiconductor chip sizes and the consequent size of semiconductor packages are increasing. On the other hand, due to the trend toward slimmer electronic devices, the thickness of semiconductor packages is actually decreasing.

[0004] In particular, as various semiconductor chips are installed, high temperatures can be generated during operation. If this high temperature is transferred to a semiconductor chip performing memory functions, it can lead to performance degradation and malfunctions, such as the destruction of memory cells. The problem to be solved

[0005] The present invention has been devised to resolve the above-mentioned problems, and the objective of the present invention is to provide a semiconductor package capable of improving heat dissipation efficiency while compensating for the size of the semiconductor package as the semiconductor chip size increases. means of solving the problem

[0006] A semiconductor package according to an embodiment of the present invention comprises a substrate, at least one semiconductor chip mounted on the upper surface of the substrate, a molding portion covering a portion of the sidewall of the semiconductor chip, and a heat dissipation member having a trench formed at the bottom that contacts the upper surface and the remaining portion of the sidewall of the semiconductor chip.

[0007] A semiconductor package according to an embodiment of the present invention comprises a substrate, at least two semiconductor chips mounted on the upper surface of the substrate, a final molding portion covering the upper surface of the substrate and a portion of the sidewall of the semiconductor chips, and two trenches engaged with the upper surface and the upper sidewall of each semiconductor chip, and a heat dissipation member attached to the upper surface edge of the substrate, the upper surface and the sidewall of the final molding portion, and the upper surface and the upper sidewall of the semiconductor chips.

[0008] A semiconductor package according to an embodiment of the present invention comprises a substrate, at least two semiconductor chips mounted on the upper surface of the substrate, a final molding portion formed to cover the upper surface of the substrate and a portion of the sidewall of the semiconductor chip, a dummy heat sink superimposed on the upper surface of the semiconductor chip, a Thermal Interface Material (TIM) disposed on the dummy heat sink, and a heat dissipation member that covers a portion of the sidewall of the semiconductor chip, the dummy heat sink, and the TIM on the final molding portion and contacts a portion of the sidewall of the semiconductor chip.

[0009] The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

[0010] Prior to this, terms and words used in this specification and claims should not be interpreted in their ordinary and dictionary senses, but should be interpreted in a sense and concept consistent with the technical spirit of the invention, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention. Brief explanation of the drawing

[0011] FIGS. 1a and 1b are cross-sectional views of a semiconductor package according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention. FIGS. 3 to 7 are illustrative drawings for explaining a method for manufacturing a semiconductor package according to a second embodiment of the present invention. FIG. 8 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention. FIGS. 9 to 13 are illustrative drawings for explaining a method for manufacturing a semiconductor package according to a third embodiment of the present invention. FIG. 14 is a cross-sectional view of a semiconductor package according to a fourth embodiment of the present invention. FIGS. 15 to 20 are illustrative drawings for explaining a method for manufacturing a semiconductor package according to a fourth embodiment of the present invention. Specific details for implementing the invention

[0012] The objects, specific advantages, and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments in conjunction with the accompanying drawings. It should be noted that in assigning reference numbers to the components of each drawing in this specification, the same components are assigned the same number whenever possible, even if they are shown in different drawings. Furthermore, terms such as "first," "second," etc., may be used to describe various components, but said components are not to be limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. Additionally, in describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions would unnecessarily obscure the essence of the invention.

[0013] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. FIGS. 1a and FIGS. 1b are cross-sectional views of a semiconductor package according to a first embodiment of the present invention.

[0014] A semiconductor package (100) according to a first embodiment of the present invention may include a substrate (101), two semiconductor chips (110, 120) mounted on the upper surface of the substrate (101), a molding portion (130) formed to cover the upper surface of the substrate (101) and a portion of the sidewall of the semiconductor chips (110, 120), and a heat dissipation member (140) attached to the upper surface and the upper sidewall of the semiconductor chips (110, 120) with a Thermal Interface Material (TIM: 145) in between. Additionally, the semiconductor package (100) according to a first embodiment of the present invention may further include a bump (115, 125) connecting the substrate (101) and the semiconductor chips (110, 120) and a solder ball (105) attached to the lower surface of the substrate (101).

[0015] The substrate (101) may be, for example, a printed circuit board (PCB). In this case, the printed circuit board may be a single-sided PCB or a double-sided PCB, or a multi-layer PCB containing one or more internal wiring patterns within the substrate. Additionally, the substrate (101) may be a rigid printed circuit board or a flexible printed circuit board.

[0016] Such substrates (101) may include, for example, epoxy resin, polyimide resin, bismalemide triazine (BT) resin, FR-4 (Flame Retardant 4), FR-5, ceramic, silicon, glass, photosensitive liquid dielectrics, photosensitive dry-film dielectrics, polyimide flexible film thermally cured dry films, thermally cured liquid dielectrics, resin coated copper foil (RCC), thermoplastic, or flexible resin.

[0017] Alternatively, the substrate (101) may be formed by bonding a plurality of rigid plates, or by bonding a thin flexible printed circuit board and a rigid plate. In this case, the plurality of rigid plates or printed circuit boards bonded to each other may each include a wiring pattern. Additionally, the substrate (101) may include an LTCC (low temperature co-fired ceramic) substrate. An LTCC substrate may have a plurality of ceramic layers stacked thereon and may include a wiring pattern therein.

[0018] The substrate (101) may include at least one insulating layer and a metal wiring layer. The metal wiring layer is a circuit pattern formed on the substrate (101) and may be formed of, for example, aluminum (Al) or copper (Cu). The surface of the metal wiring layer may be plated with tin (Sb), gold (Au), nickel (Ni), or lead (Pb).

[0019] Additionally, the substrate (101) may include a conductive pad (not shown) for connecting the semiconductor chip (110, 120) and the substrate (101) via a bump (115), and a solder ball pad (not shown) on which a solder ball (105) is located for connecting the semiconductor package (100) and an external circuit, etc. The conductive pad and the solder ball pad may be formed of, for example, aluminum (Al) or copper (Cu). The surface of such conductive pad and solder ball pad may be plated with, for example, tin (Sb), gold (Au), nickel (Ni), or lead (Pb). The conductive pad and the solder ball pad may be part of a metal wiring layer.

[0020] In addition, the substrate (101) may further include a via structure, such as a Through Silicon Via (TSV), that penetrates at least a portion of the upper and lower surfaces of the substrate (101) to connect the conductive pad and the solder ball pad to each other.

[0021] As shown in FIG. 1a, the semiconductor chips (110, 120) may include a first semiconductor chip (110) mounted on one side of the upper surface of the substrate (101) and a second semiconductor chip (120) mounted on the other side of the upper surface of the substrate (101). Of course, the structure is not limited to having two semiconductor chips (110, 120) mounted on the upper surface of the substrate (101), and one or more semiconductor chips may be mounted on the upper surface of the substrate (101).

[0022] The semiconductor chips (110, 120) may be mounted on the substrate (101) by flip-chip bonding or by wire bonding. However, this is exemplary and is not limited thereto.

[0023] When semiconductor chips (110, 120) are mounted using a flip-chip bonding method, the semiconductor chips (110, 120) can be connected to the substrate (101) through bumps (115, 125) respectively, and the active surface of the semiconductor chips (110, 120) can be attached so as to face the substrate (101).

[0024] The semiconductor chip (110, 120) may be a semiconductor chip that performs various functions such as memory, logic, microprocessor, analog device, digital signal processor, or System On Chip. Additionally, the semiconductor chip (110, 120) may be a multi-chip having a structure in which at least two semiconductor chips are stacked. In particular, the first semiconductor chip (110) and the second semiconductor chip (120) may both be of the same type of memory device, or one may be a memory device and the other may be a micro-controller device.

[0025] The molding portion (130) is formed to cover the upper surface of the substrate (101) and a portion of the sidewall of the semiconductor chip (110, 120), in particular, to cover the sidewall area excluding a predetermined heat dissipation trench depth (d) of the trench (141, 142) with respect to the sidewall height (D) of the semiconductor chip (110, 120). At this time, the predetermined heat dissipation trench depth (d) can be set up to 50% of the sidewall height (D).

[0026] These molding portions (130) can be formed, for example, through a Molded Under Fill (MUF) process. Here, the MUF process refers to a process in which the space between the semiconductor chips (110, 120) and the substrate (101) is filled together with the molding portions (130) without performing a separate process of filling the space between the semiconductor chips (110, 120) and the substrate (101) with under fill.

[0027] Of course, the molding portion (130) may be formed by a process other than the MUF process. That is, molding may be performed by first filling the space between the semiconductor chip (110, 120) and the substrate (101) with a molding material as an underfill, and then covering a portion of the sidewall of the semiconductor chip (110, 120) with the molding material. At this time, the underfill filling the space between the semiconductor chip (110, 120) and the substrate (101) and the molding material covering a portion of the sidewall of the semiconductor chip (110, 120), that is, the sidewall area excluding a predetermined heat dissipation trench depth (d) for the sidewall height (D), may be formed of the same material, but may also be formed of different materials.

[0028] The heat dissipation member (140) is attached to the upper surface and side wall of the semiconductor chip (110, 120) via the TIM (145) and has a flat plate shape that forms two trenches, including a first trench (141) and a second trench (142), into which the upper portions of the first semiconductor chip (110) and the second semiconductor chip (120), respectively, are interlocked and inserted on the lower surface. Each of these first and second trenches (141, 142) has a shape that includes a trench depth (d) into which the upper portions of the first semiconductor chip (110) and the second semiconductor chip (120), respectively, are interlocked, and may have various cross-sectional shapes such as a square or a rectangle depending on the upper shape of the first semiconductor chip (110) and the second semiconductor chip (120), respectively.

[0029] Here, the trench depth (d) can be set up to 50% of the sidewall height (D) of each of the first semiconductor chip (110) and the second semiconductor chip (120). If the trench depth (d) exceeds 50% of the sidewall height (D), problems such as undercutting occur and the process yield decreases.

[0030] The heat dissipation member (140) may be made of any one or a combination thereof selected from the group consisting of non-metallic materials such as carbon and silicon, metal materials such as nickel (Ni), copper, copper alloy, aluminum, aluminum alloy, steel, and stainless steel, metal oxides such as magnesium oxide, alumina, and titanium dioxide (TiO2), and metal nitrides.

[0031] The TIM (145) may include, for example, mineral oil, grease, gap filler putty, phase change gel, phase change material pads, or particle filled epoxy. However, the TIM (145) is not limited to these and may include various materials with excellent thermal conductivity.

[0032] The semiconductor package (100) according to the first embodiment of the present invention configured as described above has a multi-chip structure in which the first semiconductor chip (110) and the second semiconductor chip (120) are each stacked, so that even if the height of the chip increases, the overall height of the package can be maintained without increasing due to the trench of the heat dissipation member (140) having a depth including the trench depth (d). Accordingly, the semiconductor package (100) according to the first embodiment of the present invention can be provided with the height of the first semiconductor chip (110) and the second semiconductor chip (120) increased.

[0033] In addition, the semiconductor package (100) according to the first embodiment of the present invention can achieve heat transfer through the upper side walls of each of the first semiconductor chip (110) and the second semiconductor chip (120) by means of a heat dissipation member (140) having a trench with a depth including a trench depth (d), thereby improving heat dissipation efficiency.

[0034] Hereinafter, a semiconductor package (200) and a manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. 2 to 7. FIG. 2 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention, and FIGS. 3 to 7 are illustrative drawings for explaining a manufacturing method of a semiconductor package according to a second embodiment of the present invention.

[0035] A semiconductor package (200) according to a second embodiment of the present invention, similar to a semiconductor package (100) according to a first embodiment of the present invention described above, may include a substrate (201) as shown in FIG. 2, two semiconductor chips (210, 220) mounted on the upper surface of the substrate (201), a final molding part (232) formed to cover the upper surface of the substrate (201) and a part of the side wall of the semiconductor chips (210, 220), and a heat dissipation member (240) attached to the upper surface edge of the substrate (201), the upper and side of the final molding part (232), and the upper surface and side wall of the semiconductor chips (210, 220) with a TIM (245) in between. In addition, the semiconductor package (200) according to the second embodiment of the present invention may further include bumps (215, 225) connecting the substrate (201) and the semiconductor chip (210, 220) respectively, and a solder ball (205) attached to the lower surface of the substrate (201).

[0036] The semiconductor package (200) according to the second embodiment of the present invention is characterized in that a heat dissipation member (240) is attached to the upper and side of the final molding part (232) and the upper surface and side wall of the semiconductor chip (210, 220) with the TIM (245) in between.

[0037] Specifically, as shown in FIG. 2, the heat dissipation member (240) forms two trenches in which the upper portions of the first semiconductor chip (210) and the second semiconductor chip (220) are interlocked and inserted, and each trench is in the form of a groove having a depth including the trench depth (d) in which the upper portions of the first semiconductor chip (210) and the second semiconductor chip (220) are interlocked, and is mounted on the upper edge of the substrate (201) by attaching a side wall having a thickness (S) from the side of the final molding part (232).

[0038] These heat dissipation members (240) have the characteristic of dissipating heat by transferring the heat generated from each of the first semiconductor chip (210) and the second semiconductor chip (220) in the upward direction as well as the side direction.

[0039] Accordingly, the semiconductor package (200) according to the second embodiment of the present invention has a multi-chip structure in which the first semiconductor chip (210) and the second semiconductor chip (220) are stacked, so even if the height of the chip increases, the overall height of the package can be maintained without increasing due to the trench of the heat dissipation member (240) including the trench depth (d), and heat is transferred together in the lateral direction through the side wall having a thickness (S) to dissipate heat.

[0040] In addition, the semiconductor package (200) according to the second embodiment of the present invention can obtain electromagnetic interference (EMI) shielding due to the structure in which a heat dissipation member (240) surrounds the first semiconductor chip (210) and the second semiconductor chip (220) in the upper and side directions.

[0041] The method for manufacturing a semiconductor package (200) according to the second embodiment of the present invention first mounts a first semiconductor chip (210) and a second semiconductor chip (220), respectively, on the upper surface of a substrate (201) as shown in FIG. 3.

[0042] Each of the first semiconductor chip (210) and the second semiconductor chip (220) may be mounted on the substrate (201), for example, by a flip-chip bonding method, and connected to the substrate (201) using bumps (215, 225). Of course, they may also be mounted by a wire bonding method in addition to the flip-chip bonding method, and this is exemplary and not limited thereto.

[0043] After mounting the first semiconductor chip (210) and the second semiconductor chip (220) respectively on the upper surface of the substrate (201), an initial molding portion (230) is formed that covers the upper surface of the substrate (201) and a portion of the sidewalls of the semiconductor chips (210, 220) as shown in FIG. 4.

[0044] The initial molding portion (230) is formed to cover the upper surface of the substrate (201) and a portion of the sidewall of the semiconductor chip (210, 220), in particular, to cover the sidewall area excluding a predetermined heat dissipation trench depth (d) with respect to the sidewall height (D) of the semiconductor chip (210, 220). At this time, the exposed heat dissipation trench depth (d) can be set up to 50% of the sidewall height (D).

[0045] This initial molding portion (230) can be formed by a Molded Under Fill (MUF) process that fills the space between the semiconductor chip (210, 220) and the substrate (201) together, without performing a separate process of filling the space between the semiconductor chip (210, 220) and the substrate (201) with underfill.

[0046] Of course, the initial molding portion (230) may be formed by a process other than the MUF process. That is, a process may be performed in which a molding material is first filled as an underfill between the semiconductor chip (210, 220) and the substrate (201), and then a part of the sidewall of the semiconductor chip (210, 220) is covered with the molding material so that the heat dissipation trench depth (d) is exposed. At this time, the underfill filling between the semiconductor chip (210, 220) and the substrate (201) and the molding material covering the sidewall area excluding a predetermined heat dissipation trench depth (d) for a part of the sidewall of the semiconductor chip (210, 220), i.e., the sidewall height (D), may be formed of the same material, but may also be formed of different materials.

[0047] After forming the initial molding portion (230), a removal process is performed to remove an area corresponding to the thickness (S) along the edge of the initial molding portion (230) as shown in FIG. 5.

[0048] To remove an area corresponding to the thickness (S) along the edge of the initial molding part (230), for example, laser drilling, wet etching, dry etching, a blade, etc., can be used.

[0049] Through this removal process, as shown in FIG. 5, an area corresponding to the thickness (S) at the edge of the initial molding part (230) is removed, and the upper edge surface of the corresponding substrate (201) is exposed, thereby forming the final molding part (232).

[0050] After forming the final molding part (232) through a removal process, a TIM (245) is provided on the upper surface of the semiconductor chip (210, 220) as shown in FIG. 6. Of course, the TIM (245) may also be provided on the upper surface of the edge of the exposed substrate (201) and on the outer surface of the final molding part (232), in addition to the upper surface of the semiconductor chip (210, 220).

[0051] TIM (245) may include, for example, mineral oil, grease, gap filler putty, phase change gel, phase change material pads or particle filled epoxy, and may include various materials with excellent thermal conductivity.

[0052] These TIMs (245) are provided by methods such as application using a dispenser or coating using a roller.

[0053] After providing the TIM (245), as shown in FIG. 7, a pre-prepared heat dissipation member (240) is attached to the upper edge surface of the substrate (201), the upper and side surfaces of the final molding part (232), and the upper and side walls of the semiconductor chips (210, 220) with the TIM (245) in between.

[0054] At this time, the heat dissipation member (240) may be prepared in advance in a form that corresponds to the upper surface of each semiconductor chip (210, 220) by means such as injection molding or a compression jig, forms two trenches with a depth including trench depth (d), and forms a side wall having a thickness (S).

[0055] In this way, the method for manufacturing a semiconductor package (200) according to the second embodiment of the present invention can easily manufacture a semiconductor package that dissipates heat by transferring heat from a semiconductor chip (210, 220) together in a lateral direction through a side wall having a thickness (S).

[0056] Hereinafter, a semiconductor package (300) according to a third embodiment of the present invention will be described using FIGS. 8 to 13. FIG. 8 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention, and FIGS. 9 to 13 are illustrative drawings for explaining a method of manufacturing a semiconductor package according to a third embodiment of the present invention.

[0057] A semiconductor package (300) according to the third embodiment of the present invention may include, as shown in FIG. 8, a substrate (301), two semiconductor chips (310, 320) mounted on the upper surface of the substrate (301), a final molding portion (332) formed to cover the upper surface of the substrate (301) and a portion of the side wall of the semiconductor chips (310, 320), a dummy heat sink (350) provided overlappingly across the upper surface of the two semiconductor chips (310, 320), and a heat dissipation member (340) attached to the upper part of the final molding portion (332), the upper surface and side of the dummy heat sink (350), and the upper part of the outer wall of the semiconductor chips (310, 320) with a TIM (345) in between. In addition, the semiconductor package (300) according to the third embodiment of the present invention may further include bumps (315, 325) connecting the substrate (301) and the semiconductor chip (310, 320) respectively, and a solder ball (305) attached to the lower surface of the substrate (301).

[0058] The semiconductor package (300) according to the third embodiment of the present invention further comprises a dummy heat sink (350) superimposed on the upper surface of the semiconductor chips (310, 320), so as to store heat generated while achieving thermal equilibrium between the semiconductor chips (310, 320) and to dissipate heat in the upper and side directions through the heat dissipation member (340).

[0059] In addition, the semiconductor package (300) according to the third embodiment of the present invention is characterized by having a flat plate shape in which a heat dissipation member (340) forms a trench in which a dummy heat sink (350) and the upper portions of the first semiconductor chip (310) and the second semiconductor chip (320) are interlocked and inserted in the center of the lower surface. This trench is formed in the shape of a groove having a depth including the thickness of the TIM (345), the thickness of the dummy heat sink (350), and the trench depth (d) of the semiconductor chips (310, 320).

[0060] Accordingly, the semiconductor package (300) according to the third embodiment of the present invention can maintain its size without increasing the overall height of the package by means of the trench of the heat dissipation member (340), even if the height of the first semiconductor chip (310) and the second semiconductor chip (320) each increase due to the multi-chip structure and a dummy heat sink (350) is provided, and has the effect of dissipating heat by transferring heat together in the lateral direction through the heat dissipation member (340) that contacts the upper side wall of the semiconductor chips (310, 320).

[0061] The method for manufacturing a semiconductor package (300) according to the third embodiment of the present invention first mounts a first semiconductor chip (310) and a second semiconductor chip (320), respectively, on the upper surface of a substrate (301) as shown in FIG. 9.

[0062] Each of the first semiconductor chip (310) and the second semiconductor chip (320) can be mounted on the substrate (301), for example, by a flip-chip bonding method, and connected to the substrate (201) using bumps (315, 325). Of course, they may also be mounted by a wire bonding method in addition to the flip-chip bonding method, and this is exemplary and not limited thereto.

[0063] After mounting the first semiconductor chip (310) and the second semiconductor chip (320) respectively on the upper surface of the substrate (301), an initial molding portion (330) is formed that contacts the upper surface of the substrate (301) and the entire side wall of the semiconductor chips (310, 320) so that the upper surface of the semiconductor chips (310, 320) is exposed as shown in FIG. 10.

[0064] This initial molding portion (330) can be formed by a MUF process that fills the space between the semiconductor chip (310, 320) and the substrate (301) together, without performing a separate process of filling the space between the semiconductor chip (310, 320) and the substrate (301) with underfill. Of course, the initial molding portion (330) can be formed by a process other than the MUF process, so that a process of first filling the space between the semiconductor chip (310, 320) and the substrate (301) with molding material as underfill, and then covering the sidewalls of the semiconductor chip (310, 320) with molding material may be performed.

[0065] After forming the initial molding part (330), a dummy heat sink (350) is mounted on the upper surface of the exposed semiconductor chip (310, 320) as shown in FIG. 11.

[0066] The dummy heat sink (350) has a plate shape and can be formed from the same material as the heat dissipation member (340), for example, it can be formed from any one or a combination of materials selected from the group consisting of non-metallic materials such as carbon and silicon, metallic materials such as nickel (Ni), copper, copper alloy, aluminum, aluminum alloy, steel, and stainless steel, and metal oxides and metal nitrides such as magnesium oxide, alumina, and titanium dioxide (TiO2).

[0067] At this time, the dummy heat sink (350) can be bonded to the upper surface of each of the first semiconductor chip (310) and the second semiconductor chip (320) using TIM.

[0068] Since these dummy heat sinks (350) are bonded over the upper surfaces of the first semiconductor chip (310) and the second semiconductor chip (320), the heat transfer path generated from the first semiconductor chip (310) and the second semiconductor chip (320) can be widened to achieve heat dissipation.

[0069] After mounting the dummy heat sink (350), a removal process is performed to remove the area along the outer edge of the initial molding part (330) to a predetermined heat dissipation trench depth (d) as shown in FIG. 12.

[0070] Through this removal process, as shown in FIG. 12, a final molding part (332) is formed in which an area is removed from the outer edge of the initial molding part (330) to a predetermined heat dissipation trench depth (d), and the outer upper sidewalls of each of the first semiconductor chip (310) and the second semiconductor chip (320) are exposed by the heat dissipation trench depth (d). At this time, the exposed heat dissipation trench depth (d) can be set up to 50% of the sidewall height (D) of each of the first semiconductor chip (310) and the second semiconductor chip (320).

[0071] After forming the final molded portion (332) through a removal process, a TIM (345) is provided on the upper surface of the dummy heat sink (350) as shown in FIG. 12. Here, the TIM (345) may include, for example, mineral oil, grease, gap filler putty, phase change gel, phase change material pads, or particle filled epoxy, and may also include various materials with excellent thermal conductivity.

[0072] These TIMs (345) can be provided by methods such as application using a dispenser or coating using a roller.

[0073] After providing the TIM (345), as shown in FIG. 13, a pre-prepared heat dissipation member (340) is attached to the upper surface and side of the dummy heat sink (350), the upper edge of the final molding part (332), and the upper outer wall of the semiconductor chip (310, 320) with the TIM (345) in between.

[0074] At this time, the heat dissipation member (340) may be prepared in advance as a plate-shaped structure having a groove-shaped trench having a depth including the thickness of the TIM (345), the thickness of the dummy heat dissipation plate (350), and the trench depth (d) of the semiconductor chips (310, 320), corresponding to the dummy heat dissipation plate (350) by means such as injection molding or a compression jig.

[0075] In this way, the method for manufacturing a semiconductor package (300) according to the third embodiment of the present invention can easily manufacture a semiconductor package (300) that can transfer heat generated while achieving thermal equilibrium between semiconductor chips (310, 320) using a dummy heat sink (350) and dissipate heat in the upper and side directions through a heat dissipation member (340).

[0076] In particular, the method for manufacturing a semiconductor package (300) according to the third embodiment of the present invention can easily manufacture a semiconductor package (300) that maintains its size without increasing the overall height of the package by means of a trench of a heat dissipation member (340), even if the height of the semiconductor chip (310, 320) increases and a dummy heat sink (350) is provided.

[0077] Hereinafter, a semiconductor package (400) according to the fourth embodiment of the present invention will be described with reference to FIGS. 14 to 20. FIG. 14 is a cross-sectional view of a semiconductor package according to the fourth embodiment of the present invention, and FIGS. 15 to 20 are illustrative drawings for explaining a method of manufacturing a semiconductor package according to the fourth embodiment of the present invention.

[0078] A semiconductor package (400) according to the fourth embodiment of the present invention, similar to the semiconductor package (200) according to the second embodiment of the present invention described above, may include a substrate (401) as shown in FIG. 14, two semiconductor chips (410, 420) mounted on the upper surface of the substrate (401), a final molding part (432) formed to cover the upper surface of the substrate (401) and a part of the side wall of the semiconductor chips (410, 420), and a heat dissipation member (440) attached to the upper surface edge of the substrate (401), the upper and side of the final molding part (432), and the upper and side wall of the semiconductor chips (410, 420) with the TIM in between. In addition, the semiconductor package (400) according to the fourth embodiment of the present invention may further include bumps (415, 425) connecting the substrate (401) and the semiconductor chip (410, 420) respectively, and a solder ball (405) attached to the lower surface of the substrate (401).

[0079] The semiconductor package (400) according to the fourth embodiment of the present invention is characterized in that the heat dissipation member (440) is composed of a heat dissipation base (443) and a heat dissipation portion (442) comprising a porous pattern formed by a plurality of pores that are three-dimensionally interconnected on the upper surface of the heat dissipation base (443), and is attached to the upper and side of the final molding portion (432) and the upper and side walls of the semiconductor chips (410, 420) with the TIM in between.

[0080] Specifically, the heat dissipation base (443) is formed by including a polymer and a thermally conductive filler.

[0081] The polymer is an insulating polymer and may include, for example, polypropylene, acrylonitrile butadiene styrene, polycarbonate, nylon, polyphenylene sulfide, polythiophene, and polyetheretherketone. Of course, the polymer component is not limited to the materials mentioned above and can be used regardless of whether it is an insulating polymer.

[0082] The thermally conductive filler is a ceramic component or a metal component that can be optionally added to form a thermal conduction path at the grain boundaries between polymer particles, and the ceramic component may include, for example, at least one or a composite of boron nitride, aluminum nitride, magnesium oxide, aluminum oxide, silicon carbide, and silicon nitride, and the metal component may include at least one or a composite of copper, aluminum, gold, and silver.

[0083] The heat dissipation base (443) configured in this way performs the function of transferring heat from the semiconductor chips (410, 420) to the heat dissipation part (442) by means of a thermally conductive filler while being electrically insulated by a polymer component.

[0084] As shown in FIG. 14, the heat dissipation portion (442) is composed of a porous structure consisting of a plurality of pores that are interconnected in three dimensions, and the porous structure can be formed by selecting or combining, for example, non-metallic materials such as carbon or silicon, metallic materials such as nickel (Ni), copper (Cu), or aluminum, or metal oxides or metal nitrides such as magnesium oxide, alumina, or titanium dioxide (TiO2).

[0085] At this time, the pores can be provided with diameters ranging from tens of micrometers to several millimeters, and are connected to each other in three dimensions by forming multiple connecting passages with other pores. At this time, the connecting passages between the pores are formed by surface contact between multiple beads (41) to be described later, and the surface contact portion between the beads (41) formed in the Closest Packing Structure formed by the multiple beads (41) is formed as multiple connecting passages.

[0086] Since this heat dissipation part (442) is a structure in which a plurality of pores are connected to each other in three dimensions, the porosity can be maximized to increase the amount of heat released per unit area, thereby improving heat dissipation efficiency.

[0087] The heat dissipation member (440) configured in this manner forms two trenches (498, 499) that are inserted into the upper portions of the first semiconductor chip (410) and the second semiconductor chip (420), respectively, as shown in FIG. 14, and each of the trenches (498, 499) is in the shape of a groove having a depth including a trench depth (d) into which the upper portions of the first semiconductor chip (410) and the second semiconductor chip (420) respectively are inserted.

[0088] These heat dissipation members (440) are characterized by transferring heat generated from each of the first semiconductor chip (210) and the second semiconductor chip (220) in both the upward and side directions through the heat dissipation base (443), and maximizing heat dissipation efficiency through the heat dissipation section (442).

[0089] Accordingly, the semiconductor package (400) according to the fourth embodiment of the present invention has a multi-chip structure in which the first semiconductor chip (410) and the second semiconductor chip (420) are stacked, so even if the height of the chip increases, the overall height of the package can be maintained without increasing due to the trench of the heat dissipation member (440) including the trench depth (d), and heat dissipation is achieved in the lateral direction, and the heat dissipation efficiency is maximized through the heat dissipation part (442).

[0090] The method for manufacturing a semiconductor package (400) according to the fourth embodiment of the present invention first involves immersing a bead (41) in an internal groove of a mold (50) corresponding to the size of the heat dissipation member (440) together with an ethanol solution and depositing it into a stacked structure at a temperature below room temperature, as shown in FIG. 15, in order to manufacture a heat dissipation member (440) constituting a heat dissipation member (440).

[0091] Afterward, as shown in FIG. 16, a first jig (61) is pressed into the inner groove of the mold (50) to arrange a plurality of deposited beads (41) in the shape of a heat dissipation section (442). The first jig (61) may be in the shape of a piston having a square lower surface corresponding to the shape of the heat dissipation section (442).

[0092] By performing slow drying or freeze drying with the multiple beads (41) arranged in this manner, the multiple beads (41) can form a closest packed structure, such as a hexagonal closest packed structure or a cubic closest packed structure.

[0093] After completely evaporating the ethanol, a pressurizing and heating process is performed on the stacked structure of beads (41) to increase the contact area between the beads (41) in the stacked structure of beads (41).

[0094] Through this pressurization and heating process, a plurality of beads (41) in the laminated structure of the beads (41) are more closely packed together, and the contact area between the beads (41) is increased.

[0095] As shown in FIG. 16, a heat dissipation precursor (precursor: 441) is injected into the stacked structure of the beads (41) that has become more densely packed in this way and heated.

[0096] Here, the heat dissipation precursor material (441) can be selected according to the material of the porous structure described above, and can be prepared in various ways depending on the material selected from, for example, non-metallic materials such as carbon or silicon, metallic materials such as nickel (Ni), copper (Cu), or aluminum, or metal oxides or metal nitrides such as magnesium oxide, alumina, or titanium dioxide (TiO2). For example, when the porous structure is formed with carbon material, the heat dissipation precursor material (441) may use, for example, resorcinol.

[0097] The heat dissipation precursor material (441) prepared in this way may be introduced into the stacked structure of the bead (41) as shown in FIG. 16 and then heated to perform a gelation process. Here, in order to smoothly introduce the heat dissipation precursor material (441), the introduction of the carbon heat dissipation precursor material (441) may be performed by compression using the first jig (61).

[0098] Afterwards, a carbonization process is performed on the stacked structure of beads (41) containing a heat dissipation precursor (441) by heating it in a nitrogen atmosphere for a predetermined time.

[0099] Through this carbonization process, as shown in FIG. 17, the beads (41) are destroyed and the heat dissipation precursor material (441) is carbonized, so that a heat dissipation part (442) of a porous structure having a plurality of pores connected in three dimensions through a plurality of connecting passages can be formed.

[0100] After forming the heat dissipation portion (442) of the porous structure in this way, as shown in FIG. 17, a mixture containing a polymer and a thermally conductive filler is filled into the interior of the heat dissipation portion (442) and cured by pressing through the second jig (62).

[0101] The lower surface of the second jig (62) has a shape corresponding to the inner surface shape of the heat dissipation base (443), and the second jig (62) compresses the mixture to form a bond with the heat dissipation part (442) and hardens the mixture.

[0102] After the mixture is cured, the second jig (62) is removed and separated from the mold (50), and a heat dissipation member (440) composed of a heat dissipation base (443) and a heat dissipation part (442) is obtained as shown in FIG. 18.

[0103] These heat dissipation members (440) form two trenches (498, 499) that are inserted into the upper portions of the first semiconductor chip (410) and the second semiconductor chip (420), respectively, on the inner surface of the heat dissipation base (443), and each of the trenches (498, 499) has a rectangular groove shape with a depth including a trench depth (d) into which the upper portions of the first semiconductor chip (410) and the second semiconductor chip (420), respectively, are engaged.

[0104] The heat dissipation member (440) obtained in this way is attached to the semiconductor chips (410, 420) and the final molding part (432) provided on the upper surface of the substrate (401) as shown in FIG. 19. At this time, the heat dissipation member (440) can be attached to the semiconductor chips (410, 420) and the final molding part (432) with the TIM already provided on the inner surface of the heat dissipation base part (443) of the heat dissipation member (440).

[0105] Accordingly, as shown in FIG. 20, a semiconductor package (400) according to the fourth embodiment of the present invention is formed, in which a heat dissipation member (440) is attached to the upper edge of the substrate (401), the upper and side of the final molding part (432), and the upper and side walls of the semiconductor chips (410, 420), with the TIM in between.

[0106] The method for manufacturing a semiconductor package (400) according to the fourth embodiment of the present invention allows for the easy manufacturing of a heat dissipation member (440) composed of a heat dissipation base (443) and a heat dissipation part (442), and enables the size to be maintained without increasing the overall height of the package by means of a trench of the heat dissipation member (440), and enables heat dissipation in the lateral direction, and enables the acquisition of a semiconductor package with maximized heat dissipation efficiency through the heat dissipation part (442).

[0108] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the aforementioned embodiments are for illustrative purposes only and are not intended to be limiting.

[0109] Furthermore, a person skilled in the art will understand that various implementations are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0110] 100,200,300,400: Semiconductor package 101,201,301,401: Substrate 105,205,305,405: Solder ball 115,125,215,225,315,325,415,425: Bump 110,210,310,410: 1st semiconductor chip 120,220,320,420: 2nd semiconductor chip 130, 230, 330: Molding part 140, 240, 340, 440: Heat dissipation member 145,245,345: TIM 350: Dummy heat sink 442: Heat dissipation section 443: Heat dissipation base

Claims

Claim 1 A semiconductor package comprising: a substrate; at least one semiconductor chip mounted on the upper surface of the substrate; a molding portion covering a portion of the sidewall of the semiconductor chip; and a heat dissipation member having a trench formed at the bottom that contacts the upper surface of the semiconductor chip and the remainder of the sidewall, wherein the heat dissipation member comprises: a heat dissipation base portion that is in direct contact with the semiconductor chip; and a heat dissipation portion that is in direct contact with the upper surface and sidewall of the heat dissipation base portion, is spaced apart from the semiconductor chip, and includes a porous pattern composed of a plurality of voids. Claim 2 A semiconductor package according to claim 1, further comprising: a bump connecting the substrate and the semiconductor chip; and a solder ball attached to the lower surface of the substrate. Claim 3 A semiconductor package according to claim 1, characterized in that the trench is formed to a depth equal to or smaller than 50% of the sidewall height of the semiconductor chip. Claim 4 A semiconductor package according to claim 1, characterized in that the heat dissipation member has the upper surface of the semiconductor chip and the remaining portion of the side wall attached to the trench with a Thermal Interface Material (TIM) in between. Claim 5 A semiconductor package according to claim 1, wherein the heat dissipation member is in the shape of a flat plate. Claim 6 A semiconductor package according to claim 1, characterized in that the heat dissipation member is attached to the upper and side of the molding portion and mounted on the upper edge of the substrate. Claim 7 A semiconductor package according to claim 1, characterized by further comprising a dummy heat sink at the bottom of the heat dissipation member. Claim 8 delete Claim 9 A semiconductor package comprising: a substrate; at least two semiconductor chips mounted on the upper surface of the substrate; a final molding portion covering the upper surface of the substrate and a portion of the sidewall of the semiconductor chips; and a heat dissipation member having two trenches engaged with the upper surface and the upper sidewall of each of the semiconductor chips, and attached to the upper surface edge of the substrate, the upper and side portions of the final molding portion, the upper surface of the semiconductor chips, and the remainder of the sidewall of the semiconductor chips, wherein the heat dissipation member comprises: a heat dissipation base portion in direct contact with the semiconductor chips; and a heat dissipation portion in direct contact with the upper surface and sidewall of the heat dissipation base portion, spaced apart from the semiconductor chips, and comprising a porous pattern consisting of a plurality of voids. Claim 10 A semiconductor package comprising: a substrate; at least two semiconductor chips mounted on the upper surface of the substrate; a final molding portion formed to cover the upper surface of the substrate and a portion of the sidewall of the semiconductor chips; a dummy heat sink superimposed on the upper surface of the semiconductor chips; a Thermal Interface Material (TIM) disposed on the dummy heat sink; and a heat dissipation member on the final molding portion that covers a portion of the upper sidewall of the semiconductor chips, the dummy heat sink, and the TIM, and is in direct contact with the portion of the upper sidewall of the semiconductor chips and is in direct contact with the sidewall of the dummy heat sink and the sidewall of the TIM, respectively.

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