Method for manufacturing a wiring board

Abstract

A method for manufacturing a wiring board is provided that can suppress damage to the device layer during carrier peeling and can also perform a photolithography process with high precision on the device layer after carrier peeling. The method for manufacturing a wiring board comprises: a step of preparing a laminated sheet having a peeling layer, a metal layer, and a device layer in sequence on a carrier; a step of making a cutting line from the carrier-side surface of the laminated sheet such that, when viewed from a planar view, both ends reach the ends of the laminated sheet through the inner side of the outline of the device layer, and when viewed from a cross-sectional view, it penetrates the carrier, the peeling layer, and the metal layer; and a step of removing an outer edge portion from the cutting line in the carrier, the peeling layer, and the metal layer, thereby exposing a portion of the surface of the device layer on the metal layer side to form a pressurizable exposed portion to promote the peeling of the carrier.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a wiring board. Background Technology

[0002] In recent years, multilayering of printed circuit boards has become widespread in order to increase mounting density and achieve miniaturization. These multilayer printed circuit boards are used in most portable electronic devices for the purpose of weight reduction and miniaturization. Furthermore, these multilayer printed circuit boards require a reduction in the thickness of the interlayer insulation layer and further weight reduction as a circuit board.

[0003] As a technology that satisfies these requirements, a method for manufacturing a multilayer printed circuit board using a coreless build-up method is employed. The coreless build-up method is a method of creating a multilayer structure by alternately stacking (building up) insulating layers and wiring layers without using a so-called core substrate. In the coreless build-up method, it is proposed to use a metal foil equipped with a carrier so that the support and the multilayer printed circuit board can be easily separated. For example, Patent Document 1 (Japanese Patent Publication No. 2005-101137) discloses a method for manufacturing a package substrate for mounting a semiconductor device, comprising attaching an insulating resin layer to the carrier surface of a copper foil equipped with a carrier to form a support, forming a first wiring conductor on the ultra-thin copper layer side of the copper foil equipped with a carrier through processes such as photoresist processing, pattern electrolytic copper plating, and resist removal, forming a build-up wiring layer, separating the support substrate equipped with a carrier, and removing the ultra-thin copper layer.

[0004] In addition, for miniaturization of embedded circuits such as that disclosed in Patent Document 1, a metal foil having a carrier having a metal layer thickness of 1 μm or less is desired. Therefore, to realize a reduction in the thickness of the metal layer, it is proposed to form a metal layer by a vapor phase method such as sputtering. For example, Patent Document 2 (International Publication No. 2017 / 150283) discloses a copper foil having a carrier on which a peeling layer, an anti-reflective layer, and an ultra-thin copper layer (e.g., film thickness 300 nm) are formed by sputtering on a carrier such as a glass sheet. In addition, Patent Document 3 (International Publication No. 2017 / 150284) discloses a copper foil having a carrier on which an intermediate layer (e.g., an adhesive metal layer and a peeling auxiliary layer), a peeling layer, and an ultra-thin copper layer (e.g., film thickness 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent documents 2 and 3 also disclose that by interposing an intermediate layer composed of a predetermined metal, the mechanical peel strength of the carrier is improved, and by the anti-reflective layer exhibiting a desirable dark color, visibility in image inspection (e.g., automatic image inspection (AOI)) is improved.

[0005] In particular, along with the further miniaturization and energy saving of electronic devices, there is a growing demand for the high integration and thinning of semiconductor chips and printed circuit boards. In recent years, the adoption of FO-WLP (Fan-Out Wafer Level Packaging) and PLP (Panel Level Packaging) has been considered as next-generation packaging technologies to satisfy these demands. Furthermore, the adoption of coreless build-up methods is being considered for FO-WLP and PLP. As one such method, there is a process called the RDL-First (Redistribution Layer-First) method, in which a wiring layer and, if necessary, a build-up wiring layer are formed on the surface of a coreless support, followed by chip mounting and sealing, and then the support is peeled off. For example, Patent Document 4 (Japanese Patent Publication No. 2015-35551) discloses a method for manufacturing a semiconductor device comprising: forming a metal peel layer on the main surface of a support made of glass or silicon wafer; forming an insulating resin layer thereon; forming a redistribution layer including a build-up layer thereon; mounting and sealing a semiconductor integrated circuit thereon; exposing the peel layer by removing the support; exposing a secondary mounting pad by removing the peel layer; forming a solder bump on the surface of the secondary mounting pad; and secondary mounting.

[0006] However, when peeling off a carrier equipped with a wiring layer manufactured using a coreless build-up method, the wiring layer may bend significantly, causing disconnection or peeling, which may result in a decrease in the connection reliability of the wiring layer. Therefore, a method for removing a carrier to address this problem has been proposed. For example, Patent Document 5 (Japanese Patent Publication No. 2020-119952) discloses a method for removing a carrier from a work (e.g., including a wiring layer in contact with the temporary adhesive layer, a plurality of chips bonded to the wiring layer, and a mold layer sealing each chip) provided on the surface of a carrier through a temporary adhesive layer. In the method disclosed in Patent Document 5, a step portion is formed on the back side of the carrier that protrudes laterally compared to the surface side of the carrier on which the work is provided, and the carrier can be easily removed from the work by applying a downward force to the step portion while holding and supporting the work from above. In addition, Patent Document 6 (Japanese Patent Publication No. 2020-27888) discloses a method for removing a carrier from a workpiece provided on the surface of a carrier through a temporary adhesive layer, wherein a cutting blade is cut along the outer circumference of the carrier from the workpiece side to a depth that does not reach the back side of the carrier, thereby forming a stepped portion in which the back side of the carrier protrudes outwardly from the surface side. Prior art literature

[0007] Japanese Patent Publication No. 2005-101137, International Publication No. 2017 / 150283, International Publication No. 2017 / 150284, Japanese Patent Publication No. 2015-35551, Japanese Patent Publication No. 2020-119952, Japanese Patent Publication No. 2020-27888 The problem to be solved

[0008] There are cases where a photolithography process including the photolithographic transfer of a circuit pattern is performed on the surface of a wiring layer after the carrier has been peeled off. In this case, in a general exposure device, the corresponding size of the wafer or panel to which the exposure is performed is determined, and it is required to prepare a wafer or the like that matches this corresponding size. That is, if the size of the wafer or the like deviates from the predetermined corresponding size (for example, if it is smaller than the corresponding size), misalignment of the alignment mark that serves as the position alignment reference before exposure occurs, resulting in improper position alignment and potentially causing interference with subsequent exposure. In this regard, the carrier peeling method disclosed in Patent Documents 5 and 6 suppresses damage to the device layer (e.g., including a wiring layer, an electronic device (chip), and a mold layer) during carrier peeling, but because it involves processing of the device layer itself, the size inevitably becomes smaller, making it difficult to perform a photolithography process with high precision on the device layer after processing.

[0009] The inventors have obtained the finding that, by inserting a predetermined cutting line into a portion other than the device layer of a laminated sheet having a carrier, a release layer, a metal layer, and a device layer in sequence, and removing an outer edge portion from the cutting line to form a pressurizable exposed portion in the device layer, damage to the device layer during carrier release can be suppressed, and a wiring substrate can be manufactured that allows a photolithography process to be performed with high precision on the device layer after carrier release.

[0010] Accordingly, the objective of the present invention is to provide a method for manufacturing a wiring substrate that can suppress damage to the device layer during carrier peeling and also enables a high-precision photolithography process to be performed on the device layer after carrier peeling. means of solving the problem

[0011] According to one aspect of the present invention, a method for manufacturing a wiring board is provided,

[0012] A process for preparing a laminated sheet having a release layer, a metal layer, and a device layer in sequence on a carrier, and

[0013] A process of inserting a cutting line from the surface on the carrier side of the laminated sheet such that, when viewed in a planar view, both ends reach the ends of the laminated sheet through the inner side beyond the contour of the device layer, and also when viewed in a cross-sectional view, it penetrates the carrier, the release layer, and the metal layer;

[0014] A process of removing an outer edge portion from the cutting line in the above carrier, the above peeling layer, and the above metal layer, and thereby exposing a portion of the surface of the device layer on the metal layer side to form a pressurizable exposed portion for promoting peeling of the carrier.

[0015] A method including is provided.

[0016] According to another aspect of the present invention, a wiring substrate material having a peeling layer, a metal layer, and a device layer in sequence on a carrier, and

[0017] A wiring board material is provided such that, when viewed in a planar view, at least one outer edge portion of the carrier, the release layer, and the metal layer is missing along at least one line passing inward from the contour of the device layer, and accordingly, a portion of the surface of the device layer on the metal layer side is exposed. Brief explanation of the drawing

[0018] FIG. 1a is a process flow diagram illustrating an example of a method for manufacturing a wiring board of the present invention in a schematic cross-sectional view. FIG. 1b is a process flow diagram illustrating a process corresponding to FIG. 1a in a schematic top view of a laminated sheet viewed from the carrier side. FIG. 2 is a drawing illustrating an example of a process of pre-cutting an extended protruding portion of a metal layer along the contour of a device layer, and corresponds to a process prior to the process shown in (ii) of FIG. 1a. FIG. 3a is a top view showing (i) an example of the position of a cutting line in a rectangular laminated sheet and (ii) the state after removing the outer edge portion from the cutting line. FIG. 3b is a top view showing (i) an example of the position of a cutting line in a disc-shaped laminated sheet, and (ii) the state after removing the outer edge portion from the cutting line. FIG. 4 is a drawing illustrating an example of a process for peeling a carrier from a laminated sheet, and corresponds to a process after the process shown in (iii) of FIG. 1a. FIG. 5 is a process flow diagram illustrating an example of a conventional method for manufacturing a wiring board in a schematic cross-sectional view, corresponding to the overall process (processes (i) and (ii)). FIG. 6 is a process flow diagram illustrating an example of a conventional method for manufacturing a wiring board in a schematic cross-sectional view, and corresponds to the later processes (processes (iii) and (iv)) following the process shown in FIG. 5. FIG. 7a is a process flow diagram illustrating, in a top view, a case where the carrier is a silicon wafer, the direction of external stress progression due to peeling coincides with the cleavage orientation, and cracks occur in the silicon wafer, corresponding to the overall process (processes (i) and (ii)). FIG. 7b is a process flow diagram illustrating, in a top view, a case where the carrier is a silicon wafer, the direction of external stress progression due to peeling coincides with the cleavage orientation, and cracks occur in the silicon wafer, and corresponds to the later processes (processes (iii) and (iv)) following the process shown in FIG. 7a. FIG. 8a is a process flow diagram illustrating, in a top view, a case where the carrier is a silicon wafer, the direction of external stress progression due to peeling and the cleavage orientation are mismatched, and cracking of the silicon wafer is suppressed, corresponding to the overall process (processes (i) and (ii)). FIG. 8b is a process flow diagram illustrating, in a top view, a case where the carrier is a silicon wafer, the direction of external stress progression due to peeling and the cleavage orientation are mismatched, and cracking of the silicon wafer is suppressed, and corresponds to the later processes (processes (iii) and (iv)) following the process shown in FIG. 8a. Specific details for implementing the invention

[0019] Method for manufacturing a wiring board

[0020] The present invention relates to a method for manufacturing a wiring board. The method of the present invention comprises each of the following steps: (1) preparation of a laminated sheet, (2) formation of a cutting line, (3) formation of a pressurizable exposed portion, (4) peeling of a carrier as desired, and (5) removal of a metal layer as desired.

[0021] Hereinafter, each of processes (1) to (5) will be described with reference to the drawings.

[0022] (1) Preparation of laminated sheets

[0023] An example of a method for manufacturing a wiring board of the present invention is illustrated in FIGS. 1a and 1b. First, as illustrated in (i) of FIG. 1a, a laminated sheet (10) is prepared having a release layer (15), a metal layer (16), and a device layer (20) in sequence on a carrier (12). The release layer (15) is a layer provided on the carrier (12) and contributes to the release of the carrier (12) and the metal layer (16). The metal layer (16) is a layer composed of metal provided on the release layer (15). The device layer (20) is a layer having a device function provided on the metal layer (16).

[0024] The laminated sheet (10) may further have an intermediate layer (14) between the carrier (12) and the release layer (15). Each of the intermediate layer (14), the release layer (15), and the metal layer (16) may be a single layer consisting of one layer, or a multilayer consisting of two or more layers.

[0025] The carrier (12) may be composed of any of glass, ceramics, silicon, resin, and metal, but preferably is a glass carrier, a single-crystal silicon carrier, or a polycrystalline silicon carrier. According to a preferred embodiment of the present invention, the carrier (12) is a disc shape with a diameter of 100 mm or more, and more preferably is a disc shape with a diameter of 200 mm or more and 450 mm or less. According to another preferred embodiment of the present invention, the carrier (12) is a rectangular shape with a short side of 100 mm or more, and more preferably has a short side of 150 mm or more and 600 mm or less, and also has a rectangular shape with a long side of 200 mm or more and 650 mm or less.

[0026] The device layer (20) preferably comprises a wiring layer (20a), an electronic element (20b) provided on the wiring layer (20a), and at least a mold layer (20c) surrounding the electronic element (20b), and more preferably, the mold layer (20c) surrounds the wiring layer (20a) and the electronic element (20b). Above all, the device layer (20) may be composed mainly of the wiring layer (20a) and may not include the electronic element (20b) and / or the mold layer (20c).

[0027] Preferably, the laminated sheet (10) can be prepared as follows. First, a metal foil (18) having a carrier is prepared on a carrier (12), having an intermediate layer (14) (i.e., any layer) provided as desired, a release layer (15), and a metal layer (16). Next, a first wiring layer is formed on the surface of the metal layer (16). After that, a device layer (20) is constructed based on the first wiring layer. The formation of the first wiring layer and the construction of the device layer (20) can be performed by known methods, and for example, the coreless build-up method described above may be preferably adopted. In the following description, the carrier (12), the intermediate layer (14) (if present), the release layer (15), and the metal layer (16) may be collectively referred to as "metal foil (18) having a carrier." Furthermore, a preferred embodiment of the metal foil (18) having a carrier will be described later.

[0028] The laminated sheet (10) may have an extended protrusion E in which the metal layer (16) protrudes from the end of the device layer (20) when viewed from a planar view. In this case, as shown in (i) and (ii) of FIG. 2, it is preferable to pre-cut the metal layer (16) (and, if desired, the peeling layer (15) and intermediate layer (14) (if present)) in the extended protrusion E along the contour of the device layer (20) before inserting the cutting line C described later. By doing so, the metal foil (18) equipped with a carrier can be peeled off from the device layer (20) more easily and reliably.

[0029] (2) Formation of the cutting line

[0030] A cutting line C is inserted from the surface of the carrier (12) side of the prepared laminated sheet (10). As shown in (ii) of FIG. 1a, this cutting line C is inserted into the laminated sheet (10) so as to penetrate the carrier (12), intermediate layer (14) (if present), release layer (15), and metal layer (16) when viewed from a cross-section. At this time, as shown in (ii) of FIG. 1b, the cutting line C is inserted such that both ends (i.e. both ends of the cutting line C) reach the ends of the laminated sheet (10) through the inner side of the outline of the device layer (20) when viewed from a planar view. By inserting such a cutting line C into the laminated sheet (10), the outer edge portion of the metal foil (18) equipped with the carrier, which is outside the cutting line C, is separated from the inner portion of the cutting line C. As a result, in the process of forming the pressurizable exposed portion P described below, it becomes possible to remove the outer edge portion from the cutting line C of the metal foil (18) equipped with a carrier. The method of forming the cutting line C may be any known method and is not particularly limited. For example, the cutting line C can be formed on the laminated sheet (10) using a cutting tool such as a cutter or a machine tool such as a cutting blade.

[0031] In the laminated sheet (10), it is preferable to provide a cutting line C so that the pressurizable exposed portion P, described later, has a polygonal or arc shape. Here, FIGS. 3a and 3b respectively show (i) an example of the position of the cutting line C and (ii) the state after removing the outer edge portion from the cutting line C, in a rectangular laminated sheet (Fig. 3a) and a disc-shaped laminated sheet (Fig. 3b). When the laminated sheet (10) has a rectangular shape, for example, a pressurizable exposed portion P having a triangular shape can be formed by inserting the cutting line C into the metal foil (18) equipped with the carrier using a cutting blade from the carrier (12) side along the dotted line shown in FIG. 3a (i) (ii)). In addition, when the laminated sheet (10) is in the shape of a disc, for example, a cutting line C can be formed in the metal foil (18) equipped with the carrier using a cutting blade from the carrier (12) side along the dotted line shown in (i) of FIG. 3b, thereby forming a pressurizable exposed portion P having an arc shape ((ii) of FIG. 3b).

[0032] In the laminated sheet (10), at least two cutting lines C are provided so that at least two pressurizable exposed portions P, which will be described later, are formed in the device layer (20), which is desirable from the perspective of effectively suppressing damage to the wiring layer (20a) and electronic element (20b) during peeling of the carrier (12). For example, when the laminated sheet (10) has a rectangular shape, it is desirable to provide cutting lines C such that two corners (or four corners) on the diagonal of the metal foil (18) having the carrier and the device layer (20) are cut and detached, as shown in (i) of FIG. 3a. In addition, when the laminated sheet (10) is in the form of a disc, as shown in (i) of FIG. 3b, it is preferable to provide a cutting line C along two parallel straight lines (or two straight lines perpendicular to said two straight lines) passing through both sides of the metal foil (18) having a carrier and the device layer (20). In the laminated sheet (10), the upper limit of the number of locations where the cutting line C (and pressurizable exposed portion P) is provided is not particularly limited, but is typically four or fewer.

[0033] When the device layer (20) comprises a wiring layer (20a), an electronic element (20b) provided on the wiring layer (20a), and a mold layer (20c) surrounding the wiring layer (20a) and the electronic element (20b), it is preferable that the cutting line C is provided to cross the mold layer (20c) without crossing the wiring layer (20a) and the electronic element (20b) when viewed from a planar view. By doing so, the pressurizable exposed portion P described later can be formed in the portion consisting only of the mold layer (20c), thereby effectively suppressing damage to the wiring layer (20a) and the electronic element (20b) during peeling of the carrier (12). In this regard, the cutting line C is preferably arranged to pass through an area of ​​0.5 mm or more and 30.0 mm or less inside the contour of the device layer (20) when viewed in a plane, more preferably 1.0 mm or more and 15.0 mm or less, and even more preferably 1.5 mm or more and 5.0 mm or less inside.

[0034] (3) Formation of a pressurizable exposed portion

[0035] From the laminated sheet (10) forming the cutting line C, the outer edge portion from the cutting line C in the carrier (12), intermediate layer (14) (if present), peeling layer (15), and metal layer (16) is removed. By doing so, as shown in (iii) of FIG. 1A and (iii) of FIG. 1B, a portion of the surface on the metal layer (16) side of the device layer (20) can be exposed to form a pressurizable exposed portion P. The pressurizable exposed portion P is a portion where force can be applied directly to the device layer (20) because it promotes peeling of the carrier (12). In this specification, "pressure" means applying force to a material (object) and includes both meanings of "pressing" and "pulling" the material (object). In the following description, a laminated sheet (10) having a pressurizable exposed portion P provided on the device layer (20) may be referred to as a “wiring board (22)” or “wiring board material”.

[0036] As described above, a photolithography process including the exposure transfer of a circuit pattern may be performed on the surface of the device layer (20) (e.g., including the wiring layer (20a)) after peeling off the carrier (12). Here, in a general exposure device, the corresponding size of the wafer or panel, etc., to which the exposure is performed is determined, and it is required to prepare the wafer, etc. that matches this corresponding size. That is, if the size of the wafer, etc. deviates from the predetermined corresponding size (e.g., if it is smaller than the corresponding size), the alignment mark, which serves as the reference for position alignment before exposure, becomes misaligned, resulting in improper position alignment and potentially causing interference with subsequent exposure.

[0037] In this regard, conventional methods as disclosed in Patent Documents 5 and 6 made it difficult to perform a photolithography process with high precision on a device layer including a wiring layer after carrier peeling. Here, FIGS. 5 and 6 illustrate an example of a conventional method for manufacturing a wiring substrate. In the conventional process illustrated in FIGS. 5 and 6, a laminated sheet (110) having a device layer (120) provided on a metal foil (118) having a carrier is prepared first (process (i) of FIG. 5). In this example, the metal foil (118) having a carrier has an intermediate layer (114), a peeling layer (115), and a metal layer (116) in sequence on the carrier (112). Additionally, the device layer (120) includes a wiring layer (120a), an electronic element (120b), and a mold layer (120c). Next, a cutting blade B is used to make a cut reaching the metal foil (118) equipped with a carrier from the device layer (120) side of the prepared laminated sheet (110), and an outer edge portion is removed from the cut in the device layer (120) to form an extended protrusion portion E (Process (ii) of FIG. 5). Then, with the device layer (120) fixed by a suction device S, a force is applied to the formed extended protrusion portion E in a direction to detach the carrier (112) from the device layer (120) (Process (iii) of FIG. 6). In this way, the carrier (112) and the intermediate layer (114) are peeled from the device layer (120) at the location of the peeling layer (115) (Process (iv) of FIG. 6).

[0038] As such, the conventional method of manufacturing a wiring board involves removing the outer edge portion of the device layer (120) (for example, the outer portion at a position of 0.2 mm or more and 5 mm or less from the outline of the device layer (120). Because of this, even if the device layer (120) before processing matches the corresponding size of the exposure device (for example, a disc with a diameter of 300 mm), the size of the device layer (120) after processing (for example, a disc with a diameter of 295 mm) is smaller than the corresponding size of the exposure device. Therefore, when a photolithography process is performed on the device layer (120) after the carrier (112) peels off, there is a risk that the alignment mark will be misaligned due to the difference in size between the device layer (120) and the exposure device, resulting in improper position alignment before exposure. Consequently, the conventional method of manufacturing a wiring board makes it difficult to perform a photolithography process with high precision on the device layer after the carrier peels off.

[0039] In contrast, the method of the present invention maintains the size of the device layer (20) in order to form a pressurizable exposed portion P by processing the carrier (12), intermediate layer (14) (if present), peeling layer (15), and metal layer (16) in the laminated sheet (10). Therefore, as a result of properly performing position alignment before exposure based on alignment marks for the device layer (20) after peeling the carrier (12), the photolithography process can be performed with high precision. Furthermore, when peeling the carrier (12), the carrier (12) can be easily peeled by applying an appropriate force to the pressurizable exposed portion P, so damage to the device layer (20) can be suppressed. In addition, since the peeling removal of the carrier (12) can be easily performed by physical peeling, there is an advantage that a peeling method involving processes such as immersion in a solution that dissolves the peeling layer or laser irradiation does not need to be adopted.

[0040] (4) Detachment of carrier (optional process)

[0041] Depending on the desired outcome, after removing the outer edge portion of the metal foil (18) equipped with a carrier, the carrier (12) and the intermediate layer (14) (if present) are peeled from the wiring board (22) at the location of the peeling layer (15). At this time, the wiring board (22) has a pressurizable exposed portion P, thereby making it possible to easily peel off the carrier (12). Here, FIG. 4 illustrates an example of a process for peeling off the carrier (12). As shown in FIG. 4 (i) and (ii), peeling off the carrier (12), etc. is preferably performed by applying force to the pressurizable exposed portion P of the device layer (20) in a direction that separates the device layer (20) from the carrier (12) (the direction indicated by the arrow in FIG. 4 (i)) while the carrier (12) is fixed. The method of applying pressure to the pressurizable exposed portion P is not particularly limited, and a hand, a tool, a machine, etc., may be used. For example, the carrier (12) can be peeled off by using a compression member to compress the pressurizable exposed portion P, or by hooking a hook member onto the pressurizable exposed portion P and tensioning it in a direction that separates the device layer (20) from the carrier (12).

[0042] In this peeling process, when the carrier is a single-crystal silicon carrier, it is desirable to pay attention to the direction of progress of the peeling. Here, the peeling process of the carrier (12) in the case where the carrier (12) of the metal foil (18) having the carrier is a single-crystal silicon carrier is illustrated in FIGS. 7a, 7b, 8a, and 8b, respectively. In the process illustrated in FIGS. 7a to 8b, a metal foil (18) having a carrier in which the carrier (12) is a single-crystal silicon carrier is prepared ((i) in FIG. 7a and (i) in FIG. 8a), a device layer (20) is formed on the metal layer (16) of the metal foil (18) having the carrier ((ii) in FIG. 7a and (ii) in FIG. 8a), and then the carrier (12) is peeled ((iii) and (iv) in FIG. 7b and (iii) and (iv) in FIG. 8b).

[0043] As shown in (iii) and (iv) of FIG. 7b, when peeling is performed in a direction in which the direction of external stress ST progresses and the cleavage orientation CL coincide, there is a possibility that the silicon carrier may be destroyed, such as by the occurrence of a crack CR along the cleavage orientation CL starting from the point where the external stress ST was applied due to the initial peeling. In order to suppress such destruction of the silicon carrier due to cleavage, when the carrier (12) is a single-crystal silicon carrier, it is preferable to apply an external stress ST to peel the carrier (12) so that it is inconsistent with either the direction of the cleavage orientation CL of the x-axis (left-right direction in the drawing) and the y-axis (up-down direction in the drawing) on ​​the silicon carrier, as shown in (iii) and (iv) of FIG. 8b.

[0044] This will be explained in more detail. As shown in (i) of FIG. 7a and (i) of FIG. 8, if the angle θ is defined in a clockwise direction starting from the half-line L from the center of the carrier (12) to the notch N, then θ = 0°, 90°, 180°, and 270° correspond to the cleavage orientation CL. For this reason, regarding the direction of progression of the external stress ST due to peeling θr, as shown in (iii) of FIG. 8b, it is preferable to perform peeling while maintaining the direction of progression of the external stress ST so that θr is within the range of 1° < θr < 89°, and it is more preferable to make it within the range of 5° < θr < 85°. By a peeling method that satisfies this range of θr, it is possible to suppress the destruction of the carrier (12) composed of a silicon wafer. The particularly desirable range of θr during this peeling is θr = 45±5°, 135±5°, 225±5°, and 315±5° rotated to the right from the ray L. These angles correspond to the crystal orientation of the silicon wafer. <100> Since the wafer is most difficult to cleave in the direction, by advancing the external stress at these angles, it becomes possible to effectively suppress the destruction of the wafer and remove the carrier. In addition, in order to make the direction of advancement of the external stress ST θr the above angle, it is preferable to form a pressurizable exposed portion P at θr = 45±10°, 135±10°, 225±10° and / or 315±10°, and then perform peeling of the carrier (12).

[0045] When at least two pressurizable exposed portions P are formed, it is preferable that the peeling of the carrier (12) be performed by applying force in a direction that separates the device layer (20) from the carrier (12) at the at least two pressurizable exposed portions P. By doing so, compared to the case where there is only one pressurizable exposed portion P, the force applied to the pressurizable exposed portion P can be dispersed, and consequently, damage to the device layer (20) can be suppressed more effectively. To further enhance this effect, it is preferable that the peeling of the carrier (12) be performed by applying force in a direction that separates the device layer (20) perpendicular to the surface (carrier surface) defined by the carrier (12).

[0046] Typically, the elastic modulus of the device layer (20) may be lower than the elastic modulus of the carrier (12). For example, the elastic modulus of the device layer (20) is less than 1 time the elastic modulus of the carrier (12), more typically less than 0.7 times, and more preferably less than 0.5 times. An example of this embodiment is when the device layer (20) (e.g., the mold layer (20c)) contains resin. In this case, before peeling off the carrier (12), it is preferable to bring a reinforcing material into contact with the side opposite to the metal layer (16) of the device layer (20) and / or the exposed end of the device layer (20). By doing so, the peeling off of the carrier (12) can be performed more smoothly, and further damage to the device layer (20) during the peeling of the carrier (12) can be further reduced. The contact of the reinforcing material may be achieved by adhering the reinforcing material to the device layer (20) (e.g., by using an adhesive or adhesive tape), or by simply adhering the reinforcing material to the device layer (20) without using an adhesive. It is preferable that the reinforcing material be composed of metal, rubber (e.g., silicone rubber), resin (e.g., epoxy resin), or a combination thereof. When the reinforcing material is brought into contact with the surface opposite to the metal layer (16) of the device layer (20), the entire surface may be brought into contact with the reinforcing material (e.g., a reinforcing material that does not have rigidity such as silicone rubber), or a part of the surface may be brought into contact with the reinforcing material (e.g., a reinforcing material that has rigidity such as a metal plate) so that at least the wiring layer (20a) and the electronic element (20b) are covered when viewed from a flat surface.

[0047] Alternatively, the elastic modulus of the device layer (20) may be higher than the elastic modulus of the carrier (12). For example, the elastic modulus of the device layer (20) may be greater than 1 time, more typically greater than 2 times, and more preferably greater than 4 times the elastic modulus of the carrier (12). An example of this embodiment may be a case where the device layer (20) (e.g., the mold layer (20c)) includes ceramics. In this case, the carrier (12) can be preferably peeled without bringing the aforementioned reinforcing material into contact with the device layer (20). However, it goes without saying that even in this embodiment, the carrier (12) may be peeled after bringing the reinforcing material into contact with the device layer (20).

[0048] (5) Removal of metal layer (optional process)

[0049] Depending on the preference, the metal layer (16) exposed after peeling off the carrier (12) is removed by etching. By doing so, the buried wiring is exposed, making it more suitable for forming an additional layer of circuit on it by a photolithography process. The etching of the metal layer (16) can be performed based on known methods and is not particularly limited.

[0050] Wiring board material

[0051] According to a preferred embodiment of the present invention, a wiring board (22) (wiring board material) is provided, comprising a metal foil (18) having a carrier and a device layer (20) provided on the metal foil (18) having a carrier. In this wiring board (22), at least one outer edge portion of the metal foil (18) having a carrier is missing along at least one line passing inward from the contour of the device layer (20) when viewed from a planar view (see (iii) in FIG. 1b). Accordingly, the wiring board (22) has a portion of the surface of the metal foil (18) having a carrier on the side of the device layer (20) exposed, forming a pressurizable exposed portion P to promote peeling of the carrier (12) (and, if present, the intermediate layer (14)) (see (iii) in FIG. 1a). According to this wiring substrate (22), damage to the device layer (20) during peeling of the carrier (12) (and, if present, the intermediate layer (14)) can be suppressed, and a photolithography process can be performed with high precision on the device layer (20) after peeling.

[0052] The wiring board (22) (wiring board material) may be manufactured by any method. Typically, the wiring board (22) corresponds to a laminated sheet (10) after forming a pressurizable exposed portion P on the device layer (20) in the above-described method of manufacturing the wiring board, and before peeling off the carrier (12). Accordingly, the wiring board (22) may adopt a configuration such as that shown, for example, in (iii) of FIG. 1a and (iii) of FIG. 1b. The device layer (20) included in the wiring board (22) is as described above.

[0053] Metal foil equipped with a carrier

[0054] As described above with reference to FIG. 1a, the metal foil (18) having a carrier used in the method of the present invention, as desired, comprises a carrier (12), an intermediate layer (14), a peeling layer (15), and a metal layer (16) in order as desired.

[0055] As described above, the material of the carrier (12) may be any of glass, ceramics, silicon, resin, or metal. Preferably, the carrier (12) is composed of glass, single-crystal silicon, polycrystalline silicon, or ceramics. The shape of the carrier (12) may be any of a sheet, film, or plate. Additionally, the carrier (12) may be a laminate of these sheets, films, plates, etc. For example, the carrier (12) may be capable of functioning as a rigid support such as a glass plate, ceramic plate, silicon wafer, or metal plate, or it may be in a shape that does not have rigidity such as a metal foil or resin film. Preferred examples of the metal constituting the carrier (12) include copper, titanium, nickel, stainless steel, aluminum, etc. Preferred examples of the ceramics include alumina, zirconia, silicon nitride, aluminum nitride, and various other fine ceramics. Preferred examples of resins include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyamide, polyimide, nylon, liquid crystal polymer, polyetheretherketone (PEEK (registered trademark)), polyamideimide, polyethersulfone, polyphenylene sulfide, polytetrafluoroethylene (PTFE), ethylenetetrafluoroethylene (ETFE), etc. More preferably, for the purpose of preventing warping of the coreless support due to heating when mounting an electronic device, the material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K (typically 1.0 ppm / K or more and 23 ppm / K or less), and examples of such materials include various resins as described above (particularly low thermal expansion resins such as polyimide and liquid crystal polymer), glass, single-crystal silicon, polycrystalline silicon, and ceramics, etc. In addition, from the perspective of ensuring handling and flatness during chip mounting, it is preferable that the carrier (12) has a Vickers hardness of 100 HV or higher, and more preferably 150 HV or higher and 2500 HV or lower.As a material satisfying these characteristics, the carrier (12) is preferably composed of glass, silicon, or ceramic, more preferably of glass or ceramic, and particularly preferably of glass. As a carrier (12) composed of glass, for example, a glass plate can be used. When glass is used as the carrier (12), it has advantages such as being lightweight, having a low coefficient of thermal expansion, high insulation, and having a rigid and flat surface, which allows the surface of the metal layer (16) to be extremely smooth. In addition, when the carrier (12) is glass, it has advantages such as having surface flatness (coplanarity) which is advantageous for forming microcircuits, having chemical resistance in desmearing or various plating processes in wiring manufacturing processes, and being able to employ a chemical separation method when peeling the carrier (12) from the metal foil (18) equipped with the carrier. Preferred examples of glass constituting the carrier (12) include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, aluminosilicate glass, and combinations thereof, more preferably alkali-free glass, soda-lime glass, and combinations thereof, and particularly preferably alkali-free glass. Alkali-free glass is a glass that substantially does not contain alkali metals, with silicon dioxide, aluminum oxide, boron oxide, and alkaline earth metal oxides such as calcium oxide or barium oxide as main components, and also contains boric acid. This alkali-free glass has the advantage of being able to minimize warping of the glass in a heating process because its coefficient of thermal expansion is low and stable in the range of 3 ppm / K or more and 5 ppm / K or less over a wide temperature range from 0°C to 350°C. The thickness of the carrier (12) is preferably 100㎛ or more and 2000㎛ or less, more preferably 300㎛ or more and 1800㎛ or less, and even more preferably 400㎛ or more and 1100㎛ or less.If the carrier (12) has a thickness within this range, it is possible to achieve thinning of the wiring and reduction of bending that occurs when mounting electronic components while securing appropriate strength that does not hinder handling.

[0056] The intermediate layer (14), provided as desired, may be composed of one layer or two or more layers. When the intermediate layer (14) is composed of two or more layers, the intermediate layer (14) includes a first intermediate layer provided immediately above the carrier (12) and a second intermediate layer provided adjacent to the peeling layer (15). The first intermediate layer is preferably a layer composed of at least one metal selected from the group consisting of Ti, Cr, Al, and Ni in order to ensure adhesion with the carrier (12). The first intermediate layer may be a pure metal or an alloy. The thickness of the first intermediate layer is preferably 5 nm or more and 500 nm or less, more preferably 10 nm or more and 300 nm or less, even more preferably 18 nm or more and 200 nm or less, and particularly preferably 20 nm or more and 100 nm or less. The second intermediate layer is preferably a layer composed of Cu in order to control the peeling strength with the peeling layer (15) to a desired value. The thickness of the second intermediate layer is preferably 5 nm or more and 500 nm or less, more preferably 10 nm or more and 400 nm or less, even more preferably 15 nm or more and 300 nm or less, and particularly preferably 20 nm or more and 200 nm or less. There may be other interlayers between the first intermediate layer and the second intermediate layer, and examples of constituent materials of the interlayer include an alloy of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ni and Cu. Meanwhile, if the intermediate layer (14) is composed of a single layer, the first intermediate layer described above may be adopted as the intermediate layer, or the first intermediate layer and the second intermediate layer may be replaced with a single intermediate alloy layer. This intermediate alloy layer is preferably composed of a copper alloy having a content of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, Al, and Ni of 1.0 at% or more, and a Cu content of 30 at% or more.The thickness of the intermediate alloy layer is preferably 5 nm or more and 500 nm or less, more preferably 10 nm or more and 400 nm or less, even more preferably 15 nm or more and 300 nm or less, and particularly preferably 20 nm or more and 200 nm or less. In addition, the thickness of each layer described above is a value measured by analyzing the cross-section of the layer using an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope. The metal constituting the intermediate layer (14) may contain unavoidable impurities resulting from raw material components or the film deposition process. In addition, although not particularly limited, the presence of oxygen introduced due to exposure to the atmosphere after the intermediate layer (14) is formed is permitted. The intermediate layer (14) may be manufactured by any method, but it is particularly preferred that it be a layer formed by a magnetron sputtering method using a metal target, as this allows for uniformity in the film thickness distribution.

[0057] The peeling layer (15) is a layer that enables or facilitates the peeling of the carrier (12) and, if present, the intermediate layer (14). The peeling layer (15) may be either an organic peeling layer or an inorganic peeling layer. Examples of organic components used in the organic peeling layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids, etc. Examples of nitrogen-containing organic compounds include triazole compounds, imidazole compounds, etc. Meanwhile, examples of inorganic components used in the inorganic peeling layer include metal oxides or metal oxynitrides containing at least one of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, or carbon, etc. Among these, the peeling layer (15) is preferably a layer mainly composed of carbon, in terms of ease of peeling and film formation, more preferably a layer mainly composed of carbon or hydrocarbons, and even more preferably a layer composed of amorphous carbon, which is a hard carbon film. In this case, the peeling layer (15) (i.e., the carbon-containing layer) preferably has a carbon concentration of 60 atomic percent or more as measured by XPS, more preferably 70 atomic percent or more, even more preferably 80 atomic percent or more, and particularly preferably 85 atomic percent or more. The upper limit of the carbon concentration is not specifically limited and may be 100 atomic percent, but 98 atomic percent or less is practical. The peeling layer (15) may contain unavoidable impurities (e.g., oxygen, carbon, hydrogen, etc. originating from the surrounding environment such as the atmosphere). Additionally, metal atoms of a type other than the metal contained in the peeling layer (15) may be incorporated into the peeling layer (15) due to the film formation method of the metal layer (16), etc., which is subsequently laminated.When a carbon-containing layer is used as the peeling layer (15), the mutual diffusion and reactivity with the carrier are low, and even when subjected to press processing at a temperature exceeding 300°C, the formation of a metal bond due to high-temperature heating between the metal layer and the bonding interface is prevented, thereby maintaining a state where the peeling and removal of the carrier is easy. It is preferable that the peeling layer (15) be a layer formed by a vapor phase method such as sputtering, in order to suppress excessive impurities in the peeling layer (15) and to ensure continuous productivity of other layers. When a carbon-containing layer is used as the peeling layer (15), the thickness is preferably 1 nm or more and 20 nm or less, and more preferably 1 nm or more and 10 nm or less. This thickness is a value measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope.

[0058] The peeling layer (15) may include a metal oxide layer and a carbon-containing layer, or a layer containing both metal oxide and carbon. In particular, when the metal foil (18) having a carrier includes an intermediate layer (14), the carbon-containing layer contributes to the stable peeling of the carrier (12), and the metal oxide layer can suppress the diffusion of metal elements originating from the intermediate layer (14) and the metal layer (16) upon heating, and consequently, it is possible to maintain stable peelability even after heating at a high temperature of, for example, 350°C or higher. The metal oxide layer is preferably a layer containing oxides of metals composed of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, and combinations thereof. It is particularly preferable that the metal oxide layer be a layer formed by a reactive sputtering method using a metal target and sputtering under an oxidizing atmosphere, in that the film thickness can be easily controlled by adjusting the film deposition time. The thickness of the metal oxide layer is preferably 0.1 nm or more and 100 nm or less. As for the upper limit of the thickness of the metal oxide layer, it is more preferably 60 nm or less, even more preferably 30 nm or less, and particularly preferably 10 nm or less. This thickness is a value measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope. At this time, the order in which the metal oxide layer and the carbon layer are stacked as the peeling layer (15) is not particularly limited. In addition, the peeling layer (15) may exist in a mixed state (i.e., a layer containing both metal oxide and carbon) in which the boundary between the metal oxide layer and the carbon-containing layer is not clearly specified.

[0059] Likewise, in terms of maintaining stable peelability even after heat treatment at high temperature, the peeling layer (15) may be a metal-containing layer in which the side adjacent to the metal layer (16) is a fluorine-treated surface and / or a nitride-treated surface. In the metal-containing layer, it is preferable that a region (hereinafter referred to as the "(F+N) region") in which the sum of the fluorine content and nitrogen content is 1.0 atomic% or more exists over a thickness of 10 nm or more, and the (F+N) region is preferably located on the metal layer (16) side of the metal-containing layer. The thickness of the (F+N) region (converted to SiO2) is a value determined by performing a depth-direction elemental analysis of the metal foil (18) equipped with a carrier using XPS. The fluorine-treated surface or the nitride-treated surface can preferably be formed by reactive ion etching (RIE) or a reactive sputtering method. Meanwhile, the metal element included in the metal-containing layer is preferably to have a negative standard electrode potential. Preferred examples of metal elements included in the metal-containing layer include Cu, Ag, Sn, Zn, Ti, Al, Nb, Zr, W, Ta, Mo, and combinations thereof (e.g., alloys or intermetallic compounds). It is preferable that the content of metal elements in the metal-containing layer be 50 atomic% or more and 100 atomic% or less. The metal-containing layer may be a single layer or a multilayer composed of two or more layers. The total thickness of the metal-containing layer is preferably 10 nm or more and 1000 nm or less, more preferably 30 nm or more and 500 nm or less, even more preferably 50 nm or more and 400 nm or less, and particularly preferably 100 nm or more and 300 nm or less. The thickness of the metal-containing layer itself is a value measured by analyzing the layer cross-section using an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope.

[0060] Alternatively, the peeling layer (15) may be a metal oxynitride-containing layer instead of a carbon layer, etc. The surface opposite to the carrier (12) of the metal oxynitride-containing layer (i.e., the metal layer (16) side) preferably contains at least one metal oxynitride selected from the group consisting of TaON, NiON, TiON, NiWON, and MoON. In addition, in order to ensure adhesion between the carrier (12) and the metal layer (16), the surface of the metal oxynitride-containing layer on the carrier (12) side preferably contains at least one selected from the group consisting of Cu, Ti, Ta, Cr, Ni, Al, Mo, Zn, W, TiN, and TaN. By doing so, the number of foreign particles on the surface of the metal layer (16) is suppressed to improve circuit formation, and it is also possible to maintain stable peel strength even after being heated at a high temperature for a long time. The thickness of the metal oxynitride-containing layer is preferably 5 nm or more and 500 nm or less, more preferably 10 nm or more and 400 nm or less, even more preferably 20 nm or more and 200 nm or less, and particularly preferably 30 nm or more and 100 nm or less. This thickness is a value measured by analyzing the cross-section of the layer using an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope.

[0061] The metal layer (16) is a layer composed of metal. The metal layer (16) may be composed of one layer or two or more layers. When the metal layer (16) is composed of two or more layers, the metal layer (16) may be configured such that each metal layer from the first metal layer to the m-th metal layer (m is an integer greater than or equal to 2) is stacked in order on the side opposite to the carrier (12) of the peeling layer (15). The total thickness of the metal layer (16) is preferably 1 nm or more and 2000 nm or less, preferably 100 nm or more and 1500 nm or less, more preferably 200 nm or more and 1000 nm or less, even more preferably 300 nm or more and 800 nm or less, and particularly preferably 350 nm or more and 500 nm or less. The thickness of the metal layer (16) is a value measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope. Hereinafter, an example in which the metal layer (16) is composed of two layers, a first metal layer and a second metal layer, will be described.

[0062] It is preferable that the first metal layer imparts a desired function, such as an etching stopper function or an anti-reflection function, to the metal foil (18) equipped with a carrier. Preferred examples of metals constituting the first metal layer include Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, Mo, and combinations thereof; more preferably, Ti, Zr, Al, Cr, W, Ni, Mo, and combinations thereof; even more preferably, Ti, Al, Cr, Ni, Mo, and combinations thereof; and particularly preferably, Ti, Mo, and combinations thereof. These elements have the property that they do not dissolve in a flash etching solution (e.g., copper flash etching solution), and as a result, can exhibit excellent chemical resistance to the flash etching solution. Therefore, the first metal layer becomes a layer that is more difficult to etch by the flash etching solution than the second metal layer described later, and thus can function as an etching stopper layer. In addition, since the aforementioned metal constituting the first metal layer also has the function of preventing light reflection, the first metal layer can also function as an anti-reflection layer to improve visibility in image inspection (e.g., Automatic Optical Inspection (AOI)). The first metal layer may be a pure metal or an alloy. The metal constituting the first metal layer may contain unavoidable impurities resulting from raw material components or film deposition processes. Furthermore, the upper limit of the content of the metal is not particularly limited and may be 100 atomic percent. The first metal layer is preferably a layer formed by physical vapor deposition (PVD), and more preferably a layer formed by sputtering. The thickness of the first metal layer is preferably 1 nm or more and 500 nm or less, more preferably 10 nm or more and 400 nm or less, even more preferably 30 nm or more and 300 nm or less, and particularly preferably 50 nm or more and 200 nm or less.

[0063] Preferred examples of metals constituting the second metal layer include transition elements of Group 4, Group 5, Group 6, Group 9, Group 10, and Group 11, Al, and combinations thereof (e.g., alloys or intermetallic compounds), more preferably transition elements of Group 4 and Group 11, Al, Nb, Co, Ni, Mo, and combinations thereof, even more preferably transition elements of Group 11, Ti, Al, Mo, and combinations thereof, particularly preferably Cu, Ti, Mo, and combinations thereof, most preferably Cu. The second metal layer may be manufactured by any method and may be a metal foil formed by, for example, wet deposition methods such as electroless metal plating and electrolytic metal plating, physical vapor deposition (PVD) methods such as sputtering and vacuum deposition, chemical vapor deposition, or a combination thereof. A particularly preferred second metal layer is a metal layer formed by a physical vapor deposition (PVD) method, such as sputtering or vacuum deposition, in order to facilitate fine pitch reduction through ultra-thinning, and most preferably, a metal layer manufactured by sputtering. Additionally, while it is preferable for the second metal layer to be a non-fine metal layer, it may be a metal layer that has undergone secondary fusing through preliminary fusing, soft etching treatment, cleaning treatment, or redox treatment, as long as it does not hinder the formation of the wiring pattern. In order to facilitate fine pitch reduction, the thickness of the second metal layer is preferably 10 nm or more and 1000 nm or less, more preferably 20 nm or more and 900 nm or less, even more preferably 30 nm or more and 700 nm or less, even more preferably 50 nm or more and 600 nm or less, particularly preferably 70 nm or more and 500 nm or less, and most preferably 100 nm or more and 400 nm or less. It is preferable for metal layers with a thickness within this range to be manufactured by the sputtering method, in terms of in-plane uniformity of film thickness and productivity in sheet or roll form.

[0064] In the case where the metal layer (16) is composed of a single layer, it is preferable to adopt the aforementioned second metal layer as the metal layer (16). On the other hand, in the case where the metal layer (16) is composed of n layers (n is an integer greater than or equal to 3), it is preferable to make the first metal layer from the first metal layer to the (n-1) metal layer of the metal layer (16) the composition of the aforementioned first metal layer, and it is preferable to make the outermost layer of the metal layer (16), that is, the nth metal layer, the composition of the aforementioned second metal layer.

[0065] It is preferable that the metal layer (16), an intermediate layer (14) as desired, and a peeling layer (15) as desired (i.e., at least the metal layer (16), for example, the metal layer (16) and the intermediate layer (14)) extend and protrude to the end surface of the carrier (12), thereby covering the end surface. That is, it is preferable that not only the surface of the carrier (12) but also the end surface be covered with at least the metal layer (16). By covering the end surface as well, in addition to preventing the intrusion of chemical solution into the carrier (12) during the manufacturing process of the wiring board, it is possible to firmly prevent chipping caused by peeling at the side end when handling the metal foil (18) or laminated sheet (10) equipped with the carrier, i.e., the detachment of the film (i.e., the metal layer (16)) on the peeling layer (15). The covering area on the end surface of the carrier (12) is oriented in the thickness direction (i.e., perpendicular to the surface of the carrier) from the surface of the carrier (12), preferably an area of ​​0.1 mm or more, more preferably an area of ​​0.2 mm or more, and even more preferably extending across the entire end surface of the carrier (12).

Claims

Claim 1 A method for manufacturing a wiring board, comprising: a process of preparing a laminated sheet having a release layer, a metal layer, and a device layer in sequence on a carrier; a process of making a cutting line from the surface on the carrier side of the laminated sheet such that, when viewed in a planar view, both ends thereof reach the ends of the laminated sheet through the inner side beyond the outline of the device layer, and when viewed in a cross-sectional view, it penetrates the carrier, the release layer, and the metal layer; and a process of removing an outer edge portion from the cutting line in the carrier, the release layer, and the metal layer, thereby exposing a portion of the surface on the metal layer side of the device layer to form a pressurizable exposed portion to promote the release of the carrier. Claim 2 The method according to claim 1, wherein the laminated sheet has an extended protruding portion of the metal layer protruding from the end of the device layer when viewed in a planar view, and the method further comprises a process of pre-cutting the metal layer along the contour of the device layer at the extended protruding portion before inserting the cutting line. Claim 3 A method according to claim 1 or 2, further comprising the process of peeling the carrier from the laminated sheet at the location of the peeling layer after removing the outer portion. Claim 4 A method according to paragraph 3, wherein the peeling of the carrier comprises applying force in a direction that separates the device layer from the carrier while the carrier is fixed, wherein the pressurizable exposed portion of the device layer is pressed. Claim 5 A method according to claim 1 or 2, wherein the cutting line is arranged to pass through an area 0.5 mm or more and 30.0 mm or less inward from the contour of the device layer when viewed in a planar view. Claim 6 A method according to claim 1 or 2, wherein the cutting line is provided such that the pressurizable exposed portion has a polygonal shape or an arc shape. Claim 7 A method according to claim 3, wherein the cutting line is provided in at least two places so that the pressurizable exposed portion is formed in at least two places, and the peeling of the carrier is performed by applying force in a direction that separates the device layer from the carrier at least two pressurizable exposed portions. Claim 8 A method according to claim 7, wherein the peeling of the carrier is performed by applying force in a direction perpendicular to the surface defined by the carrier to detach the device layer. Claim 9 A method according to claim 1 or 2, wherein the device layer comprises a wiring layer, an electronic element provided on the wiring layer, and a mold layer surrounding the wiring layer and the electronic element, and wherein the cutting line is provided to cross the mold layer without crossing the wiring layer and the electronic element when viewed in a planar view. Claim 10 A method according to claim 1 or 2, wherein the elastic modulus of the device layer is lower than the elastic modulus of the carrier. Claim 11 In claim 10, the method wherein the device layer comprises a resin. Claim 12 A method according to claim 1 or 2, wherein the elastic modulus of the device layer is higher than the elastic modulus of the carrier. Claim 13 In claim 12, the method wherein the device layer comprises ceramics. Claim 14 A method according to claim 1 or 2, wherein the carrier is a glass carrier. Claim 15 A method according to claim 1 or 2, wherein the carrier is in the shape of a disc with a diameter of 100 mm or more, or a rectangular shape with a shorter side of 100 mm or more. Claim 16 A method according to claim 1 or 2, wherein the preparation of the laminated sheet comprises the steps of: preparing a metal foil having a carrier having a release layer and a metal layer on a carrier; forming a first wiring layer on the surface of the metal layer; and constructing the device layer based on the first wiring layer. Claim 17 A method according to claim 3, further comprising a process of removing the metal layer exposed after peeling off the carrier by etching. Claim 18 A wiring board material having a release layer, a metal layer, and a device layer in sequence on a carrier, wherein, when viewed in a planar view, the outer edges of the carrier, the release layer, and the metal layer are missing at least one place along at least one line passing inward from the contour of the device layer, and accordingly, a portion of the surface of the device layer on the metal layer side is exposed to form a pressurizable exposed portion.

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