GaN substrate wafer and method of manufacturing the same

Abstract

(0001) An oriented GaN substrate wafer having improved productivity that can be preferably used in the manufacture of a nitride semiconductor device having a horizontal device structure. (0001) An oriented GaN substrate wafer having a first region formed on the N polarity side with a regrowth interface in between, and a second region having a minimum thickness formed on the Ga polarity side, wherein the minimum thickness of the second region is 20 μm or more, and the total concentration of compensation impurities in at least a part of the second region is 1 × 10¹⁷ atoms / cm³ or more.

Description

Technology Field

[0001] The present invention relates to a substrate wafer made of GaN (gallium nitride) and a method for manufacturing the same. A substrate wafer refers to a wafer used as a substrate when manufacturing a semiconductor device. Background Technology

[0002] A GaN substrate wafer having a high resistance region partially formed only on the surface side is proposed by a method in which a GaN thick film having a high transition metal atom concentration region formed only on the upper side is grown on a sapphire wafer by HVPE (Hydride Vapor Phase Epitaxy), and then the GaN thick film is peeled off from the sapphire wafer (Patent Document 1). Although GaN crystals that have high resistance due to impurity doping are prone to cracking, it is stated in Patent Document 1 that cracks are not easily formed in the GaN substrate wafer produced by this method. Prior art literature

[0003] Japanese Patent Publication No. 2012-232884 The problem to be solved

[0004] When manufacturing a GaN substrate wafer having a region with partially increased resistivity formed only on the surface side by the method disclosed in Reference 1, it is necessary to grow a GaN thick film with HVPE on a sapphire wafer for each GaN substrate wafer manufactured. means of solving the problem

[0005] The inventors realized that, instead of the method disclosed in Reference 1, by first manufacturing a GaN wafer with a low impurity concentration and then growing a GaN layer doped with a compensation impurity thereon, a GaN substrate wafer having a region with partially increased resistivity only on the surface side can be produced more efficiently.

[0006] The present invention is based on such an idea, and its embodiments include the following.

[0007] [1] (0001) As an oriented GaN substrate wafer,

[0008] It has a first region formed on the N polarity side with the regrowth interface in between, and a second region having a minimum thickness formed on the Ga polarity side, and

[0009] The minimum thickness of the second region is 20 μm or more, and

[0010] In at least a part of the second region, the total concentration of compensating impurities is 1 × 10 17 GaN substrate wafer with atoms / cm³ or more.

[0011] [2] A GaN substrate wafer described in [1], wherein the first region above satisfies one or more conditions selected from (a) to (c) below.

[0012] (a) Si concentration of 5 × 10 16 It is greater than atoms / cm³.

[0013] (b) O concentration is 3 × 10 16 It is less than atoms / cm³.

[0014] (c) H concentration is 1 × 10 17 It is less than atoms / cm³.

[0015] [3] A GaN substrate wafer described in [1] or [2], wherein in the first region above, the total concentration of compensation impurities is lower than the total concentration of donor impurities.

[0016] [4] In the first region above, the total concentration of compensation impurities is 1 × 10 17 A GaN substrate wafer described in any one of [1] to [3] above, having less than atoms / cm³.

[0017] [5] In the first region above, the concentration of impurity elements other than Si, O and H is independently 5 × 10 15A GaN substrate wafer described in any one of [1] to [4] above, having atoms / cm³ or less.

[0018] [6] A GaN substrate wafer described in any one of [1] to [5], satisfying any of the conditions selected from (1) to (3) below.

[0019] (1) It has a diameter of 50 mm or more and 55 mm or less and a thickness of 250 µm or more and 450 µm or less.

[0020] (2) It has a diameter of 100 mm or more and 105 mm or less, and a thickness of 350 µm or more and 750 µm or less.

[0021] (3) It has a diameter of 150 mm or more and 155 mm or less, and a thickness of 450 µm or more and 800 µm or less.

[0022] [7] The second region above has a main plane on the Ga polar side and a main plane, and the total concentration of the compensation impurity in the main plane is 1 × 10 17 A GaN substrate wafer described in any one of [1] to [6] above, having at least atoms / cm³.

[0023] [8] The total concentration of compensation impurities in the above-mentioned Zudov region is 1 × 10 18 A GaN substrate wafer described in [7] above, having at least atoms / cm³.

[0024] [9] A GaN substrate wafer described in [7] or [8], wherein in the above-mentioned main region, the total concentration of compensation impurities is at least twice the total concentration of donor impurities.

[0025]

[10] A GaN substrate wafer described in any one of [7] to [9], wherein the above-mentioned Zudov region contains one or more elements selected from carbon and transition metal elements.

[0026]

[11] A GaN substrate wafer described in any one of [7] to

[10] , wherein the impurity contained in the highest concentration in the above-mentioned main region is Fe, Mn or C.

[0027]

[12] A GaN substrate wafer described in any one of [7] to

[11] , wherein the above-mentioned main-side region is within a specific length from the main side of the Ga polarity side, and the specific length is 20 μm or more.

[0028]

[13] A GaN substrate wafer described in any one of [7] to

[12] , wherein, in the above-mentioned main-prep region, the variation in the total concentration of compensation impurities along the c-axis direction is within ± 25% of the median value.

[0029]

[14] A GaN substrate wafer described in

[12] or

[13] , with a specific length greater than 50 μm.

[0030]

[15] A GaN substrate wafer described in any one of

[12] to

[14] , wherein the specific length is at least 50% of the minimum thickness of the second region.

[0031]

[16] The total concentration of compensation impurities in the second region above is 5 × 10 19 A GaN substrate wafer described in any one of [1] to

[15] above, having atoms / cm³ or less.

[0032]

[17] A GaN substrate wafer described in any one of [1] to

[16] , wherein the minimum thickness of the second region is 300 μm or less.

[0033]

[18] A GaN substrate wafer described in any one of [1] to

[17] , wherein the main surface of the Ga polarity side is a flat surface.

[0034]

[19] A GaN substrate wafer described in

[18] , wherein the regrowth interface is inclined with respect to the main surface of the Ga polarity side.

[0035]

[20] A GaN substrate wafer described in

[19] , wherein the thickness difference between one end and the other end in the direction in which the regrowth interface in the second region is inclined does not exceed 200 μm.

[0036]

[21] An epitaxial wafer having a GaN substrate wafer described in any one of [1] to

[20] above, and a nitride semiconductor layer epitaxially grown on the main surface of the Ga polarity side of the GaN substrate wafer.

[0037]

[22] A method for manufacturing an epitaxial wafer having a process of preparing a GaN substrate wafer as described in any one of [1] to

[20] above, and a process of growing a nitride semiconductor layer on the main surface of the Ga polarity side of the GaN substrate wafer.

[0038]

[23] A method for manufacturing a nitride semiconductor device comprising the steps of preparing a GaN substrate wafer described in any one of [1] to

[20] above, growing a nitride semiconductor layer on the main surface of the Ga polarity side of the GaN substrate wafer to obtain an epitaxial wafer, and removing the first region of the GaN substrate wafer in at least a portion of the epitaxial wafer.

[0039]

[24] A second process of obtaining a second c-plane GaN wafer by growing a second GaN thick film oriented (0001) on a substrate using HVPE, and then slicing the second GaN thick film, and

[0040] The third process involves growing a GaN film greater than 50 μm with (0001) orientation on the second c-plane GaN wafer by HVPE, and also

[0041] The GaN film has a total concentration of compensating impurities of 1 × 10⁻⁶ 17 A method for manufacturing a GaN substrate wafer characterized by forming a region with atoms / cm³ or more.

[0042]

[25] A method for manufacturing a GaN substrate wafer having an N polarity side region and a Ga polarity side region with a regrowth interface in between,

[0043] (i) a first GaN thick film made of unintentionally undoped GaN and oriented (0001) is grown on a seed wafer using HVPE, and the first GaN thick film is processed to obtain at least one first c-plane GaN wafer,

[0044] (ii) a second process of growing a second GaN thick film made of unintentionally undoped GaN and oriented (0001) on a first c-plane GaN wafer obtained in the first process using HVPE, and slicing the second c-plane GaN wafer from the second GaN thick film, and,

[0045] (iii) having a third process for obtaining a stacked structure by growing a (0001) oriented GaN film with a thickness greater than 50 μm on a second c-plane GaN wafer obtained in the second process using HVPE, and the GaN film grown in the third process has a total concentration of compensation impurities of 1 × 10 17 A method for manufacturing a GaN substrate wafer characterized by forming a region with atoms / cm³ or more.

[0046]

[26] A method for manufacturing a GaN substrate wafer as described in

[25] , wherein the thickness of the GaN film is 300 μm or less.

[0047]

[27] A method for manufacturing a GaN substrate wafer as described in

[25] or

[26] , wherein the above GaN substrate wafer satisfies any of the conditions selected from (1) to (3) below.

[0048] (1) It has a diameter of 50 mm or more and 55 mm or less and a thickness of 250 µm or more and 450 µm or less.

[0049] (2) It has a diameter of 100 mm or more and 105 mm or less, and a thickness of 350 µm or more and 750 µm or less.

[0050] (3) It has a diameter of 150 mm or more and 155 mm or less, and a thickness of 450 µm or more and 800 µm or less.

[0051]

[28] The above GaN film has a region length in the c-axis direction of 20 μm or more, and the total concentration of compensation impurities in the region is 1 × 10 17 A method for manufacturing a GaN substrate wafer having a specific dope region of at least atoms / cm³ as described in any one of

[25] to

[27] .

[0052]

[29] The total concentration of compensation impurities in the specific dope region above is 1 × 10 18 A method for manufacturing a GaN substrate wafer described in

[28] above, having at least atoms / cm³.

[0053]

[30] A method for manufacturing a GaN substrate wafer as described in

[28] or

[29] , wherein in the specific dope region above, the total concentration of the compensation impurity is at least twice the total concentration of the donor impurity.

[0054]

[31] A method for manufacturing a GaN substrate wafer described in any one of

[28] to

[30] , wherein the variation in the total concentration of compensation impurities within the specific dope region along the c-axis direction is within ± 25% from the median value.

[0055]

[32] A method for manufacturing a GaN substrate wafer as described in any one of

[28] to

[31] , wherein the length of the region is 50% or more of the thickness of the GaN film.

[0056]

[33] A method for manufacturing a GaN substrate wafer described in any one of

[28] to

[32] , wherein the length from the bottom of the specific dope region to the interface between the GaN film and the second c-plane GaN wafer is 1 μm or more.

[0057]

[34] A method for manufacturing a GaN substrate wafer as described in any one of

[28] to

[33] , wherein the specific dope region above contains one or more elements selected from carbon and transition metal elements.

[0058]

[35] A method for manufacturing a GaN substrate wafer as described in any one of

[28] to

[34] , wherein the impurity contained in the highest concentration in the specific dope region is Fe, Mn or C.

[0059]

[36] The total concentration of compensation impurities in the above GaN film is 5 × 10 19 A method for manufacturing a GaN substrate wafer having atoms / cm³ or less, as described in any one of

[24] to

[35] above.

[0060]

[37] A method for manufacturing a GaN substrate wafer described in any one of

[24] to

[36] , having a thinning process for thinning the stacked structure after the third process above.

[0061]

[38] A method for manufacturing a GaN substrate wafer as described in

[37] , wherein the difference in thickness of the GaN film before and after the above thinning process is 50 μm or more.

[0062]

[39] A method for manufacturing a GaN substrate wafer as described in

[37] or

[38] , wherein the difference in thickness of the GaN film before and after the above thinning process is 200 μm or less.

[0063]

[40] A method for manufacturing a GaN substrate wafer as described in any one of

[37] to

[39] , wherein the offcut orientation of the above GaN substrate wafer is different from the offcut orientation of the above 2 c-plane GaN wafer.

[0064]

[41] A method for manufacturing a GaN substrate wafer described in any one of

[24] to

[40] , having a flattening process in which the main surface of the Ga polarity side of the second c-plane GaN wafer sliced ​​from the second GaN thick film in the second process is flattened before growing the GaN film in the third process, and a roughening process in which the roughening is further roughened by etching. Effects of the invention

[0065] A GaN substrate wafer having improved productivity, which can be preferably used in the manufacture of a nitride semiconductor device having a horizontal device structure, and a method for manufacturing the same are provided. Brief explanation of the drawing

[0066] FIG. 1 is a perspective view showing a GaN substrate wafer related to an embodiment. FIG. 2 is a cross-sectional view showing a GaN substrate wafer related to an embodiment. FIG. 3 is a cross-sectional view showing a GaN substrate wafer related to an embodiment. FIG. 4 is a cross-sectional view of a process for explaining the manufacturing process of a nitride semiconductor device using a GaN substrate wafer related to an embodiment. FIG. 5 is a process cross-sectional view for explaining a method for manufacturing a GaN substrate wafer related to an embodiment. FIG. 6 is a process cross-sectional view for explaining a method for manufacturing a GaN substrate wafer related to an embodiment. FIG. 7 is a process cross-sectional view for explaining a method for manufacturing a GaN substrate wafer related to an embodiment. Figure 8 is a schematic diagram showing the basic configuration of an HVPE device. Specific details for implementing the invention

[0067] Embodiments of the present invention are described in detail below. The description of the constituent requirements described below is an example (representative example) of an embodiment of the present invention, and the present invention is not specified in these contents unless it exceeds the gist thereof.

[0068] In the present specification, when expressed as “X ~ Y” (where X and Y are arbitrary numbers), unless specifically stated otherwise, it includes the meaning of “X or greater and Y or less,” as well as the meanings of “preferably greater than X” and “preferably smaller than Y.”

[0069] In addition, in this specification, the term “independently” used when describing two or more objects together is used to mean that the two or more objects may be the same or different.

[0070] 1. GaN substrate wafer

[0071] One embodiment of the present invention relates to a GaN substrate wafer.

[0072] The GaN substrate wafer related to the embodiment is a (0001) oriented GaN substrate wafer and has a first region formed on the N polarity side with a regrowth interface in between, and a second region having a minimum thickness formed on the Ga polarity side. The minimum thickness of the second region is 20 μm or more. In addition, in at least a portion of the second region, the total concentration of compensation impurities is 1 × 10 17 It is greater than atoms / cm³.

[0073] In addition, regarding the impurity concentration in the first region, it is preferable that one or more conditions selected from (a) to (c) below are satisfied for the above GaN substrate wafer.

[0074] (a) Si (silicon) concentration 5 × 10 16 It is greater than atoms / cm³ ;

[0075] (b) O (oxygen) concentration is 3 × 10 16 is less than atoms / cm³ ;

[0076] (c) H (hydrogen) concentration is 1 × 10 17 It is less than atoms / cm³.

[0077] In addition, in this specification, "impurities" refers to components other than Ga and N elements contained in the GaN substrate.

[0078] (0001) An oriented GaN wafer is a GaN wafer having a main surface (large area surface) that is parallel or approximately parallel to the (0001) crystal plane, i.e., the c plane, and is also called a c plane GaN wafer.

[0079] FIGS. 1 and FIGS. 2 show an example of a GaN substrate wafer related to an embodiment. FIGS. 1 is a perspective view, and FIGS. 2 is a cross-sectional view.

[0080] The GaN substrate wafer (100) shown in FIGS. 1 and 2 is a self-supporting substrate wafer made only of GaN crystals, and one of the two main surfaces is an N polarity surface (101) and the other is a Ga polarity surface (102). The N polarity surface (101) and the Ga polarity surface (102) are parallel to each other.

[0081] The GaN substrate wafer (100) is oriented (0001), and the inclination of the Ga polar plane (102) with respect to the crystal plane (0001) is 10 degrees or less, preferably 5 degrees or less, more preferably 2.5 degrees or less. The inclination may be 0.2 degrees or more and less than 1 degree, 1 degree or more and 2.5 degrees or less, etc.

[0082] The diameter of the GaN substrate wafer (100) is typically 45 mm or more, 95 mm or more, or 145 mm or more. Typically, it is 50 to 55 mm (about 2 inches), 100 to 105 mm (about 4 inches), 150 to 155 mm (about 6 inches), etc.

[0083] The preferred range of thickness of the GaN substrate wafer (100) varies depending on the diameter. When the diameter is about 2 inches, the thickness is preferably 250 μm or more, more preferably 300 μm or more, and also preferably 450 μm or less, more preferably 400 μm or less. When the diameter is about 4 inches, the thickness is preferably 350 μm or more, more preferably 400 μm or more, and also preferably 750 μm or less, more preferably 650 μm or less. When the diameter is about 6 inches, the thickness is preferably 450 μm or more, more preferably 550 μm or more, and also preferably 800 μm or less, more preferably 700 μm or less.

[0084] As described above, the GaN substrate wafer (100) is typically disc-shaped, but in a modified example, the shape of the main surface may be square, rectangular, hexagonal, octagonal, elliptical, etc., or may be irregular. In such a modified example, the diameter may be replaced with "the shortest length as a straight line passing through the center of gravity on the main surface."

[0085] The N polarity side (101) of the GaN substrate wafer (100) is the “back side” and may be mirror-finished, rough-finished, or degloss-finished.

[0086] The Ga polarity surface (102) of the GaN substrate wafer (100) is a "surface," and when the GaN substrate wafer (100) is used to manufacture a nitride semiconductor device, a nitride semiconductor layer is typically epitaxially grown on the Ga polarity surface (102).

[0087] The Ga polar surface (102) may be an as-grown surface, but typically, it is flattened by processing. Processing performed to flatten the Ga polar surface (102) to make it a flat surface may include one or more selected from polishing and CMP (Chemical Mechanical Polishing). In addition to these processes, etching may be performed for the purpose of removing a damaged layer. The roughness of the flat surface is not limited, but, for example, as the root mean square (RMS) roughness of the Ga polar surface (102) measured by an atomic force microscope (AFM), in a measurement range of 2 μm × 2 μm, it is preferably less than 5 nm, more preferably less than 2 nm, even more preferably less than 1 nm, and may be less than 0.5 nm.

[0088] The Ga polar surface (102) may be a surface formed by cutting, but it is preferable that it be a surface that has been flattened by polishing, CMP, etching, etc. without cutting.

[0089] A GaN substrate wafer (100) has a regrowth interface (103) between its two main surfaces, and has a first region (110) on the N polarity side and a second region (120) on the Ga polarity side with the regrowth interface (103) in between. "Regrowth interface" refers to a boundary surface that occurs when a GaN crystal is grown on any substrate, and its existence can be confirmed, for example, by observing a cross-section of the GaN substrate wafer using scanning electron microscope cathode luminescence or fluorescence microscope.

[0090] It is preferable that the regrowth interface (103) is parallel to the Ga polar plane (102). When the regrowth interface (103) is inclined from the Ga polar plane (102), the thickness of the second region (120) is typically minimized at one end of the inclined direction and maximized at the other end. It is preferable that the difference between the thickness at one end of the second region (120) and the thickness at the other end does not exceed 200 μm.

[0091] In the manufacturing process of a nitride semiconductor device using a GaN substrate wafer (100), it is assumed that the first region (110) is ultimately removed. In short, it is assumed that the nitride semiconductor device chip manufactured using the GaN substrate wafer (100) does not include a portion originating from the first region (110). With such a usage mode, there are no special restrictions on the electrical properties of the GaN crystal forming the first region (110).

[0092] The first region (110) is typically composed of a GaN crystal grown by HVPE, and thus satisfies one or more of the following conditions selected from (a) to (c) regarding impurity concentration. In this specification, HVPE means Hydride Vapor Phase Epitaxy.

[0093] (a) Si concentration of 5 × 10 16 atoms / cm³ or more

[0094] (b) O concentration is 3 × 10 16 atoms / cm³ or less

[0095] (c) H concentration is 1 × 10 17 atoms / cm³ or less

[0096] In GaN crystals grown by HVPE, the total concentration of compensation impurities is usually lower than the total concentration of donor impurities unless they are intentionally doped with compensation impurities. In addition, "intentional doping" means adding a target element as a raw material during the process of growing GaN crystals.

[0097] Also, in the first region, the total concentration of compensation impurities is 1 × 10 17 It is desirable that it be less than atoms / cm³.

[0098] The GaN crystal forming the first region (110) is preferably a GaN crystal that is not intentionally doped.

[0099] The second region (120) is grown as HVPE on the first region (110). The reason a regrowth interface (103) exists between the first region (110) and the second region (120) is that the process of growing the first region (110) and the process of growing the second region (120) are not continuous.

[0100] The minimum thickness of the second region (120) is 20 μm or more. This is so that, in the manufacturing process of a nitride semiconductor device chip using a GaN substrate wafer (100), after the first region (110) is removed from the substrate wafer (100), the remaining second region (120) can serve as a substrate that supports the structure of the semiconductor device chip. The minimum thickness refers to the thickness at the point where the thickness is minimum.

[0101] The minimum thickness of the second region (120) may be 50 μm or more, or greater than 50 μm, furthermore 75 μm or more, furthermore 100 μm or more, furthermore 150 μm or more, etc.

[0102] The minimum thickness of the second region (120) is preferably 350 μm or less, more preferably 300 μm or less, and may be 250 μm or less, 200 μm or less, etc.

[0103] When the Ga polar plane (102) and the regrowth interface (103) are parallel and the thickness of the second region (120) is constant, the thickness of the second region is considered to be the minimum thickness at all points.

[0104] Preferably, among the second region (120), the region including at least the main plane on the Ga polarity side, specifically the region within a specific length (L) from the Ga polarity plane (102) of the GaN substrate wafer (100), is defined as the main region (120a). In the second region (120), the total concentration of compensation impurities in at least the main region (120a) is 1 × 10 17 It is doped to an amount greater than atoms / cm³.

[0105] The total concentration of compensating impurities refers to the sum of the concentrations of all types of compensating impurities. In GaN crystals grown by HVPE, unless intentionally doped, the total concentration of compensating impurities is 1 × 10⁻⁶ 17 It usually does not exceed atoms / cm³. Therefore, by intentionally doping, the total concentration of compensating impurities is increased to 1 × 10⁻⁶ 17 It can be done with more than atoms / cm³.

[0106] The compensating impurities referred to in this specification mean impurities that have the function of compensating for n-type carriers in GaN crystals. Well-known compensating impurities are C (carbon) and transition metal elements. Among transition metal elements, Fe (iron) and Mn (manganese) are representative, and others include Co (cobalt), Cr (chromium), V (vanadium), Ni (nickel), Cu (copper), etc.

[0107] The total concentration of compensating impurities in the Zudoff region (120a) is 1 × 10 17 atoms / cm³ or more 2 × 10 17 Less than atoms / cm³, 2 × 10⁻⁶ 17 atoms / cm³ or more 5 × 10 17 Less than atoms / cm³, 5 × 10 17 atoms / cm³ or more 1 × 10 18 Less than atoms / cm³, 1 × 10⁻⁶ 18 atoms / cm³ or more 2 × 10 18 Less than atoms / cm³, 2 × 10⁻⁶ 18 atoms / cm³ or more 5 × 10 18 Less than atoms / cm³, 5 × 10 18 atoms / cm³ or more 1 × 10 19 Less than atoms / cm³, 1 × 10⁻⁶ 19 atoms / cm³ or more 2 × 10 19 Less than atoms / cm³, 2 × 10⁻⁶ 19 atoms / cm³ or more 5 × 10 19 It may be less than atoms / cm³, etc.

[0108] In the main region (120a), the total concentration of the compensating impurities is preferably at least 2 times the total concentration of the donor impurities, more preferably at least 5 times, and even more preferably at least 10 times, and may be at least 50 times. In addition, it is preferable that the compensating impurities contained at the highest concentration in the main region (120a) are Fe, Mn, or C.

[0109] In a preferred example, the GaN crystal forming the Zudoff region (120a) is semi-insulating, that is, its room temperature resistivity is 1 × 10⁻⁶ 5 The concentration of the compensation impurity added to the main region (120a) is set so that it is greater than or equal to Ω·cm.

[0110] Elements that can act as donor impurities in GaN crystals include Group 14 elements such as Si, Ge (germanium), and Sn (tin), and Group 16 elements such as O, S (sulfur), Se (selenium), and Te (tellurium); among these, Si and O, even when not intentionally added, contain 10 in GaN crystals grown by HVPE 16 They can be contained at concentrations of atoms / cm³ or higher. In contrast, Group 14 elements other than Si and Group 16 elements other than O, unless intentionally added, are present in GaN crystals grown by HVPE at concentrations of 10 15 It is not contained at a concentration greater than atoms / cm³.

[0111] A specific length (L) can be arbitrarily determined within a range that is at least 1 μm, preferably 20 μm, more preferably 25 μm, and even more preferably 50 μm, and does not exceed the minimum thickness of the second region (120).

[0112] In the main pressure region (120a), it is desirable that the variation in resistivity along the c-axis direction, which is the thickness direction of the GaN substrate wafer (100), be small. Accordingly, the variation in the total concentration of compensation impurities along the c-axis direction in the main pressure region (120a) is preferably within ± 25% from the median value, more preferably within ± 20%, even more preferably within ± 15%, and even more preferably within ± 10%.

[0113] In a preferred embodiment, during the manufacturing process of a nitride semiconductor device chip using a GaN substrate wafer (100), a second region (120) is also partially removed from the GaN substrate wafer (100) in addition to the first region (110) so that when the main region (120a) is exposed, the GaN substrate consisting only of the remaining main region (120a) can support the structure of the semiconductor device chip, the specific length (L) is greater than 50 μm.

[0114] In this preferred embodiment, the specific length (L) may be 75 μm or more, 100 μm or more, furthermore 150 μm or more, furthermore 200 μm or more.

[0115] In this preferred embodiment, the specific length (L) is preferably 50% or more, more preferably 75% or more, and even more preferably 90% or more of the minimum thickness of the second region (120).

[0116] Also, the length from the bottom of a specific length (L) (the end on the N polarity side (101)) to the regrowth interface is preferably 1 μm or more, more preferably 5 μm or more, and 10 μm or more, and the length from the bottom to the interface is preferably 50 μm or less, more preferably 30 μm or less.

[0117] Including the doping region (120a), the total concentration of compensation impurities in the second region (120) is 5 × 10⁻⁶ to avoid a significant deterioration in crystal quality due to excessive doping. 19 atoms / cm³ or less, and furthermore, 2 × 10⁻⁶ 19 atoms / cm³ or less, and furthermore, 1 × 10⁻⁶ 19 It can be less than atoms / cm³.

[0118] In the lowest part of the second region (120), that is, the part adjacent to the first region (110), the concentration of compensation impurities of the same type as the compensation impurities intentionally added to the Zudoff region (120a) may increase continuously or in steps as it moves away from the first region (110).

[0119] Since the second region (120) is typically grown as HVPE, regarding the impurity concentration, it satisfies one or more conditions selected from the following (a') to (c').

[0120] (a') Si concentration is 5 × 10 16 atoms / cm³ or more

[0121] (b') O concentration is 3 × 10 16 atoms / cm³ or less

[0122] (c') H concentration is 1 × 10 17 atoms / cm³ or less

[0123] In one example, as shown in FIG. 3, the regrowth interface (103) may be rough. For example, when the surface of the first region (110) is roughened by etching before growing the second region (120), the regrowth interface (103) may be rough. When the direction from the first region (110) toward the second region (120) perpendicular to the regrowth interface (103) is defined as the height direction and the difference in height between the highest point and the lowest point on the regrowth interface is defined as the roughness (r) of the regrowth interface, the roughness (r) may be, for example, 0.3 μm or more and 12 μm or less.

[0124] In addition, although not shown in FIGS. 1 to 3, the edges of the GaN substrate wafer (100) may be chamfered. Also, on the GaN substrate wafer (100), various markings may be performed as needed, such as an orientation flat or notch indicating the orientation of the crystal, or an index flat to facilitate identification between the front and back sides.

[0125] A GaN substrate wafer (100) can be preferably used to manufacture a nitride semiconductor device with a horizontal device structure such as a GaN-HEMT. A nitride semiconductor device is a semiconductor device in which the main part of the device structure is formed of a nitride semiconductor. Nitride semiconductors are also called nitride-based group III-V compound semiconductors, group III nitride-based compound semiconductors, GaN-based semiconductors, etc., and in addition to containing GaN, they include compounds in which some or all of the gallium in GaN is substituted with other Group 13 elements (B, Al, In, etc.).

[0126] The horizontal device structure can be adopted in electronic devices other than high electron mobility transistors (HEMTs), such as bipolar transistors, and also in light-emitting devices such as light-emitting diodes (LEDs) and laser diodes (LDs).

[0127] When manufacturing a GaN-HEMT using a GaN substrate wafer (100), after the GaN substrate wafer (100) is prepared as shown in FIG. 4(a), an epitaxial film (200) comprising at least an undoped GaN channel layer (210) and an undoped AlGaN carrier supply layer (220), as shown in FIG. 4(b), is grown on the Ga polarity surface (102), for example by an organometallic vapor phase growth method (MOVPE), thereby forming an epitaxial wafer.

[0128] After a semiconductor process including etching, ion implantation, electrode formation, and protective film formation is executed, the epitaxial wafer is divided to become a GaN-HEMT chip. In order to thin the epitaxial wafer before division, at least a portion of the first region (110) of the GaN substrate wafer (100) is typically removed by methods such as grinding and etching, as shown in FIG. 4(c).

[0129] This thinning process can be performed so that a ring-shaped thick portion remains on the outer periphery of the epitaxial wafer. In short, the first region (110) of the GaN substrate wafer (100) can be removed only in the portion excluding the outer periphery of the epitaxial wafer.

[0130] In FIG. 4(c), the second region (120) is also partially removed from the GaN substrate wafer (100) so that the main region (120a) is exposed on the N polarity side of the epitaxial wafer after thinning. Additionally, the semiconductor device using the GaN substrate wafer (100) is not limited to only nitride semiconductor devices.

[0131] 2. Method for manufacturing a GaN substrate wafer

[0132] Next, a method for manufacturing a GaN substrate wafer, which is another embodiment of the present invention, will be described. The manufacturing method described below is a preferred form for manufacturing the GaN substrate wafer described above. Furthermore, a preferred embodiment of the GaN substrate wafer obtained by the manufacturing method for the GaN substrate wafer described below may be the GaN substrate wafer described above.

[0133] The above-described GaN substrate wafer (100) related to the embodiment can preferably be manufactured by the method described below. This method is applied to the manufacture of a GaN substrate wafer having an N polarity side region and a Ga polarity side region with a regrowth interface in between, and preferably has a resistivity increased in at least a part of the Ga polarity side, and has the following process.

[0134] (ii') a second process of obtaining a second c-plane GaN wafer by growing a second GaN thick film oriented (0001) on a substrate using HVPE, and then slicing the second GaN thick film; and

[0135] (iii') A third process of growing a GaN film with a thickness greater than 50 μm oriented (0001) on the second c-plane GaN wafer by HVPE, and a region with a higher total concentration of donor impurities than the second c-plane GaN wafer is formed in the GaN film.

[0136] In addition, it is preferable to perform the following process, which adds a first process, as a process for manufacturing a substrate in the second process above. Accordingly, the first process below is optional.

[0137] (i) A first GaN thick film made of unintentionally undoped GaN and oriented (0001) is grown on a seed wafer using HVPE, and the first GaN thick film is processed to obtain at least one first c-plane GaN wafer.

[0138] (ii) A second process of growing a second GaN thick film made of unintentionally undoped GaN and oriented (0001) on a first c-plane GaN wafer obtained in the first process using HVPE, and slicing the second c-plane GaN wafer from the second GaN thick film.

[0139] (iii) A third process for obtaining a stacked structure by growing a (0001) oriented GaN film with a thickness greater than 50 μm on a second c-plane GaN wafer obtained in the second process using HVPE. provided that the total concentration of compensation impurities in the GaN film is 1 × 10 17 A region with more than atoms / cm³ is formed.

[0140] In this specification, "on the wafer" has the same meaning as "on the surface of the wafer."

[0141] Hereinafter, the first to third processes described above will be explained in more detail. In addition, as the structure or characteristics of the first c-plane GaN wafer obtained in the first process and the second GaN thick film obtained in the second process, the structure or characteristics of the first region and the second region described above can be applied, respectively.

[0142] In the first process, after preparing a seed wafer (1) shown in FIG. 5(a), a first GaN thick film (2) made of undoped GaN and oriented (0001) is grown on it using HVPE as shown in FIG. 5(b). Additionally, as shown in FIG. 5(c), at least one first c-plane GaN wafer (3) is obtained by processing the first GaN thick film (2).

[0143] An example of a seed wafer (1) is a c-sided sapphire wafer, and preferably, a peeling layer may be formed on the main surface. For example, a c-sided sapphire wafer can be formed by growing a GaN layer with a thickness of several hundred nm on a c-sided sapphire wafer by interposing a low-temperature buffer layer with MOVPE, and additionally, forming a Ti (titanium) layer with a thickness of several tens of nm on the GaN layer by vacuum deposition, and then annealing for 30 minutes at, for example, 1060°C in a mixed gas of 80% H2 (hydrogen gas) and 20% NH3 (ammonia).

[0144] The seed wafer (1) may be a c-plane GaN wafer manufactured in a separate process.

[0145] The first GaN thick film (2) is grown to a thickness sufficient to manufacture at least one self-standing c-plane GaN wafer by processing the first GaN thick film (2). In a preferred example, the first GaN thick film (2) is grown to a thickness of several mm or more, and at least two first c-plane GaN wafers (3) are sliced ​​from therefrom.

[0146] FIG. 6(a) is a cross-sectional view showing one first c-plane GaN wafer (3) manufactured in the first process. However, the first c-plane GaN wafer (3) is not limited to that obtained by the first process.

[0147] In the second process, as shown in FIG. 6(b), a second GaN thick film (4) made of undoped GaN and oriented (0001) is grown on the Ga polarity plane of the first c-plane GaN wafer (3) using HVPE, and then, as shown in FIG. 6(c), the second c-plane GaN wafer (5) is sliced ​​from the second GaN thick film (4). The second GaN thick film (4) is grown to a thickness sufficient to manufacture at least one second c-plane GaN wafer (5) by processing the second GaN thick film (4). In a preferred example, the second GaN thick film (4) is grown to a thickness of several mm or more, and at least two second c-plane GaN wafers (5) are sliced ​​from there.

[0148] Since the second GaN thick film (4) has weak n-type conductivity, it is possible to use a wire discharge machining device on the slice. The wire discharge machining device has a higher cutting speed than a glass abrasive wire saw and is also easier to handle. In addition, when cutting a GaN crystal using a wire discharge machining device, the kerf loss is less than when using a fixed abrasive wire saw.

[0149] The second c-plane GaN wafer (5) has N polarity planes and Ga polarity planes parallel to each other as shown in the cross-sectional view in FIG. 7(a).

[0150] When manufacturing the above-described GaN substrate wafer (100) related to the embodiment, when slicing the second c-plane GaN wafer (5) from the second GaN thick film (4) in the second process, it is preferable, but not mandatory, to make the angle of inclination (offcut angle) and the direction of inclination (offcut direction) of the Ga polarity plane (0001) in the second c-plane GaN wafer (5) the same as the offcut angle and offcut direction that the GaN substrate wafer (100) must have.

[0151] The offcut orientation that the GaN substrate wafer (100) must have varies according to the requirements of the manufacturer of the semiconductor device using the GaN substrate wafer (100), but preparing a second c-plane GaN wafer (5) having various offcut orientations may lead to a decrease in the production efficiency of the GaN substrate wafer (100). It is also necessary to be careful that the optimal conditions for growing a GaN film (6) with HVPE on the second c-plane GaN wafer (5) in the next third process may change depending on the offcut orientation of the second c-plane GaN wafer (5).

[0152] Initial thickness (t) of the second c-plane GaN wafer (5) 5i) may be thinner than the thickness typically used for manufacturing nitride semiconductor devices. This is because, unlike GaN substrate wafers that need to withstand semiconductor processes consisting of multiple steps, the second c-sided GaN wafer (5) only needs not be damaged during the subsequent third step.

[0153] For example, when the diameter of the second c-plane GaN wafer (5) is about 2 inches, its initial thickness (t 5i ) is preferably 300 μm or less, 250 μm or less, and furthermore, 200 μm or less.

[0154] Initial thickness (t) of the second c-plane GaN wafer (5) 5i By making ) smaller, the number of second c-plane GaN wafers (5) that can be sliced ​​from the second GaN thick film (4) can be increased.

[0155] In the third process, as shown in FIG. 7(b), on the Ga polarity plane of the second c-plane GaN wafer (5), a growth thickness (t 6g A GaN film (6) oriented (0001) with a thickness exceeding 50 μm is grown in HVPE to obtain a stacked structure. At this time, a regrowth interface is formed between the second c-plane GaN wafer (5) and the GaN film (6).

[0156] Typically, the Ga polarity surface of the second c-plane GaN wafer (5) is flattened using appropriate techniques such as grinding, polishing, and CMP before growing the GaN film (6) (flattening process), but in one example, the flattened Ga polarity surface may be roughened by etching (roughening process) before growing the GaN film (6).

[0157] If HCl (hydrogen chloride) is used as an etching gas, the Ga polarity surface of GaN can be harmonized without using an etching mask. If an HCl supply line for etching is formed in the HVPE device used for growing the GaN film (6), the Ga polarity surface of the second c-plane GaN wafer (5) can be harmonized within the reactor of the HVPE device immediately before the growth of the GaN film (6).

[0158] The preferred etching conditions when using HCl as an etching gas are as follows.

[0159] The partial pressure of HCl is, for example, 0.002 to 0.05 atm.

[0160] The H2 partial pressure is, for example, 0.2 to 0.8 atm.

[0161] The NH3 partial pressure is, for example, 0.01 to 0.05 atm. By flowing NH3, the Ga polar planes of GaN are more uniformly harmonized.

[0162] The etching temperature is, for example, 900 to 1050 ℃.

[0163] The etching time is, for example, 1 to 60 minutes.

[0164] When the roughness of the Ga polarity plane of the second c-plane GaN wafer (5) after etching is defined as the difference in height between the highest point and the lowest point, the roughness can be, for example, 0.3 to 12 μm.

[0165] In etching using HCl, when conditions other than the etching time are fixed, the roughness of the Ga polarity plane of the second c-plane GaN wafer tends to increase along with the etching time.

[0166] When using HCl as the etching gas, the etching time may be set so that the roughness of the Ga polar plane does not exceed 0.5 μm.

[0167] For example, when etching the Ga polarity surface of the second c-plane GaN wafer (5) under conditions of HCl partial pressure 0.01 to 0.02 atm, H2 partial pressure 0.05 to 0.08 atm, NH3 partial pressure 0.01 to 0.03 atm, and temperature 970 to 1000 ℃, the roughness of the Ga polarity surface can be reduced to 0.5 μm or less by making the etching time 5 minutes or less.

[0168] In one example, the Ga polarity surface of the second c-plane GaN wafer (5) may be roughened by dry etching after forming an etching mask patterned by a photolithography technique. Dot patterns and net patterns are typical examples of preferred patterns for the etching mask. Dry etching may be RIE (reactive ion etching) using Cl2 (chlorine gas) or a chlorine-containing compound as the etching gas.

[0169] The GaN film (6) has a total concentration of compensation impurities of 1 × 10 in at least some parts. 17 It is doped to have at least atoms / cm³. Particularly preferably used compensation impurities are Fe, Mn, and C.

[0170] In a preferred example, a specific doped region (6a) may be formed in the GaN film (6). The specific doped region (6a) preferably has a region length in the c-axis direction of 20 μm or more, and also has a total concentration of compensation impurities within the region of 1 × 10⁻⁶ 17 It is a region where the concentration is greater than atoms / cm³. In other words, the length of this region is such that the total concentration of compensating impurities is 1 × 10⁻⁶ 17 It refers to the thickness (height in the thickness direction) of the region greater than atoms / cm³.

[0171] The length of the region in the c-axis direction of a specific dope region (6a) may be 25 μm or more, 50 μm or more, 75 μm or more, 100 μm or more, 150 μm or more, 200 μm or more, etc.

[0172] The top of a specific dope region (6a) (the end on the

[0001] side) is preferably within 10 μm, more preferably within 5 μm from the upper surface of the GaN film (6), and may be the upper surface of the GaN film (6).

[0173] The length from the bottom of a specific dope region (6a) (the end on the [000-1] side) to the interface between the second c-plane GaN wafer (5) and the GaN film (6) is preferably 1 μm or more, more preferably 5 μm or more, and 10 μm or more, and the length from the bottom to the interface is preferably 50 μm or less, more preferably 30 μm or less.

[0174] The length of the region in the c-axis direction of a specific dope region (6a) is also preferably 50% or more of the thickness of the GaN film (6), more preferably 75% or more, and even more preferably 90% or more.

[0175] In a specific dope region (6a), the total concentration of compensation impurities is at least 1 × 10 17 atoms / cm³ and 2 × 10 17 atoms / cm³ or more, 5 × 10 17 atoms / cm³ or more, 1 × 10⁻⁶ 18 atoms / cm³ or more, 2 × 10⁻⁶ 18 atoms / cm³ or more, 5 × 10 18 It may be atoms / cm³ or more.

[0176] In a specific dope region (6a), the total concentration of the compensation impurity is preferably 2 times or more than the total concentration of the donor impurity, more preferably 5 times or more, even more preferably 10 times or more, and may be 50 times or more.

[0177] Within a specific dope region (6a), the GaN crystal is semi-insulating, that is, its room temperature resistivity is 1 × 10⁻⁶ 5 It may be Ω·cm or more.

[0178] In a specific dope region (6a), it is desirable that the variation in resistivity along the c-axis direction be small. Accordingly, the variation in the total concentration of compensation impurities along the c-axis direction in the specific dope region (6a) is preferably within ± 25% from the median, more preferably within ± 20%, even more preferably within ± 15%, and even more preferably within ± 10%.

[0179] The total concentration of compensation impurities in the GaN film (6), including a specific doped region (6a), is 5 × 10⁻⁶ to avoid a significant deterioration in crystal quality due to excessive doping. 19 atoms / cm³ or less, and furthermore, 2 × 10⁻⁶ 19 atoms / cm³ or less, and furthermore, 1 × 10⁻⁶ 19 It can be less than atoms / cm³.

[0180] In the lower part of the GaN film (6), that is, the part adjacent to the second c-plane GaN wafer (5), a compensation impurity of the same type as the compensation impurity added to a specific dope region (6a) may be added so that its concentration increases continuously or in steps as it moves away from the second c-plane GaN wafer (5).

[0181] Growth thickness (t) of the GaN film (6) 6g ) can be set according to the design thickness of the Ga polarity side region of the GaN substrate wafer to be manufactured. Specifically, it may be 20 μm or more, 50 μm or more, or greater than 50 μm, and furthermore, 75 μm or more, 100 μm or more, 150 μm or more, etc., and may also be 500 μm or less, 350 μm or less, 300 μm or less, 250 μm or less, 200 μm or less, etc.

[0182] When manufacturing the aforementioned GaN substrate wafer (100), the growth thickness (t) of the GaN film (6) 6g) may be the same as the design thickness of the second region (120) in the GaN substrate wafer, but preferably made larger than the design thickness so that the surface of the GaN film (6) can be flattened in the subsequent thinning process. Accordingly, the growth thickness (t) of the GaN film (6) 6g In order to secure a processing margin for planarization, it is preferable that the second region (120) be at least 50 μm larger than the design maximum thickness, and more preferable that it be at least 100 μm larger. A processing margin exceeding 200 μm is usually not required. In other words, it is preferable that the thickness difference of the GaN film (6) before and after the thinning process be 200 μm or less.

[0183] For example, the growth thickness (t) of the GaN film (6). 6g When ) is 50 μm or more larger than the design maximum thickness of the second region (120), the thickness of the GaN film (6) is reduced by 50 μm or more in the subsequent thinning process. In other words, the difference in thickness of the GaN film (6) before and after the thinning process is 50 μm or more.

[0184] When manufacturing the aforementioned GaN substrate wafer (100), even if it is a wafer with a large diameter, for example, a wafer with a diameter of 6 inches, the growth thickness (t) of the GaN film (6) 6g It is possible to suppress ) to 500 μm or less.

[0185] Growth thickness (t 6g In this respect, the GaN film (6) can be formed in a relatively short time, and therefore, it is possible to grow GaN films (6) on multiple second-sided GaN wafers (5) at once without worrying about the byproduct NH4Cl (ammonium chloride) clogging the exhaust system of the HVPE device. In this respect, the throughput in the third process can be very high.

[0186] In addition, the short time required to form the GaN film (6) can also contribute to reducing costs related to cleaning and maintenance of the HVPE reactor. Generally, when the time required for a single growth process is short, the progression of degradation of the HVPE reactor is slower and the service life is extended.

[0187] After the third process, if necessary, a thinning process is provided to thin the laminated structure obtained in the third process, as shown in FIG. 7(c).

[0188] In FIG. 7(c), the thickness of the second c-plane GaN wafer (5) is the initial thickness (t 5i From ) final thickness (t 5f As the thickness of the GaN film (6) decreases to the initial thickness (t 6i From ) final thickness (t 6f Although it is reduced to ), in the thinning process, only one of the second c-sided GaN wafer (5) and the GaN film (6) may be processed.

[0189] When manufacturing the aforementioned GaN substrate wafer (100) related to the embodiment, in the thinning process, the thickness of the second c-plane GaN wafer (5) and the GaN film (6) is reduced until it matches the design thickness of the first region (110) and the second region (120) of the GaN substrate wafer, respectively.

[0190] When the offcut orientation of the GaN substrate wafer (100) to be manufactured and the offcut of the second c-plane GaN wafer (5) are the same, the back side (N polarity side of the stacked structure) of the second c-plane GaN wafer (5) can be used as a reference for the surface orientation during thinning process.

[0191] When the offcut orientation of the GaN substrate wafer (100) to be manufactured is different from the offcut of the second c-plane GaN wafer (5), that is, when at least one of the offcut angle and the offcut direction is different, the crystal orientation of the stacked structure is confirmed by an X-ray diffraction device before thinning processing.

[0192] The processing technique used in the thinning process can be appropriately selected from grinding, lapping, CMP, dry etching, wet etching, etc.

[0193] By using the manufacturing method described above, a GaN substrate wafer (100) related to the embodiment can be produced in good yield.

[0194] The reason is that there is no process for growing intentionally doped GaN thick films to a thickness of 1 mm or more using HVPE, and no process for slicing the GaN thick films grown in this way.

[0195] In the first and second processes, the GaN thick film may be grown to a thickness of the millimeter order using HVPE, and the first GaN thick film (2) and the second GaN thick film (4) grown in these processes are not intentionally doped, so morphological abnormalities or cracks do not occur easily during growth, and the frequency of cracking during slicing is also low.

[0196] Meanwhile, the GaN film (6) grown in the third process has 1 × 10 17 A portion containing compensation impurities at a concentration of atoms / cm³ or higher is formed, and since the growth thickness of the GaN film (6) is 500 μm or less, morphological abnormalities or cracks do not easily occur during growth. Furthermore, the GaN film (6) does not need to be sliced. That is, there is no need to perform slice processing in the thinning process described above. In particular, it is preferable that the GaN film (6) formed in the third process undergoes the thinning process without slice processing.

[0197] In addition, in the GaN substrate wafer obtained by the manufacturing method described above, the deviation of the off-cut orientation within the main body can be made very small.

[0198] The reason is that the warping of the second GaN thick film (4) grown homoepitaxially without intentional doping on the first c-plane GaN wafer (3) without intentional doping can be very small, and therefore, the deviation of the off-cut orientation in the second c-plane GaN wafer (5) sliced ​​from the second GaN thick film (4) can be very small.

[0199] Examples of HVPE devices that can be used in the first to third processes included in the manufacturing method described above are explained below with reference to FIG. 8.

[0200] The HVPE device (10) shown in FIG. 8 comprises a hot wall-type reactor (11), a gallium reservoir (12) and a susceptor (13) disposed within the reactor, and a first heater (14) and a second heater (15) disposed outside the reactor. The first heater (14) and the second heater (15) each surround the reactor (11) in an annular shape.

[0201] The reactor (11) is a quartz tube chamber. Inside the reactor (11), there is a first zone (Z1) heated mainly by a first heater (14) and a second zone (Z2) heated mainly by a second heater (15). The exhaust pipe (P E ) is connected to the reactor terminal on the second zone (Z2) side.

[0202] The gallium reservoir (12) placed in the first zone (Z1) is a quartz container having a gas inlet and a gas outlet.

[0203] The susceptor (13) placed in the second zone (Z2) is formed of, for example, graphite. The mechanism for rotating the susceptor (13) can be formed arbitrarily.

[0204] To grow GaN using an HVPE device (10), after placing a seed on a susceptor (13), the inside of the reactor (11) is heated with a first heater (14) and a second heater (15), NH3 (ammonia) diluted with a carrier gas is supplied to the second zone (Z2) through an ammonia inlet pipe (P1), and HCl (hydrogen chloride) diluted with a carrier gas is supplied to the gallium reservoir (12) through a hydrogen chloride inlet pipe (P2). This HCl reacts with metallic gallium in the gallium reservoir (12), and the generated GaCl (gallium chloride) is transferred to the second zone (Z2) through a gallium chloride inlet pipe (P3).

[0205] In the second zone (Z2), NH3 and GaCl react, and the resulting GaN crystallizes on a seed placed on the susceptor (13).

[0206] When intentionally doping the growing GaN, the doping gas diluted with a carrier gas is introduced into the second zone (Z2) in the reactor (11) through the dopant introduction tube (P4).

[0207] The ammonia inlet tube (P1), hydrogen chloride inlet tube (P2), gallium chloride inlet tube (P3) and dopant inlet tube (P4) are formed of quartz in the portions placed inside the reactor (11).

[0208] For the carrier gas used to dilute each of the NH3, HCl, and doping gas, H2 (hydrogen gas), N2 (nitrogen gas), or a mixture of H2 and N2 is preferably used.

[0209] The preferred conditions for growing GaN using an HVPE device (10) are as follows.

[0210] The temperature of the gallium reservoir is, for example, 500 to 1000 ℃, preferably 700 ℃ or higher, and preferably 900 ℃ or lower.

[0211] The susceptor temperature is, for example, 900 to 1100°C, preferably 930°C or higher, more preferably 950°C or higher, and also preferably 1050°C or lower, more preferably 1020°C or lower.

[0212] The V / III ratio, which is the ratio of the partial pressure of NH3 to the partial pressure of GaCl in the reactor, is, for example, 1 to 20, preferably 2 or more, more preferably 3 or more, and also preferably 10 or less.

[0213] Whether the V / III ratio is excessively large or excessively small, it causes the morphology of the GaN growth surface to deteriorate. Deterioration of the growth surface morphology can cause a decrease in crystal quality.

[0214] For certain types of impurities, the introduction efficiency into GaN crystals strongly depends on the crystal orientation of the growth surface. In GaN crystals grown under conditions where the growth surface morphology is poor, the uniformity of the concentration of these impurities decreases. This is because facets of various orientations exist on growth surfaces with poor morphology.

[0215] A typical example of an impurity whose introduction efficiency into a GaN crystal clearly differs depending on the crystal orientation of the growth surface is O (oxygen). Since O is a donor impurity, a decrease in the uniformity of its concentration leads to a decrease in the uniformity of resistivity.

[0216] Furthermore, using an excessively low V / III ratio increases the nitrogen vacancy concentration in the growing GaN crystal. Although the effect of nitrogen vacancies on the GaN crystal, the GaN substrate using it, or the nitride semiconductor device formed on the GaN substrate is not yet clear, it is thought that the concentration should be kept as low as possible given that they are point defects.

[0217] The growth rate of GaN is preferably 40 to 200 μm / h and can be controlled by using the product of the partial pressure of NH3 and GaCl in the reactor as a parameter. An excessively high growth rate degrades the surface morphology of the growing GaN.

[0218] When doping the GaN film (6) in the aforementioned third process, in order to prevent deterioration of the growth surface morphology, it is desirable to gradually increase the doping gas supply rate to a predetermined value over a period of several minutes to tens of minutes from the start of supply.

[0219] For the same reason, it is preferable to start supplying the doping gas when the GaN film (6) has grown at least several μm.

[0220] The method of incorporating compensation impurities into the GaN film (6) is not limited, but typically, a method of introducing doping gas into the HVPE device is employed.

[0221] For doping gas for C doping, hydrocarbon gases such as CH4 (methane), for example, can be used.

[0222] For the doping gas for Fe doping, for example, vaporized iron chloride can be used. In addition to being generated by contacting HCl with metallic iron heated under a carrier gas flow, iron chloride vapor can also be generated by reacting ferrocene (bis(cyclopentadienyl)iron) heated under a carrier gas flow with HCl in a dopant introduction tube. Here, ferrocene may be substituted with other organic compounds containing iron.

[0223] For doping gas for Mn doping, for example, metallic Mn can be installed in an inlet tube and heated, and can be used with a flow of carrier gas, etc.

[0224] When adding other transition metal elements to GaN, the vapor of the said transition metal element or the vapor of the said transition metal element's chloride can also be used as a doping gas.

[0225] GaN grown using an HVPE device (10) can contain O and Si at concentrations detectable by SIMS (secondary ion mass spectrometry) even when not intentionally doped. The Si source is quartz (SiO2) used in the reactor or piping within the reactor, and the O source is either or both of this quartz and moisture remaining or infiltrated within the reactor.

[0226] In FIG. 8, the parts placed inside the reactor (11), including parts where the city is omitted, include SiC (silicon carbide) and SiN in addition to quartz and carbon. x It may be formed from silicon nitride (SNO), boron nitride (BN), alumina, tungsten (W), molybdenum (Mo), etc. By doing so, the concentration of impurity elements other than Si, O, and H in the GaN grown using the HVPE device (10) is independently 5 × 10, unless intentional doping is performed. 15 It can be reduced to atoms / cm³ or less.

[0227] Examples

[0228] The present invention will be explained in more detail below by presenting examples. However, the present invention is not limited to these examples, and various applications are possible within the scope of the technical concept of the present invention.

[0229] [Example]

[0230] <Manufacturing of Planar GaN Wafer (Process 1)>

[0231] First, a GaN seed was set on the susceptor of the HVPE device. As the GaN seed, a sapphire-based GaN template substrate prepared by MOCVD (organometallic chemical vapor deposition) was used, and the c-plane side was set as the growth plane.

[0232] <Manufacturing of Planar GaN Wafer (Process 2)>

[0233] Next, N2, H2, and NH3 were supplied into the reactor at partial pressures of 0.67 atm, 0.31 atm, and 0.02 atm, respectively, while heating the inside of the reactor by a heater installed on the outside of the reactor.

[0234] After the susceptor temperature reached 1000 ℃, GaN was grown while maintaining the susceptor temperature at a constant. The temperature of the gallium reservoir was set to 900 ℃. During growth, the carrier gas supplied into the reactor consisted of 69 mol% H2 and the remainder N2.

[0235] The partial pressures of GaCl and NH3 are 7.9 × 10⁻⁶, respectively -3 By supplying atm and 0.024 atm into the reactor, a second GaN thick film not containing donor impurities was grown to a thickness of about 2.5 mm. The growth rate of the second GaN thick film calculated from the thickness and growth time was about 40 μm / h.

[0236] Subsequently, this GaN thick film was sliced ​​parallel to the c-plane to obtain a wafer, and the Ga polarity side of the wafer was subjected to planarization by grinding followed by CMP finishing. Slice damage on the N polarity side of the wafer was removed by etching. Additionally, by cutting the wafer, a second c-plane GaN wafer free of donor impurities with a thickness of 400 μm was manufactured. The dislocation density of the obtained wafer was approximately 2 × 10⁻⁶. 6 ~ 4 × 10 6 cm -2 was.

[0237] In addition, by extending the growth time to increase the thickness of the second GaN film, two or more second c-plane GaN wafers can be obtained.

[0238] <Manufacturing of GaN Substrate (Process 3)>

[0239] The above second c-plane GaN wafer was used as a seed, and the c-plane side was set on the susceptor of the HVPE device as the growth plane.

[0240] Next, N2 and NH3 were introduced into the reactor at partial pressures of 0.84 atm and 0.16 atm, respectively, and the inside of the reactor was heated by a heater installed on the outside of the reactor.

[0241] After the temperature of the gallium reservoir reached 900 ℃ and the susceptor temperature reached 1030 ℃, the growth of the GaN crystal was initiated by maintaining the susceptor temperature constant and supplying GaCl and NH3 at partial pressures of 0.013 atm and 0.16 atm, respectively. The carrier gas supplied during growth was N2 only.

[0242] Fe doping involves 9.4 × 10⁻⁶ HCl 1 minute after the onset of growth. -4The process was initiated by flowing metallic Fe into a dopant introduction tube equipped with atm. A GaN film doped with Fe as a donor impurity was grown to a thickness of approximately 0.4 mm. The growth rate of the Fe-doped GaN crystal layer was 1.6 μm / min.

[0243] The entire surface of the GaN film was observed using a differential interference microscope, and it was confirmed that no surface defects, such as pits or cracks, were occurring.

[0244] If a GaN film is grown to about 0.8 mm under the same growth conditions as above, pits may occur on the crystal surface due to the influence of irregular falling debris caused by the degradation of the device components. Since the crystal planes constituting the pits introduce donor impurities that exhibit conductivity, such as oxygen or silicon, at high concentrations, a problem may arise where points with different resistivity occur on the crystal surface. In addition, doping with a high concentration of compensation impurities tends to generate stress in the GaN film, and this becomes more pronounced as the growth thickness increases. Stress accumulated in the GaN film can cause defects such as dislocations or cracks. In this embodiment, it is believed that the main achievement was limiting the growth thickness of the GaN film (Fe-doped GaN crystal layer) to about 0.4 mm. When the growth thickness is increased, defects such as dislocations or cracks can be suppressed by taking countermeasures such as lowering the doping concentration of compensation impurities, improving the device, or improving manufacturing conditions.

[0245] The surface of the GaN film grown to a thickness of about 0.4 mm was not sliced, and the surface (side of the GaN film) and the back surface (side of the second c-sided GaN wafer) were finished by grinding and polishing, respectively, to produce an Fe-doped GaN substrate wafer with a total thickness of 400 μm and a diameter of about 50 mm.

[0246] The obtained GaN substrate wafer is a two-layer substrate having a regrowth interface, a first region with a thickness of 100 μm on the N polarity side (equivalent to a second c-sided GaN wafer), and a second region with a thickness of 300 μm on the Ga polarity side (equivalent to a GaN film).

[0247] As a result of measuring the impurity concentration of the fabricated Fe-doped GaN substrate wafer by SIMS, Fe was 6.4 × 10⁻⁶ 18 atoms / cm³, Si is 1.9 × 10⁻⁶ 16 atoms / cm³, O is 2.0 × 10 16 atoms / cm³, C is 7.1 × 10⁻⁶ 15 It was atoms / cm³.

[0248] Five appropriate points were selected from the surface of the fabricated Fe-doped GaN substrate, and the dislocation density at each point was calculated from the number of blind spots observed in a 100 µm × 100 µm square region using cathode luminescence, resulting in approximately 2 × 10⁻⁶ 6 ~ 3 × 10 6 cm -2 As such, it was equivalent to the dislocation density of the single-crystal GaN (0001) substrate used as a seed.

[0249] Evaluation of resistivity by the double-ring method

[0250] As a result of measuring the resistivity of the fabricated Fe-doped GaN substrate by the double-ring method, the room temperature resistivity was 7 × 10⁻⁶ 11 It was Ω㎝.

[0251] Although the present invention has been described above based on specific embodiments, each embodiment is presented as an example and does not limit the scope of the invention. Each embodiment described herein may be modified in various ways without departing from the spirit of the invention, and may also be combined with features described by other embodiments within the scope of feasibility. Explanation of the symbols

[0252] 1 : Seed wafer 2: 1st GaN Thick Film 3: 1st c-plane GaN wafer 4: Second GaN Thick Film 5: 2c-plane GaN wafer 6: GaN film 6a: Specific dope region 10: HVPE device 11 : Reactor 12: Gallium reservoir 13: Susceptor 14: 1st Heater 15: 2nd heater 100: GaN substrate wafer 101 : N polar surface 102 : Ga polar surface 103 : Regrowth interface 110: Zone 1 120 : Second Zone 120a : Judoff zone 200 : Epitaxial membrane 210 : Undoffed GaN channel layer 220 : Undoff AlGaN carrier supply layer

Claims

Claim 1 (0001) An oriented GaN substrate wafer having a first region formed on the N polarity side with a regrowth interface in between, and a second region having a minimum thickness formed on the Ga polarity side, wherein the minimum thickness of the second region is 20 μm or more and 200 μm or less, and the total concentration of compensation impurities in at least a part of the second region is 2 × 10 17 GaN substrate wafer with atoms / cm³ or more. Claim 2 A GaN substrate wafer according to claim 1, wherein the first region satisfies one or more conditions selected from (a) to (c) below. (a) Si concentration of 5 × 10 16 (b) O concentration is greater than 3 × 10 atoms / cm³. 16 (c) H concentration is 1 × 10⁻¹⁰ atoms / cm³ or less. 17 It is less than atoms / cm³. Claim 3 A GaN substrate wafer according to claim 1 or 2, wherein in the first region, the total concentration of compensation impurities is lower than the total concentration of donor impurities. Claim 4 In claim 1 or 2, in the first region, the total concentration of the compensation impurity is 1 × 10 17 GaN substrate wafer with less than atoms / cm³. Claim 5 In claim 1 or 2, in the first region, the concentration of impurity elements other than Si, O, and H is independently 5 × 10 15 GaN substrate wafer with atoms / cm³ or less. Claim 6 A GaN substrate wafer according to claim 1 or 2, satisfying any of the following conditions selected from (1) to (3). (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less. (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less. (3) having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less. Claim 7 In claim 1 or 2, the second region has a main pressure region that includes at least a main plane on the Ga polar side, and the total concentration of compensation impurities in the main pressure region is 2 × 10 17 GaN substrate wafer with atoms / cm³ or more. Claim 8 In claim 7, the total concentration of compensation impurities in the above-mentioned Zudoff region is 1 × 10 18 GaN substrate wafer with atoms / cm³ or more. Claim 9 A GaN substrate wafer according to claim 7, wherein, in the main region, the total concentration of compensation impurities is at least twice the total concentration of donor impurities. Claim 10 In claim 7, the above-mentioned mainspring region contains one or more elements selected from carbon and transition metal elements, a GaN substrate wafer. Claim 11 In claim 7, a GaN substrate wafer in which the impurity contained at the highest concentration in the main region is Fe, Mn, or C. Claim 12 A GaN substrate wafer according to claim 7, wherein the main pipe region is a region within a specific length from the main body on the Ga polarity side, and the specific length is 20 μm or more. Claim 13 In claim 7, a GaN substrate wafer in which, in the above-mentioned main-dough region, the variation in the total concentration of compensation impurities along the c-axis direction is within the range of ± 25% from the median value. Claim 14 In claim 12, a GaN substrate wafer having a specific length greater than 50 μm. Claim 15 A GaN substrate wafer according to claim 12, wherein the specific length is 50% or more of the minimum thickness of the second region. Claim 16 In claim 1 or 2, the total concentration of compensation impurities in the second region is 5 × 10 19 GaN substrate wafer with atoms / cm³ or less. Claim 17 delete Claim 18 A GaN substrate wafer according to claim 1 or 2, wherein the main surface of the Ga polarity side is a flat plane. Claim 19 In claim 18, a GaN substrate wafer in which the regrowth interface is inclined with respect to the main surface on the Ga polar side. Claim 20 A GaN substrate wafer according to claim 19, wherein the thickness difference between one end and the other end in the direction in which the regrowth interface in the second region is inclined does not exceed 200 μm. Claim 21 An epitaxial wafer having a GaN substrate wafer described in claim 1 or 2 and a nitride semiconductor layer epitaxially grown on a main surface on the Ga polarity side of the GaN substrate wafer. Claim 22 A method for manufacturing an epitaxial wafer having a process of preparing a GaN substrate wafer as described in claim 1 or 2, and a process of growing a nitride semiconductor layer on a main body on the Ga polarity side of the GaN substrate wafer. Claim 23 A method for manufacturing a nitride semiconductor device comprising: a process for preparing a GaN substrate wafer as described in claim 1 or 2; a process for growing a nitride semiconductor layer on a main body on the Ga polarity side of the GaN substrate wafer to obtain an epitaxial wafer; and a process for removing the first region of the GaN substrate wafer in at least a portion of the epitaxial wafer. Claim 24 The method comprises a second process of obtaining a second c-plane GaN wafer by growing a second GaN thick film oriented (0001) on a substrate using HVPE and then slicing the second GaN thick film, and a third process of obtaining a stacked structure by growing a GaN film oriented (0001) on the second c-plane GaN wafer using HVPE with a thickness greater than 50 μm and less than or equal to 200 μm, wherein the GaN film has a total concentration of compensation impurities of 2 × 10 17 A method for manufacturing a GaN substrate wafer characterized by forming a region with atoms / cm³ or more. Claim 25 A method for manufacturing a GaN substrate wafer having an N polarity-side region and a Ga polarity-side region with a regrowth interface in between, comprising: (i) a first process of growing a first GaN thick film made of unintentionally undoped GaN and oriented (0001) on a seed wafer using HVPE, and processing the first GaN thick film to obtain at least one first c-plane GaN wafer; (ii) a second process of growing a second GaN thick film made of unintentionally undoped GaN and oriented (0001) on the first c-plane GaN wafer obtained in the first process using HVPE, and slicing a second c-plane GaN wafer from the second GaN thick film; and (iii) a GaN film having a thickness greater than 50 μm and less than or equal to 200 μm and oriented (0001), and the second c-plane GaN obtained in the second process A third process for obtaining a stacked structure by growing on a wafer with HVPE, and the GaN film grown in the third process has a total concentration of compensation impurities of 2 × 10 17 A method for manufacturing a GaN substrate wafer characterized by forming a region with atoms / cm³ or more. Claim 26 delete Claim 27 A method for manufacturing a GaN substrate wafer according to claim 25, wherein the GaN substrate wafer satisfies any of the following conditions selected from (1) to (3): (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less. (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less. (3) having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less. Claim 28 In claim 25, the GaN film has a region length in the c-axis direction of 20 μm or more, and the total concentration of compensation impurities within the region is 2 × 10 17 A method for manufacturing a GaN substrate wafer having a specific dope region having atoms / cm³ or more. Claim 29 In claim 28, the total concentration of compensation impurities in the specific dope region is 1 × 10 18 A method for manufacturing a GaN substrate wafer having atoms / cm³ or more. Claim 30 A method for manufacturing a GaN substrate wafer according to claim 28, wherein, in the specific dope region, the total concentration of compensation impurities is at least twice the total concentration of donor impurities. Claim 31 A method for manufacturing a GaN substrate wafer according to claim 28, wherein the variation in the total concentration of compensation impurities within the specific dope region along the c-axis direction is within the range of ± 25% from the median value. Claim 32 A method for manufacturing a GaN substrate wafer according to claim 28, wherein the region length is 50% or more of the thickness of the GaN film. Claim 33 A method for manufacturing a GaN substrate wafer according to claim 28, wherein the length from the bottom of the specific dope region to the interface between the GaN film and the second c-plane GaN wafer is 1 μm or more. Claim 34 A method for manufacturing a GaN substrate wafer according to claim 28, wherein the specific dope region contains one or more elements selected from carbon and transition metal elements. Claim 35 A method for manufacturing a GaN substrate wafer according to claim 28, wherein the impurity contained at the highest concentration in the specific dope region is Fe, Mn, or C. Claim 36 In claim 24 or 25, the total concentration of compensation impurities in the GaN film is 5 × 10 19 A method for manufacturing a GaN substrate wafer having atoms / cm³ or less. Claim 37 A method for manufacturing a GaN substrate wafer according to claim 24 or 25, having a thinning process for thinning the stacked structure after the third process. Claim 38 A method for manufacturing a GaN substrate wafer according to claim 37, wherein the difference in thickness of the GaN film before and after the thinning process is 50 μm or more. Claim 39 A method for manufacturing a GaN substrate wafer according to claim 37, wherein the difference in thickness of the GaN film before and after the thinning process is 200 μm or less. Claim 40 A method for manufacturing a GaN substrate wafer according to claim 37, wherein the offcut orientation of the GaN substrate wafer is different from the offcut orientation of the second c-plane GaN wafer. Claim 41 A method for manufacturing a GaN substrate wafer according to claim 24 or 25, comprising a planarization process in which the main surface of the Ga polarity side of the second c-plane GaN wafer sliced ​​from the second GaN thick film in the second process is planarized before growing the GaN film in the third process, and a harmonization process further harmonized by etching.

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