Multi-gate dielectric for monolithic stacked devices

Abstract

A semiconductor structure comprising a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and reliability of each of the stacked devices.

Description

Background Technology

[0001] The present application relates to semiconductor technology, and more specifically, to a semiconductor structure comprising a plurality of stacked devices having different gate dielectrics designed to improve the performance and reliability of each stacked device.

[0002] For example, stacking of devices such as field effect transistors (FETs) is an attractive architecture for future complementary metal oxide semiconductor (CMOS) scaling and potentially ultimately for scaled technology. Significant area scaling can be achieved by directly stacking devices on top of each other (e.g., pFET on top of nFET, nFET on top of pFET, pFET on top of pFET, or nFET on top of nFET). The technology forming the background of the present invention is disclosed in U.S. Patent Publication No. 2021-0202323 (July 1, 2021).

[0003] A semiconductor structure comprising a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics include an interface dielectric layer and a high-k gate dielectric layer. The difference may be thickness and / or material composition. The different gate dielectrics for the stacked devices are designed to improve performance and reliability for each of the stacked devices. Throughout this application, the term "high-k" refers to a material having a dielectric constant greater than 4.0 when measured in vacuum.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure comprises a first device region comprising a first logic device pair stacked together and having a first threshold voltage. The first logic device pair comprises a first gate region comprising a first interface dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interface dielectric layer, and a first gate electrode located on the first high-k gate dielectric layer. The semiconductor structure of the present disclosure further comprises a second device region comprising a second logic device pair stacked together and having a second threshold voltage different from the first threshold voltage. The second logic device pair comprises a second interface dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interface dielectric layer, and a second gate electrode located on the second high-k gate dielectric layer. In this embodiment, the second high-k gate dielectric layer has a thickness greater than the thickness of the first high-k gate dielectric layer. The structure comprises a third device region comprising an I / O device pair stacked together. The I / O device pair includes a third interface dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interface dielectric layer, and a third gate electrode located on the third high-k gate dielectric layer. In this embodiment, the third thickness of the third interface dielectric layer is greater than the first thickness of the first interface dielectric layer and the second thickness of the second interface dielectric layer.

[0005] In another embodiment of the present disclosure, a semiconductor structure comprises a first device region comprising a first logic device pair stacked together and having a first threshold voltage. The first logic device pair comprises a first gate region comprising a first interface dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interface dielectric layer, and a first gate electrode located on the first high-k gate dielectric layer. The structure further comprises a second device region comprising a second logic device pair stacked together and having a second threshold voltage different from the first threshold voltage. The second logic device pair comprises a second interface dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interface dielectric layer, and a second gate electrode located on the second high-k gate dielectric layer. The structure comprises a third device region comprising an I / O device pair stacked together. The I / O device pair comprises a third interface dielectric layer having a third thickness, a third high-k gate dielectric layer positioned on the third interface dielectric layer, and a third gate electrode positioned on the third high-k gate dielectric layer. According to this embodiment of the application, the third thickness of the third interface dielectric layer is greater than the first thickness of the first interface dielectric layer and the second thickness of the second interface dielectric layer, and at least one of the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer is composed of a compositionally different high-k gate dielectric material. Brief explanation of the drawing

[0006] FIG. 1 is a top-down drawing of a device layout that may be employed in the present application, and the device layout includes a plurality of gate structures (GS1, GS2 and GS3) oriented parallel to each other and perpendicular to an active region (AA), and the illustrated device layout includes a cutting portion XX. FIGS. 2a, 2b, and 2c are cross-sectional views of different device regions of an exemplary semiconductor structure that may be employed in the present application, namely a first device region (illustrated in FIG. 2a), a second device region (illustrated in FIG. 2b), and a third device region (illustrated in FIG. 2c), wherein each of the exemplary structures D1, D2, and D3 comprises a second nanosheet material stack positioned on top of a first nanosheet material stack, and a sacrificial gate structure positioned on the stacked first and second nanosheet material stacks, wherein each first nanosheet material stack comprises alternating first sacrificial semiconductor material nanosheets and first semiconductor channel material nanosheets, and each second nanosheet material stack comprises alternating second sacrificial semiconductor material nanosheets and second semiconductor channel material nanosheets. FIGS. 3a, FIGS. 3b, and FIGS. 3c are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 2a, FIGS. 2b, and FIGS. 2c, respectively, after the formation of a first block mask in D2 and D3 and nanosheet device processing in D1, wherein the nanosheet device processing in D1 includes exposing stacked first and second nanosheet material stacks, removing each second sacrificial semiconductor material nanosheet and each first sacrificial semiconductor material nanosheet, forming a first high-k gate dielectric layer, and forming a first gate replacement layer. FIGS. 4a, FIGS. 4b, and FIGS. 4c are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 3a, FIGS. 3b, and FIGS. 3c, respectively, after performing a first planarization process in D1, D2, and D3 to remove the first gate replacement layer and the first high-k gate dielectric layer from D2 and D3. FIGS. 5a, FIGS. 5b, and FIGS. 5c are cross-sectional views of the exemplary semiconductor structure illustrated in FIGS. 4a, FIGS. 4b, and FIGS. 4c, respectively, after the formation of a second block mask in D1 and D3, the removal of a first block mask from D2, and nanosheet device processing in D2, wherein the nanosheet device processing in D2 includes exposing stacked first and second nanosheet material stacks, and removing each second sacrificial semiconductor material nanosheet and each first sacrificial semiconductor material nanosheet to form an opening in D2. FIGS. 6a, FIGS. 6b, and FIGS. 6c are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 5a, FIGS. 5b, and FIGS. 5c, respectively, after the removal of the second block mask in D1 and D3 and additional nanosheet device processing in D2, wherein the additional nanosheet device processing in D2 includes forming a second high-k gate dielectric layer and forming a second gate replacement layer. FIGS. 7a, FIGS. 7b, and FIGS. 7c are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 6a, FIGS. 6b, and FIGS. 6c, respectively, after performing a second planarization process in D1, D2, and D3 to remove the second gate replacement layer and the second high-k gate dielectric layer from D1 and D3. FIGS. 8a, FIGS. 8b, and FIGS. 8c are cross-sectional views of the exemplary semiconductor structure illustrated in FIGS. 7a, FIGS. 7b, and FIGS. 7c, respectively, after forming a third block mask in D1 and D2. FIGS. 9a, FIGS. 9b, and FIGS. 9c are cross-sectional views of the exemplary semiconductor structure illustrated in FIGS. 8a, FIGS. 8b, and FIGS. 8c, respectively, after the removal of the first block mask from D3 and the nanosheet device processing in D3, wherein the nanosheet device processing in D3 includes exposing the stacked first and second nanosheet material stacks and removing each of the second sacrificial semiconductor material nanosheets and each of the first sacrificial semiconductor material nanosheets to form an opening in D3. FIGS. 10a, FIGS. 10b, and FIGS. 10c are cross-sectional views of the exemplary semiconductor structure illustrated in FIGS. 9a, FIGS. 9b, and FIGS. 9c, respectively, after the removal of the third block mask in D1 and D2 and additional nanosheet device processing in D3, wherein the additional nanosheet device processing in D3 includes physically thinning the exposed portions of the first semiconductor channel material nanosheet and the second semiconductor channel material, forming a third interface dielectric layer and a third high-k gate dielectric layer, forming a third gate replacement layer, and performing a third planarization process in D1, D2, and D3 to remove the third gate replacement layer and the third high-k gate dielectric layer from D1 and D2. FIGS. 11a, FIGS. 11b, and FIGS. 11c are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 10a, FIGS. 10b, and FIGS. 10c, respectively, after removing the first gate replacement layer from D1, the second gate replacement layer from D2, and the third gate replacement layer from D3. FIGS. 12a, FIGS. 12b, and FIGS. 12c are cross-sectional views of the exemplary semiconductor structure illustrated in FIGS. 11a, FIGS. 11b, and FIGS. 11c, respectively, after forming a first gate electrode at D1, a second gate electrode at D2, and a third gate electrode at D3. FIGS. 13a, FIGS. 13b, and FIGS. 13c are cross-sectional views showing portions of the gate regions present in D1, D2, and D3, respectively. Specific details for implementing the invention

[0007] The present application will now be described in more detail by reference to the following discussion and drawings accompanying this application. It should be noted that the drawings of this application are provided for illustrative purposes only and, accordingly, are not drawn to scale. It should also be noted that identical elements and corresponding elements are referred to by the same reference numerals.

[0008] In the following description, numerous specific details, such as specific structures, components, materials, dimensions, processing steps, and techniques, are described to provide an understanding of the various embodiments of the present application. However, it will be recognized by those skilled in the art that the various embodiments of the present application may be practiced without these specific details. In other cases, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0009] When an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, it will be understood that the element may be directly on the other element, or that other elements or intervening elements may exist. In contrast, when an element is referred to as being "directly on" or "directly above" another element, no intervening elements exist. When an element is referred to as being "below" or "under" another element, it will also be understood that it may be directly below or under the other element, or that intervening elements may exist. In contrast, when an element is referred to as being "directly below" or "directly under" another element, no intervening elements exist.

[0010] In today's technology, high-performance computing for servers and low-power computing for mobile devices typically share the same platform to reduce R&D and manufacturing costs.

[0011] Typically, low-power applications for mobile applications are the first to have products within a generation of technology, defining the base for the technology platform. Generally, high-performance computing for server applications is the last product within a generation. However, reliability for high-performance computing for server applications is also the final criterion for verifying this technology. If reliability issues arise in high-performance computing for server applications, developing and modifying processes from scratch—particularly for technologies involving dipoles for threshold voltage (Vt) modulation—is impossible due to the time-consuming and costly nature of the process. A method to address reliability issues is required.

[0012] Specifically, different functional devices require different gate dielectrics due to performance and reliability requirements, such as thin oxide devices, thicker oxide devices (I / O devices), SRAM, high VT devices, or low VT devices. Methods for providing different gate dielectrics are important for having competitive technology for stacked devices.

[0013] In one embodiment of the present application (i.e., the first embodiment), the semiconductor structure comprises a first device region (D1) comprising a first logic device pair stacked together and having a first threshold voltage (see FIG. 12a). The first logic device pair comprises a first gate region (see FIG. 13a) comprising a first interface dielectric layer (IL-1) having a first thickness, a first high-k gate dielectric layer (40L) located on the first interface dielectric layer (IL-1), and a first gate electrode (64A) located on the first high-k gate dielectric layer (40L). The semiconductor structure of the present disclosure further comprises a second device region (D2) comprising a second logic device pair stacked together and having a second threshold voltage different from the first threshold voltage (see FIG. 12b). The second logic device pair comprises a second interface dielectric layer (IL-2) having a second thickness, a second high-k gate dielectric layer (48L) located on the second interface dielectric layer (IL-2), and a second gate electrode (64B) located on the second high-k gate dielectric layer (48L). In this first embodiment, the second high-k gate dielectric layer (48L) has a thickness greater than that of the first high-k gate dielectric layer (40L). The structure further comprises a third device region (D3) comprising an I / O device pair stacked on top of each other (see FIG. 12c). The I / O device pair comprises a third interface dielectric layer (55) having a third thickness, a third high-k gate dielectric layer (56L) located on the third interface dielectric layer (55), and a third gate electrode (46C) located on the third high-k gate dielectric layer (56L) (see FIG. 12c and FIG. 13c). In this first embodiment, the third thickness of the third interface dielectric layer (55) is greater than the first thickness of the first interface dielectric layer (IL-1) and the second thickness of the second interface dielectric layer (IL-2). Due to different applications, purposes, or functions, the reliability requirements of the device are different.I / O devices require a thick interfacial dielectric layer to have a breakdown voltage sufficient to suppress time-dependent gate oxide breakdown. For logic devices, devices with different threshold voltages require different breakdown voltages and negative or positive bias temperature instability. Therefore, by optimizing the gate stack dielectric to eliminate reliability limitations, overall device performance can be further optimized and circuit performance improved.

[0014] In another embodiment (i.e., a second embodiment) and as illustrated in FIGS. 12a through 13c, the semiconductor structure comprises a first device region (D1) comprising a first logic device pair stacked on top of each other and having a first threshold voltage. The first logic device pair comprises a first gate region comprising a first interface dielectric layer (IL-1) having a first thickness, a first high-k gate dielectric layer (40L) located on the first interface dielectric layer (IL-1), and a first gate electrode (64A) located on the first high-k gate dielectric layer (40L). The structure further comprises a second device region (D2) comprising a second logic device pair stacked on top of each other and having a second threshold voltage different from the first threshold voltage. The second logic device pair comprises a second interface dielectric layer (IL-2) having a second thickness, a second high-k gate dielectric layer (48L) located on the second interface dielectric layer (IL-2), and a second gate electrode (64B) located on the second high-k gate dielectric layer (48L). The structure comprises a third device region (D3) comprising an I / O device pair stacked on top of each other. The I / O device pair comprises a third interface dielectric layer (55) having a third thickness, a third high-k gate dielectric layer (56L) located on the third interface dielectric layer (55), and a third gate electrode (64C) located on the third high-k gate dielectric layer (56L). According to this second embodiment of the present application, the third thickness of the third interface dielectric layer (55) is greater than the first thickness of the first interface dielectric layer (IL-1) and the second thickness of the second interface dielectric layer (IL-2), and at least one of the first high-k gate dielectric layer (40L), the second high-k gate dielectric layer (48L), and the third high-k gate dielectric layer (56L) is composed of a high-k gate dielectric material that is compositionally different.Thicker interface layers can provide better breakdown voltage, but they can have a significantly greater impact on device performance than high-k material thickness. However, high-k thickness can cause significant negative or positive bias temperature instability. Therefore, the method of balancing device performance using interface dielectric layer thickness and high-k thickness is based on device function.

[0015] In some embodiments (applicable to both the first and second embodiments mentioned above) and as illustrated in FIG. 12a, the first logic device pair comprises a first nanosheet stack comprising at least one second semiconductor channel material nanosheet (20) positioned on at least one first semiconductor channel material nanosheet (14). In such an embodiment, the first interface dielectric layer (IL-1) illustrated in FIG. 13a wraps around a portion of the at least one second semiconductor channel material nanosheet (20) and a portion of the at least one first semiconductor material nanosheet (14) of the first nanosheet stack. Additionally, as illustrated in FIG. 12b, the second logic device pair comprises a second nanosheet stack comprising at least one second semiconductor channel material nanosheet (20) positioned on at least one first semiconductor channel material nanosheet (14). In such an embodiment, the second interface dielectric layer (IL-2) shown in FIG. 13b surrounds the perimeter of at least one portion of the second semiconductor channel material nanosheet (20) and at least one portion of the first semiconductor material nanosheet (14) of the second nanosheet stack. Additionally, as shown in FIG. 12c, the I / O device pair comprises a third nanosheet stack comprising at least one second semiconductor channel material nanosheet (20) positioned on top of at least one first semiconductor channel material nanosheet (14). In such an embodiment, and as shown in FIG. 12c, the third interface dielectric layer (55) surrounds the perimeter of at least one portion of the second semiconductor channel material nanosheet (20) and at least one portion of the first semiconductor material nanosheet (14) of the third nanosheet stack. In the present application, each nanosheet stack is derived from a second nanosheet material stack stacked on top of a first nanosheet material stack.Nanosheet gate-all-around (GAA) devices utilize Extreme Ultraviolet Lithography (EUV) to provide a larger effective device width (Weff) per active footprint and superior performance compared to FinFETs, using less complex photolithography strategies. Unlike FinFETs, where the gate wraps around only three sides, GAA devices offer better power performance design points due to superior electrostatic control where the gate wraps around the channel on all sides. Therefore, in next-generation technology, nanosheets must serve as the foundational device structure for stacked transistors.

[0016] In some embodiments (applicable to both the first and second embodiments mentioned above) and as illustrated in FIGS. 12a, 12b, and 12c, the structure may further include an intermediate dielectric insulating layer (16) positioned between at least one first semiconductor channel material nanosheet (14) and at least one second semiconductor channel material nanosheet (20) in each of the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The intermediate dielectric insulating layer (16) electrically separates each pair of stacked devices from each other.

[0017] In some embodiments (applicable to both the first and second embodiments mentioned above) and as illustrated in FIG. 12c, at least one first semiconductor material channel material nanosheet (14) and at least one second semiconductor channel material nanosheet (20) of the third nanosheet stack are dumbbell-shaped, having a middle portion of a first thickness and an end portion of a second thickness greater than the first thickness of the middle portion, and a third interfacial dielectric layer (55) wraps around the middle portion. These embodiments provide a semiconductor channel material nanosheet with a larger surface area.

[0018] In an embodiment (applicable to both the first and second embodiments mentioned above), the first device region (D1), the second device region (D2), and the third device region (D3) each exist on the same semiconductor substrate, i.e., the semiconductor substrate (10). This enables monolithic device stacking.

[0019] In some embodiments of the present application (applicable to both the first and second embodiments mentioned above), the first gate electrode (64A), the second gate electrode (64B), and the third gate electrode (64C) are composed of the same gate electrode material in composition. In other embodiments of the present application (applicable to both the first and second embodiments mentioned above), at least one of the first gate electrode (64A), the second gate electrode (64B), and the third gate electrode (64C) is composed of a gate electrode material that is different in composition. These embodiments exemplify the flexibility of the present application.

[0020] In some embodiments of the present application (applicable to the first embodiment mentioned above), the first high-k gate dielectric layer (40L), the second high-k gate dielectric layer (48L), and the third high-k gate dielectric layer (56L) are composed of the same high-k gate dielectric material. In other embodiments of the present application (applicable to the first embodiment mentioned above), at least one of the first high-k gate dielectric layer (40L), the second high-k gate dielectric layer (48L), and the third high-k gate dielectric layer (56L) is composed of a high-k gate dielectric material that is different in composition. These embodiments exemplify the flexibility of the present application.

[0021] In some embodiments (applicable to both the first and second embodiments mentioned above), each logic device of the first logic device pair is of a different conductivity type (p-type or n-type), each logic device of the second logic device pair is of a different conductivity type, and each I / O device of the I / O device pair is of a different conductivity type. This demonstrates the flexibility of the present application.

[0022] In some embodiments (applicable to both the first and second embodiments mentioned above), the first high-k gate dielectric layer (40L), the second high-k gate dielectric layer (48L), and the third high-k gate dielectric layer (56L) are each composed of compositionally different high-k gate dielectric materials. This demonstrates the flexibility of the present application.

[0023] Now, referring to FIG. 1, a device layout that may be employed in the present application is illustrated. The device layout includes a plurality of gate structures, namely GS1, GS2, and GS3, oriented parallel to each other and perpendicular to an active region (AA); the illustrated device layout includes a cut portion XX. The cut portion XX penetrates the longitudinal direction of the active region, and the XX cut portion penetrates each of GS1, GS2, and GS3. The illustrated device layout further includes a first device region (D1) where a first type of stacked device is subsequently formed, a second device region (D2) where a second type of stacked device is subsequently formed, and a third device region (D3) where a first type of stacked device is subsequently formed.

[0024] In the present application, D1 is a device region where a first logic device pair having a first threshold voltage (Vt1) is formed, D2 is a device region where a second logic device pair having a second threshold voltage (Vt2) is formed, Vt2 is different from Vt1, and D3 is a device region where a pair of input / output (I / O) devices is formed. In D1 and D2, the logic device pairs are stacked on top of each other, and in D3, the I / O device pairs are stacked on top of each other. These different device regions require different gate dielectrics due to performance and reliability requirements.

[0025] In this application, logic devices and I / O devices are described and illustrated as stacked nanosheet transistors. The transistor comprises a source region, a drain region, a semiconductor channel region located between the source region and the drain region, and a gate electrode located above the semiconductor channel region. The nanosheet transistor is a non-planar transistor comprising a vertical stack of spaced semiconductor channel material nanosheets, and a semiconductor channel region having a pair of source / drain regions located at each end of the vertical stack of spaced semiconductor channel material nanosheets. A gate structure (referred to herein as a gate region) comprising a gate dielectric and a gate electrode surrounds the perimeter of each spaced semiconductor channel material nanosheet. The stacked nanosheet transistor is a transistor comprising a first vertical stack of spaced first semiconductor channel material nanosheets and a second vertical stack of spaced second semiconductor channel material nanosheets stacked on top of the first vertical stack. Although stacked nanosheet transistors are described and exemplified, the present application may be used with stacked planar transistors, or other non-planar transistors, such as, for example, stacked semiconductor nanowire transistors or stacked finFET transistors. Any combination of these types of stacked devices may be used.

[0026] Now, referring to FIGS. 2a, 2b, and 2c, an exemplary semiconductor structure that may be employed in the present application is illustrated. The exemplary semiconductor structure exists in D1, D2, and D3, respectively. Although the device regions (D1, D2, and D3) are illustrated in separate drawings, D1, D2, and D3 will exist adjacent to each other (in any order) on the same semiconductor substrate (10). Within D1, D2, and D3, the exemplary semiconductor structure comprises a second nanosheet material stack positioned above a first nanosheet material stack. Each first nanosheet material stack comprises alternating first sacrificial semiconductor material nanosheets (12) and first semiconductor channel material nanosheets (14). Each second nanosheet material stack comprises alternating second sacrificial semiconductor material nanosheets (18) and second semiconductor channel material nanosheets (20). As illustrated, an intermediate dielectric isolation layer (16) separates the first nanosheet material stack from the second nanosheet material stack.

[0027] The illustrated exemplary structure further includes a sacrificial gate structure located in each of the stacked first and second nanosheet material stacks. Each sacrificial gate structure may include a sacrificial gate dielectric layer (22) and a sacrificial gate layer (24). In some embodiments, the sacrificial gate dielectric layer (22) is optional.

[0028] In some embodiments and as illustrated in FIGS. 2a through 2c, a sacrificial gate cap (26) may be located on each sacrificial gate structure. In other embodiments, the sacrificial gate cap (26) may be omitted. If present, the sacrificial gate cap (26) is located on the uppermost surface of the sacrificial gate layer (24).

[0029] Within each of D1, D2, and D3, the exemplary semiconductor structure may also include a gate spacer (28), an internal spacer (30), a first source / drain region (32), a second source / drain region (34), and an interlayer dielectric (ILD) layer (36). The gate spacer (28) is positioned along the sidewall of the sacrificial gate structure and, if present, along the sacrificial gate cap (26). The internal spacer (30) is positioned at the end of each second sacrificial semiconductor material nanosheet (18), the end of the intermediate dielectric insulating layer (16), and the end of each first sacrificial semiconductor material nanosheet (12). The first source / drain region (32) extends from the respective sidewall of each first semiconductor channel material nanosheet (14). The second source / drain region (34) extends from the respective sidewall of each second semiconductor channel material nanosheet (20). The first source / drain region (32) is separated from the second source / drain region (34) by a dielectric material (in the illustrated embodiment, the dielectric material is illustrated as part of the ILD layer (36)). The ILD layer (36) includes the first source / drain region (32) and the second source / drain region (34).

[0030] A semiconductor substrate (10) comprises at least one semiconductor material. The term “semiconductor material” is used throughout this application to denote a material having semiconductor properties. Examples of semiconductor materials that may be used to provide the first semiconductor material and the second semiconductor material in this application include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductor, or II / VI compound semiconductor. In some embodiments, the semiconductor substrate (10) is a bulk semiconductor substrate comprising a single semiconductor material, e.g., Si. In other embodiments, the semiconductor substrate (10) is composed of a plurality of semiconductor material layers, e.g., Si / SiGe. In yet another embodiment, the semiconductor substrate (10) is a semiconductor-on-insulator (SOI) substrate comprising, from bottom to top, a material stack of a lower semiconductor layer, an embedded dielectric layer (silicon dioxide and / or boron nitride), and an upper semiconductor layer. An example of an SOI substrate is one comprising Si / silicon dioxide / Si.

[0031] As described above, each first nanosheet material stack includes alternating first sacrificial semiconductor material nanosheets (12) and first semiconductor channel material nanosheets (14).

[0032] In some embodiments and as illustrated in FIGS. 2a through 2c, each first semiconductor channel material nanosheet (14) is sandwiched between a lower first sacrificial semiconductor material nanosheet and an upper first sacrificial semiconductor material nanosheet. In such embodiments, "n+1" first sacrificial semiconductor material nanosheets (12) and "n" first semiconductor channel material nanosheets (14) exist together with each first nanosheet material stack, where n is an integer starting from 1. As one example, each first nanosheet material stack comprises three first sacrificial semiconductor material nanosheets (12) and two first semiconductor channel material nanosheets (14).

[0033] Each first sacrificial semiconductor material nanosheet (12) is composed of a first semiconductor material, whereas each first semiconductor channel material nanosheet (14) is composed of a second semiconductor material that is compositionally different from the first semiconductor material. In some embodiments, the second semiconductor material providing each first semiconductor channel material nanosheet (14) can provide high channel mobility for an n-type field effect transistor (FET) device. In other embodiments, the second semiconductor material providing each first semiconductor channel material nanosheet (14) can provide high channel mobility for a p-type FET device. The first semiconductor material providing each first sacrificial semiconductor material nanosheet (12) and the second semiconductor material providing each first semiconductor channel material nanosheet (14) may include one of the semiconductor materials described above for a semiconductor substrate (10). In one example, each first sacrificial semiconductor material nanosheet (12) is composed of a silicon germanium alloy having a germanium content of 20 atomic percent to 40 atomic percent, and each first semiconductor channel material nanosheet (14) is composed of silicon.

[0034] Each first sacrificial semiconductor material nanosheet (12) may have a first thickness, and each first semiconductor channel material nanosheet (14) may have a second thickness. In the present application, the first thickness may be equal to, greater than, or less than the second thickness. As illustrated in FIGS. 2a through 2c, each first sacrificial semiconductor material nanosheet (12) has a reduced length compared to the length of each first semiconductor channel material nanosheet (14).

[0035] As described above, each second nanosheet material stack comprises alternating second sacrificial semiconductor material nanosheets (18) and second semiconductor channel material nanosheets (20). In some embodiments, and as illustrated in FIGS. 2a through 2c, an equal number of second semiconductor channel material nanosheets (20) and second sacrificial semiconductor material nanosheets (18) exist. In such embodiments, "x" second sacrificial semiconductor material nanosheets (18) and "x" second semiconductor channel material nanosheets (20) exist together with each first nanosheet material stack, where x is an integer starting from 1. As one example, each second nanosheet material stack comprises two second sacrificial semiconductor material nanosheets (18) and two second semiconductor channel material nanosheets (20).

[0036] Each second sacrificial semiconductor material nanosheet (18) is composed of a third semiconductor material, whereas each second semiconductor channel material nanosheet (20) is composed of a fourth semiconductor material that is compositionally different from the third semiconductor material. In the present application, the third semiconductor material providing each second sacrificial semiconductor material nanosheet (18) is typically compositionally identical to the first semiconductor material providing each first sacrificial semiconductor material nanosheet (12). In the present application, the fourth semiconductor material providing each second semiconductor channel material nanosheet (20) may be compositionally identical to or compositionally different from the second semiconductor material providing each first semiconductor channel material nanosheet (14). In some embodiments, the second semiconductor material providing each first semiconductor channel material nanosheet (14) may provide high channel mobility for an n-type field-effect transistor (FET) device, while the fourth semiconductor material providing each second semiconductor channel material nanosheet (20) may provide high channel mobility for a p-type FET device. In some embodiments, the fourth semiconductor material providing each second semiconductor channel material nanosheet (20) may provide high channel mobility for an n-type field-effect transistor (FET) device, whereas the second semiconductor material providing each first semiconductor channel material nanosheet (14) may provide high channel mobility for a p-type FET device. The third semiconductor material and the fourth semiconductor material may include one of the semiconductor materials described above for the semiconductor substrate (10). In one exemplary embodiment, each first sacrificial semiconductor material nanosheet (12) and each second sacrificial semiconductor material nanosheet (18) are composed of a silicon germanium alloy having a germanium content of 20 atomic percent to 40 atomic percent, each first semiconductor channel material nanosheet (14) is composed of silicon, and each second semiconductor channel material nanosheet (20) is composed of Ge.

[0037] Each second sacrificial semiconductor material nanosheet (18) may have a third thickness, and each second semiconductor channel material nanosheet (20) may have a fourth thickness. In the present application, the third thickness may be equal to, greater than, or less than the fourth thickness. As illustrated in FIGS. 2a through 2c, each second sacrificial semiconductor material nanosheet (18) has a reduced length compared to the length of each second semiconductor channel material nanosheet (20).

[0038] The intermediate dielectric isolation layer (16), the gate spacer (28), and the inner spacer (30) may be composed of a dielectric spacer material including, but not limited to, silicon dioxide, SiN, SiBCN, SiOCN, or SIOC. The intermediate dielectric isolation layer (16) and the gate spacer (28) are generally composed of the same dielectric spacer material in composition, as both the intermediate dielectric isolation layer (16) and the gate spacer (28) are typically formed simultaneously. The inner spacer (30) may be in composition identical to or different from the intermediate dielectric isolation layer (16) and the gate spacer (28).

[0039] The optional sacrificial gate dielectric layer (22) of the sacrificial gate structure comprises a sacrificial gate dielectric material, for example, silicon dioxide. The sacrificial gate layer (24) of the sacrificial gate structure is a sacrificial gate material, for example, polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium.

[0040] A sacrifice gate cap (26) located on the sacrifice gate layer (24) is composed of a hard mask material, such as silicon nitride, for example. Again, and in some embodiments, the sacrifice gate cap (26) may be omitted from the top of the sacrifice gate structure.

[0041] Each first source / drain region (32) is composed of a fifth semiconductor material and a first dopant. Each second source / drain region (34) is composed of a sixth semiconductor material and a second dopant. As used herein, the “source / drain” region may be a source region or a drain region depending on the application of voltage and subsequent wiring during the operation of the transistor. The first semiconductor and the sixth semiconductor material may be compositionally identical or compositionally different semiconductor materials. In this application, the fifth semiconductor material providing each first source / drain region (32) may be compositionally identical or compositionally different from the second semiconductor material providing each first semiconductor channel material nanosheet (14). In this application, the sixth semiconductor material providing each second source / drain region (34) may be compositionally identical or compositionally different from the fourth semiconductor material providing each second semiconductor channel material nanosheet (20). The first dopant present in each first source / drain region (32) and the second dopant present in each second source / drain region (34) may be p-type dopants or n-type dopants. In some embodiments, the first dopant is of the same conductivity type as the second dopant. In other embodiments, the first dopant is of a different conductivity type. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates defects in valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium, phosphorus, and indium. "n-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon containing semiconductor materials, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic, and phosphorus. In one example, each of the first and second source / drain regions (32, 34) is 4x10 20 atoms / cm 3 Up to 3x10 21 atoms / cm3 It can have a dopant concentration of

[0042] The first source / drain region (32) and the second source / drain region (34) are typically formed by an epitaxial growth process. Throughout this application, the terms “epitaxially grow” or “epitaxially growing” refer to the growth of a semiconductor material on a growth surface of another semiconductor material such that the semiconductor material being grown has the same crystalline characteristics as the growth surface of the other semiconductor material. In an epitaxial deposition process, chemical reactants provided by a source gas are controlled, and system parameters are set so that the depositing atoms reach the growth surface of another semiconductor substrate with sufficient energy to move onto the growth surface and orient themselves into the crystalline arrangement of atoms on the growth surface. Examples of various epitaxial growth process devices that may be employed in this application include, for instance, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The epitaxial deposition temperature is generally within the range of 550°C to 900°C. While higher temperatures accelerate deposition, faster deposition can lead to crystal defects and film cracking.

[0043] The ILD layer (36) is composed of a dielectric material comprising, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term “low-k” as used throughout this application refers to a material having a dielectric constant of less than 4.0 (all dielectric constants mentioned herein are for vacuum unless otherwise noted).

[0044] The semiconductor structures illustrated in FIGS. 2a through 2c can be formed using a conventional stacked nanosheet device process comprising various deposition, patterning, and planarization steps. The various deposition steps may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxial deposition as defined above, and / or spin-on coating. The patterning step may include lithography and etching. Etching may include a dry etching process (e.g., reactive etching (RIE), ion beam etching (IBE), or plasma etching) and / or a chemical wet etching process. Planarization may include chemical mechanical polishing (CMP) and / or polishing. To avoid obscuring the method of the present application, the processing details used to form the exemplary structures illustrated in FIGS. 2a to 2c are omitted.

[0045] Now, referring to FIGS. 3A, 3B, and 3C, an exemplary semiconductor structure illustrated in FIGS. 2A, 2B, and 2C, respectively, is shown after the formation of the first block mask (38) in D2 and D3 and the nanosheet device processing in D1, wherein the nanosheet device processing in D1 includes exposing stacked first and second nanosheet material stacks, removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12), forming a first high-k gate dielectric layer (40L), and forming a first gate replacement layer (42). The first block mask (38) is composed of any block mask material, for example, an organic planarization layer (OPL). The first block mask (38) may be formed by depositing a blanket layer of the block mask material on D1, D2, and D3, respectively. Deposition of the blanket layer of the block mask material may include, but is not limited to, CVD, PECVD, or PVD. The blanket layer of the block mask material is subsequently removed from D1 by lithography and etching, and the block mask material is retained in D2 and D3. The retained block mask material in D2 and D3 is the first block mask (38). In one example, the etching includes RIE.

[0046] The first block mask (38) is used to protect D2 and D3 during nanosheet device processing in D1. Nanosheet device processing in D1 first involves exposing the stacked first and second nanosheet material stacks present in D1. Exposing the stacked first and second nanosheet material stacks present in D1 involves removing the sacrificial gate cap (26), if present, and the sacrificial gate structure (including an optional sacrificial gate dielectric layer (22) and a sacrificial gate layer (24)). The removal process includes one or more etching processes. One or more etching processes may include RIE.

[0047] Removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12) from D1 includes an optional optional material removal process (e.g., etching) or a combination of removal processes (a combination of two etching processes) for removing the first sacrificial semiconductor material nanosheet (12) and the second sacrificial semiconductor material nanosheet (18). These removal steps suspend portions of each first semiconductor channel material nanosheet (14) and each second semiconductor channel material nanosheet (20) present in D1.

[0048] Before forming the first high-k gate dielectric layer (40L), a first interfacial dielectric layer (not specifically illustrated in FIG. 3a for clarity, but referenced in FIG. 13a) is formed around each of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material nanosheet (20) and on the top surface of the semiconductor substrate (10) in D1. The first interfacial dielectric layer of D1 will be constructed in the same manner as the third interfacial dielectric layer (55) illustrated in D3 (e.g., refer to FIG. 12c). The first interfacial dielectric layer is composed of at least one semiconductor oxide, such as silicon oxide. The semiconductor oxide of the first interfacial dielectric layer will match the semiconductor material formed thereon. The first interfacial dielectric layer of D1 has a first thickness. The first interfacial dielectric layer can be formed by a thermal oxidation process. In FIG. 13a, the first interfacial layer (IL-1) is illustrated.

[0049] The first high-k gate dielectric layer (40L) is subsequently formed on D1, D2, and D3, respectively. In D1, the first high-k gate dielectric layer (40L) is formed on and around the first interface dielectric layer located on the respective suspended first and second semiconductor channel material nanosheets (14, 20) and on the intermediate dielectric isolation layer (16). In D1, the first high-k gate dielectric layer (40L) is also formed along the inner sidewall of the inner spacer (30), along the top surface of the semiconductor substrate (10), and on the gate spacer (28) and ILD layer (36). In D2 and D3, the first high-k gate dielectric layer (40L) is formed on the top of the first block mask (38).

[0050] The first high-k gate dielectric layer (40L) is a first high-k gate dielectric material. The high-k gate dielectric material has a dielectric constant greater than 4.0. Exemplary examples of the first high-k gate dielectric material include hafnium dioxide (HFO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrCO4), and zirconium silicon oxynitride (ZrSiO2). x N y ), tantalum oxide (TaO x The first high-k gate dielectric material comprises, but is not limited to, titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobite (Pb(Zn,Nb)O). The first high-k gate dielectric material may further comprise dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0051] The first high-k gate dielectric layer (40L) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD. The first high-k gate dielectric layer (40L) may have a first high-k gate dielectric thickness.

[0052] The first gate replacement layer (42) is subsequently formed in each of D1, D2, and D3. In each of D1, D2, and D3, the first gate replacement layer (42) is formed on the surface of the first high-k gate dielectric layer (40L). It should be noted that within D1, the first gate replacement layer (42) fills the gap between the respective suspended first and second semiconductor channel material nanosheets (14, 20) and between the suspended intermediate dielectric insulating layer (16). The first gate replacement layer (42) may include one of the sacrificial gate materials described above for the sacrificial gate layer (24) of the sacrificial gate structure. The first gate replacement layer (42) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD.

[0053] Now, referring to FIGS. 4a, 4b, and 4c, an exemplary semiconductor structure illustrated in FIGS. 3a, 3b, and 3c, respectively, is shown after a first planarization process has been performed in D1, D2, and D3 to remove the first gate replacement layer (42) and the first high-k gate dielectric layer (40L) from D2 and D3. This first planarization process may also remove the upper portion of the first gate replacement layer (42) from D1. The first planarization process may include CMP or polishing. In D2 and D3, the first planarization process reveals a first block mask (38).

[0054] Now, referring to FIGS. 5A, 5B, and 5C, an exemplary semiconductor structure illustrated in FIGS. 4A, 4B, and 4C is shown after the formation of a second block mask (44) in D1 and D3, the removal of a first block mask (38) from D2, and nanosheet device processing in D2, wherein the nanosheet device processing in D2 includes exposing stacked first and second nanosheet materials in D2, and removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12) to form an opening (46) in D2.

[0055] The second block mask (44) comprises one of the block mask materials described above for the first block mask (38). The block mask material providing the second block mask (44) may be compositionally identical or compositionally different from the block mask material providing the first block mask (38). The second block mask (44) may be formed using the same technique described above for forming the first block mask (38). In D1, the second block mask (44) is formed on the first gate replacement layer (42). In D3, the second block mask (44) is formed on the first block mask (38).

[0056] The first block mask (38) is removed from D2 using an optional etching process to remove the first block mask (38) from D2. In some embodiments, the removal of the first block mask (38) from D2 occurs simultaneously with the removal of the blanket layer of the hard mask material from D2, which provides the second block mask (44). In other embodiments, the removal of the first block mask (38) from D2 occurs using a different material removal process, such as etching, which was used to remove the blanket layer of the hard mask material from D2.

[0057] In the absence of a block mask present in D2, nanosheet device processing in D2 first involves exposing the stacked first and second nanosheet material stacks present in D2. Exposing the stacked first and second nanosheet material stacks present in D2 involves removing a sacrificial gate cap (26), if present, and a sacrificial gate structure (including an optional sacrificial gate dielectric layer (22) and a sacrificial gate layer (24)). The removal process includes one or more etching processes. One or more etching processes may include RIE.

[0058] Removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12) from D2 includes an optional optional material removal process (e.g., etching) or a combination of removal processes (a combination of two etching processes) for removing the first sacrificial semiconductor material nanosheet (12) and the second sacrificial semiconductor material nanosheet (18). These removal steps suspend portions of each first semiconductor channel material nanosheet (14) and each second semiconductor channel material nanosheet (20) present in D2 and provide an opening (46) in D2. It should also be noted that the intermediate dielectric isolation layer (16) is suspended during these steps of the present application.

[0059] Now, referring to FIGS. 6a, 6b, and 6c, an exemplary semiconductor structure illustrated in FIGS. 5a, 5b, and 5c is shown after the removal of the second block mask (44) in D1 and D3 and additional nanosheet device processing in D2, wherein the additional nanosheet device processing in D2 includes forming a second high-k gate dielectric layer (48L) and forming a second gate replacement layer (50). The removal of the second block mask (44) in D1 and D3 includes an optional optional material removal process in removing the second block mask (44). In D1, the removal of the second block mask (44) physically exposes the first gate replacement layer (42). In D3, the removal of the second block mask (44) physically exposes the first block mask (38).

[0060] Before forming the second high-k gate dielectric layer (48L), a second interfacial dielectric layer (not specifically illustrated for clarity) is formed around each of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material nanosheet (20) and on the top surface of the semiconductor substrate (10) at D2. The second interfacial dielectric layer at D2 will be constructed in the same manner as the third interfacial dielectric layer (55) shown at D3 (see, for example, FIG. 12c). The second interfacial dielectric layer is composed of at least one semiconductor oxide, such as silicon oxide, for example. The semiconductor oxide of the second interfacial dielectric layer will match the semiconductor material formed thereon. The second interfacial dielectric layer at D2 has a second thickness. In an embodiment of the present application, the second thickness of the second interfacial dielectric layer is greater than the first thickness of the first interfacial dielectric layer. The second interfacial dielectric layer may be formed by a thermal oxidation process. The second interface layer is shown as IL-2 in Fig. 13b.

[0061] A second high-k gate dielectric layer (48L) is subsequently formed in D1, D2, and D3, respectively. In D1, the second high-k dielectric layer (48L) is formed on the first gate replacement layer (42). In D2, the second high-k gate dielectric layer (48L) is formed on and around the respective suspended first and second semiconductor channel material nanosheets (14, 20), and on the second interface dielectric layer located on the intermediate dielectric isolation layer (16) within the opening (46). In D2, the second high-k gate dielectric layer (48L) is also formed along the inner sidewall of the inner spacer (30), along the top surface of the semiconductor substrate (10), and on the gate spacer (28) and ILD layer (36). In D3, the second high-k gate dielectric layer (48L) is formed on the top of the first block mask (38).

[0062] The second high-k gate dielectric layer (48L) is a second high-k gate dielectric material. The second high-k gate dielectric material has a dielectric constant greater than 4.0. Exemplary examples of the second high-k gate dielectric material include hafnium dioxide (HFO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrCO4), and zirconium silicon oxynitride (ZrSiO2). x N y ), tantalum oxide (TaO xThe first high-k gate dielectric material comprises, but is not limited to, titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobite (Pb(Zn,Nb)O). The first high-k gate dielectric material may further comprise dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The second high-k gate dielectric material providing the second high-k gate dielectric layer (48L) may be compositionally identical or compositionally different from the first high-k gate dielectric material providing the first high-k gate dielectric layer (40L).

[0063] The second high-k gate dielectric layer (48L) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD. The second high-k gate dielectric layer (48L) may have a second high-k gate dielectric thickness. The second high-k gate dielectric thickness may be equal to, smaller than, or larger than the first high-k gate dielectric thickness.

[0064] A second gate replacement layer (50) is subsequently formed in each of D1, D2, and D3. In each of D1, D2, and D3, the second gate replacement layer (50) is formed on the surface of the second high-k gate dielectric layer (48L). It should be noted that within D2, the second gate replacement layer (50) fills the gap between the respective suspended first and second semiconductor channel material nanosheets (14, 20) and between the suspended intermediate dielectric insulating layer (16). The second gate replacement layer (50) may include one of the sacrificial gate materials described above for the sacrificial gate layer (24) of the sacrificial gate structure. The second gate replacement layer (50) may be compositionally identical to or compositionally different from the first gate replacement layer (42). The second gate replacement layer (50) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD.

[0065] Now, referring to FIGS. 7A, 7B, and 7C, an exemplary semiconductor structure illustrated in FIGS. 6A, 6B, and 6C, respectively, is shown after a second planarization process has been performed in D1, D2, and D3 to remove the second gate replacement layer (50) and the second high-k gate dielectric layer (48L) from D1 and D3. This second planarization process may also remove the upper portion of the second gate replacement layer (50) from D2. The second planarization process may include CMP or polishing. In D1, the second planarization process exposes the first gate replacement layer (42). In D3, the second planarization process exposes the first block mask (38).

[0066] Now, referring to FIGS. 8A, 8B, and 8C, an exemplary semiconductor structure illustrated in FIGS. 7A, 7B, and 7C, respectively, is shown after the third block mask (52) is formed in D1 and D2. The third block mask (52) comprises one of the block mask materials described above for the first block mask (38). The block mask material providing the third block mask (52) may be compositionally identical or compositionally different from the block mask material providing the first block mask (38). The third block mask (52) may be formed using the same technique described above for forming the first block mask (38). In D1, the third block mask (52) is formed on the first gate replacement layer (42). In D2, the third block mask (52) is formed on the third block mask (52) and on the second gate replacement layer (50).

[0067] Now, referring to FIGS. 9a, 9b, and 9c, an exemplary semiconductor structure illustrated in FIGS. 8a, 8b, and 8c, respectively, is shown after the removal of the first block mask (38) from D3 and the nanosheet device processing in D3, wherein the nanosheet device processing in D3 includes removing the sacrificial gate structure to reveal stacked first and second nanosheet material stacks, and removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12) to form an opening (54) in D3.

[0068] The first block mask (38) is removed from D3 using an optional etching process to remove the first block mask (38) from D3. In some embodiments, the removal of the first block mask (38) from D3 occurs simultaneously with the removal of the blanket layer of the hard mask material from D3, which provides the third block mask (52). In other embodiments, the removal of the first block mask (38) from D3 occurs using a different material removal process, such as etching, which was used to remove the blanket layer of the hard mask material from D3.

[0069] With the third block mask (52) present in D1 and D2, nanosheet device processing in D3 first involves exposing the stacked first and second nanosheet material stacks present in D3. Exposing the stacked first and second nanosheet material stacks present in D3 involves removing the sacrificial gate cap (26), if present, and the sacrificial gate structure (including an optional sacrificial gate dielectric layer (22) and a sacrificial gate layer (24)). The removal process includes one or more etching processes. One or more etching processes may include RIE.

[0070] Removing each second sacrificial semiconductor material nanosheet (18) and each first sacrificial semiconductor material nanosheet (12) from D3 includes an optional optional material removal process (e.g., etching) or a combination of removal processes (a combination of two etching processes) for removing the first sacrificial semiconductor material nanosheet (12) and the second sacrificial semiconductor material nanosheet (18). These removal steps suspend portions of each first semiconductor channel material nanosheet (14) and each second semiconductor channel material nanosheet (20) present in D3 and provide an opening (54) in D3. It should also be noted that the intermediate dielectric isolation layer (16) is suspended during these steps of the present application.

[0071] Now, referring to FIGS. 10a, 10b, and 10c, an exemplary semiconductor structure illustrated in FIGS. 9a, 9b, and 9c is shown after the removal of the third block mask (52) in D1 and D2 and additional nanosheet device processing in D3, wherein the additional nanosheet device processing in D3 includes physically thinning the exposed portions of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material (20), forming a third interface dielectric layer (55) and a third high-k gate dielectric layer (56L), forming a third gate replacement layer (58), and performing a third planarization process in D1, D2, and D3 to remove the third gate replacement layer (58) and the third high-k gate dielectric layer (56L) from D1 and D2. The third block mask (52) is removed from D1 and D2 using an optional etching process to remove the third block mask (52) from the structure.

[0072] Thinning of the physically exposed portions of each of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material nanosheet (20) may include an oxidation process followed by etching. Oxidation / etching may be repeated multiple times in the thinning of the physically exposed portions of each of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material nanosheet (20). The thinning process provides a dumbbell-shaped first semiconductor channel material nanosheet (14A) and a dumbbell-shaped semiconductor channel material nanosheet (20A). The term "dumbbell shape" refers to a material having a middle portion that is thinner than the end portion of the same material. In this application, the dumbbell-shaped semiconductor channel material nanosheet has a middle portion having a first thickness (T1) and an end portion having a second thickness (T2), wherein T1 is smaller than T2. ​​In some embodiments, the thinning step may be omitted.

[0073] Subsequently, a third interface dielectric layer (55) is formed around each of the first semiconductor channel material nanosheet (14) and the second semiconductor channel material nanosheet (20) and on the top surface of the semiconductor substrate (10) at D2. The third interface dielectric layer (55) is composed of a third semiconductor oxide, such as silicon oxide, for example. The semiconductor oxide of the third interface dielectric layer (55) will match the semiconductor material formed thereon. The third interface dielectric layer (55) at D3 has a third thickness. The third thickness of the third interface dielectric layer (55) at D3 is greater than the first thickness of the first interface layer and the second thickness of the second interface layer. The third interface dielectric layer (55) can be formed by a thermal oxidation process.

[0074] A third high-k gate dielectric layer (56L) is subsequently formed on D1, D2, and D3, respectively. In D1, the third high-k gate dielectric layer (56L) is formed on the first gate replacement layer (42). In D2, the third high-k gate dielectric layer (48L) is formed on the second gate replacement layer (50). In D3, the third high-k gate dielectric layer (56L) is formed on and around the third interface dielectric layer (55) existing on each of the suspended first and second semiconductor channel material nanosheets (14, 20), and the intermediate dielectric isolation layer (16) within the opening (54). In D3, the third high-k gate dielectric layer (56L) is also formed along the inner sidewall of the inner spacer (30), along the top surface of the semiconductor substrate (10), and on the gate spacer (28) and the ILD layer (36).

[0075] The third high-k gate dielectric layer (56L) is a third high-k gate dielectric material. The third high-k gate dielectric material has a dielectric constant greater than 4.0. Exemplary examples of the third high-k gate dielectric material include hafnium dioxide (HFO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrCO4), and zirconium silicon oxynitride (ZrSiO2). x N y ), tantalum oxide (TaO x The first high-k gate dielectric material comprises, but is not limited to, titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobite (Pb(Zn,Nb)O). The first high-k gate dielectric material may further comprise dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The third high-k gate dielectric material providing the third high-k gate dielectric layer (56L) may be compositionally identical or compositionally different from the first high-k gate dielectric material providing the first high-k gate dielectric layer (40L) and / or the second high-k gate dielectric material providing the second high-k gate dielectric layer (48L).

[0076] The third high-k gate dielectric layer (56L) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD. The third high-k gate dielectric layer (56L) may have a third high-k gate dielectric thickness. The third high-k gate dielectric thickness may be equal to, smaller than, or larger than the first high-k gate dielectric thickness and / or the second high-k gate dielectric thickness.

[0077] A third gate replacement layer (58) is subsequently formed in D1, D2, and D3, respectively. In D1, D2, and D3, the third gate replacement layer (58) is formed on the surface of the third high-k gate dielectric layer (56L). It should be noted that within D3, the third gate replacement layer (58) fills the gap between the respective suspended first and second semiconductor channel material nanosheets (14, 20) and between the suspended intermediate dielectric insulating layer (16). The third gate replacement layer (58) may comprise one of the sacrificial gate materials described above for the sacrificial gate layer (24) of the sacrificial gate structure. The third gate replacement layer (50) may be compositionally identical to or compositionally different from the first gate replacement layer (42) and / or the second gate replacement layer (50). In some embodiments, the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58) are each composed of the same sacrificial gate material. Such embodiments provide ease in the manufacturing process because a single etching can be used to remove each of the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58). Such embodiments may allow the formation of the same gate electrode material in each of D1, D2, and D3. In another embodiment, the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58) are each composed of a compositionally different sacrificial gate material. Such embodiments allow the formation of gate structures in each of D1, D2, and D3 having different gate electrode materials. The third gate replacement layer (58) may be formed by a deposition process including, but not limited to, CVD, PECVD, or ALD.

[0078] The third planarization process of D1, D2, and D3 is intended to remove the third gate replacement layer (58) and the third high-k gate dielectric layer (56L) from D1 and D2. This third planarization process may also remove the upper portion of the third gate replacement layer (58) from D3. The third planarization process may include CMP or polishing. In D1, the third planarization process exposes the first gate replacement layer (42). In D2, the third planarization process exposes the second gate replacement layer (50). In D3, the third planarization process exposes the third gate replacement layer (58).

[0079] In some embodiments of the present application, a dielectric annealing step may now be performed. In other embodiments of the present application, the dielectric annealing step may be omitted. When performed, dielectric annealing reduces defects present in each high-k gate dielectric layer, namely the first high-k gate dielectric layer (40L), the second high-k gate dielectric layer (48L), and the third high-k gate dielectric layer (56L). The dielectric annealing step may be performed in an environment such as, for example, helium, argon, and / or neon. The dielectric annealing step may be performed at a temperature of 700°C to 1000°C.

[0080] Now, referring to FIGS. 11a, 11b, and 11c, there is a cross-sectional view of the exemplary semiconductor structure illustrated in FIGS. 10a, 10b, and 10c after removing the first gate replacement layer (42) from D1, the second gate replacement layer (50) from D2, and the third gate replacement layer (58) from D3. The removal of the first gate replacement layer (42) from D1, the second gate replacement layer (50) from D2, and the third gate replacement layer (58) from D3 may be performed using one or more etching processes. In an embodiment where the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58) are composed of the same sacrificial gate material, a single etching may be used to remove each of the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58). In an embodiment (not shown) in which the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58) are composed of compositionally different sacrificial gate materials, a multiple etching process may be used to remove each of the first gate replacement layer (42), the second gate replacement layer (50), and the third gate replacement layer (58). In D1, the first gate opening (62A) is formed by this step. In D2, the second gate opening (62B) is formed. In D3, the third gate opening (62C) is formed by this step. When multiple etchings are used, a gate electrode may be formed in one of the device regions before removing the gate replacement layer from other device regions.

[0081] Referring to FIGS. 12a, 12b, and 12c, an exemplary semiconductor structure illustrated in FIGS. 11a, 11b, and 11c is shown after forming a first gate electrode (64A) at D1, a second gate electrode (64B) at D2, and a third gate electrode (64C) at D3. Each of the first gate electrode (64A), the second gate electrode (64B), and the third gate electrode (64C) is composed of a gate electrode material. In some embodiments, the gate electrode material for the first gate electrode (64A), the second gate electrode (64B), and the third gate electrode (64C) is the same material in composition. In other embodiments, the gate electrode material for the first gate electrode (64A) may be different in composition from the gate electrode material for the second gate electrode (64B) and / or the third gate electrode (64C).

[0082] The gate electrode material may comprise a work function metal (WFM) and optionally a conductive metal. The WFM may be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM may be selected to perform an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" refers to a shift of the effective work function of the work function metal-containing material toward the conduction band of silicon within the silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that may affect the n-type threshold voltage shift may include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, hafnium nitride, hafnium silicon, or combinations thereof. In another embodiment, the WFM may be selected to perform a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the channel of the device conductive. As used herein, the term “p-type threshold voltage shift” refers to a shift of the effective work function of a work function metal-containing material toward the valence band of silicon within the silicon-containing material. Examples of such materials that may affect the p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals may include, but are not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The first gate electrode (64A), the second gate electrode (64B), and the third gate electrode (64C) may be formed by the deposition of gate electrode material, followed by a planarization process.It should be noted that the gate electrode material wraps around the circumference of each of the suspended first and second semiconductor channel material nanosheets (14, 20) as well as the circumference of the intermediate dielectric insulating layer (16).

[0083] Now, referring to FIGS. 13a, 13b, and 13c, a cross-sectional view showing portions of the gate region present in D1, D2, and D3, respectively, is shown. In D1, the gate region comprises a semiconductor nanosheet (a first semiconductor material nanosheet (14) or a second semiconductor material nanosheet (20)), a first interlayer dielectric layer (IL-1), a first high-k gate dielectric layer (40L), and a first gate electrode (64A). It should be noted that the first interlayer dielectric layer (IL-1), the first high-k gate dielectric layer (40L), and the first gate electrode (64A) surround the semiconductor nanosheet. In D2, the gate region comprises a semiconductor nanosheet (a first semiconductor material nanosheet (14) or a second semiconductor material nanosheet (20)), a second interlayer dielectric layer (IL-2), a second high-k gate dielectric layer (48L), and a second gate electrode (64B). It should be noted that the second interlayer dielectric layer (IL-2), the second high-k gate dielectric layer (48L), and the second gate electrode (64B) surround the semiconductor nanosheet. In D3, the gate region includes the semiconductor nanosheet (the first semiconductor material nanosheet (14) or the second semiconductor material nanosheet (20)), the third interlayer dielectric layer (55), the third high-k gate dielectric layer (56L), and the third gate electrode (64C). It should be noted that the third interlayer dielectric layer (55), the third high-k gate dielectric layer (56L), and the third gate electrode (64C) surround the semiconductor nanosheet.

[0084] Although this application has been particularly illustrated and described with respect to its preferred embodiments, those skilled in the art will understand that the foregoing changes and other modifications regarding the form and details may be made without departing from the spirit and scope of this application. Accordingly, this application is not limited to the exact form and details described and illustrated, but is intended to fall within the scope of the appended claims.

Claims

Claim 1 A semiconductor structure comprises a first device region having a first threshold voltage and including a first pair of stacked logic devices, wherein the first pair of logic devices comprises a first interface dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interface dielectric layer, and a first gate electrode located on the first high-k gate dielectric layer; a second device region having a second threshold voltage different from the first threshold voltage and including a second pair of stacked logic devices, wherein the second pair of logic devices comprises a second interface dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interface dielectric layer, and a second gate electrode located on the second high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a thickness greater than the thickness of the first high-k gate dielectric layer. A semiconductor structure comprising: a third device region including a pair of I / O devices stacked together; wherein the pair of I / O devices includes a third interface dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interface dielectric layer, and a third gate electrode located on the third high-k gate dielectric layer, and wherein the third thickness of the third interface dielectric layer is greater than the first thickness of the first interface dielectric layer and the second thickness of the second interface dielectric layer. Claim 2 In claim 1, the first logic device pair comprises a first nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the first interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the first nanosheet stack and the perimeter of at least one portion of the first semiconductor channel material nanosheet of the first nanosheet stack; the second logic device pair comprises a second nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the second interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the second nanosheet stack and the perimeter of at least one first semiconductor material nanosheet of the second nanosheet stack; the I / O device pair comprises a third nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the third interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the third nanosheet stack and A semiconductor structure that wraps around a portion of at least one first semiconductor material nanosheet of the above-mentioned third nanosheet stack. Claim 3 A semiconductor structure according to claim 2, further comprising an intermediate dielectric isolation layer positioned between the at least one first semiconductor channel material nanosheet and the at least one second semiconductor channel material nanosheet in each of the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. Claim 4 A semiconductor structure according to claim 2, wherein at least one first semiconductor material channel nanosheet of the third nanosheet stack and at least one second semiconductor channel material nanosheet of the third nanosheet stack are dumbbell-shaped having a middle portion of a first thickness and an end portion of a second thickness, wherein the second thickness is greater than the first thickness, and the third interface dielectric layer surrounds the middle portion. Claim 5 A semiconductor structure according to claim 1, wherein each of the first device region, the second device region, and the third device region exists on the same semiconductor substrate. Claim 6 A semiconductor structure according to claim 1, wherein the first gate electrode, the second gate electrode, and the third gate electrode are composed of the same gate electrode material in composition. Claim 7 A semiconductor structure according to claim 1, wherein at least one of the first gate electrode, the second gate electrode, and the third gate electrode is composed of a gate electrode material that is compositionally different. Claim 8 A semiconductor structure according to claim 1, wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer are composed of the same high-k gate dielectric material. Claim 9 A semiconductor structure according to claim 1, wherein at least one of the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer is composed of a high-k gate dielectric material that is compositionally different. Claim 10 A semiconductor structure according to claim 1, wherein each logic device of the first logic device pair is of a different conductivity type, each logic device of the second logic device pair is of a different conductivity type, and each I / O device of the I / O device pair is of a different conductivity type. Claim 11 A semiconductor structure comprises: a first device region having a first threshold voltage and including a first pair of stacked logic devices; wherein the first pair of logic devices comprises a first interface dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interface dielectric layer, and a first gate electrode located on the first high-k gate dielectric layer; a second device region having a second threshold voltage different from the first threshold voltage and including a second pair of stacked logic devices; wherein the second pair of logic devices comprises a second interface dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interface dielectric layer, and a second gate electrode located on the second high-k gate dielectric layer. A semiconductor structure comprising a third device region including a pair of I / O devices stacked together, wherein the pair of I / O devices includes a third interface dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interface dielectric layer, and a third gate electrode located on the third high-k gate dielectric layer, wherein the third thickness of the third interface dielectric layer is greater than the first thickness of the first interface dielectric layer and the second thickness of the second interface dielectric layer, and at least one of the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer is composed of a high-k gate dielectric material that is compositionally different, and wherein at least one of the first gate electrode, the second gate electrode, and the third gate electrode is composed of a gate electrode material that is compositionally different. Claim 12 In claim 11, the first logic device pair comprises a first nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the first interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the first nanosheet stack and the perimeter of at least one portion of the first semiconductor channel material nanosheet of the first nanosheet stack; the second logic device pair comprises a second nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the second interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the second nanosheet stack and the perimeter of at least one first semiconductor material nanosheet of the second nanosheet stack; the I / O device pair comprises a third nanosheet stack comprising at least one second semiconductor channel material nanosheet positioned on at least one first semiconductor channel material nanosheet, and the third interface dielectric layer surrounds a portion of at least one second semiconductor channel material nanosheet of the third nanosheet stack A semiconductor structure that wraps around a portion of at least one first semiconductor material nanosheet of the third nanosheet stack. Claim 13 A semiconductor structure according to claim 12, further comprising an intermediate dielectric isolation layer positioned between the at least one first semiconductor channel material nanosheet and the at least one second semiconductor channel material nanosheet in each of the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. Claim 14 A semiconductor structure according to claim 12, wherein at least one first semiconductor material channel nanosheet of the third nanosheet stack and at least one second semiconductor channel material nanosheet of the third nanosheet stack are dumbbell-shaped having a middle portion of a first thickness and an end portion of a second thickness, wherein the second thickness is greater than the first thickness, and the third interface dielectric layer surrounds the perimeter of the middle portion. Claim 15 A semiconductor structure according to claim 11, wherein each of the first device region, the second device region, and the third device region exists on the same semiconductor substrate. Claim 16 delete Claim 17 delete Claim 18 A semiconductor structure according to claim 11, wherein each of the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer is composed of a high-k gate dielectric material that is compositionally different. Claim 19 A semiconductor structure according to claim 11, wherein each logic device of the first logic device pair is of a different conductivity type, each logic device of the second logic device pair is of a different conductivity type, and each I / O device of the I / O device pair is of a different conductivity type. Claim 20 A semiconductor structure according to claim 11, wherein the third thickness of the third interface dielectric layer is greater than the first thickness of the first interface dielectric layer and the second thickness of the second interface dielectric layer.

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