Hall Integrated Sensor and Corresponding Manufacturing Process

Abstract

The integrated Hall sensor comprises a main wafer (10) of a semiconductor material having a substrate (101) having a first surface (101a) and a second surface (101b) facing the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') disposed on at least one of the first and second surfaces (101a, 101b) of the substrate (101); and an isolation structure (109) of the substrate (101) forming a Hall sensor plate (103) of the integrated Hall sensor, wherein the Hall sensor terminals are arranged inside the isolation structure (109). The integrated Hall sensor further comprises at least one test and calibration coil integrated within a main wafer (10) having a plurality of windings formed at least partially by metal parts (130b, 170b; 130a, 170a) arranged on the first and second surfaces (101a, 101b) of the substrate (101), forming an internal volume (1001) that completely surrounds the Hall sensor plate (103).

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This patent application claims priority to European patent application No. 19185046.0 filed on August 7, 2019, the full disclosure of which is incorporated herein by reference.

[0003] The present invention relates particularly to a Hall integrated sensor having at least one integrated coil for final testing and calibration, and a corresponding manufacturing process. Background Technology

[0004] Magnetic sensor ICs (integrated circuits) generally utilize silicon-based Hall sensor elements monolithically integrated with the electrical circuits required for signal conditioning and amplification. Common commercial products with monolithically integrated Hall sensors include Hall switches (ICs), linear position measurement Hall (ICs), angular position sensor Hall (ICs), current sensing Hall (ICs), and 3D Hall sensors (ICs). Depending on the product type, Hall integrated sensors may include horizontal Hall elements, vertical Hall elements, or both. Horizontal Hall elements detect the strength of a magnetic field perpendicular to the silicon surface. This is used in various applications where determining magnetic field strength in only one spatial dimension is sufficient. Examples include unipolar and bipolar Hall switches (ICs) and Hall sensors (ICs) for linear position measurement along a single axis. Vertical Hall elements, which detect magnetic field strength in a direction in the plane of the silicon surface, are used in angular position sensor Hall (ICs) and in 3D Hall sensors (ICs) in conjunction with horizontal Hall elements.

[0005] Since Hall sensors can be fabricated using a standard CMOS manufacturing process, the Hall sensor and the electronic device for operation and reading can be integrated on the same chip. Alternatively, a dedicated Hall sensor wafer can be stacked on a second wafer containing the necessary circuitry. WO 2020 / 104998 A1, under the name of the applicant, discloses a method of stacking two wafers to form such a Hall sensor IC product.

[0006] The magnetic sensitivity of a Hall sensor depends on stress, temperature, aging, and thermal shock.

[0007] Offsets in Hall voltage can occur due to manufacturing defects such as optical alignment errors, non-uniform dopant density, or defects. More seriously, the plastic packages used for Hall sensor ICs can stress the silicon, also causing offsets in Hall voltage. Therefore, Hall sensor ICs undergo extensive testing. For many products, such as linear Hall ICs, each Hall sensor is calibrated, and the acquired calibration data is stored in the IC. To characterize the magnetic response of the Hall sensor, the packaged chip is placed on an external Helmholtz coil. Of course, 3D Hall sensor ICs must be characterized in all three spatial dimensions. As understood above, the final testing and calibration efforts for Hall sensor ICs are critical, and the associated costs account for a significant portion of the total manufacturing cost.

[0008] It has been proposed to equip the Hall sensor IC with integrated coil testing and calibration. For example, refer to the following:

[0009] PLC Simon, PHS de Vries, S. Middelhoek, Automatic Calibration of Silicon Hall Devices, Transducer 95, 291-A12, pp. 237-240, 1995

[0010] RS Popovich, TJA Flanagan, PA Besse, The Future of Magnetic Sensors, Sensors and Actuators A56, pp. 39-55, 1996.

[0011] The integrated coil used for the final testing and calibration of horizontal and / or vertical Hall sensors is required to induce a sufficiently large magnetic field in the range of at least several mT. Coil efficiency is defined as the ratio of the induced magnetic field strength to the coil current. The maximum coil current applied to the integrated coil during the final testing or calibration procedure may be limited by the electromigration performance of the CMOS metal layer used in the coil. More importantly, the self-heating of the Hall sensor element during testing must be taken into account. For this reason, it is important to achieve high coil efficiency for the integrated coil.

[0012] In addition, the magnetic field induced by the integrated coil must be uniform in the area of ​​the Hall sensor element being tested. This can be achieved to some extent for horizontal Hall sensors (by using standard metal layers for coil formation), but there is no known method for forming an inductor coil for vertical Hall sensors to form a uniform and homogeneous magnetic field, which is induced from the Hall sensor plate of the vertical Hall sensor.

[0013] Accordingly, the object of the present invention is to provide an improved Hall integrated sensor, in particular having at least an integrated coil for final testing and calibration.

[0014] According to the present invention, a Hall integrated sensor and a corresponding manufacturing process are consequently provided as defined in the appended claims. Brief explanation of the drawing

[0015] FIG. 1a is a plan view of a Hall integrated sensor according to an embodiment of the present invention. Figure 1b is a cross-sectional view of the Hall integrated sensor of Figure 1a. FIGS. 1c and FIGS. 2 are additional plan views of a Hall integrated sensor according to an embodiment of the present invention. FIG. 3a is a cross-sectional view of a Hall integrated sensor according to another embodiment of the present invention. Figures 3b and 3c are top views of the Hall integrated sensor of Figure 3a. FIG. 4a is a plan view of a Hall integrated sensor according to another embodiment of the present invention. Figure 4b is a cross-sectional view of the Hall integrated sensor of Figure 4a. FIG. 5a is a plan view of a Hall integrated sensor according to another embodiment of the present invention. Figure 5b is a cross-sectional view of the Hall integrated sensor of Figure 5a. FIG. 6 is a cross-sectional view of a Hall integrated sensor according to another embodiment of the present invention. FIG. 7 is a plan view of a Hall integrated sensor according to another embodiment of the present invention. FIG. 8a is a plan view of a Hall integrated sensor according to another embodiment of the present invention. Figure 8b is a cross-sectional view of the Hall integrated sensor of Figure 8a. FIG. 9a is a plan view of a Hall integrated sensor according to another embodiment of the present invention. Figure 9b is a cross-sectional view of the Hall integrated sensor of Figure 9a. FIG. 10a is a plan view of a Hall integrated sensor according to another embodiment of the present invention. Figure 10b is a cross-sectional view of the Hall integrated sensor of Figure 10a. FIG. 11-14 is a plan view of a Hall integrated sensor according to another embodiment of the present invention. FIG. 15a is a cross-sectional view of a Hall integrated sensor according to another embodiment of the present invention. FIGS. 15b-15d are top views of the Hall integrated sensor of FIG. 15a. FIGS. 16-18 is a plan view of a Hall integrated sensor according to another embodiment of the present invention. FIG. 19-20 is a cross-sectional view of a Hall integrated sensor according to another embodiment of the present invention. FIGS. 21a-21m are cross-sectional views of a Hall sensor integrated in successive stages of a corresponding manufacturing process. Specific details for implementing the invention

[0016] As will be discussed in detail below, this solution considers the fabrication of an integrated Hall sensor using process steps and materials that are fully compatible with CMOS.

[0017] FIGS. 1a, 1b, and 1c illustrate a first embodiment of the present solution. A Hall sensor product (100) comprises a vertical Hall sensor equipped with a coil for calibration and testing. FIG. 1a provides an aerial image of the Hall sensor product (100) in the xz plane. A section parallel to the x-direction from 1B to 1B' is labeled and illustrated as 1B-1B'. FIG. 1b illustrates a cross-section of the Hall sensor product (100) along the section (1B-1B'). FIG. 1b shows two sections. A first section from 1A to 1A' is labeled as 1A-1A', and a second section labeled as 1C-1C' is illustrated as 1C-1C'. Each of the two sections corresponds to a plane parallel to the xz plane, moved from the origin along the y-direction. FIG. 1a illustrates the Hall sensor product (100) of the section (1A-1A'). FIG. 1c is another aerial image of the Hall sensor product (100) at the cut section (1C-1C'). The Hall sensor product (100) includes an on-chip coil dedicated to testing and calibrating the vertical Hall element and a vertical Hall element.

[0018] Referring to FIG. 1b, a vertical hole element is formed on a wafer (10) having a semiconductor substrate (101). The semiconductor substrate (101) is preferably a silicon substrate, but other semiconductor materials may also be considered. The semiconductor substrate (101) has a first type of conductivity, preferably n-type. Referring further to FIG. 2, the semiconductor substrate has a first surface indicated as 101a. Two high-doping regions (1, 2) having the first type of conductivity are formed on the first surface (101a). The two high-doping regions (1 and 2) extend from the surface (101a) to the semiconductor substrate (101). The high-doping regions (1 and 2) can be formed by common CMOS manufacturing techniques such as photomask ion implantation and subsequent rapid thermal annealing. A dielectric structure (104) is disposed on the first surface (101a). The dielectric structure (104) may constitute a pre-metal dielectric structure and may be composed of silicon nitride, silicon oxide, phosphosilicate glass, borophosphosilicate glass, or other suitable dielectric material. The dielectric structure (104) may also include a stack of dielectric structures having the material composition as given above. Within a portion of the surface (101a) occupied by the high-doping region (1), the dielectric structure (104) has an opening that extends downward to the substrate surface (101a). In the same way, a second opening is provided in the dielectric structure (104) located within a portion of the semiconductor surface (101a) occupied by the high-doping region (2). The second opening extends to the substrate surface (101a). A first metal layer (110) is disposed on the dielectric structure (104). The first metal layer (110) may be an aluminum-based metal layer common in many CMOS manufacturing processes. As shown in FIG. 2, an aluminum-based metal layer fills two openings of the dielectric structure (104). Alternatively, the two openings may also be filled by a tungsten-based layer, while the metal layer (110) is aluminum-based or alternatively copper-based.Different metallization methods may be adopted for the metal layer (110), all of which are well known in the art. The metal layer (110) is structured to leave portions (110b, 112, 111, 111b) as shown in FIG. 1b. The metal portions (111, 112) are in contact with the high regions (1, 2), respectively. The high-doped regions (1 and 2) form two terminals of a vertical Hall sensor, both of which are formed on the first surface (101a) of the substrate (101). The metal portions (111, 112) provide wiring and electrical contacts to access the Hall terminals (1, 2), respectively. The metal wiring for each of the two Hall terminals disposed on the dielectric structure (104) is oriented in the x-direction within the vertical Hall sensor region and also near the vertical Hall sensor. The metal portion (110b, 111b) is a portion of the metal coil surrounding the vertical Hall sensor, which will become more apparent below. The metal layer (110) is embedded in the second dielectric structure (105) forming the first intermetallic dielectric. Suitable materials for the dielectric structure (105) are silicon oxide or high dielectric constant dielectric materials. A via (121b) is formed in the dielectric structure (105). The second metal layer (130) is placed on the dielectric structure (105) and configured to leave the metal portion (130b). A general metalization method can be used for the second metal layer. The via (121b) can be filled with a tungsten-based layer, and the metal layer (130) can be aluminum-based or copper-based. The via (121b) can also be filled with an aluminum-based metal layer (130) placed on the intermetallic dielectric (105). A general manufacturing process can be applied to form the metal structure illustrated in FIG. 1b. A second metal layer is embedded in a dielectric structure (106), and the dielectric structure (106) may be composed of silicon oxide or a stack comprising a high dielectric constant dielectric and silicon oxide. A via (121b) is in contact with a metal portion (111b).The metal portion (110b), metal portion (111b), via (121b), and metal portion (130b) constitute part of a coil surrounding a vertical hole element on a first surface of the substrate (101). The wafer (10) is in contact with the upper portion of the dielectric structure (106) on the second wafer (20). The second wafer (20) may be a carrier wafer, for example, the second wafer (20) may be an inexpensive silicon wafer. Alternatively, the second wafer (20) may be a CMOS wafer containing an integrated circuit necessary to operate the vertical hole element. In this case, the wafer (20) includes a silicon substrate on which a CMOS device is formed, and a metallization stack. The metallization stack on the wafer (20) may include a plurality of metal layers embedded in the dielectric structure. In this case, the wafer (10) is attached together with the upper surface of the dielectric structure (106) on the upper surface of the dielectric structure disposed on the silicon wafer (20). Furthermore, electrical contact is provided on the first surface of the wafer (20) and between the metal layers formed on the wafer (20). Such electrical contact may be achieved by hybrid bonding or other methods known in the art. Using the wafer (20) as a carrier, the wafer (10) is thinned from the rear side, i.e., from the side facing the first surface (101a). A large portion of the wafer material is removed so that only a thin layer of the semiconductor substrate (101) remains. The resulting second substrate surface facing the first surface (101a) is indicated as 101b in FIG. 1b. The second surface (101b) of the substrate layer (101) is parallel to the first surface (101a). The thickness of the remaining semiconductor substrate (101) may preferably be in the range of 10 micrometers to 50 micrometers, but lower or higher thickness values ​​may also be considered. Two high-doping regions (3, 4) are disposed on a second surface (101b) extending into the substrate (101). The high-doping regions (3, 4) have a first conductive type, which is a conductive type of the substrate layer (101).For the vertical Hall effect element in the product (100), a high-doping region (3) may be formed on the first surface (101a) opposite the high-doping region (2), and a high-doping region (4) may be formed on the first surface (101a) opposite the high-doping region (1). FIG. 1A illustrates the Hall sensor product (100) in the xz plane of the second surface (100b) along the cut section (LA-1A'). As can be seen in FIG. 1A, the high-doping regions (3 and 4) form a stripe along the z-direction. For the vertical Hall element of the product (100), the high-doping regions (1 and 2) on the first surface (100a) also form a stripe oriented in the z-direction. The high-doping regions (1, 2, 3 and 4) may all have the same lateral dimension. The highly doped regions (3, 4) of the second surface (100b) can be formed by photomasked ion implantation followed by laser thermal annealing. Using laser thermal annealing allows doping to be activated on the second surface without damaging the metallization of the first surface. The highly doped regions (3 and 4), as well as the highly doped regions (1 and 2), are surrounded by a dielectric structure (109). The dielectric structure (109) extends from the second surface (101b) of the substrate layer (101) to the first surface (101a). In FIG. 1a, the side enclosure is shown with the highly doped regions (3, 4) formed by the dielectric structure (109). The portion of the substrate layer (101) that is laterally surrounded by the dielectric structure (109) is indicated as 103 in FIG. 1a and 1b. A portion of the substrate layer (101) is the Hall sensor area (Hall sensor plate) of the vertical Hall element of the product (100). The dielectric structure (109) can be established by a deep trench isolation process. The dielectric material of the dielectric structure (109) may be silicon oxide. The deep trench isolation process is well known in the art. Referring again to FIG. 1b, the first dielectric structure (107) is placed on the second surface (101b).The dielectric structure (107) provides a pre-metal dielectric structure on a second side of the substrate layer (101). A material or material composition similar to that used for the pre-metal pre-metal dielectric structure (104) on the first side may be equally considered for the dielectric structure (107). A first through-silicon via (140b) is formed by extending from the upper surface of the dielectric structure (107) through the layer (107), through the substrate layer (101), and through the dielectric structure (104) on the first surface (101a) to reach a metal portion (110b) of the first metal layer disposed on top. The through-silicon via (140b) is filled with a metal layer which may be a tungsten-based metal layer or, more preferably, a copper-based metal layer. The metal filling of the through-silicon via is electrically isolated from the semiconductor substrate (101) by a dielectric liner (181). The dielectric liner may be composed of silicon oxide or other suitable insulating material. A second through-silicon via (141b) is formed by extending through the substrate from the upper surface of the dielectric structure (107) to the metal portion (111b) of the metal layer (110). The formation of through-silicon vias is known to those skilled in the art. Similar to the first aspect, two contact openings are formed in the dielectric structure (107) that extend to the surface (101b) and provide access to the highly doped regions (3, 4), respectively. Continuing the description of FIG. 1b, a first metal layer (150) is placed on the preliminary metal dielectric structure (107) on the second substrate surface (101b). Two trenches are filled with metal of the layer (150). Similar processes and materials may be applied to the metal layer (110) on the first surface. Four metal portions (150b, 153, 154, 151b) are shown in FIG. 1b. The metal portion (150b) is in contact with the metal filler of the through silicon via (140b). The metal portion (151b) is in contact with the metal filler of the through silicon via (141b).A metal portion (153) contacts a highly doped region (3) forming one of two hole terminals disposed on the second surface (101b). A metal portion (154) contacts a highly doped region (4) forming the other of two hole terminals disposed on the second surface (101b). The metal portions (153, 154) include wiring for the two hole terminals (3, 4). The wiring is oriented in the z-direction. A metal layer (150) is embedded in a first intermetallic dielectric structure (108). A process and material similar to that of the first dielectric structure (105) on the first surface of the substrate (101) may be applied. A via (160b) formed through the intermetallic dielectric (108) provides contact with the metal portion (150b). A second via (161b) through the dielectric structure (108) provides contact with the metal portion (151b). A second metal layer (170) is disposed on the intermetallic dielectric (108) and configured to electrically connect vias (160b) and vias (161b). The electrical connection is established by the metal portion (170b). In FIG. 1c, the metal portion (107b) and vias (160b, 161b) are shown in the xz plane along the cut section (1C-1C'). The process and materials for filling the vias with metal and forming the metal portion (170b) may be similar to those for the second metal layer on the first surface of the substrate. Finally, a dielectric structure (182) is disposed on the second metal layer (170) and the intermetallic dielectric structure (108). The dielectric structure (182) serves as a final passivation layer and may include a silicon nitride or silicon oxynitride layer. The vertical Hall element has four terminals arranged on two opposing surfaces of the semiconductor substrate layer (101) in such a way that 4-fold symmetry is obtained. During operation, a driving current can be forced from terminal (1) to terminal (3). The current flows diagonally through the semiconductor layer (101), where the current flow is limited by the dielectric structure (109). A Hall voltage can be captured between terminals (2, 4).The measured Hall voltage represents the magnetic field component in the z-direction. Likewise, the driving current can be forced at terminals (2) and (4), and the Hall voltage can be captured between the Hall terminals (3, 1). Again, the measured Hall voltage represents the magnetic field component in the z-direction. Furthermore, since the driving current can be reversed, a total of four different operating stages can be set to determine the same component of the magnetic field in the z-direction. The operation of the vertical Hall sensor requires a complex circuit for regulating and amplifying the voltage signal. The necessary integrated circuit can be formed on the first surface (101a) of the semiconductor wafer (10) or provided on the second semiconductor wafer (20). In either case, additional through-silicon vias may be required to access the Hall terminals (3 and 4) arranged on the second surface (101b) from the first side. These vertical connections and the necessary integrated circuit are not shown in FIGS. 1a and 1b. As shown in FIG. 1b, a rectangular coil is formed on the wafer (10) around the vertical Hall element. The coil includes a metal wire and pad (110b), through-silicon via (140b), metal pad (150b), via (160b), metal wire (170b), via (161b), metal pad (151b), through-silicon via (141b), metal pad (111b), via (121b), and metal wiring (130b). The rectangular coil is in the xy plane. When current is supplied to the coil and flows counterclockwise, a magnetic field is induced. The magnetic field is inside the coil directed in the z direction. The strength of the induced magnetic field depends on the supplied current and the geometry of the inductor coil. The magnetic field induced by the coil can be measured by a vertical Hall element sensitive to the magnetic field component in the z direction. It is evident from FIG. 1b that the coil can be arranged in the xy plane so that a nearly uniform magnetic field is induced inside the Hall sensor plate (103) of the vertical Hall element.The thickness of the dielectric structures (107, 108) on the second surface can be selected to have the same thickness value as the dielectric structures (104, 105), respectively. In this way, the metal portion (170b) has the same vertical distance to the Hall sensor plate (103) as the metal portion (130b). Furthermore, through silicon vias (140b, 141b) can be positioned to have the same transverse distance to the Hall sensor plate (103). Additionally, the distance of the through silicon vias (140b and 141b) to the Hall sensor plate is equal to the combined layer thickness of 104 and 105. As shown in FIG. 1a, the vertical Hall element of the product (100) can be mounted with seven inductor coils arranged in a row in the z-direction. Each coil is in a plane parallel to the xy plane as in FIG. 1B. Through silicon vias belonging to the coil are shown in FIG. 1A, which represents a vertical Hall element with a coil in the xz plane along the cut section (1A-1A'). As already discussed in relation to FIG. 1B, through silicon vias (140b, 141b) belong to the coil (as shown in FIG. 1B). Through silicon vias (140a, 141a) belong to another coil, through silicon vias (140c, 141c) belong to yet another coil, and the same applies to through silicon vias (140d, 141d), through silicon vias (140e, 141e), through silicon vias (140f, 141f), and through silicon vias (140g and 141g). The seven coils can be connected in series such that the current direction in the xy plane is the same for all seven single coils (i.e., counterclockwise or clockwise). In this way, seven individual coils form a winding of a single combined coil. Additionally, the magnetic field induced by a single coil or winding has the same direction. Each single coil or winding is arranged parallel to the xy plane, and the series connection of the single coils is established at a certain distance from the vertical Hall element.Those skilled in the art will understand how to provide a series connection between single coils. The series connection can be formed by the first and second metal layers (110, 130) and their respective vias. As can be seen in FIG. 1a, seven windings are spaced at equal intervals. The windings can be arranged so that a nearly homogeneous magnetic field is induced in the z-direction across the area occupied by the Hall sensor plate (103). In the Hall sensor product (100), the Hall sensor plate (103) of the vertical Hall element is placed inside the multi-winding coil. The interior of the coil (internal volume) is understood as the volume of the space enclosed by the coil windings. In FIG. 1b, as shown in the cut parallel to the xy plane, the interior of the coil is denoted and labeled as 1001. As illustrated, the Hall sensor plate (103) is placed entirely inside the internal volume (1001) of the coil. The same applies to the cut parallel to the xz plane as in FIG. 1a. The Hall sensor plate (103) is placed entirely within the internal volume (again indicated as 1001) of the (multi-winding) coil. FIG. 2 shows another Hall sensor product indicated as 200, which has a vertical Hall element equipped with a coil for testing and calibration. FIG. 2 provides a two-dimensional cross-section of the Hall sensor product parallel to the xz plane along the second surface (101b) of the substrate (101) (as in FIG. 1B of the Hall sensor product (100)). Highly doped regions (3 and 4) defining the two terminals of the vertical Hall sensor are shown. The Hall sensor plate (103) is transversely defined by a dielectric structure (109). Compared to the vertical Hall sensor of product (100), the vertical Hall sensor of product (200) has a lower width in the z-direction. FIG. 2 shows two pairs of through silicon vias. A first pair including through silicon vias (140a, 141a) belongs to the first winding. A second pair including through silicon vias (140b, 141b) belongs to the second winding of the coil. Both the first winding and the second winding are in the xy plane.As in the Hall sensor product (100), the windings are connected so that the current supplied to the coil flows through each winding in the same direction (i.e., clockwise or counterclockwise in the xy plane). In FIG. 2, the spacing between the through silicon vias (140a, 141a) is denoted as a. Length (a) is the internal length of the rectangular inductor coil in the x-direction. The spacing between the two rectangular windings in the z-direction is denoted as d in FIG. 2. If the spacing (d) is chosen to be close to a / 2, an approximate Helmholtz configuration is obtained. As is known to those skilled in the art, for a secondary winding of length a, if the distance (d) between the two windings is chosen to be 0.544*a, an approximate Helmholtz characteristic is obtained. As is also known, when current flows, a uniform magnetic field is induced inside the Helmholtz coil. As illustrated in FIG. 2, the Hall sensor plate (103) of the vertical Hall element of the product (200) is placed entirely within the interior (1001) of two coils. An additional Hall sensor product (300) is illustrated in FIG. 3a, 3b, and 3c. The Hall sensor product (300) includes a horizontal Hall sensor equipped with a coil for calibration and testing. FIG. 3a provides a cross-sectional image of the Hall sensor product (300) parallel to the xy plane. FIG. 3b and 3b are aerial images of the Hall sensor product (300) at two different locations along the y-direction. FIG. 3b illustrates the product (300) in the xz plane on the second surface (101b) of the substrate. This section is labeled 3C-3C' and is illustrated in FIG. 3a. FIG. 3c illustrates a second section parallel to the xz plane labeled 3B-3B'. In FIGS. 3b and 3c, a cutting line from 3A to 3A' is indicated. The cutting section (3A-3A') is shown in FIG. 3a. Referring to FIG. 3c, four high-doping regions (1, 2, 3, 4) are formed on the second surface (101b) of the substrate (101). Likewise, four high-doping regions (1', 2', 3' and 4') are formed on the first surface (101a) of the substrate (101).As can be seen in FIG. 3a, the highly doped regions (1, 1') formed on two opposing surfaces of the substrate (101) have the same position in the xy plane. As can be seen further, the highly doped regions (2 and 2') have the same position in the xz plane. The highly doped regions (3, 3') have the same position in the xz plane and are equally valid for the highly doped regions (4, 4'). Referring further to FIG. 3a, electrical contacts and wiring portions (151, 111', 152, and 112') are set to access the highly doped regions (1, 1', 2, and 2'), respectively. Similar electrical contacts and wiring portions are provided for the highly doped regions (3, 3', 4, 4'). A dielectric structure (109) is disposed extending from the second surface (101b) of the substrate to the first surface (101a). As illustrated in FIG. 3c, the dielectric structure surrounds a portion (103) of the substrate (101), and the portion (103) defines the Hall sensor plate of the horizontal Hall element. All high-doping regions are formed on the Hall sensor plate (103). The high-doping regions (1, 1') are electrically connected by a wiring portion (151, 111') and through-silicon vias not shown in FIG. 3a. Those skilled in the art will easily understand how the vertical electrical connection between the high-doping regions (1 and 1') can be established. In the same way, the high-doping regions (2, 2') are also electrically connected. And at the same time, the high-doping regions (3, 3') are also electrically connected. The high-doping regions (4, 4') are also electrically connected in this way. The four necessary through-silicon vias are located outside the Hall sensor plate (103) restricted by the dielectric structure (109). Pair (1, 1') forms the first hole terminal of the horizontal hole element. Pair (2, 2') forms the second hole terminal of the horizontal hole element. Pair (3, 3') forms the third hole terminal of the horizontal hole element, and pair (4, 4') forms the fourth hole terminal of the horizontal hole element.Referring further to FIG. 3c, the Hall sensor plate (103) of the horizontal Hall element has a square shape. Highly doped regions (1, 2, 3, and 4) are placed at the four corners of the square Hall sensor plate (103). Other layouts for the horizontal Hall element may be considered. In particular, the Hall sensor plate may have a Greek cross shape with four terminals placed at the four ends of the cross. During operation, a driving current may be supplied from Hall terminals (1, 1') to Hall terminals (3, 3'). In the xz plane, this driving current flows diagonally through the Hall sensor plate (103) of the secondary shape. Then, a Hall voltage is captured between Hall terminals (2, 2') and (4, 4'). The Hall voltage represents a magnetic field in the y direction. In a different operating mode, the driving current can be supplied from the Hall terminal (2, 2') to the Hall terminal (4, 4'), and the Hall voltage can be detected between the terminals (1, 1') and (3, 3'). Again, the measured Hall voltage represents a magnetic field directed in the y-direction. Reversing the current direction in the above operating mode provides two additional operating modes. Returning to FIG. 3a, at least two metal layers are applied to the first surface of the substrate (101) facing the carrier wafer (20). The first metal layer (110) is used to provide an electrical connection to the Hall terminal formed on the first surface (101a) as discussed. Additionally, at least two metal layers are applied on the second surface (101b) of the substrate (101). The first metal layer (150) is used to provide an electrical connection to the Hall terminal formed on the second surface (101b). Two coils are formed surrounding the area occupied by the Hall sensor plate (103). A first coil (130a) is formed with a second metal layer (130) on a first surface of a wafer (10). A second coil (170a) is formed by a second metal layer (170) on a second side. In FIG. 3B, the coil (170a) is shown in the xz plane (cut section 3B-3B').The coil may have a square shape as shown in FIG. 3b, but other shapes such as a hexagonal shape or a circular shape are also possible. The coil (170a) in FIG. 3b has only one winding, but the coil may have one or more windings. It is preferable that the first coil (130a) and the second coil (170a) be formed in the same way. Specifically, the first inductor coil (130a) and the second coil (170a) may preferably be formed facing each other and having the same number of windings, the same line width, the same inner radius, and the same outer radius. Furthermore, preferably, the same process and material are used on both sides of the substrate layer (101) for forming the second metal layer (130, 170), so that the series resistance of the two inductor coils is nearly the same. Furthermore, preferably, the combined thickness of the dielectric structures (104 and 105) is the same as the combined thickness of the dielectric structures (107 and 108). Two coils are connected in series by through silicon vias (not shown) to form two windings of a single coil. The connection is set so that the current direction in the xz plane is the same for both windings. When current is supplied through the coil in a counterclockwise direction, a magnetic field is induced, which is oriented in the y direction. In this way, the coil generates a magnetic field that is measured by a horizontal Hall element. The Hall sensor plate (103) of the horizontal Hall element is placed inside the coil containing the windings (130a, 170a). For reference, the internal volume of the coil is indicated as 1001 in FIGS. 3a and 3b.

[0019] As illustrated in FIGS. 4a and 4b, the Hall sensor product (400) includes a vertical Hall element equipped with an on-chip coil for testing and calibration. FIG. 4a is an aerial image of the Hall sensor product, and FIG. 4b is a cross-sectional image. The cut-off location for the aerial image is, in this case, along the first surface (101a) of the substrate (101) (cut-off 4A-4A'). The cut-off location for the cross-sectional image is illustrated in FIG. 4a. The Hall sensor product (400) is preferably formed on a substrate having a second conductivity type (p-type). A well (701) is formed extending from the first surface (101a) into the substrate. The well (701) has a conductivity type opposite to the conductivity type of the substrate, i.e., a first conductivity type (n-type). A plurality of high-doping regions (1, 2, 3, 4, 5) having the first conductivity type are formed on the first surface (101a) extending into the substrate.

[0020] The highly doped regions (1, 2, 3, 4, and 5) are entirely placed within the region of the well (701). The electrical contact and wiring portions (111, 112, 113, 114, 115) are formed using the first metal layer (110). The well (701) constitutes the Hall sensor plate (previously indicated as 103) of the vertical Hall element, and the highly doped regions (1, 2, 3, 4, and 5) define the Hall terminals of the vertical Hall element. As shown in FIG. 4a, the Hall terminals (1, 2, 3, 4, 5) are formed in a line along the x-axis. Such vertical Hall elements are known in the art. Their operation does not need to be discussed here. As is known, this type of vertical Hall element can have different numbers of Hall elements, such as 3, 4, or 5. In any case, the vertical Hall element shown in FIG. 4b is sensitive to a magnetic field in the z-direction. The coil for testing and calibrating the vertical Hall element is set up in the same way as for the Hall sensor product (100). Again, the Hall sensor plate of the Hall element (here, the well (701)) is placed entirely inside the internal volume (1001) of the coil.

[0021] Another Hall sensor product, denoted as 500, is illustrated in FIGS. 5a and 5b. The Hall sensor product (500) includes a horizontal Hall element equipped with an on-chip coil for testing and calibration. The Hall sensor product (500) is formed on a substrate (101) having a second conductivity type (p-type). A well (701) having a first conductivity type is formed on the substrate extending from the first surface (101a). Four high-doping regions (1, 2, 3, 4) having the first conductivity type are formed on the first surface (101a) extending into the well (701). In the xz plane, the well (701) may have a square shape as illustrated in FIG. 5a. Additionally, the four high-doping regions (1, 2, 3, 4) defining the Hall terminals may be located at the four corners of the square well (701). The well (701) may have the shape of a Greek cross and four hole terminals located at the four corners of the cross. The horizontal hole element shown in FIGS. 5a and 5b is sensitive to a magnetic field oriented in the z-direction. The coil dedicated to testing and calibrating the horizontal hole element of the hole sensor product (500) is formed in the same manner as the hole sensor product (300). The hole sensor plate of the horizontal hole sensor is placed entirely inside the internal volume (1001) of the coil.

[0022] FIG. 6 illustrates a Hall sensor product (600) comprising a vertical Hall element that may be identical to the vertical Hall element of the Hall sensor product (100). FIG. 6 provides a cross-sectional view of the Hall sensor product. The vertical Hall element, having a Hall sensor plate (103) and Hall terminals (1, 2, 3, 4), is surrounded by two coils, an inner coil and an outer coil. The inner coil is formed by a metal part (110b), a through-hole silicon via (140b), a metal part (150), a via (160b), a metal wire (170a), a via (161b), a metal part (151b), a through-hole silicon via (141b), a metal part (111b), a via (121b), and a metal line (130b). This inner coil is identical to the coil shown in FIG. 1b in relation to the Hall sensor product (100). As illustrated in FIG. 6, the outer coil is formed by a metal structure (114b, 142b, 155b, 162b, 171b, 192b, 270b, 193b, 172b, 163b, 156b, 143b, 115b, 123b, 133b, 223b, 230b). To form the outer coil, an additional metal layer (230) is added to a first side of the substrate facing the carrier wafer (20). The metal layer (230) is placed on the upper surface of the dielectric structure (106) and is embedded in the dielectric structure (206).

[0023] A vertical connection to the metal layer (130), such as vias (223b), is provided. Along the same line, an additional metal layer (270) is added to the second side of the substrate (101). The metal layer (270) is placed on the dielectric structure (182) and vias such as 192b and 193b are provided. The metal layer (270) is embedded in the final passivation layer (193). The inner coil and the outer coil are connected in series so that when current flows, the current direction of the inner coil and the outer coil is the same (clockwise or counterclockwise in the xy plane). The electrical connection required between the inner coil and the outer coil is not shown in FIG. 6. Consequently, a coil having one inner winding and one outer winding is created. Similar to the Hall sensor product (100), a plurality of such coils may be arranged along the z-direction, each comprising an inner winding and an outer winding both placed in the xy plane. When multiple coils are connected in series, a multi-winding coil with internal and external winding loops is established. The Hall sensor plate (103) of the vertical Hall element is located inside the resulting coil, and the interior is again shown as 1001 in FIG. 6.

[0024] FIG. 7 is an aerial image of a Hall sensor product (700). The Hall sensor product (700) differs from the Hall sensor product (300) in that a coil winding (130a) (not shown herein) placed on a dielectric structure (105) is set up as a helical coil having multiple windings, and a coil winding (170a) placed on a dielectric structure (108) is established as a helical coil having multiple windings. The helical coil (170a) is shown in FIG. 7 above. The helical coil (130a) may have the same or similar layout and number of windings. As in the Hall sensor product (300), two coils (130a, 170a) are connected in series such that the current direction in the xz plane is the same for the two helices. The series connection requires through silicon vias and possible underpasses for the internal ports or ends of the helical coils (130a and 170a). The underpass can be formed by each first metal layer (110, 150).

[0025] A person skilled in the art will easily understand how to set up a series connection. A horizontal Hall element is also shown in FIG. 7. The horizontal Hall element is illustrated through a cut along the second surface (101b). In FIG. 7, the spiral coil (170a) and the horizontal Hall element belong to two different cut positions along the y-axis. 1001 represents a volume enclosed by the spiral coils (130a, 170a). The Hall sensor plate (103) is entirely inside the internal volume (1001).

[0026] The Hall sensor product (800) illustrated in FIGS. 8a and 8b is a different product having a horizontal Hall element, which is similar to, for example, the Hall sensor product (300). An on-chip coil for testing and calibration is formed by through-silicon vias (140) that surround the horizontal Hall element laterally. FIG. 8b provides a cross-sectional image of the horizontal Hall element and the surrounding coil. A cut section (8A-8A') lying on the plane of the second surface (101b) is shown. In FIG. 8a, the horizontal Hall element and the surrounding coil are shown in the xz plane of the cut section (8A-8A'). As shown in FIG. 8b, the coil includes a metal portion (114) of a metal layer (110) on the first side of the substrate, through-silicon vias (140) through the substrate (101), and a metal portion (154) of a metal layer (150) on the second side of the same substrate.

[0027] Through-silicon vias (140) are isolated from the substrate (101) by dielectric liners (181). In FIG. 8a, through-silicon vias (140) are shown transversely surrounding horizontal Hall elements with Hall sensor plates (103). When current is supplied to the coil, a homogeneous magnetic field is induced inside the coil. The direction of the induced magnetic field inside the coil is perpendicular to the xz plane. The coil is square in shape, but other shapes such as circular, octagonal, or hexagonal are also possible. The coil extends from a first metal layer (110) on a first surface of the substrate to a first metal layer (150) on a second surface of the substrate, and because additional coils transversely surround Hall elements, a second metal layer on the second surface of the substrate is required to access the Hall terminals from the second metal layer on the first surface and outside the coil.

[0028] In FIG. 8b, the metal line (171) and via (161) provide access to the metal portion (151) and thus to the Hall terminal (1). Similarly, the metal line (172) and via (162) provide access to the metal portion (152) and thus to the Hall terminal (2). On the first side of the substrate (101) facing the carrier wafer (20), the metal line (131') and via (121') provide access to the metal portion (111') and thus to the Hall terminal (1'). Similarly, the metal line (132') and via (112') provide access to the metal portion (112') and thus to the Hall terminal (2'). The coil of the Hall sensor product (800) may also have one or more windings. That is, the spiral coil may be set through the metal portion (154), the silicon via (140), and the metal portion (114). In this case, at least one underpass is required. As is evident from FIG. 8b, such an underpass can be achieved by a metal layer (130) and a corresponding via. The underpass can also be formed by a metal (170) and a corresponding via. As can be seen in FIG. 8a and FIG. 8b, the Hall sensor plate (103) of the horizontal Hall element is placed entirely inside a volume (1001) surrounded by a coil integrated into the same wafer (10).

[0029] The Hall sensor product (900) illustrated in FIGS. 9a and 9b includes a horizontal Hall element equipped with a test and calibration coil comprising three coil windings oriented in the xz plane. The first coil winding is formed by a metal part (130a). This coil winding may be identical to the coil winding (130a) of the Hall sensor product (300). The second coil winding includes a metal part (110a), a through silicon via (140a), and a metal part (150a). This coil winding may be identical to the coil of the Hall sensor product (800). The third coil winding is formed by a metal part (170a). This coil winding may again be identical to the coil winding (170a) of the Hall sensor product (300). The first, second, and third coil windings are connected in series such that when current is supplied, the current direction in the xz plane is the same.

[0030] FIGS. 10a and 10b illustrate a Hall sensor product (1000) having a vertical Hall element and a coil for testing and calibrating said Hall element. It differs from the Hall sensor product (100) only in that through silicon vias (140a-g, 141a-g) are positioned far (i.e. further) from the Hall sensor plate (103). This is illustrated by the symbol 777. Consequently, when current is supplied to the multi-winding coil, the magnetic field induced in the Hall sensor plate (103) is largely generated by the transverse segments of the coil winding, i.e., the metal parts (130a, 170a, 130b, 170b), etc.

[0031] As is known in the art, in this configuration as well, a uniform magnetic field can be generated inside the coil such that the sum of the thicknesses of the dielectric structures (107, 108) on the second side of the substrate (101) is equal to the sum of the thicknesses of the dielectric structures (104, 105) on the first surface of the substrate facing the carrier wafer (20). That is, when the vertical distance between the metal line (170b) and the Hall sensor plate (103) is equal to the vertical distance between the Hall sensor plate (103) and the metal line (130b), a homogeneous magnetic field can be induced within the Hall sensor plate (103).

[0032] The Hall sensor product (1100) illustrated in FIG. 11a has the same coil configuration as the Hall sensor product (1000), but one or more vertical Hall elements are placed inside the coil. Three vertical Hall elements, labeled H1, H2, and H3 in FIG. 11a, are shown being placed inside a volume (1001) representing the interior of a multi-winding coil. FIG. 11a illustrates a cut along the second surface (101b) of the substrate (101). The vertical Hall elements (H1, H2, H3) are all placed so that the distance to the through silicon vias (140a-g, 141a-g) increases. The large gap is indicated by the symbol 777. The vertical Hall elements (H1, H2, and H3) are oriented to be sensitive to the magnetic field component in the z-direction. The Hall sensor plates of the vertical Hall elements (H1, H2, and H3) are entirely inside the multi-winding coil.

[0033] A multi-winding coil is oriented so that a homogeneous magnetic field directed in the z-direction can be induced within the coil. Three vertical Hall elements are illustrated in FIG. 11a. This is merely an example. Generally speaking, multiple vertical Hall elements oriented to be sensitive to a magnetic field component in the z-direction can be placed inside (1001) a multi-winding coil oriented such that the magnetic field is induced from within and directed in the z-direction. Similarly, multiple vertical Hall elements oriented to be sensitive to a magnetic field component in the x-direction can be placed inside (1001) a multi-winding coil such that the magnetic field is induced from within and directed in the x-direction. In this way, multiple vertical Hall elements can be tested and calibrated by a single multi-winding coil for each of the two directions. This approach can be extended to the case of horizontal Hall elements. In the Hall sensor product (300) (Fig. 3a), the inner radius of the coil winding (130a, 170a) can be set sufficiently large so that multiple horizontal Hall elements can be placed inside two coil windings.

[0034] This is illustrated in FIG. 11b, where, as an example, four horizontal hole elements labeled H1, H2, H3, and H4 are placed inside (1001) a test and calibration coil. The test and calibration coil has a winding (170a) and a winding (130a) (not shown). In this way, multiple horizontal hole elements can be tested and calibrated with a single coil.

[0035] In the Hall sensor product (1200) of FIG. 12a, four vertical Hall elements, denoted as H1, H2, H3, and H4, are placed inside (1001) a multi-winding coil, with a distance to all through silicon vias (140a-g, 141a-g). The four Hall elements (H1, H2, H3, H4) are orthogonally coupled. In FIG. 12a, the orthogonal coupling of the Hall elements (H1, H2, H3, H4) is denoted as OC. The orthogonal coupling creates a new Hall element or Hall sensor (H). The orthogonal coupling of the four Hall elements (H1, H2, H3, and H4) requires various electrical connections, including electrical connections between metal layers on the first surface of the substrate facing the carrier.

[0036] A portion of the electrical connection may be formed outside the multi-winding coil. However, the Hall sensor plates (103) of all four Hall elements are placed inside the multi-winding coil (1001). The Hall sensor (H) is tested and calibrated by this multi-winding coil. In FIG. 12a, a vertical Hall element sensitive to the magnetic field component in the z-direction is shown. This is merely an example. Although four Hall elements are orthogonally coupled in FIG. 12a, only two Hall elements may be orthogonally coupled to create a new Hall element or Hall sensor (H). Furthermore, two or four horizontal Hall elements may be orthogonally coupled and tested and calibrated by a suitable coil as discussed above. This is shown in FIG. 12b. In FIG. 12c, at least some of the Hall sensor elements are orthogonally coupled elements that jointly form a Hall sensor (H) designed to be tested and calibrated by a test and calibration coil. An orthogonal coupling of two horizontal Hall elements (H1, H2) is shown as an example. Referring to FIG. 12c, the four Hall terminals of the first Hall element (H1) are each labeled 1a, 2a, 3a, and 4a. The four Hall terminals of the second Hall element (H2) are each labeled 1b, 2b, 3b, and 4b. The Hall terminal (1a) of H1 is electrically connected to the Hall terminal (4b) of H2. The Hall terminal (2a) of H1 is electrically connected to the Hall terminal (1b) of H2. Likewise, the Hall terminal (3a) of H1 is electrically connected to the Hall terminal (2b) of H2, and the Hall terminal (4a) of H1 is electrically connected to the Hall terminal (3b) of H2. By forming these bidirectional electrical connections between the Hall terminal of H1 and the Hall terminal of H2, the Hall elements (H1, H2) are effectively connected in parallel. The parallel connection of Hall elements (H1, H2) forms a Hall sensor (H) composed of four terminals: 1 (connection 1a - 4b), 2 (connection 2a - 1b), 3 (connection 3a - 2b), and 4 (connection 4a - 3b). The Hall elements (H1, H2) are orthogonally connected by the rectification of the terminals.As a result, the horizontal Hall sensor (H) features improved performance (e.g., reduced offset). As shown in FIG. 12c, the horizontal Hall elements (H1, H2) are placed within the internal volume (1001) of a multi-winding coil. Thus, the multi-winding coil is also suitable for testing and calibrating the Hall sensor (H) created by the orthogonal combination of H1 and H2. The principle of orthogonally combining two Hall elements by pairing terminals in a rectifying manner can be extended to four Hall elements in a simple manner. Those skilled in the art will understand that the principle of orthogonally combining two or four Hall elements can also be applied to vertical Hall elements. The vertical Hall sensor (H) created by the orthogonal combination of two or four vertical Hall elements can again be placed within the internal volume of a suitable multi-winding coil as shown in FIG. 12a. In the Hall sensor product (1300) of FIG. 13, other devices are placed within the multi-winding coil along with the Hall elements (H). For example, a vertical Hall element (H) is illustrated in FIG. 13, which is sensitive to a magnetic field component along the z-axis of the Hall element. Through silicon vias (140a-g, 141a-g) belong to a multi-winding coil suitable for inducing a uniform magnetic field in the z-direction inside. The Hall sensor plate of the Hall element (H) is arranged in the internal volume (1001) of the multi-winding coil. D1 and D2 represent semiconductor elements other than the Hall element. The large internal space of the multi-winding coil dedicated to testing and calibrating the Hall element in the Hall sensor product (1300) is also used for other devices.

[0037] delete

[0038] In the Hall sensor product (1400) of FIG. 14, the entire Hall (IC) is placed inside a multi-winding coil. In FIG. 14, the Hall (IC) denoted as IC includes a vertical Hall element (H) oriented so that the vertical Hall element is sensitive to the z-component of the magnetic field. The Hall (IC) and the Hall element (H) are placed inside (1001) of a multi-winding coil oriented so that a uniform magnetic field in the z-direction is induced inside. The Hall (IC) may include one or more vertical Hall elements sensitive to the z-component of the magnetic field. The basic concept of the Hall sensor product can also be extended to a case where the Hall (IC) includes a horizontal Hall element and a test and calibration coil.

[0039] Another Hall sensor product (1500) is illustrated in FIGS. 15A, 15B, 15C, and 15D. In FIG. 15A, which is a cross-sectional image of the Hall sensor product (1500) parallel to the xy plane, a vertical Hall element having a Hall sensor plate (103) and Hall terminals (1, 2, 3, 4) placed on a substrate (101) is illustrated. The illustrated vertical Hall element is sensitive to the z component of an external magnetic field. A winding loop of a first coil formed by a metal part (115) (left and right), through silicon vias (145) (left and right), a metal part (155) (left and right), vias (165) (left and right), vias (125), and metal bars (175 and 135) is illustrated. As indicated by 777, the vertical segment of the first coil is at a distance, i.e., far from the vertical Hall element illustrated in FIG. 15A. As described, when current is supplied through the coil, the winding is parallel to the xy plane, and a magnetic field in the z direction is induced inside the coil.

[0040] Furthermore, at the location of the illustrated vertical hole element, i.e., at a location far from the through silicon via (145), the magnetic field is induced mainly by the current flow through the metal bar (135, 175). A third metal layer (230) is arranged on the first side of the substrate (101) facing the carrier (20), and a third metal layer (270) is arranged on the second side of the substrate.

[0041] A second multi-winding coil is formed by metal layers (230, 270), and the xz plane orientation of this coil is rotated 90 degrees relative to the first coil. FIG. 15b is an aerial image showing the orientation of a metal bar (175) parallel to the xz plane (cut section (15B-15B')). FIG. 15c is an aerial image showing the orientation of a metal bar (275) parallel to the xz plane (cut section (15C-15C')). The vertical segments of the second coil are not shown in any of the figures, but it can be seen in FIG. 6 how these vertical segments can be set.

[0042] In FIG. 15a, 1001 represents an internal volume shared by the first (inner) and second (outer) multiple winding coils. When current (11) is supplied to the first coil, a magnetic field in the z-direction is induced in the volume (1001). When current (12) is supplied to the second coil, a magnetic field in the x-direction is induced in the volume (1001). By appropriately adjusting the currents (11 and 12), the absolute value of the z-direction magnetic field and the absolute value of the x-direction magnetic field may be the same. FIG. 15d provides another cut section of the Hall sensor product (1500) parallel to the xz plane, this time following the second surface (101b) (cut section (15D-15D'). Two vertical Hall elements (H1 and H2) are placed inside (1001) two multi-winding coils, one oriented to be sensitive to a magnetic field in the z-direction (H1) and the other oriented to be sensitive to a magnetic field in the x-direction (H2). The vertical Hall element (H1) is tested and calibrated by the first (inner) coil, and the vertical Hall element (H2) is tested and calibrated by the second (outer) coil.

[0043] The coil configuration of the Hall sensor product (1500) is used in the Hall sensor product (1600) to test and calibrate circular vertical Hall elements (see FIG. 16). FIG. 16 illustrates a cross section of the Hall sensor product (1600) along the second surface (101b). 145 indicates a plurality of through silicon vias belonging to the first (inner) and second (outer) multiple winding coils. The internal volume shared by the two coils is shown as 1001.

[0044] A circular vertical Hall element (CVH) is placed inside two coils so that a Hall sensor plate (103) is fully arranged within the volume (1001). The Hall sensor plate (103) has a ring shape and is transversely partitioned by two dielectric structures shown as 109. As illustrated, a plurality of n Hall terminals (1, 2, 3, n) are formed on the Hall sensor plate on the second surface (101b) of the substrate (101). A second plurality of Hall terminals (1', 2', 3, n') may be formed on the first surface (101a) of the substrate. The circular vertical Hall element (CVH) is sensitive to an external magnetic field parallel to the xz plane, i.e., the surfaces (101a and 101b) of the substrate. This type of vertical Hall element is particularly useful for angular position measurement applications. The circular vertical Hall element (CVH) is tested and calibrated by the combined operation of the first (inner) and second (outer) multiple winding coils.

[0045] In the Hall sensor product (1700) of FIG. 17, two coils are connected in series for testing and calibrating Hall elements. Referring to FIG. 17, a first coil labeled Cl is shown. A vertical Hall element (H1 Cl) is placed inside (1001) of the coil (C1). The vertical Hall element is oriented to be sensitive to an external magnetic field in the z-direction. The coil (Cl) is used to test and calibrate the vertical Hall element. Thus, the coil winding of the coil (C1) is oriented so that a magnetic field in the z-direction is induced into its interior (1001). C2 represents a second coil. A second vertical Hall element (H2) placed inside (1001) of the coil (C2) is shown. The vertical Hall element (H2) is oriented to be sensitive to an external magnetic field in the x-direction. The coil (C2) dedicated to testing and calibrating the vertical Hall element (H2) is oriented accordingly. Two coils (C1 and C2) are in series, and Hall elements (H1, H2) can be tested and calibrated simultaneously. The basic concept of the Hall sensor product (1700) applies when there are three or more test and calibration coils connected in series. In particular, it can be considered to have three coils (C1, C2 and C3), where Cl and C2 are used to test and calibrate two vertical Hall elements as in FIG. 17, and C3 is used to test and calibrate a horizontal Hall element. In this way, the 3D Hall sensor can be tested and calibrated by a coil setup consisting of a series connection of three coils (Cl, C2 and C3), one for each direction in space.

[0046] The Hall sensor product (18) illustrated in FIG. 18 includes a plurality of identical Hall elements, and only a subset of the identical Hall elements is equipped with an on-chip coil for testing and calibration. Referring to FIG. 18, four vertical Hall elements (H1, H2, H3, H4) are illustrated as examples. Only the vertical Hall element (H3) is placed inside (1001) of the multi-winding coil. The basic concept also applies to a plurality of identical horizontal Hall elements.

[0047] Another Hall sensor product (1900) is illustrated in FIG. 19, which is a cross-sectional image. Vertical Hall elements are formed on a substrate (101) belonging to a wafer (10). A Hall sensor plate (103) is disposed within the substrate (101). A dielectric structure (109) constrains the Hall sensor plate laterally. Hall terminals (1 and 2) are formed on a first surface (101a) of the substrate (101), and Hall terminals (3 and 4) are formed on a second surface (101b) of the substrate (101). The wafer (10) is attached to the wafer (20) with the first surface (101a) facing the carrier (20). In the Hall sensor product (1900), the carrier (20) is a structured wafer, for example, the carrier (20) is a CMOS wafer. In FIG. 19, the wafer (20) includes at least one metal layer (230) disposed on a substrate (201) and a dielectric structure (206). An electrical connection between the metal layer (130) of the substrate (101) and the metal layer (230) of the substrate (201) can be formed by hybrid bonding.

[0048] By this technique known in the art, direct bonding between dielectric structures (oxides) (106, 206) is achieved, while electrical connection is established by copper-to-copper bonding. In FIG. 19, 2313b and 1323b represent such copper-to-copper bonding. Other techniques for wafer stacking are known in the art and may also be used in Hall sensor products (1900). A third wafer (30) is provided, having at least one metal layer (370) embedded in a substrate (301) and a dielectric structure (306). The wafer (30) is attached to the wafer (10) such that the dielectric structure (306) faces the dielectric structure (182) of the wafer (20). The electrical connection between the wafer (30) and the wafer (20) is preferably established in the same manner as the electrical connection between the wafer (20) and the wafer (10), and is thus re-established by a hybrid bonding technique as illustrated in FIG. 19, for example. 1737b and 3717b represent copper-to-copper bonds between substrates (101 and 301).

[0049] As additionally illustrated in FIG. 19, a coil for testing and calibrating a vertical Hall element is formed, which extends across all three wafers (10, 20, 30). In particular, the transverse segments (370b and 230b) of the coil are formed by the metal layers of the wafers (30, 20). The Hall sensor plate (103) of the vertical Hall element is located inside (1001) of a multi-winding coil extending across the three wafers (10, 20, 30).

[0050] The basic concept of the Hall sensor product (1900) can also be applied to horizontal Hall elements. In this case, the first spiral coil is formed by the metal layer (230) of the substrate (201). The second spiral coil is formed by the metal layer (370) of the substrate (301). To connect the two spiral coils in series, electrical connection between the wafers is required through through silicon vias. This may be the same type of structure shown and discussed in relation to FIG. 19.

[0051] The Hall sensor product (2000) of FIG. 20 is another Hall sensor product in which a coil for testing and calibrating the Hall element extends across three substrates. However, unlike the Hall sensor product (1900), the three substrates are stacked at the die level rather than the wafer level. That is, the connection is performed after singulation during the assembly process. Referring to FIG. 20, a vertical Hall element is formed on the substrate (101). A Hall sensor plate (103) is placed on the substrate (101). A dielectric structure (109) defines the Hall sensor plate in the transverse direction. Hall terminals (1 and 2) are formed on the first surface (101a) of the substrate (101), and Hall terminals (3 and 4) are formed on the second surface (101b) of the substrate (101). A carrier wafer is required for processing the second side of the substrate (201). However, this carrier wafer is a temporary carrier and is not part of the final Hall sensor product. In FIG. 20, temporary is no longer indicated.

[0052] After the manufacturing process of the substrate (101) is completed, the substrate (101) is singulated into a die. In FIG. 20, 10 represents a single die comprising at least one vertical hole element. Another die (20) is provided comprising at least two metal layers (230, 250) embedded in the substrate (201) and the dielectric structure (206). Additionally, another die (30) is provided comprising at least two metal layers (370, 350) embedded in the substrate (201) and the dielectric structure. Electrical connections between the die (10) and the die (20) are established by copper or solder bumps, such as the bumps (2513b and 1325b) shown in FIG. 20. Similarly, electrical connections between the die (30) and the die (20) are established by copper or solder bumps, such as the bumps (1735b and 3517b) shown in FIG. 20. Such assembly processes are known in the art and may deviate in some aspects and details from the foregoing discussion.

[0053] Referring again to FIG. 20, a coil for testing and calibrating a vertical Hall element is formed, which extends over the die (30), die (10), and die (20). In particular, the transverse segments of the coils (230b and 370b) are formed by the metal layers of the respective substrates (201 and 301). As with the Hall sensor product (1900), the basic concept of the Hall sensor product (2000) can also be applied to the horizontal Hall element. In this case, the first spiral coil will be formed by the metal layer (230) of the substrate (201) (die (20)). The second spiral coil will be formed by the metal layer (370) of the substrate (301) (die (30)). The electrical series connection of the spiral coils has the same structure as the vertical portion of the coil shown in FIG. 20. Now, manufacturing process steps of the Hall sensor product (100) of FIGS. 1a to 1c are disclosed as examples with reference to FIGS. 21a to 22m.

[0054] As illustrated in FIG. 21a, a wafer (10) comprising a semiconductor substrate (101) having a first surface (101a) and a second surface (101c) is provided. The substrate (101) is preferably a silicon substrate of a first conductive type that is n-type. Two shallow high-doping regions (1, 2) having a first conductive type are formed on the first surface (101a). The two high-doping regions (1, 2) extend from the surface (101a) to the semiconductor substrate (101). The high-doping regions (1, 2) are created by resist removal and laser thermal annealing after photomask injection. The high-doping regions (1, 2) have n-type conductivity and extend to the surface (10b). The doping concentration may be in the range of 1020 atoms / cm3 to 1022 atoms / cm3. In laser thermal annealing, the wafer receives very short thermal pulses so that heat can penetrate the silicon only to a limited depth depending on the pulse time, energy dose, and wavelength. The depth of the highly doped region can range from 50 nanometers to 200 nanometers.

[0055] As illustrated in FIG. 21b, a dielectric structure (104) is deposited on the surface (10b). The dielectric structure may be TEOS (tetraethyl orthosilicate) deposited by PECVD (plasma-enhanced chemical vapor deposition). By a photo-masked etching process, first and second openings are etched through the oxide layer (104) so ​​that a highly doped region (1) is exposed. A first metal layer (110) is deposited on the dielectric structure (104). The first metal layer (110) is formed by a photo-masked etching step as illustrated in FIG. 21b, which fills two openings below the portions, leaving portions (110b, 112, 111, 111b). Refer to 111 and 112 so that the metal comes into contact with the exposed highly doped silicon regions (1 and 2). The metal layer is preferably an aluminum-based metal stack comprising a titanium adhesive layer, a titanium nitride barrier layer, an aluminum layer, and a titanium nitride cap layer.

[0056] A first dielectric structure (105) is deposited on top of a metal structure (110) and an exposed oxide layer (104). The first dielectric structure (105) is flattened by chemical mechanical polishing (CMP). Silicon vias (121b) are etched by anisotropic dry etching through the dielectric structure (105), which selectively stops at a titanium nitride barrier layer of the metal structure (111b). The silicon vias are filled with a tungsten-based layer. Preferably, a second metal layer (130) of an aluminum-based or copper-based layer is deposited on the dielectric structure (105) and configured to leave a portion (130b). Then, a third dielectric structure (106) is deposited on top of the second metal layer (130b) and the exposed first dielectric structure (105). The third dielectric structure (106) is flattened by chemical mechanical polishing (CMP).

[0057] Referring to FIGS. 21c and 21d, the wafer (10) is flipped and attached to the surface of the second wafer (20) together with the third dielectric structure surface (106a). The second wafer (20) may be a carrier wafer or a CMOS wafer containing an integrated circuit necessary for the operation of a vertical Hall element. Permanent bonding is achieved between the wafer (10) and the wafer (20). Several methods for permanent wafer bonding are known. An example of a bonding process is described in the applicant’s aforementioned international application WO 2020 / 104998 A1. Using the CMOS wafer (20) as a carrier wafer, the Hall sensor wafer (10) is processed from its rear surface (101c).

[0058] As shown in FIG. 21e, the wafer (10) is thinned from the back side, removing most of the silicon material. The resulting second substrate surface of the wafer (10) after thinning is indicated as 101b. The thickness of the remaining semiconductor substrate (101) may preferably be in the range of 10 to 50 micrometers.

[0059] Referring further to FIG. 21f, shallow and high-doping regions (3, 4) having n-type conductivity are formed on the second surface (101b) in the same manner as the high-doping regions (1, 2) on the first surface. In particular, the same implant species, injection dose, and energy used to create the doping regions (1 and 2) on the first surface are used. More specifically, the same laser thermal annealing conditions applied to the first surface are applied after resist removal to activate the doping regions (1 and 2). As understood by those skilled in the art, by using laser thermal annealing for dopant activation on the second surface, the aluminum-based metallization on the first surface of the Hall sensor wafer (10) can be as follows: Unlike other activation methods such as furnace annealing or rapid thermal processing, it prevents breakage by heat treatment. Furthermore, laser thermal annealing does not add to the thermal budget of the device formed on the CMOS wafer (20).

[0060] As illustrated in FIG. 21g, a dielectric structure (109) is created and extends from the second surface (101b) of the substrate layer (101) to the first surface (101a), and laterally surrounds a portion of the substrate layer (101) that includes a Hall sensor region (Hall sensor plate) (103). The dielectric structure is created by a deep trench separation process well known in the art.

[0061] Referring to FIG. 21h, the first dielectric structure (107) is deposited on the second surface (101b) using the same process and material used for the first dielectric structure (104) of the first side.

[0062] Referring to FIG. 21i, a deep silicon etching process is performed using a silicon nitride layer as a hard mask to form via openings (11). The deep silicon etching is first optionally stopped on the oxide layer (104). A thin oxide layer (181) is deposited. More specifically, the layer (181) may be tetraethyl orthosilicate (TEOS) deposited by plasma-enhanced chemical vapor deposition (PECVD) at a temperature of 400°C or lower. The oxide layer (181) serves as a dielectric liner on the silicon sidewalls exposed by the preceding deep silicon etching. The thickness of the oxide layer (181) may be, for example, 3000 Angstroms, but is not limited thereto.

[0063] Then, a thin oxide (181) is etched through the bottom of the deep silicon via opening (11). Dry etching is optionally stopped at the titanium nitride barrier layer of the metal structure (110). The via opening (11) is filled with a metal layer, which is a tungsten-based metal layer, more preferably a copper-based metal layer.

[0064] Referring to FIG. 2, the contact trench or hole (17) is formed by a photomask etching process through the dielectric structure (107) to expose the high-doping region (3, 4). Thanks to high selectivity for silicon, etching can be stopped within the shallow high-doping region (3 and 4), ensuring that the doping concentration on the silicon surface inside the trench or hole (17) is in the range of 1020 atoms / cm3 to 1022 atoms / cm3.

[0065] A first metal layer (150) is deposited on the dielectric structure (107) and fills the contact trench or hole (17). A similar process and material are applied to the metal layer (110) on the first surface. After deposition, the metal layer is structured by a photomask etching process as shown in FIG. 21. As shown, the metal structure (150) completely covers the upper surface of the through-silicon vias (140b, 141b) and achieves an electrical connection between the two through the through-silicon vias.

[0066] Next, an intermetallic dielectric structure (108) is deposited on top of the metal structure (150). Similar processes and materials used for the first side intermetallic dielectric (105) are also used. As illustrated in FIG. 21m, via structures are etched through the intermetallic dielectric structure (108) and filled with metal layers (160b and 161b). Next, a second metal layer (170) is deposited on top of the intermetallic dielectric structure (108) and configured to electrically connect the vias (160b, 161b) by a metal portion (170b). The processes and materials for filling the vias with metal and forming the metal layer portion (170b) are similar to those for the second metal layer (130) on the first side of the substrate. Finally, a dielectric structure (182) is deposited on top of the metal structure (170) and on the exposed intermetallic dielectric structure (108).

[0067] The advantages of the proposed solution are evident from the foregoing description. In particular, the Hall sensor is configured such that n inductor coils for testing and calibration induce a uniform and homogeneous magnetic field on the Hall sensor plate of a vertical or horizontal Hall sensor element. Finally, it is evident that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the invention, as defined in the appended claims.

Claims

Claim 1 As an integrated Hall sensor, a main wafer (10) of a semiconductor material having a substrate (101) having a first surface (101a) and a second surface (101b) facing the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') disposed on at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) of the substrate (101) forming a Hall sensor plate (103) of the integrated Hall sensor, wherein the Hall sensor terminals are arranged inside the isolation structure (109), and the integrated Hall sensor forms an internal volume (1001) that completely surrounds the Hall sensor plate (103) and metal portions (130b, 170b) arranged on the first and second surfaces (101a, 101b) of the substrate (101); The apparatus further comprises at least one test and calibration coil (C1) integrated within a main wafer (10) having a plurality of windings formed at least partially by 130a, 170a), wherein the test and calibration coil (C1) comprises: a first metal portion (130b; 130a) formed within a metal layer (130) formed on a first dielectric structure (104, 105) arranged on a first surface (101a) of a substrate (101); and a second metal portion (170b) formed within each metal layer (170) formed on a second dielectric structure (107, 108) arranged on a second surface (101b) of a substrate (101).170a) and a substrate (101) including a through silicon via (140b) extending from a second surface (101b) to a first surface (101a) of the substrate (101), a third dielectric structure (106) is arranged on a first dielectric structure (104, 105), the main wafer (10) is attached to the upper surface of the third dielectric structure (106) on a second wafer (20), the second wafer (20) is configured to thin the main wafer (10) from the second surface (101b), and the second wafer (20) is configured to thin the main wafer (10) from the second surface (101b) to a thickness in the range of 10 micrometers to 50 micrometers. Claim 2 An integrated Hall sensor according to claim 1, comprising at least one Hall sensor element (H1) having a second sensor terminal (3, 4, 1, 2, 3, 4) formed on a second surface (101b) of a substrate (101) facing a first sensor terminal and a first sensor terminal (1, 2; 1', 2', 3', 4') formed on a first surface (101a) of the substrate (101), wherein the isolation structure (109) includes a dielectric structure extending from the second surface (101b) to the first surface (101a) of the substrate (101) which laterally surrounds a portion of the substrate (101) forming a Hall sensor plate (103). Claim 3 In paragraph 2, the first dielectric structure (104, 105) is an integrated Hall sensor having the same thickness as the second dielectric structure (107, 108). Claim 4 In paragraph 2, an integrated Hall sensor comprising additional Hall sensor elements (H2, H3, H4) completely enclosed by an internal volume (1001) formed by a test and calibration coil. Claim 5 In paragraph 4, an integrated Hall sensor is an orthogonal coupling element that jointly forms a Hall sensor (H) designed such that at least some of the Hall sensor elements are tested and calibrated by a test and calibration coil. Claim 6 An integrated Hall sensor according to paragraph 2, further comprising an integrated circuit (IC) arranged in an internal volume (1001) formed by a test and calibration coil. Claim 7 In claim 2, the invention comprises a second wafer (20) having at least one metal layer (230) arranged on a dielectric structure (206) formed on each substrate (201), wherein the second wafer (20) is attached to the main wafer (10) on a first surface (101a) of the substrate (101), and the dielectric structure (206) faces the same first surface (101a), and a third wafer (30) having at least one metal layer (370) arranged on a dielectric structure (206) formed on each substrate (301), wherein the third wafer (30) is attached to the main wafer (10) on a second surface (101b) of the substrate (101), and the dielectric structure (306) faces the same second surface (101b), and the portion of the metal layer (230, 370) of the second and third wafers (20, 30) is a test An integrated Hall sensor that contributes to the formation of the winding of the test and calibration coil, and whose internal volume (1001) surrounds the Hall sensor plate (103) of the vertical Hall element and extends across the main wafer (10) and the second and third wafers (20, 30). Claim 8 In claim 7, at least one of the second and third wafers (20, 30) is an integrated Hall sensor, which is a CMOS wafer integrated circuit for operating a vertical Hall element. Claim 9 An integrated Hall sensor according to claim 2, wherein each internal volume (1001) that completely surrounds the Hall sensor plate of an additional Hall sensor element (H2) is further formed and further includes an additional test and calibration coil (C2) and at least one additional Hall sensor element (H2) integrated within the main wafer (10), and one or more test and calibration coils (C1 and C2) are connected in series so that one or more additional Hall sensor elements (H1 and H2) can be tested and calibrated simultaneously. Claim 10 An integrated Hall sensor according to claim 1, comprising one or more vertical Hall sensor elements (H1) having a first pair of Hall sensor terminals (1, 2) formed on a first surface (101a) of a substrate (101) and a second pair of Hall sensor terminals (3, 4) formed on a second surface (101b) of the substrate (101) facing the first pair of Hall sensor terminals. Claim 11 In claim 10, the Hall sensor terminals (1, 2, 3, 4) extend along a first horizontal axis (z) of a plane parallel to the first and second surfaces (101a, 101b) of the substrate (101), and the first and second metal parts (130b, 170b) extend along a second horizontal axis (x) of the plane crossing the first horizontal axis (z); and the windings of the test and calibration coils each have a rectangular cross-section in a plane formed by the second horizontal axis (x) and the vertical axis (y), are connected in series, and are arranged along the first horizontal axis (z) of the integrated Hall sensor. Claim 12 In claim 10, the through silicon vias (140b, 141b) are integrated Hall sensors having the same transverse distance to the Hall sensor plate (103). Claim 13 In claim 10, the through silicon vias (140b, 141b) forming the winding of the test and calibration coils are spaced apart from the Hall sensor plate (103) so as not to contribute to the magnetic field induced in the Hall sensor plate (103), in the integrated Hall sensor. Claim 14 In claim 10, the external coil further comprises an external coil formed on a main wafer (10) having a plurality of windings, wherein the external coil comprises: a first metal portion (230b) formed on a third dielectric structure (106) arranged on a first dielectric structure (104, 105); a second metal portion (270b) formed on a second external dielectric structure (182) arranged on a second dielectric structure (107, 108); and a through silicon via (142b, 143b) extending through the substrate (101) and coupled to each of the first and second metal portions (230b, 270b), and the external coil is connected in series to a test and calibration coil, an integrated Hall sensor. Claim 15 An integrated Hall sensor according to claim 10, further comprising an external coil formed within a wafer (10) having a plurality of windings, wherein the external coil comprises a first metal portion (234) formed on a third dielectric structure (106) arranged on a first dielectric structure (104, 105), and a second metal portion (275) formed on a second external dielectric structure (182) arranged on a second dielectric structure (107, 108), and wherein the orientation of the external coil is rotated 90° with respect to the test and calibration coil. Claim 16 In paragraph 15, the vertical Hall sensor element is a circular vertical Hall element (CVH), and the Hall sensor plate (103) is an integrated Hall sensor having a ring shape arranged entirely in an internal volume (1001) formed by an external and test and calibration coil. Claim 17 An integrated Hall sensor according to claim 1, comprising a first set of doped regions (1', 2', 3', 4') formed on a first surface (101a) of a substrate (101) and a second set of doped regions (1, 2, 3, 4) formed on a second surface (101b) of a substrate (101) facing the first set of doped regions, and further comprising a horizontal Hall element of a Hall sensor terminal. Claim 18 In claim 17, the first and second windings (130a, 130b) are arranged facing each other and surround the Hall sensor plate (103), forming an integrated Hall sensor. Claim 19 In claim 17, the test and calibration coil is an integrated Hall sensor formed at least partially by through silicon vias (140) that surround a horizontal Hall element transversely and surround an isolation structure (109). Claim 20 In paragraph 17, the test and calibration coil is an integrated Hall sensor having a helical configuration. Claim 21 A method for manufacturing an integrated Hall sensor comprises: a. providing a main wafer (10) having a substrate (101) having a second surface (101b) and a first surface (101a); b. forming a Hall sensor terminal on a first side of the main wafer (10) by forming a doped region (1, 2) having a first conductive type on the first surface of the main wafer (10); c. contacting the Hall sensor terminal by filling first and second openings formed in the first dielectric structure (104) among the first dielectric structures (104, 105) with a first metal layer (110); d. forming a silicon via through a second dielectric structure that is stopped at the top of the first metal layer (110) and depositing the first dielectric structure (105) among the first dielectric structures (104, 105), and filling the silicon via with a tungsten-based layer; A step of forming a first winding of a test and calibration coil by depositing a second metal layer (130) on a second dielectric structure and etching the metal layer in a portion (130b); e. A step of depositing and flattening a third dielectric structure (106) on the exposed first dielectric structure (105) and the second metal layer (130) among the first dielectric structures (104, 105); f. A step of flipping the main wafer (10) and attaching the second wafer (20) by permanently bonding it onto the third dielectric structure (106), and thinning the main wafer (10) from the second surface (101b) to a thickness in the range of 10 micrometers to 50 micrometers; g. A step of forming a Hall sensor terminal on the thinned second surface (101b) of the main wafer (10) by forming a doped region (3, 4) having a first conductive type on the thinned second surface (101b) of the substrate (101) of the main wafer (10); h.A step of forming the isolation structure (109) extending from the thinned second surface (101b) to the first surface (101a) of the substrate (101) by a deep trench isolation process and transversely surrounding a portion of the substrate (101) including a Hall sensor region (103); i. depositing a second dielectric structure (107) on the thinned second surface (101b), forming through silicon vias (11) by a deep silicon etching process, optionally stopping at the top of the first metal layer (110), and filling the through silicon vias (11) with a tungsten-based or copper-based metal layer (141b); l. m. A step of contacting the Hall sensor terminals (3, 4) on the thinned second surface (101b) of the main wafer (10) by filling the through hole formed within the second dielectric structure (107) with the first metal layer (150); m. A step of depositing the second dielectric structure (108) on the upper part of the first metal layer (150) and forming silicon vias (160b, 161b) through the second dielectric structure (108) which stops at the upper part of the first metal layer (150), and filling the silicon vias (160b, 161b) with a tungsten base layer; and a step of forming the second winding of the test and calibration coil by depositing the second metal layer (170) on the second dielectric structure and etching the second metal layer (170) with the metal structure (170b); n. A method comprising the step of depositing a third dielectric structure (182) on the exposed second dielectric structure (108) and on top of the second metal layer (170).

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