Memory Fault Data Transmission Apparatus and Method Based on Repairability

Abstract

A method for transmitting memory failure information according to an embodiment of the present invention relates to a method for transmitting test information about a memory to a server, and may include the steps of: storing overall failure information obtained by testing the memory in a first storage space; storing a failure address and repair-related information among the overall failure information in a second storage space; determining whether the memory is repairable based on the information stored in the second storage space; and transmitting the information stored in the second storage space to a server if the memory is repairable, and transmitting the information stored in the first storage space to a server if the memory is not repairable.

Description

Technology Field

[0001] The present invention relates to a device and method for transmitting memory failure information, and more specifically, to a memory information processing technology that selectively compresses and transmits memory failure information based on repairability. Background Technology

[0002] Memory semiconductors have established themselves as essential components in modern electronic systems that require both high-speed data processing and large-capacity storage. Due to the complexity of manufacturing processes and increasing integration density, these memory devices are susceptible to various types of failure; in particular, failures caused by cell-level defects, row or column-level damage, and electrical interference are frequently reported. Since these failures can degrade product reliability and severely impact the overall system performance, precise testing and failure analysis must be performed during the mass production phase.

[0003] Against this backdrop, various test algorithms have been applied in conventional technology to guarantee the quality of memory devices. Generally, test devices determine whether there is an operational abnormality in a memory cell by recording a specific pattern of data into the cell and then reading and comparing it. When a fault is detected, the most commonly used method involves identifying the corresponding location or range and recording it as separate fault information, or transmitting it to an internal or external analysis system within the test device. Furthermore, some technologies classify functional defects in the memory based on test results and utilize this information to determine classification based on error rates or to decide whether to discard the device.

[0004] However, existing technologies adopt a structure that processes and transmits all data in the same manner regardless of the intended use of the failure information, leading to a problem where the volume of transmitted data and the load on server analysis increase excessively as memory capacity grows. In particular, by transmitting data without distinguishing between repairable and unrepairable failures, unnecessary data can hinder the speed and efficiency of repair procedures. These limitations are becoming more pronounced as the commercialization of high-density memory accelerates, and the need for new methods for the efficient classification and utilization of failure information is emerging. Prior art literature

[0005] Korean Registered Patent Publication No. 10-0750416 ("Memory array test method and memory-based device", Publication Date: August 9, 2001) The problem to be solved

[0006] To solve the aforementioned problem, the present invention aims to provide a repairability-based memory failure information transmission device and method capable of simultaneously improving repair efficiency and data processing efficiency by storing all failure information obtained by testing a memory, separately storing information related to repair among them, and selectively transmitting different failure information to a server depending on whether the memory is repairable. means of solving the problem

[0007] A method for transmitting memory failure information according to an embodiment of the present invention relates to a method for transmitting test information about a memory to a server, and may include the steps of: storing overall failure information obtained by testing the memory in a first storage space; storing a failure address and repair-related information among the overall failure information in a second storage space; determining whether the memory is repairable based on the information stored in the second storage space; and transmitting the information stored in the second storage space to a server if the memory is repairable, and transmitting the information stored in the first storage space to a server if the memory is not repairable.

[0008] According to one embodiment, the first storage space may be characterized by having a Fault bitmap structure that records, in 1-bit units, which address in memory has a fault.

[0009] According to one embodiment, the second storage space may be characterized as being a Content Addressable Memory (CAM).

[0010] According to one embodiment, the second storage space may be characterized by having a two-stage storage structure including a main CAM that stores the address of a fault that occurred as a representative address when the fault that occurred is the first fault that occurred in the row and column of the address of the fault, and a sub CAM that stores information about other faults that occurred in the same row and column as the representative address.

[0011] According to one embodiment, the main CAM may be characterized by storing information including a row address, a column address of a representative address, and a flag indicating whether the fault must be repaired.

[0012] According to one embodiment, a flag indicating whether a fault must be repaired may be characterized as information determined based on memory reserve resources pre-allocated in the row and column directions of the fault.

[0013] According to one embodiment, the sub CAM may be characterized by storing information including a pointer indicating whether another fault is associated with a representative address stored in the main CAM, and a row address or column address of the other fault.

[0014] According to one embodiment, the sub-CAM may be characterized in that, among the information regarding other faults, information that overlaps with the representative address associated with the other fault is not stored.

[0015] According to one embodiment, the step of determining whether the memory is repairable may be characterized by determining whether it is repairable based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions.

[0016] According to one embodiment, the step of determining whether the memory is repairable may be characterized by determining that it is unrepairable when all the storage space of the second storage space is exhausted.

[0017] According to one embodiment, the memory failure information transmission method may further include the step of repairing the memory by using the information of the second storage space received by the server as an input for executing a preset repair algorithm when repair is possible.

[0018] According to one embodiment, the step of repairing memory may be characterized by repairing the memory by utilizing memory reserve resources pre-allocated in the row and column directions of the failure.

[0019] According to one embodiment, the memory failure information transmission method may further include the step of using information of a first storage space received by a server as data for process abnormality pattern analysis when repair is impossible.

[0020] According to one embodiment, the memory failure information transmission method may further include a step of compressing the information before transmitting it to a server.

[0021] According to one embodiment, the test may be characterized by detecting whether a fault exists by performing a pattern-based inspection that generates fault information by applying a test pattern generated from a pattern generator to a memory.

[0022] A memory failure information transmission device according to one embodiment of the present invention relates to a device for transmitting test information about a memory to a server, and may include a storage unit comprising a first storage space in which overall failure information obtained by testing the memory is stored, and a second storage space in which a failure address and repair-related information among the overall failure information is stored; a judgment unit for determining whether the memory is repairable based on the information stored in the second storage space; and a communication unit for transmitting the information stored in the second storage space to a server if the memory is repairable, and the information stored in the first storage space if the memory is not repairable.

[0023] According to one embodiment, the first storage space may be characterized by having a Fault bitmap structure that records, in 1-bit units, which address in memory has a fault.

[0024] According to one embodiment, the second storage space may be characterized as being a Content Addressable Memory (CAM).

[0025] According to one embodiment, the second storage space may be characterized by having a two-stage storage structure including a main CAM that stores the address of a fault that occurred as a representative address when the fault that occurred is the first fault that occurred in the row and column of the address of the fault, and a sub CAM that stores information about other faults that occurred in the same row and column as the representative address.

[0026] According to one embodiment, the main CAM may be characterized by storing information including a row address, a column address of a representative address, and a flag indicating whether the fault must be repaired.

[0027] According to one embodiment, a flag indicating whether a fault must be repaired may be characterized as information determined based on memory reserve resources pre-allocated in the row and column directions of the fault.

[0028] According to one embodiment, the sub CAM may be characterized by storing information including a pointer indicating whether another fault is associated with a representative address stored in the main CAM, and a row address or column address of the other fault.

[0029] According to one embodiment, the sub-CAM may be characterized in that, among the information regarding other faults, information that overlaps with the representative address associated with the other fault is not stored.

[0030] According to one embodiment, the judgment unit may be characterized by determining whether repair is possible based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions.

[0031] According to one embodiment, the judgment unit may be characterized by determining that repair is impossible when all of the storage space of the second storage space is exhausted.

[0032] According to one embodiment, the server may be characterized by using information from a second storage space received by the server as input for executing a preset repair algorithm to repair the memory when repair is possible.

[0033] According to one embodiment, the server may be characterized by repairing memory by utilizing memory reserve resources pre-allocated in the row and column directions of the failure.

[0034] According to one embodiment, the server may be characterized by using information from a first storage space received by the server as data for analyzing process abnormal patterns when repair is impossible.

[0035] According to one embodiment, the memory failure information transmission device may include a compression unit that compresses the information before transmitting it to a server.

[0036] According to one embodiment, the test may be characterized by detecting whether a fault exists by performing a pattern-based inspection that generates fault information by applying a test pattern generated from a pattern generator to a memory. Effects of the invention

[0037] A memory failure information transmission device and method according to one embodiment of the present invention can simultaneously improve repair efficiency and data processing efficiency by storing all failure information obtained by testing a memory, separately storing information related to repair among them, and selectively transmitting different failure information to a server depending on whether the memory is repairable. Brief explanation of the drawing

[0038] FIG. 1 is a block diagram of a memory failure test and repair system according to one embodiment. FIG. 2 is a schematic diagram showing the result of determining whether there is a memory failure according to a memory test according to one embodiment. FIG. 3 is a schematic diagram of a memory repair process according to one embodiment. FIG. 4 is a block diagram of a memory failure information transmission device according to one embodiment. FIG. 5 is a schematic diagram showing a memory failure according to one embodiment as a fault bitmap. FIGS. 6 and 7 are schematic diagrams illustrating a two-stage structure of a second storage space and information stored therein according to one embodiment. FIGS. 8 to 10 are schematic diagrams illustrating a compression method of a fault bitmap according to one embodiment. FIG. 11 is a diagram showing a flowchart and an example of a compression algorithm performed on a fault address stored in a CAM according to one embodiment. FIGS. 12 to 15 are flowcharts of a memory failure information transmission method according to each embodiment. Specific details for implementing the invention

[0039] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0040] The terms used in this specification will be briefly explained, and the invention will be described in detail.

[0041] The terms used in this invention have been selected based on currently widely used general terms, taking into account their functions within the invention; however, these terms may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms have been arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the invention.

[0042] When a part of a specification is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0043] Below, embodiments of the present invention are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the invention. Additionally, parts of the drawings that are irrelevant to the description are omitted to clearly explain the invention.

[0044] Terms including ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of multiple related items or any one of the multiple related items.

[0046] Hereinafter, the testing of a memory semiconductor, a repair system thereof, and the memory fault information transmission device and method of the present invention for increasing the efficiency thereof will be described.

[0047] In modern information processing systems, the performance and reliability of memory semiconductors serve as key factors determining the overall system quality. As memory devices become more highly integrated and faster, the likelihood of minute defects occurring during the manufacturing process increases; therefore, it is crucial to detect these defects in advance and respond appropriately during the mass production phase. To this end, memory testing has established itself as an essential process that goes beyond simple defect detection to ensure yield, quality control, and ultimately, product market competitiveness. Furthermore, repair processes based on test results function as a vital means to reduce resource waste and increase production efficiency.

[0048] In the manufacturing process of memory semiconductors, various test equipment and algorithms are utilized to verify the normal operation of the product in advance. Generally, test devices include pattern generators and comparators, and determine the presence of failures by writing data to memory cells and reading and comparing them. The failure information detected during this process is used to diagnose the operational status of the memory and to identify defects that do not meet quality standards. Particularly for highly integrated memory products, precise and high-speed testing is required due to the vast amount of test data and the increasing complexity of failure patterns.

[0049] After testing, repairable and non-repairable memory are distinguished; if repairable, a repair operation is performed to replace the faulty cell using pre-allocated reserve resources. This repair system plays the role of recovering defects by executing repair algorithms on a server or external processing unit based on fault information acquired from the test device to determine the optimal allocation of reserve resources and applying them to the memory. Therefore, the key to a memory test and repair system lies in the accurate acquisition of fault information and the design of an information flow that effectively utilizes this information according to the intended purpose.

[0050] The memory fault information transmission device and method of the present invention are incorporated within the aforementioned memory test and repair system, thereby maximizing efficiency in the process of storing and transmitting fault information. The memory fault information transmission device and method of the present invention can improve the processing efficiency of the entire system by separating and storing fault information acquired during or immediately after testing according to its intended use, determining whether repair is possible, and selectively transmitting information necessary for repair or analysis based on the determination result. Through this, the amount of fault information transmitted is minimized, the load on the server side is reduced, support is provided for rapid repair of memory subject to repair, and data necessary for process anomaly analysis for memory that cannot be repaired can be effectively provided.

[0051] FIG. 1 is a block diagram of a memory failure test and repair system (1) according to one embodiment.

[0052] Referring to FIG. 1, the memory failure test and repair system (1) may include a memory (20), a test device (30), a server (40), and a memory failure information transmission device (10). Each component included in the system may transmit and receive data to and from each other through various devices and communication methods.

[0053] Memory (20) is an element subject to failure testing and repair in the memory failure testing and repair system (1) and may include a general memory device. For example, memory (20) may include one or more of various types of semiconductor memory such as DRAM, SRAM, flash memory, MRAM, ReRAM, etc., but is not limited to these examples. Memory (20) may be configured to be externally controlled and observed by a test device (30) within the system, and may be configured so that if repair is possible according to the test results, a repair algorithm is executed through a server (40) to recover the faulty cell, and if repair is impossible, it is utilized for subsequent processing such as process analysis.

[0054] The test device (30) can determine whether there is a fault by performing various pattern-based inspections on the memory (20). Generally, the test device (30) may include a pattern generator that generates test patterns, a comparator that determines test results, and a fault detection unit that collects and records fault information. The test device (30) records data in each cell of the memory (20), reads it back, and detects a fault by comparing it with an expected value; the fault information generated during this process can be used as basic data for subsequent repair judgment and process analysis. The test device (30) may be integrated into the system or configured as a separate external device, and in a mass production environment, it is generally implemented with a high-speed processing structure to inspect multiple memories (20) at high speed.

[0055] FIG. 2 is a schematic diagram showing the result of determining whether a memory (20) is faulty according to a memory test according to one embodiment. Referring to FIG. 2, the vertical axis and the horizontal axis in the drawing represent the column and row of the memory (20), respectively, and each grid represents an individual memory cell. A cell marked with an 'X' indicates a location where a fault was detected during the test process, and indicates that the operation of the corresponding cell is abnormal. In this way, the location of the fault is visualized in the form of a two-dimensional array, so that it can be used as reference data to identify the distribution of faults concentrated in a specific row or column or to determine the possibility of repair.

[0056] The server (40) receives fault information transmitted from the memory fault information transmission device (10) in the memory fault test and repair system (1) and performs the execution of a repair algorithm or process anomaly analysis.

[0057] For a memory (20) that is repairable, the server (40) executes a predefined repair algorithm based on the received fault address information and can derive a method for allocating spare resources to bypass or replace the faulty cell of the memory (20). The derived repair result is applied to the memory (20) through the system control unit, thereby enabling the product's functionality to be restored and converted into a good product.

[0058] FIG. 3 is a schematic diagram of a memory repair process according to one embodiment. Referring to FIG. 3, each server (40) can repair the corresponding memory failure part by utilizing redundancy allocated to the columns and rows of the memory (20).

[0059] Meanwhile, regarding the unrepairable memory (20), the server (40) can analyze information such as the received total failure bitmap to derive recurring defect patterns in the process or defect concentration phenomena in specific structures. These analysis results can be used to diagnose problems in the manufacturing process, improve quality control standards, and increase production yield. Therefore, by utilizing the failure information branched according to repairability for the intended purpose, the server (40) can advance the memory repair and quality analysis procedures and improve the overall efficiency of the system.

[0060] The operation regarding memory repair and process abnormality analysis of the server (40) will be described later.

[0062] Hereinafter, the memory failure information transmission device (10) of the present invention will be described.

[0063] The memory fault information transmission device (10) and method of the present invention can maximize data processing efficiency by classifying fault information generated during the memory test process according to repairability and selectively transmitting it according to the purpose. More specifically, fault information obtained during the test is stored, and among these, information directly related to repair is managed separately. Then, the repairability of the memory (20) is determined, and different types of fault information can be transmitted according to the result. Through this, the memory fault information transmission device (10) and method of the present invention can flexibly utilize test results for repair purposes or process analysis purposes, and can increase the processing efficiency of the entire system through structural separation of fault information and branching of the transmission path.

[0064] The present invention can improve the speed and efficiency of the repair procedure by selectively extracting and transmitting the minimum information required for repair for repairable memory (20), and can increase the precision of process abnormality analysis by transmitting the entire failure information for unrepairable memory (20). Unlike conventional technology, the present invention can reduce the amount of data transmitted and alleviate the analysis burden on the server (40) through purpose-based differential processing of failure information and branching of the transmission path, and can provide structural advantages that enable yield management and quality control to be performed more quickly and precisely, especially in large-capacity and high-density memory environments.

[0065] The memory fault information transmission device (10) of the present invention may be implemented by being composed of separate devices for performing the fault information transmission operation described below. For example, the storage unit (110) may include a memory element or storage medium for storing fault information and may be implemented through DRAM, SRAM, flash memory, or other non-volatile storage devices. The judgment unit (120) is a computational unit for analyzing stored information to determine repairability and may be configured to include a microprocessor (MCU), a digital signal processor (DSP), a dedicated computational circuit, or a logic-based computational block. Additionally, the compression unit (130) may be implemented as a hardware compression module or a processor-based software algorithm for performing data compression processing on fault information, and the communication unit (140) may be configured as a communication device that enables data transmission and reception with an external server (40), including a wired / wireless communication interface, a serial / parallel communication circuit, a network interface card (NIC), or a system bus interface.

[0066] FIG. 4 is a block diagram of a memory failure information transmission device (10) according to one embodiment.

[0067] Referring to FIG. 4, the memory fault information transmission device (10) of the present invention may include a storage unit (110), a judgment unit (120), a compression unit (130), and a communication unit (140). In addition, the memory fault information transmission device (10) of the present invention may include various components, such as an input unit, a control unit, and an output unit, without limitation, necessary to perform the operations described below. These components may be omitted or added depending on the implementation method, and various modifications are possible within the scope that does not deviate from the core technical concept of the present invention.

[0068] The storage unit (110) may include a first storage space in which overall fault information obtained by testing the memory (20) is stored, and a second storage space in which fault addresses and repair-related information, such as overall fault information, are stored. The storage unit (110) may collect memory fault information input from the test device (30) and store it separately according to the purpose, and may include a first storage space and a second storage space for this purpose. The first storage space may store overall fault information including whether a fault has occurred in the entire memory area, and this may be implemented as a data structure that encompasses test results at the memory cell level. The second storage space is a space in which additional information necessary for determining repairs and the address where the fault occurred can be selectively extracted and stored from the information stored in the first storage space, and reference data for identifying the fault location and processing related to repairs may be concentrated and stored. By recording data in a redundant structure according to the purpose of storing fault information in this way, the storage unit (110) can efficiently provide information necessary for subsequent judgment and transmission stages.

[0069] According to one embodiment, the first storage space may have a fault bitmap structure that records, in 1-bit units, which address of the memory (20) has a fault. The fault bitmap structure is a method of expressing the fault status of each location in 1-bit units based on the address of the memory cell; by setting the bit value corresponding to the address to '1' when a fault is detected and to '0' when normal operation is confirmed, the fault distribution can be intuitively expressed. FIG. 5 is a schematic diagram showing a memory fault expressed as a fault bitmap according to one embodiment. This fault bitmap is composed of a logical bit array that maps one-to-one with the array structure of the physical memory (20), and through this, the first storage space can be designed to uniformly cover the entire memory range. In addition, since the bit at the same location is repeatedly updated during each test cycle, the second storage space can accumulate and record the fault status in real time through simple logical operations. Since the fault bitmap structure is simple to implement and has efficient storage capacity, it may be suitable for quickly querying or analyzing the entire range of fault information.

[0070] According to one embodiment, the second storage space may be a Content Addressable Memory (CAM). The second storage space is an area for storing information related to fault addresses and repair judgments among fault information generated during the test process, and can be implemented as a CAM structure capable of high-speed searching and condition-based data access. Unlike general address-based memory, CAM is a memory that performs searching based on the content of stored data, and can quickly determine within a single clock cycle whether a specific fault address is already registered. When the second storage space is configured as a CAM, whenever a fault occurs, the corresponding fault address is compared with previously stored addresses to determine in real time whether there is a duplicate, and a new entry can be stored only if there is no duplicate. The CAM structure is suitable for selectively storing and managing only representative address information that directly affects repair judgment among fault information, and can provide an efficient data reference structure so that the judgment unit (120) described later can quickly determine the repairability of the memory (20).

[0071] In addition, the second storage space may have a two-stage storage structure including a main CAM and a sub CAM.

[0072] The main CAM can store the address of a reported fault as a representative address if the reported fault is the first occurrence of the fault in the corresponding row and column. When a fault is detected, the fault address is immediately compared with existing addresses through a comparison circuit within the CAM; if a fault is already registered in the same row or column, it is considered a duplicate and is not stored in the main CAM. Conversely, if it is the first occurrence of the fault in that row or column, it can be registered as a new entry in the main CAM and stored as a representative address. This stored representative address can be utilized as a reference point for subsequent faults occurring in the same row or column, and can be used as reference data in subsequent processing, such as determining repairability or compressing fault addresses. By rapidly identifying and storing this representative address information, the main CAM performs the function of selectively managing only non-duplicate core fault locations from the entire fault information.

[0073] The main CAM can store information including the row address, column address, and a flag indicating whether a fault must be repaired. Here, the flag can be used as information indicating that a specific fault has a high repair priority or must be processed first. This information can be used as basic data to determine the importance of the fault in a subsequent repair algorithm or decision-making process.

[0074] A flag indicating whether a fault must be repaired may be information determined based on memory reserve resources pre-allocated in the row and column directions of the fault. For example, if repairable reserve resources remain in only one of the row or column directions where a specific fault occurred, the fault is determined to be repairable due to the constraints of the repair resources, and the flag is set accordingly. This flag can be used to assign a repair priority in a repair algorithm or as a condition for mandatory application during resource allocation, and can serve as an important judgment criterion within the automated repair procedure of a test and repair system. Referring to FIG. 3, to explain the example of the flag in more detail, in the case of a fault occurring across (4,6) to (7,6) of memory (20), since the number of column-direction reserve resources is insufficient, it is a situation where repair can only be performed using row-direction reserve resources, and this can be defined as row must-repair. In contrast, the remaining failures (e.g., the failure located at (0,4)) are single or sparse failures, which can be repaired flexibly by dynamically selecting spare resources for rows or columns.

[0075] A sub-CAM can store information about other failures that occur in the same row and column as the representative address. Among the failures that occur during testing, the sub-CAM can store information about other failures located in the same row or column as the representative address already stored in the main CAM. When a failure occurs, the address of the failure is compared with existing representative addresses within the main CAM; if a representative address corresponding to the same row or column already exists, the failure is determined to be a duplicate failure and is stored in the sub-CAM instead of the main CAM. The sub-CAM manages this failure information in a form associated with the representative address and can generally be configured to store only the minimum address information necessary to avoid duplication, along with pointer information to reference the representative address.

[0076] A sub CAM can store information including a pointer indicating which representative address another fault is associated with in the main CAM, and the row or column address of that other fault. In this case, the pointer can be implemented in the form of an index or linkage field that references a specific entry within the main CAM, thereby enabling efficient identification of which fault among the faults stored in the main CAM each fault stored in the sub CAM is related to.

[0077] A sub-CAM may not store information regarding other failures that overlaps with the representative address associated with those failures. This is because the sub-CAM is designed to include pointer information indicating which representative address a failure is associated with, thereby avoiding the repeated storage of redundant information. For example, if the same part between a representative address and another failure address is a 'column,' only the 'row' address of that other failure is stored in the sub-CAM; conversely, if the same part is a 'row,' only the column address is stored. By doing so, redundant information can be omitted, and only the minimum necessary information can be recorded. Through this structure and method, the sub-CAM enhances storage space efficiency while maintaining clear reference relationships between failure data. Furthermore, it provides a data structure advantageous for quickly grouping or interpreting failure information based on representative addresses during subsequent processing steps.

[0078] FIGS. 6 and 7 are schematic diagrams illustrating a two-stage structure of a second storage space and information stored therein according to one embodiment. However, the information stored in the main CAM and sub CAM of the second storage space is not limited to that illustrated in the drawings.

[0079] The second storage space can efficiently classify and store failures concentrated in a specific row or column of the memory (20) through such a two-stage structure, and can minimize redundancy of failure information and reduce storage space through a hierarchical structure between the main CAM and the sub CAM.

[0081] The judgment unit (120) can determine whether the memory (20) is repairable based on information stored in the second storage space. The judgment unit (120) can determine whether the memory (20) is in a repairable state based on fault addresses and repair-related information stored in the second storage space. The second storage space stores representative fault information among the faults that occurred during testing and minimum address information required for repair judgment, and the judgment unit (120) can determine whether each fault is repairable by analyzing this information. The judgment unit (120) can execute internal judgment logic based on conditions such as whether the faults are concentrated in a specific row or column, or whether repair resources are exhausted, and this judgment process can be performed in real time or immediately after testing.

[0082] According to one embodiment, the judgment unit (120) can determine whether repair is possible based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions. For example, the judgment unit (120) can predict whether repair resources are exhausted by checking whether the number of failures in a specific row or column exceeds a predefined threshold, or by analyzing whether failures are concentrated in the same reserve resource. Additionally, the judgment unit (120) can determine that repair is highly probable if failures are distributed in multiple directions, and conversely, determine that repair is impossible due to a lack of resources if failures are confined to a specific area. Such judgment criteria can be configured according to a repair policy during system design, and the judgment result can be directly reflected in the subsequent method of transmitting failure information or whether to apply a repair algorithm.

[0083] Additionally, the judgment unit (120) may determine that repair is impossible when all available storage space of the second storage space is exhausted. The judgment unit (120) continuously monitors the available storage capacity of the second storage space and, if all of the space is exhausted, determines that the memory (20) is impossible to repair. The second storage space is designed to selectively store only representative fault information necessary for repair determination, and since its storage capacity is limited according to the number of available reserve resources or the repair complexity allowed by the system, the judgment unit (120) checks whether there is spare space in the second storage space before storing new information whenever a fault occurs, and if there is insufficient space to store any more fault information, it does not consider it a memory subject to repair and determines it as being in an unrepairable state. This structure can increase the speed of repair determination and the efficiency of resource usage, and the judgment result can be reflected in the subsequent fault information transmission method and process analysis path determination. This storage space-based repairability determination process can be performed prior to the aforementioned more specific determination action (e.g., a determination action based on the distribution of fault locations, etc.).

[0085] The compression unit (130) can compress information before transmitting it to the server (40). Within the memory fault information transmission device (10), the compression unit (130) can reduce the size of the transmitted data by compressing the fault information in a predetermined manner before transmitting the data to the server (40). The compression unit (130) is linked with the judgment unit (120) and the communication unit (140) to receive data from a first storage space or a second storage space selected according to whether repair is possible, and can apply an appropriate compression algorithm according to the characteristics of the data. For example, in the case of a fault bitmap in which consecutive '0' or '1' values ​​are repeated, a Run-Length Encoding method may be applied, and fault address data may be compressed using an Address Delta Encoding method based on relative addresses. The compression unit (130) may be implemented on a hardware or software basis considering compression efficiency, and may function as a preprocessing module to reduce transmission bandwidth and reduce the processing burden on the server (40) side.

[0086] FIGS. 8 to 10 are schematic diagrams illustrating a compression method of a fault bitmap according to one embodiment. With reference to FIGS. 8 to 10, the step-by-step explanation of how to compress and store fault information that has occurred for one row of memory (20) will be provided. In the embodiment of FIGS. 8 to 10, it is assumed that the number of reserve resources available for column-direction repair is 5 (Cs = 5), and each figure shows a general repairable situation, an example of reducing the number of compressed data when repair is possible, and a compression example corresponding to a must-repair case. First, a 1024-bit fault bitmap is compressed by dividing it into a 10×6-bit format, and each 10-bit data is interpreted as offset information indicating the location of the fault. For example, in FIG. 8, there are 5 faults, so it is divided into 6 sections, and the number of consecutive '0's in each section is represented as compressed data. This compression result enables a significant reduction in the total data size while maintaining the location information of the information constituting the actual fault bitmap without loss. Figure 9 shows a form in which the number of compressed data is reduced because the number of faults is 4, which is smaller than Cs, and Figure 10 corresponds to a must-repair situation where the number of faults in the corresponding row is greater than the number of reserve resources. In this case, since the corresponding row must be repaired with only one row reserve resource, the fault location information becomes unnecessary, and the compressed data is all set to 1 and processed in the form of a single flag.

[0087] The compression method according to the embodiments of FIGS. 8 to 10 is a run-length-based lossless compression technique that can efficiently summarize and store memory failure information organized by each line, and can achieve a high compression ratio, particularly when failures are partially concentrated within a memory line. In addition, since the compression unit is a memory line, compression of preceding lines can be performed in parallel while subsequent lines are accessed during testing, thus providing a structural advantage that does not affect test time. Furthermore, the compression method is not limited to a single method, and the method presented in FIGS. 8 to 10 is merely an example. In actual implementation, various compression algorithms (RLE, differential encoding, pattern clustering, etc.) can be applied depending on the memory structure, test algorithm, and system resource constraints, and can be extended to an optimized compression method according to the purpose.

[0088] FIG. 11 is a diagram showing a flowchart and an example of a compression algorithm performed on fault addresses stored in a CAM according to one embodiment. The top of the diagram illustrates a process of sequentially retrieving fault addresses stored in the CAM, and subsequently, compression is performed by calculating the difference between each address, converting it into a delta value, and storing it. As such, Address Delta Encoding is one of the compression methods that can represent the entire address information with fewer bits by utilizing the relative difference between fault addresses. A simple example of compression is presented on the right. For instance, if the fault addresses stored in the CAM are (100), (101), (103), and (110), the delta between each address is calculated and stored as 0, +1, +2, and +7 based on the reference address. Since the delta value can be represented with a much smaller number of bits than the original absolute address, the total amount of data transmitted can be effectively reduced. The example shown in FIG. 11 is a simplified case to aid in understanding the Address Delta Encoding-based compression method. In addition to this, the present invention may include the application of various compression algorithms (RLE, pattern-based encoding, bitmask compression, etc.) that consider the spatial distribution of memory failure addresses or the repeatability of failure types. Therefore, the present invention is not limited to a specific compression method and includes a flexible compression structure based on various algorithms.

[0090] The communication unit (140) can transmit information stored in the second storage space to the server (40) if repair is possible, and information stored in the first storage space if repair is impossible. The communication unit (140) can selectively branch the fault information to be transmitted to the server (40) according to the judgment result of the judgment unit (120). Specifically, if the memory (20) is determined to be repairable by the judgment unit (120), the communication unit (140) transmits the fault address and repair-related information stored in the second storage space to the server (40), which can be used as input for a repair algorithm. Conversely, if the memory (20) is determined to be repairable, the communication unit (140) transmits data from the first storage space, including information on whether the entire memory is faulty, to the server (40), which can be utilized for purposes such as process anomaly analysis. This transmission method is structured to consider the purpose-specific use of fault information, and the communication unit (140) can dynamically control the transmitted data to simultaneously secure data flow efficiency and suitability for the purpose.

[0092] The server (40) receives fault information regarding a repairable memory (20) from the memory fault information transmission device (10) and can perform actual repairs by utilizing this information as input to a predefined repair algorithm. At this time, the server (40) identifies the location of the fault within the memory based on the transmitted fault address information or compressed fault representation data, and determines a repair strategy that can bypass or replace the fault. The repair algorithm is executed by considering the spatial distribution of the fault, repair priority, resource consumption optimization conditions, etc., and the result is applied to the memory (20) through the system control unit to restore the function of the fault cell.

[0093] More specifically, the server (40) can perform a repair algorithm based on reserve resources pre-allocated in the row or column direction within memory. The reserve resources are a redundancy structure designed to replace fault cells. The server (40) analyzes the location and distribution of the fault within the received fault information, and then performs the repair by mapping appropriate row or column reserve resources capable of replacing the fault. In particular, depending on the type of fault, there are cases where repair is possible using only reserve resources in a specific direction; in such cases, the server (40) sets the repair path by considering only the resources in that direction. This resource-based repair method is a core process of the repair algorithm and is a factor directly related to the success or failure of the fault recovery.

[0094] Meanwhile, regarding memory (20) that cannot be repaired, the server (40) can perform process anomaly pattern analysis based on the total failure bitmap or related data received. By analyzing the repeatability of failure locations, failure concentration phenomena in specific cell structures or layers, and the statistical distribution of the number of failures, the server (40) can detect problems in the manufacturing process early and suggest directions for improvement. The results of this analysis are reflected in the quality control system to contribute to improving production yield and enable the tracing of causes for repetitive types of defects and process optimization. Therefore, in the present invention, the server (40) plays an important role in increasing the repair efficiency and process analysis accuracy of the entire system by utilizing different failure information according to repairability and impossibility to suit the purpose.

[0096] Hereinafter, the memory failure information transmission method of the present invention will be described.

[0097] FIG. 12 is a flowchart of a memory failure information transmission method according to one embodiment.

[0098] Referring to FIG. 12, the memory failure information transmission method may include the step (S100) of storing the total failure information obtained by testing the memory (20) in a first storage space and storing the failure address and repair-related information among the total failure information in a second storage space; the step (S200) of determining whether the memory (20) is repairable based on the information stored in the second storage space; and the step (S300) of transmitting the information stored in the second storage space to a server (40) if the memory is repairable, and the information stored in the first storage space if the memory is not repairable.

[0099] According to one embodiment, the first storage space may be characterized by having a Fault bitmap structure that records, in 1-bit units, which address of the memory (20) a fault has occurred.

[0100] According to one embodiment, the second storage space may be characterized as being a Content Addressable Memory (CAM).

[0101] According to one embodiment, the second storage space may be characterized by having a two-stage storage structure including a main CAM that stores the address of a fault that occurred as a representative address when the fault that occurred is the first fault that occurred in the row and column of the address of the fault, and a sub CAM that stores information about other faults that occurred in the same row and column as the representative address.

[0102] According to one embodiment, the main CAM may be characterized by storing information including a row address, a column address of a representative address, and a flag indicating whether the fault must be repaired.

[0103] According to one embodiment, a flag indicating whether a fault must be repaired may be characterized as information determined based on memory reserve resources pre-allocated in the row and column directions of the fault.

[0104] According to one embodiment, the sub CAM may be characterized by storing information including a pointer indicating whether another fault is associated with a representative address stored in the main CAM, and a row address or column address of the other fault.

[0105] According to one embodiment, the sub-CAM may be characterized in that, among the information regarding other faults, information that overlaps with the representative address associated with the other fault is not stored.

[0106] According to one embodiment, the step of determining whether the memory (20) is repairable may be characterized by determining whether it is repairable based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions.

[0107] According to one embodiment, the step of determining whether the memory (20) is repairable may be characterized by determining that it is unrepairable when all the storage space of the second storage space is exhausted.

[0108] FIG. 13 is a flowchart of a method for transmitting memory failure information when repair is possible according to one embodiment. Referring to FIG. 13, the method for transmitting memory failure information may further include a step (S410) in which, when repair is possible, the server (40) uses the information of the second storage space received as an input for executing a preset repair algorithm to repair the memory (20).

[0109] According to one embodiment, the step of repairing the memory (20) may be characterized by repairing the memory (20) by utilizing memory reserve resources pre-allocated in the row and column directions of the failure.

[0110] FIG. 14 is a flowchart of a method for transmitting memory failure information in a case where repair is impossible according to one embodiment. Referring to FIG. 14, the method for transmitting memory failure information may further include a step (S420) in which, in a case where repair is impossible, the server (40) uses the information of the first storage space received as data for analyzing process abnormal patterns.

[0111] FIG. 15 is a flowchart of a memory failure information transmission method according to one embodiment. Referring to FIG. 15, the memory failure information transmission method may further include a step (S250) of compressing the information before transmitting it to a server (40).

[0112] According to one embodiment, the test may be characterized by detecting whether there is a fault by performing a pattern-based inspection that generates fault information by applying a test pattern generated from a pattern generator to a memory (20).

[0114] Those skilled in the art related to the embodiments of the present invention will understand that they may be implemented in modified forms without departing from the essential nature of the description. Therefore, the disclosed methods should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the claims, not by the detailed description of the invention, and all variations within the scope of the claims should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0116] 1: Memory Failure Test and Repair System 10: Memory failure information transmission device 20: Memory 30: Test device 40: Server 110: Storage section 120: Judgment Department 130: Compression section 140: Communications Department

Claims

Claim 1 A method for transmitting test information regarding memory to a server, comprising: a step of storing overall fault information obtained by testing the memory in a first storage space, and storing information including a fault address and a flag indicating whether the fault at the fault address must be repaired among the overall fault information in a second storage space; a step of determining whether the memory is repairable based on the information stored in the second storage space; and a step of transmitting the information stored in the second storage space to the server if the memory is repairable, and the information stored in the first storage space to the server if the memory is not repairable. Claim 2 A method for transmitting memory fault information according to claim 1, wherein the first storage space has a Fault bitmap structure that records, in 1-bit units, which address in memory where a fault occurred. Claim 3 A method for transmitting memory failure information according to claim 1, wherein the second storage space is a CAM (Content Addressable Memory). Claim 4 A method for transmitting memory fault information according to claim 3, wherein the second storage space comprises a two-stage storage structure including: a main CAM that stores the address of the generated fault as a representative address when the generated fault is the first fault that occurred in the row and column of the address of the corresponding fault; and a sub CAM that stores information about other faults that occurred in the same row and column as the representative address. Claim 5 A method for transmitting memory fault information according to claim 4, wherein the main CAM stores information including a row address, a column address of a representative address, and a flag indicating whether the fault must be repaired. Claim 6 A method for transmitting memory fault information according to claim 5, wherein a flag indicating whether the fault must be repaired is information determined based on memory reserve resources pre-allocated in the row and column directions of the fault. Claim 7 A method for transmitting memory fault information according to claim 5, wherein the sub CAM stores information including a pointer indicating whether the other fault is associated with a representative address stored in the main CAM and a row address or column address of the other fault. Claim 8 A memory fault information transmission method according to claim 7, wherein the sub-CAM does not store information regarding other faults that overlaps with a representative address associated with the other fault. Claim 9 A method for transmitting memory failure information according to claim 1, wherein the step of determining whether the memory is repairable is characterized by determining whether it is repairable based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions. Claim 10 A method for transmitting memory failure information according to claim 1, wherein the step of determining whether the memory is repairable is characterized by determining that it is unrepairable when the storage space of the second storage space is completely exhausted. Claim 11 A method for transmitting memory failure information according to claim 1, further comprising the step of, if repair is possible, using information of a second storage space received by the server as an input for executing a preset repair algorithm to repair the memory. Claim 12 A method for transmitting memory fault information according to claim 11, wherein the step of repairing the memory is characterized by repairing the memory by utilizing memory reserve resources pre-allocated in the row and column directions of the fault. Claim 13 A method for transmitting memory failure information according to claim 1, further comprising the step of, in the case where repair is impossible, using the information of the first storage space received by the server as data for process abnormal pattern analysis. Claim 14 A method for transmitting memory failure information according to claim 1, further comprising the step of compressing the information before transmitting it to a server. Claim 15 A method for transmitting memory fault information according to claim 1, wherein the test is characterized by detecting whether a fault exists by performing a pattern-based inspection that generates fault information by applying a test pattern generated from a pattern generator to the memory. Claim 16 A device for transmitting test information about a memory to a server, comprising: a storage unit including a first storage space for storing overall fault information obtained by testing the memory, and a second storage space for storing information including a fault address and a flag indicating whether the fault at the fault address must be repaired among the overall fault information; a judgment unit for determining whether the memory is repairable based on the information stored in the second storage space; and a communication unit for transmitting the information stored in the second storage space to the server if the memory is repairable, and the information stored in the first storage space if the memory is not repairable. Claim 17 A memory fault information transmission device according to claim 16, wherein the first storage space is characterized by having a Fault bitmap structure that records, in 1-bit units, which address in memory has a fault. Claim 18 A memory failure information transmission device characterized in that, in claim 16, the second storage space is a CAM (Content Addressable Memory). Claim 19 A memory fault information transmission device according to claim 18, wherein the second storage space comprises a two-stage storage structure including: a main CAM that stores the address of the generated fault as a representative address when the generated fault is the first fault that occurred in the row and column of the address of the said fault; and a sub CAM that stores information about other faults that occurred in the same row and column as the representative address. Claim 20 A memory fault information transmission device according to claim 19, wherein the main CAM stores information including a row address, a column address of a representative address, and a flag indicating whether the fault must be repaired. Claim 21 A memory fault information transmission device according to claim 20, characterized in that a flag indicating whether the above fault must be repaired is information determined based on memory reserve resources pre-allocated in the row and column directions of the above fault. Claim 22 A memory fault information transmission device according to claim 20, wherein the sub-CAM stores information including a pointer indicating whether the other fault is associated with a representative address stored in the main CAM and a row address or column address of the other fault. Claim 23 A memory fault information transmission device according to claim 22, characterized in that the sub-CAM does not store information regarding other faults that overlaps with a representative address associated with the other fault. Claim 24 In claim 16, the above-mentioned judgment unit determines whether repair is possible based on one or more of the number of failures, the distribution of failure locations, and predefined repair conditions. Claim 25 A memory failure information transmission device according to claim 16, wherein the above-mentioned judgment unit determines that it is irreparable when all of the storable space of the above-mentioned second storage space is exhausted. Claim 26 A memory failure information transmission device according to claim 16, characterized in that, if repair is possible, the server repairs the memory by using the information of the second storage space received by the server as an input for executing a preset repair algorithm. Claim 27 A memory failure information transmission device according to claim 26, wherein the server repairs the memory by utilizing memory reserve resources pre-allocated in the row and column directions of the failure. Claim 28 A memory failure information transmission device according to claim 16, characterized in that, in the case where repair is impossible, the server uses the information of the first storage space received by the server as data for process abnormal pattern analysis. Claim 29 A memory failure information transmission device comprising, in paragraph 16, a compression unit that compresses information before transmitting it to a server. Claim 30 In claim 16, the memory fault information transmission device is characterized by the above test performing a pattern-based inspection to generate fault information by applying a test pattern generated by a pattern generator to memory to detect whether a fault exists.

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