Methods to reduce material surface roughness

Abstract

Exemplary deposition methods may include the step of delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber. The methods may include the step of providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater. The methods may include the step of forming a plasma of all precursors within the processing zone of the semiconductor processing chamber. The methods may include the step of depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber.

Description

Technology Field

[0001] This application claims the benefit of priority to U.S. Patent Application No. 62 / 933,012 filed November 8, 2019, the contents of which are incorporated by reference in their entirety for all purposes.

[0002] The present technology relates to semiconductor deposition processes. More specifically, the present technology relates to methods for depositing materials having reduced surface roughness. Background Technology

[0003] Integrated circuits are made possible by processes that create complexly patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods for forming and removing exposed materials. As device sizes continue to shrink, material uniformity can affect subsequent operations. For example, the surface roughness of masking materials can affect the uniformity of subsequent etching.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are addressed by the present technology.

[0005] Exemplary deposition methods may include the step of delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber. The methods may include the step of providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The methods may include the step of forming a plasma of all precursors within the processing zone of the semiconductor processing chamber. The methods may include the step of depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber.

[0006] In some embodiments, the silicon- and boron materials may be characterized by a surface roughness of about 2 nm or less immediately after deposition. The plasma power density is about 0.5 W / cm² while forming the plasma of all precursors within the processing zone of the semiconductor processing chamber. 2 The substrate temperature may be maintained above about 400°C or higher while depositing silicon- and boron materials on the substrate. The pressure may be maintained below about 10 Torr while depositing silicon- and boron materials on the substrate. The methods may include the step of providing an argon precursor together with a silicon-containing precursor and a boron-containing precursor. The methods may include the step of performing thermal annealing of the silicon- and boron materials following the deposition step. The silicon-containing precursor may be or may contain a silane, and the boron-containing precursor may be or may contain a diborane.

[0007] Some embodiments of the present technology may include deposition methods. The methods may include the step of delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber. The methods may include the step of forming a plasma of the silicon-containing precursor and the boron-containing precursor within the processing zone of the semiconductor processing chamber. The methods may include the step of depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber. The silicon- and boron materials may be characterized by a surface roughness immediately after deposition of about 1.5 nm or less.

[0008] In some embodiments, the methods may include the step of providing a hydrogen-containing precursor together with a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The methods may include the step of providing an argon precursor together with a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or less. The methods may include the step of thermally annealing the silicon- and boron material for a first time period following the deposition step. The substrate may be maintained at a first temperature during deposition. The substrate may be maintained at a second temperature during thermal annealing of the silicon- and boron material, the second temperature may be higher than the first temperature. The second temperature may be about 500°C or greater. The plasma power can be maintained at about 2.0 kW or more while forming plasma of silicon-containing precursors and boron-containing precursors within the processing zone of the semiconductor processing chamber.

[0009] Some embodiments of the present technology may include deposition methods. The methods may include the step of delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber. The methods may include the step of forming a plasma of all precursors within the processing zone of the semiconductor processing chamber. The plasma power may be maintained at about 1.0 kW or more while forming a plasma of all precursors within the processing zone of the semiconductor processing chamber. The methods may include the step of depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber.

[0010] In some embodiments, the methods may include the step of providing a hydrogen-containing precursor together with a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The methods may include the step of providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor. The flow rate ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or less. The methods may include the step of performing thermal annealing of the silicon- and boron material for a first time period following the deposition step. The substrate may be maintained at a first temperature during deposition. The substrate may be maintained at a second temperature during the thermal annealing of the silicon- and boron material, and the second temperature may be higher than the first temperature.

[0011] Such technology can provide numerous advantages over conventional systems and techniques. For example, processes can produce films characterized by reduced surface roughness. Additionally, the operations of embodiments of the present technology can produce improved mask materials that facilitate processing operations. These and other embodiments, along with most of their advantages and features, are described in more detail in conjunction with the detailed description below and the accompanying drawings. Brief explanation of the drawing

[0012] Further understanding of the attributes and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the drawings.

[0013] FIG. 1 illustrates a schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology.

[0014] FIG. 2 illustrates exemplary operations in a deposition method according to some embodiments of the present technology.

[0015] FIG. 3 illustrates a schematic diagram of a substrate prior to deposition according to some embodiments of the present technology.

[0016] FIGS. 4a and 4b illustrate schematic diagrams of exemplary substrates during deposition according to some embodiments of the present technology.

[0017] FIGS. 5A and 5B illustrate schematic diagrams of exemplary substrates during deposition according to some embodiments of the present technology.

[0018] Some of the drawings are included as schematics. It will be understood that the drawings are for illustrative purposes only and are not to be considered to be to actual scale unless specifically stated otherwise. Additionally, as schematics, the drawings are provided for illustrative purposes and may not include all aspects or information compared to actual representations, and may include exaggerated data for illustrative purposes.

[0019] In the attached drawings, similar components and / or features may have the same reference label. Additionally, various components of the same type may be distinguished by having a character following the reference label that distinguishes between similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the character. Specific details for implementing the invention

[0020] During semiconductor manufacturing, structures can be created on a substrate using various deposition and etching operations. Mask materials can be used to allow materials to be partially etched or etched to create features across the substrate. As device sizes continue to decrease and improved selectivity between materials facilitates structure formation, the use of improved hard masks can facilitate manufacturing. For example, compared to thermally generated amorphous silicon hard masks, boron-incorporated silicon films can feature improved hardness and other material properties, which facilitates the use of the film as a mask material. However, while thermally generated silicon can feature a substantially smooth surface, boron-incorporated silicon films can feature increased surface roughness.

[0021] The present technology can overcome these limitations by adjusting deposition parameters and materials to perform surface treatment during deposition. For example, the present technology may include etching exposed features of the film layer during deposition. This can facilitate a more uniform surface profile, which can reduce or limit surface roughness during deposition. After describing general aspects of chambers according to embodiments of the present technology in which the plasma processing operations discussed below can be performed, specific methodologies and component configurations may be discussed. It will be understood that the described techniques are not intended to be limited to the specific films and processing methods discussed, as they can be used to improve a number of film formation processes and are applicable to various processing chambers and operations.

[0022] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber (100) according to some embodiments of the present invention. The drawing may illustrate an overview of a system capable of incorporating one or more aspects of the present invention and / or performing one or more operations according to embodiments of the present invention. Additional details of the chamber (100) or the methods performed may be further described below. While the chamber (100) may be used to form film layers according to some embodiments of the present invention, it will be understood that the methods may similarly be performed in any chamber where film formation may occur. The processing chamber (100) may include a chamber body (102), a substrate support (104) disposed inside the chamber body (102), and a lid assembly (106) coupled to the chamber body (102) and surrounding the substrate support (104) in a processing volume (120). The substrate (103) may be provided to the processing volume (120) through an opening (126) that can be typically sealed for processing using a slit valve or door. The substrate (103) may be placed on the surface (105) of the substrate support during processing. The substrate support (104) may be rotatable along an axis (147) where the shaft (144) of the substrate support (104) may be positioned, as indicated by the arrow (145). Alternatively, the substrate support (104) may be lifted up to rotate as needed during the deposition process.

[0023] A plasma profile modulator (111) may be placed in a processing chamber (100) to control the plasma distribution across a substrate (103) placed on a substrate support (104). The plasma profile modulator (111) may include a first electrode (108) that may be placed adjacent to the chamber body (102) and may separate the chamber body (102) from other components of the cover assembly (106). The first electrode (108) may be part of the cover assembly (106) or may be a separate sidewall electrode. The first electrode (108) may be an annular or ring-shaped member and may be a ring electrode. The first electrode (108) may be a continuous loop around the circumference of the processing chamber (100) surrounding the processing volume (120) or, if desired, may be discontinuous at selected locations. The first electrode (108) may also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as a secondary gas distributor.

[0024] One or more isolators (110a, 110b), which may be dielectric materials such as ceramic or metal oxide, e.g. aluminum oxide and / or aluminum nitride, may be in contact with the first electrode (108) and may electrically and thermally isolate the first electrode (108) from the gas distributor (112) and the chamber body (102). The gas distributor (112) may define apertures (118) for dispensing process precursors into the processing volume (120). The gas distributor (112) may be coupled to a first electric power source (142), e.g., an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to the processing chamber. In some embodiments, the first electric power source (142) may be an RF power source.

[0025] The gas distributor (112) may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor (112) may also be formed of conductive and non-conductive components. For example, the body of the gas distributor (112) may be conductive, while the face plate of the gas distributor (112) may be non-conductive. The gas distributor (112) may be powered by a first electric power source (142), such as as shown in FIG. 1, or the gas distributor (112) may be coupled to ground in some embodiments.

[0026] The first electrode (108) may be coupled to a first tuning circuit (128) capable of controlling the ground path of the processing chamber (100). The first tuning circuit (128) may include a first electronic sensor (130) and a first electronic controller (134). The first electronic controller (134) may be or may include a variable capacitor or other circuit elements. The first tuning circuit (128) may be or may include one or more inductors (132). The first tuning circuit (128) may be any circuit that enables a variable or controllable impedance under plasma conditions present in the processing volume (120) during processing. In some embodiments as illustrated, the first tuning circuit (128) may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor (130). The first circuit leg may include a first inductor (132A). The second circuit leg may include a second inductor (132B) coupled in series with the first electronic controller (134). The second inductor (132B) may be positioned between the first electronic controller (134) and a node connecting both the first and second circuit legs to the first electronic sensor (130). The first electronic sensor (130) may be a voltage or current sensor and may be coupled with the first electronic controller (134), which may provide some degree of closed-loop control of plasma conditions within the processing volume (120).

[0027] The second electrode (122) may be coupled to the substrate support (104). The second electrode (122) may be embedded within the substrate support (104) or coupled to the surface of the substrate support (104). The second electrode (122) may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode (122) may be a tuning electrode and may be coupled to a second tuning circuit (136) by a cable having, for example, a selected resistance, such as 50 ohms, which is placed in a conduit (146), for example, the shaft (144) of the substrate support (104). The second tuning circuit (136) may have a second electronic controller (140) which may be a second variable capacitor and a second electronic sensor (138). The second electronic sensor (138) may be a voltage or current sensor and may be coupled with the second electronic controller (140) to provide additional control over plasma conditions within the processing volume (120).

[0028] A third electrode (124), which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled to a substrate support (104). The third electrode may be coupled to a second electric power source (150) through a filter (148), which may be an impedance matching circuit. The second electric power source (150) may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source (150) may be RF bias power.

[0029] The cover assembly (106) and substrate support (104) of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber (100) may provide real-time control of plasma conditions within the processing volume (120). A substrate (103) may be placed on the substrate support (104), and process gases may flow through the lead assembly (106) using the inlet (114) according to any desired flow plan. The gases may exit the processing chamber (100) through the outlet (152). Electric power may be coupled to the gas distributor (112) to set the plasma in the processing volume (120). In some embodiments, the substrate may be electrically biased using a third electrode (124).

[0030] When energizing the plasma within the processing volume (120), a potential difference may be established between the plasma and the first electrode (108). A potential difference may also be established between the plasma and the second electrode (122). Subsequently, electronic controllers (134, 140) may be used to adjust the flow properties of the ground paths represented by two tuning circuits (128 and 136). To provide independent control of plasma density uniformity and deposition rate from the center to the edge, a set point may be transmitted to the first tuning circuit (128) and the second tuning circuit (136). In embodiments where both electronic controllers may be variable capacitors, electronic sensors may adjust the variable capacitors to maximize the deposition rate and independently minimize thickness non-uniformity.

[0031] Each of the tuning circuits (128, 136) may have a variable impedance that can be adjusted using individual electronic controllers (134, 140). If the electronic controllers (134, 140) are variable capacitors, the capacitance range of each variable capacitor, and the inductances of the first inductor (132A) and the second inductor (132B) may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller (134) is at a minimum or maximum value, the impedance of the first tuning circuit (128) may be high, which results in a plasma shape having minimal aerial or lateral coverage over the substrate support. When the capacitance of the first electronic controller (134) approaches a value that minimizes the impedance of the first tuning circuit (128), the aerial coverage of the plasma grows to a maximum, so that it can effectively cover the entire working area of ​​the substrate support (104). When the capacitance of the first electronic controller (134) deviates from the minimum impedance setting, the plasma shape can be reduced from the chamber walls, and the aerial coverage of the substrate support can be reduced. The second electronic controller (140) can have a similar effect of increasing and decreasing the aerial coverage of the plasma on the substrate support, as the capacitance of the second electronic controller (140) can be changed.

[0032] Electronic sensors (130, 138) can be used to tune individual circuits (128, 136) in a closed loop. A set point for current or voltage can be installed on each sensor depending on the type of sensor used, and the sensor may be provided with control software that determines the adjustment for each individual electronic controller (134, 140) to minimize deviation from the set point. Consequently, the plasma shape can be selected and dynamically controlled during processing. Although the foregoing discussion is based on electronic controllers (134, 140) which may be variable capacitors, it will be understood that any electronic component having adjustable characteristics can be used to provide tuning circuits (128 and 136) having adjustable impedance.

[0033] FIG. 2 illustrates exemplary operations in a deposition method (200) according to some embodiments of the present invention. The method may be performed in various processing chambers including the processing chamber (100) described above. The method (200) may include a number of optional operations that may or may not be specifically associated with some embodiments of methods according to the present invention. For example, many of the operations are described to provide a wider range of structural formations, but may be performed by alternative methodologies that are not critical to the art or are readily recognizable. The method (200) may describe operations schematically illustrated in FIG. 3 through 5b, and examples of such operations will be described in relation to the operations of the method (200). It should be understood that the drawings illustrate only partial schematics and that the substrate may include any number of additional materials and features having various characteristics and aspects as illustrated in the drawings.

[0034] The method (200) may include additional operations prior to the initiation of the enumerated operations. For example, additional processing operations may include forming structures on a semiconductor substrate, which may include both forming a material and removing a material. Previous processing operations may be performed in a chamber where the method (200) may be performed, or processing may be performed in one or more other processing chambers before the substrate is transferred into the semiconductor processing chamber where the method (200) may be performed. Nevertheless, the method (200) may optionally include the step of transferring a semiconductor substrate to a processing zone of a semiconductor processing chamber, such as the processing chamber (100) described above or other chambers that may include components as described above. The substrate may be a pedestal such as a substrate support (104) and may be deposited on a substrate support that may reside in a processing zone of the chamber, such as the processing volume (120) described above. An exemplary substrate (305) prior to the initiation of deposition is illustrated in FIG. 3.

[0035] The substrate (305) may be any number of materials upon which materials can be deposited. The substrate may be dielectric materials including silicon, germanium, silicon oxide, or silicon nitride, metal materials, or any number of combinations of these materials (which may be the substrate (305)), or materials formed on the substrate (305), or may include these. In some embodiments, optional processing operations, such as pretreatment, may be performed to prepare the surface of the substrate (305) for deposition. For example, pretreatment may be performed to provide specific ligand terminations on the surface of the substrate, which may facilitate the nucleation of the film to be deposited. For example, as non-limiting examples, hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals, such as amidogen or other functional groups, may be adsorbed, reacted, or formed on the surface of the substrate (305). Additionally, material removal, such as reduction of natural oxides or etching of the material, may be performed, or any other operation that prepares one or more exposed surfaces of the substrate (305) for deposition may be performed.

[0036] In operation (205), one or more precursors may be delivered to the processing zone of the chamber. For example, in exemplary embodiments where a boron-mixed silicon film may be formed, a silicon-containing precursor and a boron-containing precursor may be delivered to the processing zone of the processing chamber. In some embodiments of the present invention, plasma-enhanced deposition may be performed to facilitate material reactions and deposition. For example, as mentioned above, some embodiments of the present invention may include the formation or deposition of silicon- and boron materials, which may feature increased surface roughness compared to silicon films traditionally, such as thermally generated silicon films. The nucleation of these silicon- and boron materials may form islands (405a) on the substrate (305) in some embodiments, as illustrated in FIG. 4a. These islands may be formed three-dimensionally to different heights during initial film formation and may be maintained during film growth.

[0037] Some embodiments of the present invention may additionally include providing a hydrogen-containing precursor provided together with a silicon-containing precursor and a boron-containing precursor in operation (210). All of the delivered precursors may be used to form a plasma within a processing zone of a semiconductor processing chamber in operation (215). In operation (220), silicon- and boron materials may be deposited on a substrate (305). In some embodiments, by incorporating a hydrogen-containing precursor, the islands formed during nucleation may be reduced or limited.

[0038] For example, as illustrated in FIG. 4b, the islands (405b) may be formed to a lower or lesser extent than the islands (405a). By incorporating an additional hydrogen source, film modification or profile etching may be performed simultaneously with the deposition of the material. For example, through reaction and / or physical interaction with features formed in silicon- and boron materials, hydrogen radicals may trim the island formation while a more uniform profile is being created. Consequently, the islands may not be extended to a significant extent compared to conventional processes. To provide sufficient hydrogen radicals in the process, the hydrogen-containing precursor may be included in a larger flow rate than either or both of the silicon-containing precursor or the boron-containing precursor. For example, in some embodiments, the flow rate ratio of the hydrogen-containing precursor to the silicon-containing precursor and / or boron-containing precursor, or both, may be about 1:1 or greater, and in some embodiments, it may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 8:1 or greater, about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 35:1 or greater, about 40:1 or greater, about 45:1 or greater, about 50:1 or greater, or greater than that. As further explained below, in some embodiments, additional dilution may be performed, wherein the ratio of hydrogen to silicon and / or boron precursors may be about 100:1 or more, about 500:1 or more, about 1,000:1 or more, about 1,500:1 or more, about 2,000:1 or more, about 2,500:1 or more, or greater than that.

[0039] For example, depending on the precursors used, the silicon-containing precursor may be delivered at a flow rate of about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 200 sccm or less, about 100 sccm or less, about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, or less. Similarly, the boron-containing precursor may be delivered at a flow rate of about 1,000 sccm or less, about 800 sccm or less, about 600 sccm or less, about 500 sccm or less, about 450 sccm or less, about 400 sccm or less, about 350 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, or less. Any additional ranges within these ranges or any number of mentioned or unmentioned combinations may also be used.

[0040] The hydrogen-containing precursor can be delivered at a flow rate of about 1,000 sccm or more, about 1,200 sccm or more, about 1,400 sccm or more, about 1,600 sccm or more, about 1,800 sccm or more, about 2,000 sccm or more, about 2,200 sccm or more, about 2,400 sccm or more, about 2,600 sccm or more, about 2,800 sccm or more, about 3,000 sccm or more, or greater than that. Increasing the hydrogen-containing precursor can further smooth the surface of the film being deposited, but increased hydrogen incorporation may occur within the deposited film. Accordingly, in some embodiments, the hydrogen-containing precursor may be delivered at a flow rate of about 4,000 sccm or less, and may be delivered at a flow rate of about 3,800 sccm or less, about 3,600 sccm or less, about 3,400 sccm or less, about 3,200 sccm or less, about 3,000 sccm or less, about 2,800 sccm or less, about 2,600 sccm or less, or less. Additionally, in some embodiments where higher dilution may be performed, the hydrogen-containing precursor may be delivered at a flow rate of about 5,000 sccm or more, and may be delivered at a flow rate of about 10,000 sccm or more, about 15,000 sccm or more, about 20,000 sccm or more, about 25,000 sccm or more, or greater than that. In some embodiments, the flow rates of silicon or boron precursors may be further reduced, for example, to about 200 sccm or less, and may be reduced to about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or less.

[0041] The film can be deposited on the substrate (305) to any thickness. The surface roughness of the resulting film may not be limited to the issues during film nucleation as mentioned above. For example, in some aspects of the present technology, film growth and plasma termination may also affect the surface roughness. For example, when sufficient film growth has occurred, the process may be stopped, for instance, by extinguishing the plasma within the processing chamber, such as by cutting off power to the plasma-generating electrode. Plasma termination may also increase the surface roughness by causing physical interactions of a certain amount of residual ions after the deposition is completed. Both the nucleation effects and the plasma termination effects may be assumed to be consistent regardless of the thickness of the film being formed. However, testing has indicated that the roughness of the deposited film increases as the film thickness increases. Consequently, roughness effects also occur during film growth, and as the film thickness increases, the roughness of the film may also increase further. As illustrated in FIG. 5a, the islands (405a) formed during nucleation can not only be maintained but can also grow or expand during deposition without one or more of the characteristics described throughout the art. Thus, the resulting film (505a) may be characterized by increased roughness that can affect the uniformity of subsequent etching.

[0042] For example, thermally generated silicon, such as polysilicon or other silicon materials, may be characterized by a relatively low average roughness, such as about 0.5 nm or less or about 0.2 nm or less. The film may also be characterized by a relatively low roughness range, such as the difference between the highest peak and the lowest peak on the formed film. For example, the roughness range may be about 1.5 nm or less, or about 1 nm or less. However, for silicon- and boron films produced without one or more aspects of the present technology, the average roughness may be about 2 nm or more, about 3 nm or more, or greater than that for films of similar thickness, but the mentioned roughness may increase with increased film thickness. Furthermore, the roughness range of the generated silicon- and boron material may again depend on the film thickness, being about 10 nm or more, about 15 nm or more, or greater than that. During subsequent etching operations, these larger discrepancies across the film can cause problems with etching operation uniformity and may require additional operations, such as additional chemical-mechanical polishing operations.

[0043] However, the present technology can reduce or significantly reduce both the average roughness and the range of roughness of the resulting silicon- and boron films by performing substantially simultaneous etching using an additional hydrogen-containing precursor or by performing one or more additional adjustments described further below. As illustrated in FIG. 5b, the resulting film (505b) may be characterized by an average roughness of about 2 nm or less, and may be characterized by an average roughness of about 1.5 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, about 0.4 nm or less, about 0.3 nm or less, about 0.2 nm or less, or less. Additionally, in some embodiments, the roughness may be substantially controlled regardless of the film thickness. This allows for the avoidance of additional chemical-mechanical polishing operations, as the film immediately after deposition may be characterized by any of the illustrated average roughness ranges. Additionally, the roughness range across the film immediately after deposition may be about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, or less. Consequently, improved materials can be produced that not only provide film and mask advantages over conventional materials and processes but also potentially reduce manufacturing operations by limiting or reducing the number of polishing operations in the sequence.

[0044] Any number of precursors may be used in the present invention in relation to silicon-containing precursors and boron-containing precursors. For example, silicon-containing precursors may include any silicon-containing material, such as organosilanes, which may include silanes, disilanes, and other materials. Additional silicon-containing materials may include silicon, carbon, oxygen, or nitrogen, such as trisilylamines. Boron-containing materials may include borans, such as borans, diboranes, or other multicenter-bonded boron materials, as well as any other boron-containing material that can be used to produce silicon- and boron-containing materials. Boron incorporation within the silicon film may be based on any percentage incorporation. For example, the resulting membrane may contain about 5% or more boron incorporation, and in some embodiments, may include about 10% or more boron incorporation, about 15% or more boron incorporation, about 20% or more boron incorporation, about 25% or more boron incorporation, about 30% or more boron incorporation, about 35% or more boron incorporation, about 40% or more boron incorporation, about 45% or more boron incorporation, about 50% or more boron incorporation, about 55% or more boron incorporation, about 60% or more boron incorporation, about 65% or more boron incorporation, about 70% or more boron incorporation, about 75% or more boron incorporation, about 80% or more boron incorporation, about 85% or more boron incorporation, about 90% or more boron incorporation, about 95% or more boron incorporation, or an amount greater than or equal to the above. It is possible.

[0045] One or more additional aspects of the deposition can also be tuned to improve the aspects of the deposition to be performed. For example, plasma power can affect the degree of hydrogen dissociation. Any number of hydrogen-containing precursors may be used, and in some embodiments, diatomic hydrogen may be included. For some silicon- and boron-containing materials, the materials are sufficiently reactive at deposition temperatures where minimal plasma enhancement may be involved. For example, some prior art uses plasma power of about 200 watts or less. The present art may use higher or much higher plasma power, which can facilitate hydrogen dissociation and increase hydrogen radicals, which can reduce roughness as previously described.

[0046] For example, in some embodiments, the plasma power may be maintained at approximately 1,000 watts or more, approximately 1,200 watts or more, approximately 1,400 watts or more, approximately 1,600 watts or more, approximately 1,800 watts or more, approximately 2,000 watts or more, approximately 2,200 watts or more, approximately 2,400 watts or more, approximately 2,600 watts or more, approximately 2,800 watts or more, approximately 3,000 watts or more, or more. Such enhanced plasma power may also improve the dissociation and activation of other precursors, which may also increase the deposition rate. Consequently, despite the simultaneous etching of the material during deposition, the film deposition rates may be similar, even if not improved compared to conventional deposition. Subsequently, deposition and simultaneous etching for profile modification may be maintained continuously or sequentially until the target film thickness is created. Depending on the plasma process performed, the plasma power density can also be maintained, which may allow for modulation of power and frequency. For example, in some embodiments, the plasma power density is about 0.25 W / cm² 2It can be maintained above this level, approximately 0.5 W / cm² 2 Above, approximately 1.0 W / cm² 2 Above, approximately 1.5 W / cm 2 Above, approximately 2.0 W / cm² 2 Above, approximately 2.5 W / cm 2 It can be maintained above, or in excess of.

[0047] Additionally, the temperatures of the substrate may affect the deposition. For example, in some embodiments, the substrate may be maintained at a temperature of about 400°C or higher, about 420°C or higher, about 440°C or higher, about 460°C or higher, about 480°C or higher, about 500°C or higher, or higher. By performing the deposition according to some embodiments of the present technology, hydrogen etching may be performed during deposition to reduce the roughness of the formed film. However, the amount of hydrogen radicals generated, for example, by using enhanced plasma and hydrogen delivery, may also increase the amount of hydrogen incorporation in the formed film. This may increase the compressive stress within the film. For example, the film immediately after deposition may be characterized by a compressive stress of about -800 MPa or higher, which may be partially based on hydrogen incorporation. Consequently, in some embodiments, the method (200) may include operations to reduce hydrogen incorporation within the film.

[0048] For example, in some embodiments, the method (200) may include, in an optional operation (225), a step of thermally annealing the formed silicon- and boron-containing material. While deposition may be performed at a first temperature, thermal annealing may be performed at a second temperature higher than the first temperature. For example, thermal annealing may be performed at a temperature of about 480°C or higher, and thermal annealing may be performed at about 500°C or higher, about 510°C or higher, about 520°C or higher, about 530°C or higher, about 540°C or higher, about 550°C or higher, about 560°C or higher, about 570°C or higher, about 580°C or higher, about 590°C or higher, about 600°C or higher, or higher. Thermal annealing may be performed for a time period of about 0.5 minutes or more, about 1 minute or more, about 2 minutes or more, about 3 minutes or more, about 4 minutes or more, about 5 minutes or more, about 6 minutes or more, or longer than that.

[0049] By performing thermal annealing, a certain amount of hydrogen incorporated into the membrane can be removed, which can relieve compressive stress. For example, in some embodiments, following thermal annealing, the compressive stress within the membrane can be maintained at about -700 MPa or less, and can be about -650 MPa or less, about -600 MPa or less, about -550 MPa or less, about -500 MPa or less, about -450 MPa or less, about -400 MPa or less, about -350 MPa or less, about -300 MPa or less, about -250 MPa or less, about -200 MPa or less, about -150 MPa or less, about -100 MPa or less, or less.

[0050] The pressure within the processing zone can affect the amount of physical interaction and ionization performed during deposition. By lowering the processing pressure, increased ion interaction may occur. Accordingly, in some embodiments, the processing pressure during deposition may be maintained at about 50 Torr or less, about 40 Torr or less, about 30 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, or less.

[0051] Testing indicated that argon incorporation can increase roughness, and accordingly, limiting or excluding argon can improve film roughness. However, testing indicated that when argon is excluded from the processing precursors, film peeling may increase. Therefore, in some embodiments, argon may nevertheless be included together with silicon-containing precursors and boron-containing precursors. To limit the effect on roughness, the flow rate ratio of argon precursor to hydrogen-containing precursor may be maintained at about 2:1 or less, and may be maintained at about 1:1 or less, about 0.8:1 or less, about 0.7:1 or less, about 0.6:1 or less, about 0.5:1 or less, about 0.4:1 or less, about 0.3:1 or less, about 0.2:1 or less, about 0.1:1 or less, or less.

[0052] Combinations or additional adjustments of processing parameters can also influence and improve additional aspects of the generated films. Incorporating boron into the hardmask films can improve selectivity for multiple films. Since film stacks contain a larger number of materials involved in both hardmask opening operations and subsequent film etching, providing improved selectivity can further reduce the number of additional operations performed. Increasing film crystallinity can also increase etching selectivity, but as film crystallinity increases, conventional techniques have reduced or worsened line-edge roughness and line-width roughness. Consequently, many techniques attempt to maintain the film as amorphous silicon. The present technique can at least partially increase the crystallinity of the formed film, which can increase etching selectivity, but by limiting the crystallinity, the present technique can maintain line-edge roughness and line-width roughness.

[0053] When increased hydrogen flow rates according to embodiments of the present technology are used for silicon and boron precursors, the degree of crystallinity may be increased. However, by using processing parameters as previously discussed, the degree of crystallinity may be maintained at about 50 Å or less, about 40 Å or less, about 30 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, about 7 Å or less, about 5 Å or less, about 3 Å or less, or less, but when the degree of crystallinity is increased to about 2 Å or more or more, improved etching selectivity may be provided.

[0054] However, as hydrogen inclusion in the plasma increases, hydrogen incorporation into the film may increase. This can affect film stress, as previously discussed, and additionally affect other film characteristics. For example, hard mask films may feature extinction coefficients for light of different wavelengths that can affect lithography operations. Amorphous silicon materials may feature extinction coefficients of about 0.2 at specific parameters, which, based on lower reflectance, may allow lithography at film thicknesses up to about 800 nm, which can affect vision through the mask. Silicon and boron films may feature increased extinction coefficients for similar parameters, but as hydrogen incorporation increases, the extinction coefficients may decrease at least partially. For example, when boron incorporation increases, the absorption coefficient may increase to about 0.3 or more, about 0.35 or more, about 0.4 or more, about 0.45 or more, or more than that.

[0055] The effect of higher absorption coefficients for light is that lithography can be difficult and may require additional processing. For example, these increased absorption coefficients may limit lithographic visibility to film thicknesses of about 400 nm or less, about 300 nm or less, or less. However, by increasing hydrogen incorporation and utilizing the increased plasma density, the absorption coefficients can be reduced to about 0.35 or less, about 0.33 or less, about 0.30 or less, about 0.28 or less, about 0.25 or less, or less. This allows lithography to be extended to thicknesses of about 400 nm or more, about 450 nm or more, about 500 nm or more, or greater than that, without performing additional alignment key opening operations. By increasing the temperatures and plasma characteristics, the film structure can be formed to improve characteristics such as the absorption coefficient and etching selectivity, even when hydrogen incorporation is increased. Hydrogen incorporation can also be increased by processing at lower temperatures, such as below 400°C or below about 350°C, but differences in the film properties of such resulting films may cause additional hydrogen outgassing during subsequent processing, as previously described. By performing processes at higher temperatures, increased thermal stability can be provided with the increased hydrogen incorporation films formed as discussed above.

[0056] In some embodiments, plasma properties can be tuned using both power and frequency. For example, at lower frequencies including 13.56 MHz, such as about 20 MHz or lower, plasma power of, for example, about 2000 W or more or about 2500 W or more can produce the aforementioned film properties. It should be understood that other plasma properties may also be used. For example, by tuning the plasma frequency, plasma power can also be tuned. As the plasma frequency increases, for example, to about 40 MHz or higher, about 60 MHz or higher, and even into the microwave frequency range, the plasma power can be lowered accordingly, which can improve chamber stability and resilience. FTIR analysis noted that in these plasma properties, transmittance may increase at peaks related to boron and hydrogen, and those peaks may shift slightly to higher wavelengths. This may indicate improved structural stability, which can provide increased thermal stability of the film during subsequent processing. Consequently, by increasing the degree of crystallinity in some embodiments, lower absorption coefficients and improved thermal stability may also be provided. By performing deposition according to embodiments of the present technology, reduced roughness of silicon- and-boron-containing films may be provided, which can improve hard mask efficiency. During subsequent etching in an optional operation (230), the critical dimension of the etching may be maintained more uniformly using the present technology than when the present technology is not implemented. By reducing surface roughness, improved etching and structural advancement may be provided.

[0057] In the preceding description, for the purposes of explanation, many details have been described to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that specific embodiments may be practiced without some of these details or using additional details.

[0058] Although several embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Additionally, many well-known processes and elements have not been described to avoid unnecessarily obscuring the art. Accordingly, the above description should not be taken as limiting the scope of the art. Additionally, while methods or processes may be described sequentially or in steps, it should be understood that operations may be performed simultaneously or in a different order than listed.

[0059] Where a range of values ​​is given, each value existing between the upper limit and the lower limit of such range is interpreted as also specifically described up to one-tenth of the single-digit value of the smallest digit of the lower limit, unless otherwise clearly indicated in the context. Any narrower range between any specified values ​​or unspecified intervening values ​​within the specified range and any other specified or intervening value within that specified range is included. The upper and lower limit values ​​of such sub-ranges may independently be included in or excluded from such ranges, and each range is also included in the invention insofar as any specifically excluded limit value is in the specified range, whether one or both of the upper and lower limit values ​​are included in such sub-ranges or both are excluded from such sub-ranges. Where the specified range includes one or both of the limit values, ranges excluding one or both of the limit values ​​so included are also included.

[0060] As used in this specification and in the appended claims, singular forms include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "precursor" includes a plurality of such precursors, and a reference to "layer" includes a reference to one or more layers and their equivalents known to those skilled in the art.

[0061] Additionally, when used in this specification and the following claims, the words “comprise(s), include(s),” “comprising, including,” “contain(s),” and “containing” are intended to specify the presence of the mentioned features, integers, components, or actions, but they do not exclude the presence or addition of one or more other features, integers, components, actions, acts, or groups.

Claims

Claim 1 A method for depositing materials having reduced surface roughness, comprising: delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber; providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor — wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is 1:1 or greater —; forming a plasma of all precursors within the processing zone of the semiconductor processing chamber; and depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber. Claim 2 A method for depositing materials having reduced surface roughness, wherein, in claim 1, the silicon- and-boron materials are characterized by a surface roughness of 2 nm or less immediately after deposition. Claim 3 In claim 1, the plasma power density is 0.5 W / cm² while forming the plasma of all the precursors within the processing zone of the semiconductor processing chamber. 2 A method for depositing materials having reduced surface roughness maintained above. Claim 4 A method for depositing materials having reduced surface roughness, wherein, in claim 1, the substrate temperature is maintained at 400°C or higher while depositing the silicon- and boron material on the substrate. Claim 5 A method for depositing materials having reduced surface roughness, wherein, in claim 1, the pressure is maintained at 10 Torr or less while depositing the silicon- and boron material on the substrate. Claim 6 A method for depositing materials having reduced surface roughness, comprising the step of providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor in claim 1. Claim 7 A method for depositing materials having reduced surface roughness according to claim 1, further comprising the step of performing thermal annealing of the silicon- and-boron material following the deposition step. Claim 8 A method for depositing materials having reduced surface roughness according to claim 1, wherein the silicon-containing precursor comprises silane and the boron-containing precursor comprises diborane. Claim 9 A method for depositing materials having reduced surface roughness, comprising the steps of: delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber; forming a plasma of the silicon-containing precursor and the boron-containing precursor within the processing zone of the semiconductor processing chamber; and depositing silicon- and boron materials on a substrate disposed within the processing zone of the semiconductor processing chamber, wherein the silicon- and boron materials are characterized by a surface roughness of 2.0 nm or less immediately after deposition. Claim 10 A method for depositing materials having reduced surface roughness, further comprising the step of providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor — wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is 2:1 or greater. Claim 11 A method for depositing materials having reduced surface roughness according to claim 10, further comprising the step of providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the argon precursor to the hydrogen-containing precursor is 1:1 or less. Claim 12 A method for depositing materials having reduced surface roughness according to claim 9, further comprising, following the deposition step, a step of thermally annealing the silicon- and-boron material for a first time period. Claim 13 In claim 12, the substrate is maintained at a first temperature during the deposition, the substrate is maintained at a second temperature during thermal annealing of the silicon- and boron material, and the second temperature is higher than the first temperature, a method for depositing materials having reduced surface roughness. Claim 14 A method for depositing materials having reduced surface roughness, wherein the second temperature is 500°C or higher, in accordance with claim 13. Claim 15 A method for depositing materials having reduced surface roughness, wherein, in claim 9, the plasma power is maintained at 2.0 kW or more while forming a plasma of the silicon-containing precursor and the boron-containing precursor within the processing zone of the semiconductor processing chamber. Claim 16 A method for depositing materials having reduced surface roughness, comprising the steps of: delivering a silicon-containing precursor and a boron-containing precursor to a processing zone of a semiconductor processing chamber; forming a plasma of all precursors within the processing zone of the semiconductor processing chamber — wherein the plasma power density is 0.25 W / cm² while forming the plasma of all precursors within the processing zone of the semiconductor processing chamber. 2 A method for depositing materials having reduced surface roughness, comprising the step of maintaining above -; and depositing silicon- and boron materials on a substrate disposed within a processing zone of the semiconductor processing chamber. Claim 17 A method for depositing materials having reduced surface roughness, further comprising the step of providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor — wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is 2:1 or greater. Claim 18 A method for depositing materials having reduced surface roughness according to claim 17, further comprising the step of providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the argon precursor to the hydrogen-containing precursor is 1:1 or less. Claim 19 A method for depositing materials having reduced surface roughness according to claim 16, further comprising the step of performing thermal annealing of the silicon- and-boron material for a first time period following the deposition step. Claim 20 A method for depositing materials having reduced surface roughness, wherein, in claim 19, the substrate is maintained at a first temperature during the deposition, the substrate is maintained at a second temperature during the thermal annealing of the silicon- and boron materials, and the second temperature is higher than the first temperature.

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