Semiconductor device and electronic system including the same

Abstract

A semiconductor device is provided. The semiconductor device comprises: a substrate disposed on a peripheral circuit region and having a cell array region formed thereon; a first mold structure including insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures that penetrate the first mold structure and are spaced apart from each other in a first direction parallel to the upper surface of the substrate; a separation structure disposed between the first and second channel structures and separating the gate electrode layers in a first direction; and first and second auxiliary channel structures that penetrate a portion of the first mold structure and are disposed between the separation structure and the first channel structure and between the separation structure and the second channel structure, respectively.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and an electronic system including the same, and more specifically, to a three-dimensional semiconductor device including a vertical channel structure and improved electrical characteristics and a method for manufacturing the same. Background Technology

[0002] To satisfy the excellent performance and low price demanded by consumers, the integration density of semiconductor devices is increasing. In the case of two-dimensional or planar semiconductor devices, the integration density is determined by the area occupied by the unit memory cell. Therefore, three-dimensional semiconductor devices that arrange unit memory cells vertically are being developed recently.

[0003] In addition, to improve the integration density of semiconductor devices, the number of word line layers and channel holes stacked vertically within the semiconductor device is increasing. In this case, there is a problem of non-uniform etch loading in the etching process for forming holes and channel holes to form a word line separation structure for separating the word lines. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device capable of ensuring component reliability while reducing the number of process steps for forming patterns constituting the semiconductor device.

[0005] The problem that the present invention aims to solve is to provide an electronic system that can ensure component reliability while reducing the number of process steps for forming patterns constituting a semiconductor device.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate disposed on a peripheral circuit region and having a cell array region formed thereon; a first mold structure including insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures that penetrate the first mold structure and are spaced apart from each other in a first direction parallel to the upper surface of the substrate; a separation structure disposed between the first and second channel structures and separating the gate electrode layers in a first direction; and first and second auxiliary channel structures that penetrate a part of the first mold structure and are disposed between the separation structure and the first channel structure and between the separation structure and the second channel structure, respectively.

[0008] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate having a plurality of cell regions, a separation region between the plurality of cell regions, and a dummy region between one of the plurality of cell regions and the separation region; a mold structure including insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures spaced apart from each other in a first direction parallel to the upper surface of the substrate and penetrating the mold structure in each of the plurality of cell regions; a separation structure disposed between the first and second channel structures in the first direction in the separation region; and first and second auxiliary channel structures spaced apart from each other in a second direction intersecting the first direction in the dummy region, wherein, with respect to the second direction, the first channel structure and the separation structure are each disposed between the first and second auxiliary channel structures.

[0009] An electronic system according to some embodiments of the present invention for achieving the above technical problem comprises a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device comprises a substrate having a plurality of cell regions spaced apart from each other in a first direction, a separation region disposed between the plurality of cell regions in the first direction, and a dummy region disposed between one of the plurality of cell regions and the separation region with respect to the first direction, a first mold structure including insulating layers and gate electrode layers alternately stacked on the substrate, a first and second channel structure spaced apart from each other in a second direction intersecting the first direction and penetrating the first mold structure in each of the plurality of cell regions, a first and second separation structure disposed at the same position as the first and second channel structures with respect to the second direction in the separation region and spaced apart from each other in the second direction, and a first and second auxiliary channel structure spaced apart from each other in the dummy region in the second direction, wherein the first and second auxiliary channel structures penetrate the upper portion of the first mold structure but do not come into contact with the bottom surface of the first mold structure.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is an exemplary block diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. FIG. 3 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 4 is a schematic diagram showing a cross-sectional view cut along line AA of Figure 3. Figure 5 is an enlarged view of R1 in Figure 4. FIG. 6 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to an enlarged view of R1 in FIG. 5. Figure 7 is an enlarged view of R2 in Figure 4. FIG. 8 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 9 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to a cross-sectional view cut along line A-A' of FIG. 4. FIG. 10 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 11 is a schematic diagram showing a cross-sectional view cut along the line B-B' of Figure 10. FIG. 12 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 13 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 14 is a schematic diagram showing a cross-sectional view cut along the line C-C' of FIG. 13. FIGS. 15 to 19 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 20 and 21 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 22 is an intermediate step diagram for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 23 is an exemplary block diagram for illustrating an electronic system according to some embodiments. FIG. 24 is an exemplary perspective view for illustrating an electronic system according to some embodiments. FIG. 25 is a schematic cross-sectional view taken along the line I-I' of FIG. 24. Specific details for implementing the invention

[0012] Hereinafter, in order to explain the present invention more specifically, it will be described in more detail with reference to the attached drawings according to some embodiments of the present invention.

[0013] Hereinafter, a semiconductor memory device according to exemplary embodiments will be described with reference to FIGS. 1 to 7.

[0014] FIG. 1 is an exemplary block diagram for illustrating a semiconductor memory device according to some embodiments.

[0015] Referring to FIG. 1, a semiconductor memory device (10) according to some embodiments includes a memory cell array (20) and a peripheral circuit (30).

[0016] A memory cell array (20) may include a plurality of memory cell blocks (BLK1-BLKn). Each memory cell block (BLK1-BLKn) may include a plurality of memory cells. The memory cell array (20) may be connected to a peripheral circuit (30) via a bit line (BL), a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Specifically, the memory cell blocks (BLK1-BLKn) may be connected to a row decoder (33) via the word line (WL), the string select line (SSL), and the ground select line (GSL). Additionally, the memory cell blocks (BLK1-BLKn) may be connected to a page buffer (35) via the bit line (BL). Although not specifically illustrated, one memory cell block may be defined by two adjacent word line cutting structures. A plurality of channel structures (CH) described below may be disposed within each memory cell block defined by wordline cutting structures.

[0017] The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the semiconductor memory device (10), and can transmit and receive data (DATA) with a device outside the semiconductor memory device (10). The peripheral circuit (30) may include control logic (37), a row decoder (33), and a page buffer (35). Although not illustrated, the peripheral circuit (30) may further include various sub-circuits, such as an input / output circuit, a voltage generation circuit that generates various voltages required for the operation of the semiconductor memory device (10), and an error correction circuit for correcting errors in data (DATA) read from the memory cell array (20).

[0018] The control logic (37) can be connected to the row decoder (33), the input / output circuit, and the voltage generation circuit. The control logic (37) can control the overall operation of the semiconductor memory device (10). The control logic (37) can generate various internal control signals used within the semiconductor memory device (10) in response to a control signal (CTRL). For example, the control logic (37) can adjust the voltage levels provided to the word line (WL) and bit line (BL) when performing memory operations such as program operation or erase operation.

[0019] The row decoder (33) can select at least one of a plurality of memory cell blocks (BLK1-BLKn) in response to an address (ADDR), and can select at least one word line (WL), at least one string select line (SSL), and at least one ground select line (GSL) of the selected memory cell blocks (BLK1-BLKn). Additionally, the row decoder (33) can transmit a voltage for performing memory operations to the word line (WL) of the selected memory cell blocks (BLK1-BLKn).

[0020] The page buffer (35) can be connected to the memory cell array (20) via a bit line (BL). The page buffer (35) can operate as a writer driver or a sense amplifier. Specifically, when performing a program operation, the page buffer (35) can operate as a writer driver to apply a voltage to the bit line (BL) according to the data (DATA) to be stored in the memory cell array (20). Meanwhile, when performing a read operation, the page buffer (35) can operate as a sense amplifier to detect the data (DATA) stored in the memory cell array (20).

[0021] FIG. 2 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments.

[0022] Referring to FIG. 2, a memory cell array of a semiconductor device according to some embodiments may include a common source line (CSL), a plurality of bit lines (BL0-BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0-BL2).

[0023] Multiple cell strings (CSTRs) can be connected in parallel to each of the bit lines (BL0-BL2). Multiple cell strings (CSTRs) can be connected in common to a common source line (CSL). That is, multiple cell strings (CSTRs) can be placed between multiple bit lines (BL0-BL2) and a single common source line (CSL). Multiple common source lines (CSLs) can be arranged two-dimensionally. Here, the same electrical voltage can be applied to the common source lines (CSLs), or each of the common source lines (CSLs) can be electrically controlled.

[0024] For example, each cell string (CSTR) may consist of a string select transistor (SST), serially connected memory cells (MCT), and a ground select transistor (GST). Additionally, each memory cell (MCT) includes a data storage element.

[0025] For example, each cell string (CSTR) may include a string select transistor (SST) connected in series with bit lines (BL0-BL2). A ground select transistor (GST) may be connected to a common source line (CSL). Memory cells (MCT) may be connected in series between the string select transistor (SST) and the ground select transistor (GST).

[0026] Furthermore, each cell string (CSTR) may further include a dummy cell (DMCT) connected between a string select transistor (SST) and a memory cell (MCT).

[0027] Although not shown in the drawing, a dummy cell (DMCT) may also be connected between the ground select transistor (GST) and the memory cell (MCT). As another example, the ground select transistor (GST) in each cell string (CSTR) may be composed of multiple MOS transistors connected in series. As yet another example, each cell string (CSTR) may include multiple string select transistors connected in series. As yet another example, each cell string (CSTR) may further include an erase control transistor placed between the bit line (BL0-BL2) and the string select transistor (SST). The erase control transistor may be connected in series with the string select transistor (SST).

[0028] According to some embodiments, a string select transistor (SST) can be controlled by a string select line (SSL). Memory cells (MCT) can be controlled by multiple word lines (WL0-WLn), and dummy cells (DMCT) can be controlled by a dummy word line (DWL). Additionally, a ground select transistor (GST) can be controlled by a ground select line (GSL). A common source line (CSL) can be connected in common to the sources of the ground select transistors (GST).

[0029] A cell string (CSTR) may be composed of multiple memory cells (MCTs) that are different in distance from common source lines (CSL). Also, multiple word lines (WL0-WLn, DWL) may be placed between the common source lines (CSL) and the bit lines (BL0-BL2).

[0030] The gate electrodes of memory cells (MCTs) that are positioned at substantially the same distance from the common source lines (CSL) may be commonly connected to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. Alternatively, even if the gate electrodes of memory cells (MCTs) are positioned at substantially the same level from the common source lines (CSL), gate electrodes positioned in different rows or columns may be controlled independently.

[0031] The ground select lines (GSL0-GSL2) and string select lines (SSL) may extend in the same direction as, for example, the word lines (WL0-WLn, DWL). The ground select lines (GSL0-GSL2) and string select lines (SSL) placed at substantially the same level from the common source lines (CSL) may be electrically isolated from each other.

[0032] Although not shown in the drawing, if the cell string (CSTR) includes erase control transistors, the erase control transistors can be controlled by a common erase control line. The erase control transistors cause Gate Induced Drain Leakage (GIDL) during the erase operation of the memory cell array. That is, the erase control transistors may be GIDL transistors.

[0033] FIG. 3 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3. FIG. 5 is an enlarged view of R1 of FIG. 4. FIG. 6 is a diagram for explaining a semiconductor device according to some embodiments, corresponding to the enlarged view of R1 of FIG. 5. FIG. 7 is an enlarged view of R2 of FIG. 4.

[0034] Referring to FIGS. 3 through 7, a semiconductor device according to some embodiments includes a second substrate (100), a mold structure (ST), a channel structure (CH), a separation structure (WLC), and an auxiliary channel structure (DCH). FIG. 3 is a drawing showing the top surface of each of the channel structure (CH), the separation structure (WLC), and the auxiliary channel structure (DCH) in contact with the mold structure (ST) of FIG. 4.

[0035] According to some embodiments, the semiconductor device may include a cell array region (CA) and a peripheral circuit region (PA).

[0036] The peripheral circuit area (PA) may include a peripheral circuit element (PTR), a lower connection wiring (PW), and a peripheral logic insulating film (102).

[0037] Peripheral circuit elements (PTR) can be formed on the first substrate (101). Peripheral circuit elements (PTR) may be circuits that operate the structures of the cell array region (CA).

[0038] A peripheral logic insulating film (102) may be formed on a first substrate (101). The peripheral logic insulating film (102) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0039] The lower connection wiring (PW) can be formed within the surrounding logic insulating film (102). The lower connection wiring (PW) can be connected to a surrounding circuit element (PTR).

[0040] A cell array region (CA) may be placed on a peripheral circuit region (PA). The cell array region (CA) may include a second substrate (100), a common source plate (105), a supporting semiconductor layer (110), a mold structure (ST), a channel structure (CH), and a bit line (BL).

[0041] The second substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the second substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0042] A common source plate (105) can be placed on a second substrate (100). The common source plate (105) can serve as the common source line (CSL) of FIG. 2.

[0043] The common source plate (105) may include at least one of a conductive semiconductor film, a metal silicide film, and a metal film. When the common source plate (105) includes a conductive semiconductor film, the common source plate (105) may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The common source plate (105) may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. The common source plate (105) may include at least one of p-type impurities, n-type impurities, and carbon contained in the semiconductor film.

[0044] The supporting semiconductor layer (110) may be disposed on a common source plate (105). The supporting semiconductor layer (110) may include, for example, polysilicon, but is not limited thereto. The supporting semiconductor layer (110) may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), or a mixture thereof.

[0045] The cell array region (CA) may include a mold structure (ST). The mold structure (ST) may be placed on a common source plate (105).

[0046] A plurality of conductive lines (GSL, WL0-WLn) may include a ground selection line (GSL), a plurality of word lines (WL0-WLn), a dummy word line (DWL), at least one string selection line (SSL), and at least one erase control line (MCL). The ground selection line (GSL), the plurality of word lines (WL0-WLn), the dummy word line (DWL), the string selection line (SSL), and the erase control line (MCL) may be sequentially stacked on a second substrate (100).

[0047] Referring to Fig. 4, only six word lines (WL0-WLn) are shown on the ground selection line (GSL), but this is for convenience of explanation only and is not limited thereto.

[0048] Referring to FIG. 4, the mold structure (ST) may include a ground selection line (GSL) and some word lines (WL0-WLn).

[0049] In some embodiments, a mold structure (ST) may be disposed on a supporting semiconductor layer (110). The mold structure (ST) may include a plurality of gate electrode layers (GSL, WL0-WLn) and a plurality of inter-electrode insulating layers (140) alternately stacked on the supporting semiconductor layer (110). For example, each gate electrode layer (GSL, WL0-WLn) and each inter-electrode insulating layer (140) may be a layered structure extending in a first direction (Y) and a second direction (X). The gate electrode layers (GSL, WL0-WLn) and inter-electrode insulating layers (140) may be alternately stacked in a third direction (Z) that intersects (e.g., perpendicular) the upper surface of the second substrate (100).

[0050] In some embodiments, a plurality of gate electrode layers (GSL, WL0-WLn) may include a ground selection line (GSL) and a plurality of first word lines (WL0-WLn) that are sequentially stacked on a second substrate (100). In some embodiments, the ground selection line (GSL) may be a gate electrode disposed at the bottom of the plurality of gate electrode layers (GSL, WL0-WLn).

[0051] The gate electrode layer (GSL, WL0-WLn) may include a conductive material. For example, the first gate electrode layer (GSL, WL0-WLn) may include a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon, but is not limited thereto.

[0052] In some embodiments, the gate electrode layer (GSL, WL0-WLn) is depicted as being formed as a single film, but this is for convenience of explanation only and is not limited thereto.

[0053] Referring to FIG. 5, an insulating film (146) may be disposed between the gate electrode layer (GSL, WL0-WLn) and the information storage pattern (152). The insulating film (146) may comprise, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). Unlike what is illustrated, the insulating film (146) may not be disposed between the gate electrode layer (GSL, WL0-WLn) and the information storage pattern (152).

[0054] The gate electrode layer (GSL, WL0-WLn) may further include a barrier conductive film (147). The barrier conductive film (147) may include at least one of a metal, a metal nitride, a metal carbonitride, and a two-dimensional (2D) material. For example, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material may include a two-dimensional allotrope or a two-dimensional compound.

[0055] The inter-electrode insulating layer (140) may include an insulating material. For example, the inter-electrode insulating layer (140) may include silicon oxide, but is not limited thereto.

[0056] The channel structure (CH) can penetrate the mold structure (ST). Additionally, a plurality of channel structures (CH) can extend in a direction intersecting a plurality of gate electrode layers (GSL, WL0-WLn). For example, each channel structure (CH) can extend in a third direction (Z).

[0057] The width of the lower surface of the channel structure (CH) in the first direction (Y) may be smaller than the width of the upper surface of the channel structure (CH) in the first direction (Y). The width of the channel structure (CH) in the first direction (Y) may increase as it moves away from the upper surface of the second substrate (100). This may be attributed to the characteristics of the etching process for forming the channel structure (CH). However, the technical concept of the present invention is not limited thereto.

[0058] The channel structure (CH) may include a semiconductor pattern (150) and an information storage pattern (152).

[0059] The semiconductor pattern (150) can penetrate the mold structure (ST). For example, the semiconductor pattern (150) can extend in a third direction (Z). The semiconductor pattern (150) may include semiconductor materials such as, for example, single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0060] The information storage pattern (152) may be interposed between the semiconductor pattern (150) and each gate electrode layer (GSL, WL0-WLn). For example, the information storage pattern (152) may extend along the side of the semiconductor pattern (150).

[0061] The information storage pattern (152) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0062] In some embodiments, the information storage pattern (152) may include a plurality of films. For example, referring to FIGS. 4 and 5, the information storage pattern (152) of the channel structure (CH) may include a tunnel insulating film (152a), a charge storage film (152b), and a blocking insulating film (152c) formed along the profile of the channel hole (CH_h) penetrating the mold structure (ST).

[0063] The tunnel insulating film (152a) may comprise, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The charge storage film (152b) may comprise, for example, silicon nitride. The blocking insulating film (152c) may comprise, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0064] Referring to FIG. 5, the tunnel insulating layer (152a), the charge storage layer (152b), and the blocking insulating layer (152c) can be separated from the bottom of the channel structure (CH). A supporting semiconductor layer (110) can be placed between the separated tunnel insulating layer (152a), the charge storage layer (152b), and the blocking insulating layer (152c). The supporting semiconductor layer (110) can electrically connect the common source plate (105) and the semiconductor pattern (150).

[0065] Alternatively, referring to FIG. 6, when the supporting semiconductor layer (110) is not positioned, the tunnel insulating film (152a), the charge storage film (152b), and the blocking insulating film (152c) can be separated from the bottom surface of the channel structure (CH). That is, the sidewalls of the semiconductor pattern (150) are not exposed, and the bottom surface of the semiconductor pattern (150) can be exposed. The semiconductor pattern (150) can be electrically connected to the common source plate (105) through the exposed bottom surface of the semiconductor pattern (150).

[0066] In some embodiments, the channel structure (CH) may further include a filling pattern (154). The filling pattern (154) may be formed to fill the interior of the semiconductor pattern (150). For example, the semiconductor pattern (150) may extend along the side and bottom surfaces of the filling pattern (154). The filling pattern (154) may include, for example, silicon oxide, but is not limited thereto.

[0067] In some embodiments, the channel structure (CH) may further include a channel pad (156). The channel pad (156) may be formed to be connected to the upper portion of the semiconductor pattern (150). For example, the channel pad (156) may be formed within an inter-electrode insulating layer (140) disposed on the upper portion of the mold structure (ST).

[0068] In FIG. 4, the channel pad (156) is shown as being formed on the upper surface of the semiconductor pattern (150), but this is merely exemplary. For example, the upper surface of the semiconductor pattern (150) may be formed to extend along the side of the channel pad (156). The channel pad (156) may comprise, for example, impurity-doped polysilicon, but is not limited thereto.

[0069] Referring to FIGS. 3 and 4, a first and second cell region (A1_1, A1_2), a separation region (A2) between the first and second cell region (A1_1, A1_2), a first dummy region (A3_1) between the first cell region (A1_1) and the separation region (A2), and a second dummy region (A3_2) between the second cell region (A1_2) and the separation region (A2) may be formed on the second substrate (100).

[0070] The channel structure (CH) may penetrate the mold structure (ST) and include first and second channel patterns (CH_11, CH_12) and third and fourth channel patterns (CH_13, CH_14) that are spaced apart from each other in a second direction (X). Additionally, the channel structure (CH) may include first and third channel patterns (CH_11, CH_13) and second and fourth channel patterns (CH_12, CH_14) that are spaced apart from each other in a first direction (Y). The first and second channel patterns (CH_11, CH_12) may be formed in a first cell array region (CA_1), and the third and fourth channel patterns (CH_13, CH_14) may be formed in a second cell array region (CA_2).

[0071] In some embodiments, the first channel structure (CH_1) may be arranged in a zigzag shape. For example, as shown in FIG. 3, a plurality of channel structures (CH) may be arranged alternately in a first direction (Y) and a second direction (X). A plurality of channel structures (CH) arranged in a zigzag shape can further improve the integration density of a non-volatile memory device.

[0072] The first interlayer insulating film (165) and the second interlayer insulating film (173) may include, for example, silicon oxide, but are not limited thereto.

[0073] Multiple bit lines (180) can be extended side by side in the first direction (Y) at spaced intervals from each other.

[0074] Each bit line (180) can be connected to a plurality of channel structures (CH). For example, as shown in FIG. 4, a bit line (BL) can be connected to a plurality of channel structures (CH) through a bit line contact (177). The bit line contact (177) can electrically connect the bit line (180) and the channel structures (CH) by penetrating, for example, a first interlayer insulating film (165) and a second interlayer insulating film (173).

[0075] The mold structure (ST) can be separated by the separation structure (WLC). The separation structure (WLC) can be extended in a direction intersecting the bit line (180). For example, the separation structure (WLC) can be extended in a third direction (Z) to completely cut the mold structure (ST).

[0076] Accordingly, multiple gate electrode layers (GSL, WL0-WLn) can be cut by the separation structure (WLC). The cell array region (CA) of the mold structure (ST) can be separated by the separation structure (WLC).

[0077] Referring to FIG. 3, the separation structure (WLC) may include first and second separation patterns (WLC_1, WLC_2) spaced apart from each other in a second direction (X) in a separation region (A2) between first and second cell array regions (CA_1, CA_2).

[0078] An auxiliary channel structure (DCH) may be placed in a dummy area (A3) between a separation structure (WLC) and a channel structure (CH). Specifically, the auxiliary channel structure (DCH) may include a first auxiliary channel pattern (DCH_11) placed in a first dummy area (A3_1) between a first channel pattern (CH_11) and a first separation pattern (WLC_1), and a second auxiliary channel pattern (DCH_12) spaced apart from the first auxiliary channel pattern (DCH_11) in a second direction (X) and placed in a first dummy area (A3_1) between a second channel pattern (CH_12) and a second separation pattern (WLC_2).

[0079] Additionally, the auxiliary channel structure (DCH) may include a third auxiliary channel pattern (DCH_13) placed in a second dummy area (A3_2) between the third channel pattern (CH_13) and the first separation pattern (WLC_1), and a fourth auxiliary channel pattern (DCH_14) spaced apart from the third auxiliary channel pattern (DCH_13) in a second direction (X) and placed in a second dummy area (A3_2) between the fourth channel pattern (CH_14) and the second separation pattern (WLC_2).

[0080] The auxiliary channel structure (DCH) may penetrate a portion of the mold structure (ST). The auxiliary channel structure (DCH) may penetrate the upper part of the mold structure (ST) but may not come into contact with the bottom surface of the mold structure (ST). In this case, the auxiliary channel structure (DCH) may penetrate the upper part of the mold structure (ST) but may not come into contact with the lowest gate electrode layer (GSL) or the common source plate (105). For example, referring to FIGS. 3 and 4, the height of the bottom of the first and third auxiliary channel patterns (DCH_11, DCH_13) may be placed at a higher level than the height of the bottom of the first_1 and first_3 channel patterns (CH_11, CH_13).

[0081] The diameter of the auxiliary channel hole (DCH_h) may be smaller than the diameter of the channel hole (CH_h). That is, referring to FIG. 3, the diameter (r1) of the upper surface of the auxiliary channel structure (DCH) in contact with the mold structure (ST) may be smaller than the diameter (r2) of the upper surface of the channel structure (CH) and the diameter (r3) of the upper surface of the separation structure (WLC). In some embodiments, the diameter described as relative to the comparison may mean the diameter at the same height or the maximum diameter.

[0082] The auxiliary channel structure (DCH) may include a plurality of membranes. Referring to FIGS. 4 and 7, the auxiliary channel structure (DCH) may include at least one of a first layer (162c), a second layer (162b), and a third layer (162a) formed along the profile of an auxiliary channel hole (DCH_h) penetrating a part of the mold structure (ST).

[0083] The first layer (162c) may contain an oxide, the second layer (162b) may contain a nitride, and the third layer (162a) may contain an oxide. In this case, the oxides contained in the first layer (162c) and the third layer (162a) may be different from each other. Additionally, the oxide contained in the mold structure (ST) and the oxide contained in the first layer (162c) may be different from each other. However, the technical concept of the present invention is not limited thereto.

[0084] Each bit line (180) can be connected to a plurality of auxiliary channel structures (DCH). For example, as shown in FIG. 4, a bit line (BL) can be connected to a plurality of auxiliary channel structures (DCH) through a bit line contact (177).

[0085] The auxiliary channel structure (DCH) can be positioned alternately with the channel structure (CH) and the separation structure (WLC). For example, referring to FIG. 3, the first auxiliary channel pattern (DCH_11) can be positioned alternately with the first channel pattern (CH_11) and the first separation pattern (WLC_1) with respect to the first direction (Y). The third auxiliary channel pattern (DCH_13) can be positioned alternately with the third channel pattern (CH_13) and the first separation pattern (WLC_1) with respect to the first direction (Y).

[0086] Meanwhile, the channel structure (CH) and the separation structure (WLC) can be positioned at the same location relative to the second direction (X). For example, referring to FIG. 3, the first channel pattern (CH_11) and the first separation pattern (WLC_1), and the second channel pattern (CH_12) and the second separation pattern (WLC_2) can each be positioned at the same location relative to the second direction (X).

[0087] Based on a direction parallel to the upper surface of the second substrate (100), adjacent auxiliary channel structures (DCH) and channel structures (CH), and adjacent auxiliary channel structures (DCH) and separation structures (WLC) can form a triangular shape. For example, referring to FIG. 3, the first auxiliary channel pattern (DCH_11), the first separation pattern (WLC_1), and the second separation pattern (WLC_2) can form a triangular shape. The first auxiliary channel pattern (DCH_11), the first channel pattern (CH_11), and the second channel pattern (CH_12) can form a triangular shape.

[0088] The distance between adjacent auxiliary channel structures (DCH), the distance between adjacent auxiliary channel structures (DCH) and channel structures (CH), and the distance between adjacent auxiliary channel structures (DCH) and separation structures (WCL) can be formed as a specific range of the distance between adjacent channel structures (CH).

[0089] For example, referring to FIG. 3, the first distance (D1) between the first auxiliary channel pattern (DCH_11) and the second auxiliary channel pattern (DCH_12), the second distance (D2) between the first auxiliary channel pattern (DCH_11) and the first channel pattern (CH_11), and the third distance (D3) between the first auxiliary channel pattern (DCH_11) and the first separation pattern (WLC_1) may each be an integer multiple of the fourth distance (D4) between the first channel pattern (CH_11) and the second channel pattern (CH_12), or at least 0.5 times and no more than 1.5 times.

[0090] The distance between adjacent auxiliary channel structures (DCH), the distance between adjacent auxiliary channel structures (DCH) and channel structures (CH), and the distance between adjacent auxiliary channel structures (DCH) and separation structures (WCL) can be formed as a specific range of the distance between adjacent separation structures (WLC).

[0091] Each of the first distance (D1) between the first auxiliary channel pattern (DCH_11) and the second auxiliary channel pattern (DCH_12), the second distance (D2) between the first auxiliary channel pattern (DCH_11) and the first channel pattern (CH_11), and the third distance (D3) between the first auxiliary channel pattern (DCH_11) and the first separation pattern (WLC_1) may be at least 0.5 times and no more than 1.5 times the fifth distance (D5) between the first separation pattern (WLC_1) and the second separation pattern (WLC_2).

[0092] In some embodiments, the first to fifth distances (D1 to D5) may refer to the distance measured with respect to the centers of the upper surfaces, i.e., the pitch between the patterns, with respect to the upper surface where each pattern contacts the first mold structure (ST1).

[0093] FIG. 8 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 7 are briefly explained or omitted.

[0094] The auxiliary channel structures (DCH) and the separation structures (WLC) adjacent to each other can be merged with each other. For example, the first and second auxiliary channel patterns (DCH_11, DCH_12) and the first and second separation patterns (WLC_1, WLC_2) can be merged with each other to form a single merge pattern (MP) on the upper surface of the mold structure (ST).

[0095] Referring to FIG. 8, in this case, the merge pattern (MP) may include a first extension pattern (P1) forming a bar shape extended in a second direction (X) and first and second protruding patterns (P2, P3) protruding from the first extension pattern (P1) in a first direction (Y). The first length (L1) of the first protruding pattern (P2) protruding in the first direction (Y) and the second length (L2) of the second protruding pattern (P3) protruding in the first direction (Y) may be different from each other.

[0096] FIG. 9 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to a cross-sectional view cut along line A-A' of FIG. 4. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 8 are briefly explained or omitted.

[0097] Referring to FIG. 9, the mold structure (ST) may further include a second mold structure (ST2) on the first mold structure (ST1). The first mold structure (ST1) may include a ground select line (GSL) and some word lines (WL0-WLk). The second mold structure (ST2) may include the remaining word lines (WLk+1-WLn), a dummy word line (DWL), a string select line (SSL), and an erase control line (ECL). Here, n is a natural number greater than k.

[0098] In some embodiments, the first mold structure (ST1) may be disposed on the supporting semiconductor layer (110). The first mold structure (ST1) may include a plurality of first gate electrode layers (GSL, WL0-WLk) and a plurality of first inter-electrode insulating layers (141) alternately stacked on the supporting semiconductor layer (110). For example, each of the first gate electrode layers (GSL, WL0-WLk) and each of the first inter-electrode insulating layers (141) may be a layered structure extending in a first direction (Y) and a second direction (X). The first gate electrode layers (GSL, WL0-WLk) and the first inter-electrode insulating layers (141) may be alternately stacked in a third direction (Z) that intersects (e.g., perpendicular) the upper surface of the second substrate (100).

[0099] In some embodiments, a plurality of first gate electrode layers (GSL, WL0-WLk) may include a ground selection line (GSL) and a plurality of first word lines (WL0-WLk) that are sequentially stacked on a second substrate (100). In some embodiments, the ground selection line (GSL) may be a gate electrode disposed at the bottom of the plurality of first gate electrode layers (GSL, WL0-WLk).

[0100] A second mold structure (ST2) may be disposed on a first mold structure (ST1). The second mold structure (ST2) may include a plurality of second gate electrode layers (WLk+1-WLn) and a plurality of second inter-electrode insulating layers (142) alternately stacked on the first mold structure (ST1). For example, each second gate electrode layer (WLk+1-WLn) and each second inter-electrode insulating layer (142) may be a layered structure extending in a first direction (Y) and a second direction (X).

[0101] The first gate electrode layer (GSL, WL0-WLk) and the second gate electrode layer (WLk+1-WLn) may include a conductive material. For example, the first gate electrode layer (GSL, WL0-WLk) and the second gate electrode layer (WLk+1-WLn) may include a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon, but are not limited thereto.

[0102] The first inter-electrode insulating layer (141) and the second inter-electrode insulating layer (142) may include an insulating material. For example, the first inter-electrode insulating layer (141) and the second inter-electrode insulating layer (142) may include silicon oxide, but are not limited thereto.

[0103] The first channel structure (CH_1) can penetrate the first mold structure (ST1), and the second channel structure (CH_2) can penetrate the second mold structure (ST2). The first and second channel structures (CH_1, CH_2) can be connected continuously. That is, the first and second channel structures (CH_1, CH_2) can be a single body.

[0104] A plurality of first and second channel structures (CH_1, CH_2) may be extended in a direction intersecting a plurality of gate electrode layers (GSL, WL0-WLn). For example, the first and second channel structures (CH_1, CH_2) may be extended in a third direction (Z).

[0105] The width of the lower surface of the second channel structure (CH_2) in the first direction (Y) may be smaller than the width of the upper surface of the second channel structure (CH_2) in the first direction (Y). The width of the second channel structure (CH_2) in the first direction (Y) may increase as it moves away from the upper surface of the second substrate (100). This may be attributed to the characteristics of the etching process for forming the second channel structure (CH_2).

[0106] The width of the top surface of the first channel structure (CH_1) in the first direction (Y) may be greater than the width of the bottom surface of the second channel structure (CH_2) in the first direction (Y). That is, the side walls of the first and second channel structures (CH_1, CH_2) may have a step difference. This may be due to the fact that the etching process penetrating the first mold structure (ST1) and the etching process penetrating the second mold structure (ST2) are performed separately.

[0107] The second channel structure (CH_2) may include a semiconductor pattern (150), an information storage pattern (152), and a filling pattern (154). The semiconductor pattern (150) may extend in a third direction (Z) through the first mold structure (ST1) and the second mold structure (ST2).

[0108] The description regarding the semiconductor pattern (150), information storage pattern (152), and filling pattern (154) of the second channel structure (CH_2) can be likewise applied to the description regarding the semiconductor pattern (150), information storage pattern (152), and filling pattern (154) of the first channel structure (CH_1) described above.

[0109] In some embodiments, the second channel structure (CH_2) may further include a channel pad (156). The channel pad (156) may be formed to be connected to the upper portion of the semiconductor pattern (150). For example, the channel pad (156) may be formed within a second inter-electrode insulating layer (142) disposed at the top of the second mold structure (ST2). The description of the material of the channel pad (156) of the second channel structure (CH_2) may likewise apply to the description of the material of the channel pad (156) of the first channel structure (CH_1) described above.

[0110] In some embodiments, a plurality of second channel structures (CH_2) are arranged in a zigzag shape to further improve the integration density of the non-volatile memory device.

[0111] The first mold structure (ST1) and the second mold structure (ST2) can be separated by a first separation pattern (WLC_1). The first separation pattern (WLC_1) can be extended in a direction intersecting the bit line (180). For example, the first separation pattern (WLC_1) can be extended in a third direction (Z) to completely cut the first mold structure (ST1) and the second mold structure (ST2). Accordingly, a plurality of first gate electrode layers (GSL, WL0-WLk) and a plurality of second gate electrode layers (WLk+1-WLn) can be cut by the first separation pattern (WLC_1).

[0112] The auxiliary channel structure (DCH) may be formed to penetrate the entirety of the second mold structure (ST2) and a portion of the first mold structure (ST1). For example, referring to FIG. 9, the first and third auxiliary channel patterns (DCH_11, DCH_13) may penetrate the entirety of the second mold structure (ST2) and a portion of the upper part of the first mold structure (ST1).

[0113] FIG. 10 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. FIG. 11 is a schematic cross-sectional view taken along the line B-B' of FIG. 10. FIG. 12 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 9 are briefly explained or omitted.

[0114] Referring to FIGS. 10 and 11, an auxiliary channel structure (DCH) may not be formed between the separation structure (WLC) and the channel structure (CH). In this case, an auxiliary channel structure (DCH) may not be formed on the upper surface of the mold structure (ST).

[0115] Referring to FIG. 12, the first and second separation patterns (WLC_1, WLC_2) can be merged with each other to form a single merge pattern (MP).

[0116] In this case, the merge pattern (MP) may include a first extension pattern (P1) forming a bar shape extended in a second direction (X) and a first protrusion pattern (P2) protruding in a first direction (Y) from the first extension pattern (P1).

[0117] FIG. 13 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. FIG. 14 is a schematic cross-sectional view taken along the line C-C' of FIG. 13. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 12 are briefly explained or omitted.

[0118] Referring to FIGS. 13 and 14, an auxiliary channel structure (DCH) may be partially formed between the separation structure (WLC) and the channel structure (CH). In this case, the auxiliary channel structure (DCH) may be formed to have a smaller diameter and depth than in FIG. 4. For example, referring to FIG. 14, the auxiliary channel structure (DCH) may be in contact with the insulating layer (140) at the top of the mold structure (ST) and may not be in contact with the gate electrode layer (WLn) at the top.

[0119] In this case, an oxide layer may be formed inside the auxiliary channel structure (DCH). However, the technical concept of the present invention is not limited thereto.

[0120] FIGS. 15 to 19 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 7 are briefly explained or omitted. In some embodiments, a cell array region (CA) may be formed on a peripheral circuit region (PA) after the peripheral circuit region (PA) is formed, but the technical concept of the present invention is not limited thereto. In FIGS. 15 to 19, the peripheral circuit region (PA) is excluded from the description for convenience of explanation.

[0121] Referring to FIG. 15, a common source plate (105) and a supporting semiconductor layer (110) may be formed on a second substrate (100). On the common source plate (105), a pre-molded structure (ST') may be formed, comprising an inter-electrode insulating layer (140) and a sacrificial layer (121) that are stacked in sequence. The sacrificial layer (121) may include a material having an etching selectivity ratio with respect to the inter-electrode insulating layer (140). For example, if the inter-electrode insulating layer (140) includes silicon oxide, the sacrificial layer (121) may include polysilicon.

[0122] A hard mask film (HM) and a resist film (RE) can be formed on a pre-molded structure (ST').

[0123] Referring to FIG. 16, a hard mask film (HM) can be formed into a hard mask pattern (HP). Although not specifically illustrated, a resist film (RE) can be patterned into a resist pattern using a photomask pattern, and a hard mask film (HM) can be patterned into a hard mask pattern (HP) using a resist pattern.

[0124] Referring to FIG. 17, channel holes (CH_h), separation structure holes (WLC_h), and auxiliary channel holes (DCH_h) penetrating a pre-molded structure (ST') can be formed simultaneously using a hard mask pattern (HP).

[0125] A channel sacrifice pattern (124) can be formed within the channel hole (CH_h). An auxiliary channel sacrifice pattern (124') can be formed within the auxiliary channel hole (DCH_h).

[0126] The channel sacrifice pattern (124) may include, for example, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0127] The hard mask pattern (HP) can be removed.

[0128] Referring to FIG. 18, a channel structure (CH) can be formed by removing a channel sacrifice pattern (124), and an auxiliary channel structure (DCH) can be formed by removing an auxiliary channel sacrifice pattern (124'). A first interlayer insulating film (165) can be formed on an inter-electrode insulating layer (140).

[0129] According to some embodiments, by forming an auxiliary channel structure (DCH) between a separation structure (WLC) and a channel structure (CH), the difference in etch loading between patterns can be reduced while further reducing the height difference of the hard mask pattern (HP) in the etching process for forming the separation structure hole (WLC_h) and the channel hole (CH_h). Furthermore, according to some embodiments, by simultaneously forming the channel hole (CH_h), the separation structure hole (WLC_h), and the auxiliary channel hole (DCH_h), the process for forming the patterns can be simplified.

[0130] Referring to FIG. 19, a separation pattern (WLC) can be formed in a separation structure hole (WLC_h). An insulating material can be filled inside the separation structure hole (WLC_h) to form the separation pattern (WLC). The type of insulating material is not limited, but may include, for example, an oxide.

[0131] Subsequently, gate electrode layers (GSL, WL0-WLn) can be formed in the space where the sacrificial layer (121) has been removed. That is, the sacrificial layer (121) can be replaced with the gate electrode layers (GSL, WL0-WLn) through a replacement metal gate process. Accordingly, the mold structure (ST) of FIG. 4, in which an auxiliary channel structure (DCH) is formed in the outermost region of the first and second cell array regions (CA_1, CA_2), can be formed.

[0132] FIGS. 20 and 21 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 19 are briefly explained or omitted.

[0133] Referring to FIG. 20, after forming a hard mask film and a resist film, the hard mask film can be patterned into a hard mask pattern (HP) using a photomask pattern and a resist pattern. In this case, only a portion of the hard mask film can be patterned in the region where an auxiliary channel structure (DCH) is to be formed between the separation structure (WLC) and the channel structure (CH). That is, only a portion of the hard mask film is etched so that the bottom surface of the hard mask film is not patterned.

[0134] Referring to FIG. 21, a channel hole (CH_h) and a separation structure hole (WLC_h) penetrating a pre-molded structure (ST') can be formed simultaneously using a hard mask pattern (HP) that is only partially patterned. In this case, an auxiliary channel structure (DCH) may not be formed on the upper surface of the pre-molded structure (ST'). That is, as in FIG. 10 and FIG. 11, an auxiliary channel structure (DCH) may not be formed between the separation structure (WLC) and the channel structure (CH). Subsequently, a channel sacrifice pattern (124) can be formed in the channel hole (CH_h).

[0135] FIG. 22 is an intermediate step diagram for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 21 are briefly explained or omitted.

[0136] Although not specifically illustrated, a first channel hole (CH_h1) and a first auxiliary channel hole (DCH_h1) penetrating a first pre-molded structure (ST1') can be formed simultaneously using a lower hard mask pattern.

[0137] A channel sacrifice pattern (124) may be formed within the first channel hole (CH_h1). An auxiliary channel sacrifice pattern (124') may be formed within the first auxiliary channel hole (DCH_h1). Subsequently, the auxiliary channel sacrifice pattern (124') may be removed.

[0138] A second pre-molded structure (ST2') may be formed, comprising a second inter-electrode insulating layer (142) and a second sacrificial layer (122) sequentially stacked on a first pre-molded structure (ST1'). The second sacrificial layer (122) may include a material having an etching selectivity ratio with respect to the second inter-electrode insulating layer (142). For example, if the second inter-electrode insulating layer (142) includes silicon oxide, the second sacrificial layer (122) may include polysilicon.

[0139] For example, the second sacrificial layer (122) may contain the same material as the first sacrificial layer (121), and the second inter-electrode insulating layer (142) may contain the same material as the first inter-electrode insulating layer (141).

[0140] Although not specifically illustrated, an upper hard mask pattern can be formed on the second pre-mold structure (ST2').

[0141] A second channel hole (CH_h2), a separation structure hole (WLC_h), and a second auxiliary channel hole (DCH_h2) penetrating the second pre-molded structure (ST2') can be formed simultaneously.

[0142] In this case, as shown in FIG. 9, the auxiliary channel structure (DCH) can be formed to penetrate the entire second mold structure (ST2) and a part of the first mold structure (ST1).

[0143] FIG. 23 is an exemplary block diagram illustrating an electronic system according to some embodiments. FIG. 24 is an exemplary perspective view illustrating an electronic system according to some embodiments. FIG. 25 is a schematic cross-sectional view cut along the line I-I' of FIG. 24.

[0144] Referring to FIG. 23, an electronic system (1000) according to some embodiments may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100).

[0145] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In some embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0146] In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0147] In some embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0148] In some embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT1) may be used for an erase operation to erase data stored in memory cell transistors (MCTs) using the Gate Induced Drain Leakage (GIDL) phenomenon.

[0149] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0150] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The semiconductor device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0151] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1100).

[0152] The processor (1210) can control the operation of the entire electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., may be transmitted. The host interface (1230) may provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0153] Referring to FIG. 24, a semiconductor memory system (2000) according to some embodiments may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more non-volatile memory packages (2003), and a DRAM (2004). The non-volatile memory packages (2003) and the DRAM (2004) may be connected to each other by wiring patterns (2005) formed on the main board (2001) with respect to the controller (2002).

[0154] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In some embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In some embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a non-volatile memory package (2003).

[0155] The controller (2002) can write data to the non-volatile memory package (2003) or read data from the non-volatile memory package (2003), and can improve the operating speed of the electronic system (2000).

[0156] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the non-volatile memory package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations for the non-volatile memory package (2003). When the electronic system (2000) includes the DRAM (2004), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the non-volatile memory package (2003).

[0157] A semiconductor memory package (2003) may include first and second semiconductor memory packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor memory packages (2003a, 2003b) may each be a semiconductor memory package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor memory packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0158] The package substrate (2100) may be a printed circuit board including package upper pads (2130). The package substrate (2100) may include a package substrate body (2120), package upper pads (2130) disposed on the upper surface of the package substrate body (2120), lower pads (2125) disposed on the lower surface of the package substrate body (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main board (2010) of the electronic system (2000) through conductive connections (2800).

[0159] Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 23. Each of the semiconductor chips (2200) may include word lines (3210) and channel structures (3220). Each of the semiconductor chips (2200) may include the semiconductor device described above.

[0160] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor memory packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to another embodiment, in each of the first and second non-volatile memory packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0161] In exemplary embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. In an exemplary embodiment, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0162] Referring to FIG. 25, each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), memory channel structures (3220) and separation structures (3230) penetrating the gate stacking structure (3210), bit lines (3240) electrically connected to the memory channel structures (3220), and gate connection wiring (1115) electrically connected to the word lines (WL) of the gate stacking structure (3210).

[0163] The semiconductor device illustrated in FIG. 25 comprises a second substrate (100) disposed on a peripheral circuit region (PA) and having a cell array region (CA) formed thereon, a mold structure (ST) including an inter-electrode insulating layer (140) and a gate electrode layer (GSL, WL0-WLn) stacked on the second substrate (100), a plurality of channel structures (CH) that penetrate the mold structure (ST) and are spaced apart from each other in one direction parallel to the upper surface of the second substrate (100), a separation structure (WLC) disposed between the plurality of channel structures (CH) and separating the gate electrode layers (GSL, WL1-WLn) in one direction, and an auxiliary channel structure (DCH) that penetrates a part of the mold structure (ST) and is disposed between the separation structure (WLC) and each channel structure (CH).

[0164] The semiconductor device illustrated in FIG. 25 comprises: a second substrate (100) having first and second cell array regions (CA_1, CA_2) spaced apart from each other in one direction and a separation region (A2) disposed between the first and second cell array regions (CA_1, CA_2) in one direction; a mold structure (ST) including an insulating layer (140) and a gate electrode layer (GSL, WL1-WLn) alternately stacked on the second substrate (100); a plurality of channel structures (CH) spaced apart from each other in the other direction intersecting the first direction and penetrating the mold structure (ST) in each of the first and second cell array regions (CA_1, CA_2); a separation structure (WLC) spaced apart from each other in the other direction and disposed at the same position as the plurality of channel structures (CH) with respect to the other direction in the separation region (A2); and an auxiliary channel structure (DCH) spaced apart from each other in the other direction between the first and second cell array regions (CA_1, CA_2) and the separation region (A2), wherein the auxiliary The channel structure (DCH) penetrates the upper part of the mold structure (ST) but does not come into contact with the bottom surface of the mold structure (ST).

[0165] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0166] 100: Substrate 105: Common source plate 110: Support semiconductor layer ST: Mold structure CH: Channel structure DCH: Auxiliary channel structure WLC: Separation structure 180: Bit line

Claims

Claim 1 A semiconductor device comprising: a substrate disposed on a peripheral circuit region and having a cell array region formed thereon; a first mold structure including insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures that penetrate the first mold structure and are spaced apart from each other in a first direction parallel to the upper surface of the substrate; a separation structure disposed between the first and second channel structures and separating the gate electrode layers in the first direction; and first and second auxiliary channel structures that penetrate a part of the first mold structure and are respectively disposed between the separation structure and the first channel structure and between the separation structure and the second channel structure, wherein the first and second auxiliary channel structures and the separation structure are merged with each other to form a merge pattern. Claim 2 A semiconductor device according to claim 1, further comprising a common source plate disposed below the gate electrode layers on the substrate and in contact with the first and second channel structures, wherein the first and second auxiliary channel structures penetrate the upper portion of the first mold structure but do not contact the common source plate. Claim 3 A semiconductor device according to claim 1, wherein the height of the bottom of the first and second auxiliary channel structures is placed at a level higher than the height of the bottom of the first and second channel structures. Claim 4 A semiconductor device according to claim 1, further comprising a second mold structure including alternately stacked insulating layers and gate electrode layers on the first mold structure, wherein the first and second auxiliary channel structures penetrate the second mold structure. Claim 5 A semiconductor device according to claim 1, wherein the first and second channel structures each include a blocking film, a charge storage film, a tunnel insulating film, and a semiconductor pattern formed along the profiles of the first and second channel holes penetrating the first mold structure, and the first and second auxiliary channel structures each include an oxide layer formed along the profiles of the first and second auxiliary channel holes penetrating a part of the first mold structure, and the diameters of the first and second auxiliary channel holes are smaller than the diameters of the first and second channel holes. Claim 6 delete Claim 7 delete Claim 8 A semiconductor device comprising: a substrate having a plurality of cell regions, a separation region between the plurality of cell regions, and a dummy region between one of the plurality of cell regions and the separation region; a mold structure including insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures spaced apart from each other in a first direction parallel to the upper surface of the substrate, penetrating the mold structure in each of the plurality of cell regions; a separation structure disposed between the first and second channel structures in the first direction in the separation region; and first and second auxiliary channel structures spaced apart from each other in a second direction intersecting the first direction in the dummy region, wherein, with respect to the second direction, the first channel structure and the separation structure are each disposed between the first and second auxiliary channel structures, and the first and second auxiliary channel structures and the separation structure are merged with each other to form a merge pattern. Claim 9 A semiconductor device according to claim 8, wherein the first and second auxiliary channel structures penetrate the upper part of the mold structure but do not come into contact with the bottom surface of the mold structure. Claim 10 In claim 8, the merge pattern includes first and second protruding patterns protruding in the first direction, and the first length of the first protruding pattern protruding in the first direction and the second length of the second protruding pattern protruding in the first direction are different from each other in the semiconductor device.

Images