Display device

Abstract

The present invention relates to a display device capable of preventing a touch detection signal of a touch wiring from being affected by a data voltage of a data fan-out wiring or a scan control signal of a scan fan-out wiring. A display device according to one embodiment comprises a substrate including a display area and a non-display area, touch electrodes disposed in the display area, touch wiring disposed in the non-display area and connected to the touch electrodes, a low-potential wiring disposed in the non-display area to which a low-potential voltage is applied, and a high-potential wiring disposed in the non-display area to which a high-potential voltage higher than the low-potential voltage is applied. Any one of the touch wirings overlaps with at least one of the low-potential wiring and the high-potential wiring. The low-potential wiring overlaps with the high-potential wiring.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may further include pixels emitting a predetermined light, scan lines for driving the pixels, data lines, power lines, a scan driver that outputs scan signals to the scan lines, and a display driver that outputs data voltages to the data lines. In this case, data fan-out lines may be arranged between the data lines and the display driver, and scan fan-out lines may be arranged between the scan driver and the display driver.

[0004] Additionally, the display device may include a touch detection unit for detecting a user's touch as one of the input interfaces. The touch detection unit detects a user's touch by including a plurality of touch electrodes driven by a capacitive method. The plurality of touch electrodes may be connected to a plurality of touch wires.

[0005] In this case, if any one of the multiple touch wires overlaps with a data fan-out wire or a scan fan-out wire, a parasitic capacitance may be formed between the touch wire and the data fan-out wire or between the touch wire and the scan fan-out wire. Due to the parasitic capacitance, the touch signal of the touch wire may be affected by the data voltage of the data fan-out wire or the scan control signal of the scan fan-out wire, and thus a touch detection error may occur. The problem to be solved

[0006] The problem that the present invention aims to solve is to provide a display device capable of preventing the touch signal of the touch wiring from being affected by the data voltage of the data fan-out wiring or the scan control signal of the scan fan-out wiring.

[0007] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A display device according to one embodiment for solving the above problem comprises a substrate including a display area and a non-display area, touch electrodes disposed in the display area, touch wiring disposed in the non-display area and connected to the touch electrodes, low-potential wiring disposed in the non-display area to which a low potential voltage is applied, and high-potential wiring disposed in the non-display area to which a high potential voltage higher than the low potential voltage is applied. Any one of the touch wirings overlaps with at least one of the low-potential wiring and the high-potential wiring. The low-potential wiring overlaps with the high-potential wiring.

[0009] The above touch wiring can overlap with the above low potential wiring and the above high potential wiring.

[0010] The above touch wiring can overlap with the above low-potential wiring.

[0011] Data wiring disposed in the display area, and data fan-out wiring disposed in the non-display area and connected to the data wiring may be further provided. Any one of the data fan-out wirings may overlap with at least one of the low-potential wiring and the high-potential wiring.

[0012] The above data fan-out wiring can overlap with the above touch wiring.

[0013] The apparatus may further comprise scan lines disposed in the display area, a scan driving unit disposed in the non-display area and applying scan signals to the scan lines, and scan fan-out lines disposed in the non-display area and connected to the scan driving unit. Any one of the scan fan-out lines may overlap with at least one of the low potential line and the high potential line.

[0014] The above scan fan-out wiring can overlap with the above touch wiring.

[0015] The low potential wiring may include a first low potential wiring disposed on the substrate and a second low potential wiring disposed on the first low potential wiring. The high potential wiring may include a first high potential wiring disposed on the substrate and a second high potential wiring disposed on the first high potential wiring.

[0016] The above second low-potential wiring can overlap with the above first high-potential wiring.

[0017] The above first low-potential wiring can overlap with the above second high-potential wiring.

[0018] The first low-potential wiring and the first high-potential wiring may contain the same material, and the second low-potential wiring and the second high-potential wiring may contain the same material.

[0019] The above low-potential wiring may further include a third low-potential wiring disposed on the second low-potential wiring.

[0020] The above third low-potential wiring can overlap with the above first high-potential wiring.

[0021] The above first low-potential wiring can overlap with the above second high-potential wiring.

[0022] The first low-potential wiring and the first high-potential wiring may contain the same material, and the third low-potential wiring and the second high-potential wiring may contain the same material.

[0023] A display device according to another embodiment for solving the above problem comprises a substrate, a first active layer disposed on the substrate and including a channel region, a source region, and a drain region, a first gate insulating film disposed on the first active layer, a first gate electrode and a first capacitor electrode disposed on the first gate insulating film and overlapping with the channel region of the first active layer, a first interlayer insulating film disposed on the first gate electrode, a second capacitor electrode disposed on the first interlayer insulating film and overlapping with the first capacitor electrode, a second interlayer insulating film disposed on the second capacitor electrode, a first low-potential wiring and a first high-potential wiring disposed on the second interlayer insulating film, a second low-potential wiring disposed on the first low-potential wiring, and a second high-potential wiring disposed on the first high-potential wiring. At least one of the first low-potential wiring and the second low-potential wiring overlaps with at least one of the first high-potential wiring and the second high-potential wiring.

[0024] The apparatus may further comprise a first flattening film disposed between the first high-potential wiring and the second high-potential wiring, and a second flattening film disposed on the second high-potential wiring.

[0025] A display device according to another embodiment for solving the above problem comprises a substrate, a first active layer disposed on the substrate and including a channel region, a source region, and a drain region, a first gate insulating film disposed on the first active layer, a first gate electrode and a first capacitor electrode disposed on the first gate insulating film and overlapping with the channel region of the first active layer, a first interlayer insulating film disposed on the first gate electrode, a second capacitor electrode disposed on the first interlayer insulating film and overlapping with the first capacitor electrode, a second interlayer insulating film disposed on the second capacitor electrode, a first low-potential wiring and a first high-potential wiring disposed on the second interlayer insulating film, a second low-potential wiring disposed on the first low-potential wiring, a second high-potential wiring disposed on the first high-potential wiring, and a third low-potential wiring disposed on the second low-potential wiring. At least one of the first low-potential wiring and the third low-potential wiring overlaps with at least one of the first high-potential wiring and the second high-potential wiring.

[0026] The apparatus may further comprise a first flattening film disposed between the first high-potential wiring and the second high-potential wiring, a second flattening film disposed on the second high-potential wiring, and a third flattening film disposed on the third low-potential wiring.

[0027] A sealing layer comprising a first sealing inorganic film, a sealing organic film, and a second sealing inorganic film, disposed on the third flattening film, and a dam for preventing overflow of the sealing organic film may be provided. The first low-potential wiring, the second low-potential wiring, and the third low-potential wiring may overlap with the dam.

[0028] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0029] According to the display device of the embodiments, since the low-potential wiring and the high-potential wiring overlap each other in the non-display area located on the lower side of the display panel, the low-potential wiring or the high-potential wiring can be arranged between the touch wiring and the data fan-out wiring or the scan fan-out wiring. Therefore, it is possible to prevent the formation of parasitic capacitance between the touch wiring and the data fan-out wiring and between the touch wiring and the scan fan-out wiring. Accordingly, it is possible to prevent the touch driving signal or touch detection signal of the touch wiring from being affected by the data voltage of the data fan-out wiring or by the scan control signal of the scan fan-out wiring, thereby preventing touch detection errors from occurring.

[0030] In addition, according to the display device of the embodiments, the third low-potential wiring and the first high-potential wiring can overlap each other in the fan-out wiring area. Since the first flattening film and the second flattening film are disposed between the third low-potential wiring and the first high-potential wiring in the third direction, the distance between the third low-potential wiring and the first high-potential wiring in the third direction can be maximized. Therefore, the occurrence of burnt defects due to the potential difference between the high-potential voltage of the first high-potential wiring and the low-potential voltage of the third low-potential wiring can be reduced.

[0031] Furthermore, according to the display device of the embodiments, the first low-potential wiring and the second high-potential wiring can overlap each other in the fan-out wiring area. In the third direction, a first flattening film and a second flattening film can be disposed between the first low-potential wiring and the second high-potential wiring. Therefore, the distance between the first low-potential wiring and the second high-potential wiring in the third direction can be maximized. Consequently, the occurrence of burnt defects due to the potential difference between the high-potential voltage of the first high-potential wiring and the low-potential voltage of the second low-potential wiring can be reduced.

[0032] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0033] FIG. 1 is a perspective view showing a display device according to one embodiment. FIGS. 2 and FIGS. 3 are plan views showing a display device according to one embodiment. FIG. 4 is a side view showing a display device according to one embodiment. FIG. 5 is a circuit diagram showing a subpixel of a display layer according to one embodiment. FIG. 6 is a circuit diagram showing a subpixel of a display layer according to another embodiment. FIG. 7 is a circuit diagram showing a subpixel of a display layer according to another embodiment. FIG. 8 is a circuit diagram showing a subpixel of a display layer according to another embodiment. FIG. 9 is a layout diagram showing a touch sensing unit according to one embodiment. FIG. 10 is a layout diagram showing the light-emitting regions and touch electrodes of the display panel of FIG. 9. FIG. 11 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 10. FIG. 12 is a layout diagram showing a non-display area of ​​a display panel according to one embodiment. Figure 13 is a layout diagram showing area B of Figure 12 in detail. FIG. 14 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 13. FIG. 15 is a layout diagram showing a non-display area of ​​a display panel according to another embodiment. Figure 16 is a layout diagram showing in detail another example of area C of Figure 15. FIG. 17 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 16. FIG. 18 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 19 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 20 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 21 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 22 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 23 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 24 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 25 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 26 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 27 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. Specific details for implementing the invention

[0034] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0035] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0036] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0037] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0038] Specific embodiments will be described below with reference to the attached drawings.

[0039] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0040] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0041] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Although the following description focuses on the display device (10) being an organic light-emitting display device, the present invention is not limited thereto.

[0042] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0043] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0044] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0045] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include subpixels (SPX in FIG. 5) that display an image. The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA).

[0046] In FIG. 1, the sub-region (SBA) is illustrated as being unfolded, but the sub-region (SBA) can be bent, in which case it can be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it can overlap with the main region (MA) in the thickness direction (DR3) of the substrate (SUB). A display driving circuit (200) can be placed in the sub-region (SBA).

[0047] The display driving circuit (200) can generate signals and voltages to drive the display panel (100). The display driving circuit (200) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (200) may be attached to the circuit board (300) using a COF (chip on film) method.

[0048] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (200). The display panel (100) and the display driving circuit (200) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0049] FIGS. 2 and FIGS. 3 are plan views showing a display device according to one embodiment. FIG. 4 is a side view showing a display device according to one embodiment.

[0050] Figure 2 illustrates a sub-region (SBA) that is unfolded without being bent. Figures 3 and 4 illustrate a sub-region (SBA) that is bent.

[0051] Referring to FIGS. 2 to 4, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0052] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0053] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0054] The first scan driver (SDC1) and the second scan driver (SDC2) may be placed in a non-display area (NDA). The first scan driver (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driving circuit (200) through scan fan-out wiring (SFLs in FIG. 14). Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driving circuit (200), generate scan signals according to the scan control signal, and output them to the scan wiring.

[0055] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0056] The sub-region (SBA) may include a first region (A1), a second region (A2), and a bending region (BA).

[0057] The first area (A1) is an area protruding in the second direction (DR2) from one side of the main area (MA). One side of the first area (A1) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the first area (A1) may be in contact with the bending area (BA).

[0058] The second area (A2) is an area where pads (PDs) and a display driving circuit (200) are placed. The display driving circuit (200) can be attached to the driving pads of the second area (A2) using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste). The circuit board (300) can be attached to the pads (PDs) of the second area (A2) using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP. One side of the second area (A2) may be in contact with the bending area (BA).

[0059] The bending area (BA) is a bending area. When the bending area (BA) is bent, the second area (A2) may be positioned below the first area (A1) and below the main area (MA). The bending area (BA) may be positioned between the first area (A1) and the second area (A2). One side of the bending area (BA) is in contact with the first area (A1), and the other side of the bending area (BA) may be in contact with the second area (A2).

[0060] The display panel (100) may include a thin film transistor layer (TFTL), a light-emitting element layer (EML), an encapsulation layer (TFEL), and a touch sensing unit (TDU) as shown in FIG. 3.

[0061] The substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0062] A thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may be disposed in a main region (MA) and a sub-region (SBA). The thin-film transistor layer (TFTL) includes thin-film transistors.

[0063] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The light-emitting element layer (EML) can be disposed in the display area (DA) of the main area (MA). The light-emitting element layer (EML) includes light-emitting elements disposed in the light-emitting parts.

[0064] The encapsulation layer (TFEL) may be disposed on the light-emitting element layer (EML). The encapsulation layer (TFEL) may be disposed in the display area (DA) and non-display area (NDA) of the main area (MA). The encapsulation layer (TFEL) comprises at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer.

[0065] The touch detection unit (TDU) can be placed on the encapsulation layer (TFEL). The touch detection unit (TDU) can be placed in the display area (DA) and non-display area (NDA) of the main area (MA). The touch detection unit (TDU) can detect a touch of a person or object using touch electrodes.

[0066] A cover window may be disposed on the touch sensing unit (TDU) to protect the upper portion of the display panel (100). The cover window may be attached to the touch sensing unit (TDU) by a transparent adhesive material such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be an inorganic material such as glass, or an organic material such as plastic or polymer material.

[0067] Additionally, to prevent external light from reflecting off the display panel (100) and reducing the visibility of the image displayed by the display panel (100), an anti-reflection member may be additionally disposed between the touch detection unit (TDU) and the cover window. The anti-reflection member may be a polarizing film or a color filter.

[0068] The touch driving circuit (400) can be placed on the circuit board (300). The touch driving circuit (400) can be formed as an integrated circuit (IC) and attached to the circuit board (300).

[0069] The touch driving circuit (400) can be electrically connected to a plurality of driving electrodes and a plurality of sensing electrodes of the touch sensing unit (TDU). The touch driving circuit (400) applies a touch driving signal to the plurality of driving electrodes and detects a touch sensing signal of each of the plurality of touch nodes, for example, a change in the charge of mutual capacitance, through the plurality of sensing electrodes. The touch driving circuit (400) can determine whether a user touches and whether there is proximity, etc., based on the touch sensing signal of each of the plurality of touch nodes. A user touch refers to an object such as a user's finger or a pen directly contacting the front surface of the display device (10) placed on the touch sensing unit (TDU). A user proximity refers to an object such as a user's finger or a pen being positioned away from the front surface of the display device (10), such as hovering.

[0070] FIG. 5 is a circuit diagram showing a subpixel of a display layer according to one embodiment.

[0071] Referring to FIG. 5, a subpixel (SPX) can be connected to any two of the scan lines (SL), any one of the light-emitting lines (EL), and any one of the data lines. For example, the subpixel (SPX) can be connected to the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), the light-emitting line (EL), and the data line (DL).

[0072] The subpixel (SPX) includes a driving transistor (DT), a light-emitting element (LE), switching elements, and a capacitor (C1). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0073] The driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0074] The light-emitting element (LEL) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LEL) can be proportional to the driving current (Ids).

[0075] The light-emitting element (LEL) may be an organic light-emitting diode comprising an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a micro light-emitting diode.

[0076] The anode electrode of the light-emitting element (LEL) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode can be connected to the low potential wiring (VSL). A parasitic capacitance (Cel) may be formed between the anode electrode and the cathode electrode of the light-emitting element (LEL).

[0077] A capacitor (C1) is formed between the second electrode of the driving transistor (DT) and the high potential wiring (VSL). One electrode of the capacitor (C1) is connected to the second electrode of the driving transistor (DT), and the other electrode can be connected to the high potential wiring (VSL).

[0078] As shown in FIG. 5, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as P-type MOSFETs. The active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon or oxide semiconductor.

[0079] The gate electrode of the second transistor (ST2) and the gate electrode of the fourth transistor (ST4) are connected to the write scan line (GWL), and the gate electrode of the first transistor (ST1) can be connected to the control scan line (GCL). The gate electrode of the third transistor (ST3) can be connected to the initial scan line (GIL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as P-type MOSFETs, they can be turned on when a scan signal of gate low voltage and a light emission signal are applied to the control scan line (GCL), the initial scan line (GIL), the write scan line (GWL), and the light emission line (EL), respectively.

[0080] Alternatively, as shown in FIG. 6, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as P-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as N-type MOSFETs. The active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as N-type MOSFETs may be formed of an oxide semiconductor. In this case, since the transistors formed of polysilicon and the transistors formed of oxide semiconductors may be placed on different layers, the placement area of ​​each transistor in the pixels (PX) may be reduced.

[0081] The gate electrodes of the second transistor (ST2) and the fourth transistor (ST4) are connected to the write scan line (GWL), and the gate electrode of the first transistor (ST1) can be connected to the control scan line (GCL). The gate electrode of the third transistor (ST3) can be connected to the initial scan line (GIL). Since the first transistor (ST1) and the third transistor (ST3) are formed as N-type MOSFETs, they can be turned on when a scan signal with a gate high voltage is applied to the control scan line (GCL) and the initial scan line (GIL). In contrast, since the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as P-type MOSFETs, they can be turned on when a scan signal with a gate low voltage and a light emission signal are applied to the write scan line (GWL) and the light emission line (EL), respectively.

[0082] Alternatively, as shown in FIG. 7, the pixel (PX) may further include a seventh transistor (ST7). The active layer of the seventh transistor (ST7) may be formed of polysilicon. The gate electrode of the fourth transistor (ST4) and the gate electrode of the seventh transistor (ST7) may be connected to a bias scan line (GBL). Since the fourth transistor (ST4) and the seventh transistor (ST7) are formed as P-type MOSFETs, they can be turned on when a scan signal of gate low voltage is applied to the bias scan line (GBL).

[0083] Alternatively, as shown in FIG. 8, the active layer of the fourth transistor (ST4) may be formed of an oxide semiconductor. The gate electrode of the fourth transistor (ST4), the gate electrode of the fifth transistor (ST5), and the gate electrode of the sixth transistor (ST6) may be connected to the light-emitting wiring (EL). Since the fourth transistor (ST4) is formed as an N-type MOSFET, it can be turned on when a light-emitting signal of gate high voltage is applied to the light-emitting wiring (EL).

[0084] Alternatively, although not shown in FIGS. 5 to 8, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as N-type MOSFETs.

[0085] FIG. 9 is a layout diagram showing a touch sensing unit according to one embodiment.

[0086] In FIG. 9, the touch electrodes (SE) of the touch sensing unit (TDU) include two types of electrodes, for example, driving electrodes (TE) and sensing electrodes (RE), and are driven in a mutual capacitance manner in which a change in charge of each of the multiple touch nodes (TN) is detected through the sensing electrodes (RE) after a touch driving signal is applied to the driving electrodes (TE), but is not limited thereto.

[0087] In FIG. 9, for convenience of explanation, only the driving electrodes (TE), sensing electrodes (RE), dummy patterns (DE), touch wiring (SL), display pads (DP), and touch pads (TP1, TP2) are shown.

[0088] Referring to FIG. 9, the touch detection unit (TDU) includes a touch detection area (TSA) for detecting a user's touch and a touch peripheral area (TPA) disposed around the touch detection area (TSA). The touch detection area (TSA) is substantially the same as the display area (DA) shown in FIG. 1 to 4, and the touch peripheral area (TPA) may be substantially the same as the non-display area (NDA) shown in FIG. 1 to 4.

[0089] The touch sensing area (TSA) includes driving electrodes (TE), sensing electrodes (RE), and dummy patterns (DE). The driving electrodes (TE) and sensing electrodes (RE) may be electrodes for forming mutual capacitance to detect the touch of an object or person.

[0090] The sensing electrodes (RE) can be arranged in a first direction (DR1) and a second direction (DR2). The sensing electrodes (RE) can be electrically connected in the first direction (DR1). That is, adjacent sensing electrodes (RE) in the first direction (DR1) can be connected to each other. Adjacent sensing electrodes (RE) in the second direction (DR2) can be electrically separated from each other.

[0091] Driving electrodes (TE) can be arranged in a first direction (DR1) and a second direction (DR2). Driving electrodes (TE) can be electrically connected in the second direction (DR2). That is, adjacent driving electrodes (TE) in the second direction (DR2) can be connected to each other. For example, adjacent driving electrodes (TE) in the second direction (DR2) can be connected to each other through a connecting electrode (BE) as shown in FIG. 10. Adjacent driving electrodes (TE) in the first direction (DR1) can be electrically separated from each other.

[0092] A touch node (TN) in which mutual capacitance is formed can be disposed at each of the intersections of the driving electrodes (TE) and the sensing electrodes (RE). Multiple touch nodes (TN) can correspond to the intersections of the driving electrodes (TE) and the sensing electrodes (RE).

[0093] Each of the dummy patterns (DE) may be surrounded by a driving electrode (TE) or a sensing electrode (RE). Each of the dummy patterns (DE) may be electrically isolated from the driving electrode (TE) or the sensing electrode (RE). Each of the dummy patterns (DE) may be positioned apart from the driving electrode (TE) or the sensing electrode (RE). Each of the dummy patterns (DE) may be electrically floating.

[0094] In FIG. 9, the driving electrodes (TE), sensing electrodes (RE), and dummy patterns (DE) are each illustrated as having a rhombus planar shape, but are not limited thereto. For example, the driving electrodes (TE), sensing electrodes (RE), and dummy patterns (DE) may each have a planar shape other than a rhombus, a polygon other than a square, a circle, or an ellipse.

[0095] Touch wiring (SL) can be placed in a touch peripheral area (TPA). The touch wiring (SL) may include touch sensing wiring (RL) connected to sensing electrodes (RE), first touch driving wiring (TL1) and second touch driving wiring (TL2) connected to driving electrodes (TE).

[0096] Sensing electrodes (RE) positioned on one side of the touch sensing area (TSA) can be connected one-to-one to touch sensing wires (RL). For example, as shown in FIG. 9, a sensing electrode (RE) positioned at the right end among the sensing electrodes (RE) electrically connected in the first direction (DR1) can be connected to a touch sensing wire (RL). The touch sensing wires (RL) can be connected one-to-one to the second touch pads (TP2). Therefore, the touch driving circuit (400) can be electrically connected to the sensing electrodes (RE).

[0097] Driving electrodes (TE) positioned on one side of the touch detection area (TSA) may be connected one-to-one to the first touch driving wires (TL1), and driving electrodes (TE) positioned on the other side of the touch detection area (TSA) may be connected one-to-one to the second touch driving wires (TL2). For example, as shown in FIG. 9, among the driving electrodes (TE) electrically connected in the second direction (DR2), the driving electrode (TE) positioned at the lower end may be connected to the first touch driving wire (TL1), and the driving electrode (TE) positioned at the upper end may be connected to the second touch driving wire (TL2). The second touch driving wires (TL2) may be connected to the driving electrodes (TE) at the upper side of the touch detection area (TSA) via the left outer side of the touch detection area (TSA).

[0098] The first touch driving wires (TL1) and the second touch driving wires (TL2) can be connected one-to-one to the first touch pads (TP1). Therefore, the touch driving circuit (400) can be electrically connected to the driving electrodes (TE). Since the driving electrodes (TE) are connected to the driving wires (TL1, TL2) on both sides of the touch detection area (TSA) to receive the touch driving signal, it is possible to prevent a difference from occurring between the touch driving signal applied to the driving electrodes (TE) located on the lower side of the touch detection area (TSA) and the touch driving signal applied to the driving electrodes (TE) located on the upper side of the touch detection area (TSA) due to the RC delay of the touch driving signal.

[0099] A first touch pad area (TPA1) in which first touch pads (TP1) are placed may be placed on one side of a display pad area (DPA) in which display pads (DP) are placed. A second touch pad area (TPA2) in which second touch pads (TP2) are placed may be placed on the other side of the display pad area (DPA). The display pads (DP) may be electrically connected to the data wiring of the display panel (100).

[0100] The display pad area (DPA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may correspond to pads (PDs) of a display panel (100) connected to a circuit board (300) illustrated in FIG. 2. A circuit board (300) may be disposed on the display pads (DPs), the first touch pads (TP1), and the second touch pads (TP2). The display pads (DPs), the first touch pads (TP1), and the second touch pads (TP2) may be electrically connected to the circuit board (300) using a conductive adhesive member such as an anisotropic conductive film. Thus, the display pads (DPs), the first touch pads (TP1), and the second touch pads (TP2) may be electrically connected to a touch driving circuit (400) disposed on the circuit board (300).

[0101] FIG. 10 is a layout diagram showing the light-emitting regions and touch electrodes of the display panel of FIG. 9. FIG. 10 shows an example of a touch node (TN) of FIG. 9.

[0102] Referring to FIG. 10, the touch node (TN) can be defined as the intersection of driving electrodes (TE) and sensing electrodes (RE).

[0103] Since the driving electrodes (TE) and the sensing electrodes (RE) are placed on the same layer, they can be placed apart from each other. That is, a gap can be formed between adjacent driving electrodes (TE) and sensing electrodes (RE).

[0104] In addition, the dummy pattern (DE) can also be placed on the same layer as the driving electrodes (TE) and the sensing electrodes (RE). That is, a gap can be formed between adjacent driving electrodes (TE) and the dummy pattern (DE), and between adjacent sensing electrodes (RE) and the dummy pattern (DE).

[0105] The connecting electrodes (BE) may be placed on a different layer from the driving electrodes (TE) and the sensing electrodes (RE). The connecting electrode (BE) may be formed to be bent at least once. In FIG. 10, the connecting electrode (BE) is illustrated as having a bracket shape ("<" or ">"), but the planar shape of the connecting electrode (BE) is not limited thereto. Since driving electrodes (TE) adjacent to each other in the second direction (DR2) are connected by a plurality of connecting electrodes (BE), even if one of the connecting electrodes (BE) is disconnected, the driving electrodes (TE) adjacent to each other in the second direction (DR2) can be stably connected. In FIG. 10, driving electrodes (TE) adjacent to each other are illustrated as being connected by two connecting electrodes (BE), but the number of connecting electrodes (BE) is not limited thereto.

[0106] The connecting electrode (BE) can overlap adjacent driving electrodes (TE) in the second direction (DR2) from the third direction (DR3), which is the thickness direction of the substrate (SUB). The connecting electrode (BE) can overlap with the sensing electrode (RE) in the third direction (DR3). One side of the connecting electrode (BE) can be connected to any one of the driving electrodes (TE) adjacent to the second direction (DR2) through touch contact holes (TCNT1). The other side of the connecting electrode (BE) can be connected to another driving electrode (TE) adjacent to the second direction (DR2) through touch contact holes (TCNT1).

[0107] Due to the connecting electrodes (BE), the driving electrodes (TE) and the sensing electrodes (RE) can be electrically separated at their intersections. As a result, mutual capacitance can be formed between the driving electrodes (TE) and the sensing electrodes (RE).

[0108] Each of the driving electrodes (TE), sensing electrodes (RE), and connecting electrodes (BE) may have a planar shape of a mesh structure or a net structure. Additionally, each of the dummy patterns (DE) may have a planar shape of a mesh structure or a net structure. As a result, each of the driving electrodes (TE), sensing electrodes (RE), connecting electrodes (BE), and dummy patterns (DE) may not overlap with the light-emitting parts (EA1, EA2, EA3, EA4) of each pixel (PX). Therefore, the light emitted from the light-emitting parts (EA1, EA2, EA3, EA4) may be blocked by the driving electrodes (TE), sensing electrodes (RE), connecting electrodes (BE), and dummy patterns (DE), thereby preventing a reduction in the brightness of the light.

[0109] Each of the pixels (PX) may include a first light-emitting part (EA1) of a first subpixel emitting light of a first color, a second light-emitting part (EA2) of a second subpixel emitting light of a second color, a third light-emitting part (EA3) of a third subpixel emitting light of a third color, and a fourth light-emitting part (EA4) of a fourth subpixel emitting light of a second color. For example, the first color may be red, the second color may be green, and the third color may be blue.

[0110] The first light-emitting part (EA1) and the second light-emitting part (EA2) of each pixel (PX) may be adjacent to each other in the fourth direction (DR4), and the third light-emitting part (EA3) and the fourth light-emitting part (EA4) may be adjacent to each other in the fourth direction (DR4). The first light-emitting part (EA1) and the fourth light-emitting part (EA4) of each pixel (PX) may be adjacent to each other in the fifth direction (DR5), and the second light-emitting part (EA2) and the third light-emitting part (EA3) may be adjacent to each other in the fifth direction (DR5).

[0111] Each of the first light-emitting part (EA1), the second light-emitting part (EA2), the third light-emitting part (EA3), and the fourth light-emitting part (EA4) may have a rhombus-shaped planar form or a rectangular planar form, but is not limited thereto. Each of the first light-emitting part (EA1), the second light-emitting part (EA2), the third light-emitting part (EA3), and the fourth light-emitting part (EA4) may have a polygonal, circular, or elliptical planar form other than a rectangle. Additionally, FIG. 5 illustrates that the area of ​​the third light-emitting part (EA3) is the largest and the areas of the second light-emitting part (EA2) and the fourth light-emitting part (EA4) are the smallest, but is not limited thereto.

[0112] The second light-emitting parts (EA2) and the fourth light-emitting parts (EA4) may be arranged in odd rows. The second light-emitting parts (EA2) and the fourth light-emitting parts (EA4) may be arranged side by side in the first direction (DR1) in each of the odd rows. The second light-emitting parts (EA2) and the fourth light-emitting parts (EA4) may be arranged alternately in each of the odd rows. Each of the second light-emitting parts (EA2) may have a short side in the fourth direction (DR4) and a long side in the fifth direction (DR5), whereas each of the fourth light-emitting parts (EA4) may have a long side in the fourth direction (DR4) and a short side in the fifth direction (DR5). The fourth direction (DR4) may be a direction between the first direction (DR1) and the second direction (DR2), and may be a direction inclined at 45 degrees relative to the first direction (DR1). The fifth direction (DR5) may be a direction orthogonal to the fourth direction (DR4).

[0113] The first light-emitting parts (EA1) and the third light-emitting parts (EA3) may be arranged in even rows. The first light-emitting parts (EA1) and the third light-emitting parts (EA3) may be arranged side by side in the first direction (DR1) in each of the even rows. The first light-emitting parts (EA1) and the third light-emitting parts (EA3) may be arranged alternately in each of the even rows.

[0114] The second light-emitting units (EA2) and the fourth light-emitting units (EA4) may be arranged in odd columns. The second light-emitting units (EA2) and the fourth light-emitting units (EA4) may be arranged side by side in the second direction (DR2) in each of the odd columns. The second light-emitting units (EA2) and the fourth light-emitting units (EA4) may be arranged alternately in each of the odd columns.

[0115] The first light-emitting units (EA1) and the third light-emitting units (EA3) can be arranged in even columns. The first light-emitting units (EA1) and the third light-emitting units (EA3) can be arranged side by side in the second direction (DR2) in each of the even columns. The first light-emitting units (EA1) and the third light-emitting units (EA3) can be arranged alternately in each of the even columns.

[0116] FIG. 11 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 10.

[0117] Referring to FIG. 11, a barrier film (BR) may be disposed on a substrate (SUB). The substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0118] The barrier film (BR) is a film for protecting the transistors of the thin-film transistor layer (TFTL) and the light-emitting layer (172) of the light-emitting element layer (EML) from moisture penetrating through a substrate (SUB) that is vulnerable to moisture permeability. The barrier film (BR) may be composed of a plurality of inorganic films that are alternately stacked. For example, the barrier film (BR) may be formed as a multilayer film in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0119] A first thin-film transistor (TFT1) may be disposed on the barrier film (BR). The first thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIGS. 5 to 7. Alternatively, the first thin-film transistor (TFT1) may be the sixth thin-film transistor (ST6) shown in FIG. 8. The first thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0120] A first active layer (ACT1) of a first thin-film transistor (TFT1) may be disposed on a barrier film (BR). The first active layer (ACT1) of the first thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0121] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0122] A first gate insulating film (130) may be disposed on the first active layer (ACT1) of the first thin-film transistor (TFT1). The first gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0123] A first gate electrode (G1) and a first capacitor electrode (CAE1) of a first thin-film transistor (TFT1) may be disposed on the first gate insulating film (130). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being disposed apart from each other in FIG. 11, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other. The first gate electrode (G1) and the first capacitor electrode (CAE1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0124] A first interlayer insulating film (141) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the first thin-film transistor (TFT1). The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film (141) may be formed of a plurality of inorganic films.

[0125] A second capacitor electrode (CAE2) may be disposed on the first interlayer insulating film (141). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) of the first thin-film transistor (TFT1) in the third direction (DR3). When the first capacitor electrode (CAE1) is connected to the first gate electrode (G1), the second capacitor electrode (CAE2) may overlap with the first gate electrode (G1) in the third direction (DR3). Since the first interlayer insulating film (141) has a predetermined dielectric constant, a capacitor may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the first interlayer insulating film (141) disposed between them. The second capacitor electrode (CAE2) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0126] A second interlayer insulating film (142) may be disposed on the second capacitor electrode (CAE2). The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film (142) may be formed of a plurality of inorganic films.

[0127] A first anode connection electrode (ANDE1) may be disposed on the second interlayer insulating film (142). The first anode connection electrode (ANDE1) may be connected to a first drain region (D1) of a first thin-film transistor (TFT1) through a first connection contact hole (ANCT1) penetrating the first gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The first anode connection electrode (ANDE1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0128] A first flattening film (160) for flattening the step difference caused by the first thin-film transistor (TFT1) may be disposed on the first anode connection electrode (ANDE1). The first flattening film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0129] A second anode connecting electrode (ANDE2) may be disposed on the first flattening film (160). The second anode connecting electrode (ANDE2) may be connected to the first anode connecting electrode (ANDE1) through a second connecting contact hole (ANCT2) that penetrates the first flattening film (160). The second anode connecting electrode (ANDE2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0130] A second planarization film (180) may be disposed on the second anode connection electrode (ANDE2). The second planarization film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0131] Light-emitting elements (LELs) and a bank (190) may be disposed on the second planarization film (180). Each of the light-emitting elements (LELs) includes a pixel electrode (171), a light-emitting layer (172), and a common electrode (173).

[0132] The pixel electrode (171) can be placed on the second planarization film (180). The pixel electrode (171) can be connected to the second anode connection electrode (ANDE2) through a third connection contact hole (ANCT3) that penetrates the second planarization film (180).

[0133] In a top emission structure that emits light in the direction of a common electrode (173) based on a light-emitting layer (172), the pixel electrode (171) can be formed of a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (Indium Tin Oxide) (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0134] A bank (190) may be formed to partition a pixel electrode (171) on a second planarization film (180) to define a first light-emitting part (EA1), a second light-emitting part (EA2), a third light-emitting part (EA3), and a fourth light-emitting part (EA4). A bank (190) may be positioned to cover the edges of the pixel electrode (171). A bank (190) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0135] Each of the first light-emitting part (EA1), second light-emitting part (EA2), third light-emitting part (EA3), and fourth light-emitting part (EA4) represents a region in which a pixel electrode (171), a light-emitting layer (172), and a common electrode (173) are sequentially stacked, and light is emitted by the recombination of holes from the pixel electrode (171) and electrons from the common electrode (173) in the light-emitting layer (172).

[0136] A light-emitting layer (172) may be disposed on the pixel electrode (171) and the bank (190). The light-emitting layer (172) may include an organic material and emit a predetermined color. For example, the light-emitting layer (172) includes a hole transporting layer, an organic material layer, and an electron transporting layer.

[0137] A common electrode (173) may be disposed on the light-emitting layer (172). The common electrode (173) may be disposed to cover the light-emitting layer (172). The common electrode (173) may be a common layer formed commonly on the first light-emitting part (EA1), the second light-emitting part (EA2), the third light-emitting part (EA3), and the fourth light-emitting part (EA4). A capping layer may be formed on the common electrode (173).

[0138] In the upper light-emitting structure, the common electrode (173) can be formed from a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode (173) is formed from a semi-transmissive conductive material, the light emission efficiency can be increased by the micro cavity.

[0139] A spacer (191) may be placed on the bank (190). The spacer (191) may serve to support the mask during the manufacturing process of the light-emitting layer (172). The spacer (191) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0140] An encapsulation layer (TFEL) may be disposed on the common electrode (173). The encapsulation layer (TFEL) includes at least one inorganic film to prevent oxygen or moisture from penetrating the light-emitting element layer (EML). Additionally, the encapsulation layer (TFEL) includes at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust. For example, the encapsulation layer (TFEL) includes a first encapsulation inorganic film (TFE1), an encapsulation organic film (TFE2), and a second encapsulation inorganic film (TFE3).

[0141] A first encapsulating inorganic film (TFE1) may be disposed on a common electrode (173), an encapsulating organic film (TFE2) may be disposed on the first encapsulating inorganic film (TFE1), and a second encapsulating inorganic film (TFE3) may be disposed on the encapsulating organic film (TFE2). The first encapsulating inorganic film (TFE1) and the second encapsulating inorganic film (TFE3) may be formed as a multilayer film in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulating organic film (TFE2) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0142] A touch sensing unit (TDU) may be disposed on the encapsulation layer (TFEL). The touch sensing unit (TDU) includes a first touch insulating film (TINS1), a connecting electrode (BE), a second touch insulating film (TINS2), a driving electrode (TE), a sensing electrode (RE), and a third touch insulating film (TINS3).

[0143] The first touch insulating film (TINS1) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0144] A connecting electrode (BE) may be disposed on the first touch insulating film (TINS1). The connecting electrode (BE) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0145] A second touch insulating film (TINS2) is disposed on the connecting electrode (BE). The second touch insulating film (TINS2) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the second touch insulating film (TINS2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0146] Driving electrodes (TE) and sensing electrodes (RE) may be disposed on the second touch insulating film (TINS2). In addition to the driving electrodes (TE) and sensing electrodes (RE), dummy patterns (DE) shown in FIG. 4, first touch driving wires (TL1), second touch driving wires (TL2), and touch sensing wires (RL) may be disposed on the second touch insulating film (TINS2). The driving electrodes (TE) and sensing electrodes (RE) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0147] The driving electrode (TE) and the sensing electrode (RE) can overlap with the connecting electrode (BE) in the third direction (DR3). The driving electrode (TE) can be connected to the connecting electrode (BE) through a touch contact hole (TCNT1) that penetrates the first touch insulating film (TINS1).

[0148] A third touch insulating film (TINS3) is formed on the driving electrodes (TE) and the sensing electrodes (RE). The third touch insulating film (TINS3) can serve to flatten the step formed by the driving electrodes (TE), the sensing electrodes (RE), and the connecting electrodes (BE). The third touch insulating film (TINS3) can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0149] FIG. 12 is a layout diagram showing a non-display area of ​​a display panel according to one embodiment. FIG. 13 is a layout diagram showing area B of FIG. 12 in detail.

[0150] Referring to FIGS. 12 and 13, a low potential wiring (VSL), a high potential wiring (VDL), first power connection wiring (VSCL), second power connection wiring (VDCL), power connection holes (VDH), display power wiring (DDL), and touch wiring (SL) are illustrated.

[0151] Referring to FIGS. 12 and 13, the low potential wiring (VSL) may be placed in a non-display area (NDA) and a first area (A1). The low potential wiring (VSL) may be placed in a non-display area (NDA) located on the left, bottom, and right sides of the display panel (100). The low potential wiring (VSL) may extend in a first direction (DR1) from a non-display area (NDA) located on the bottom side of the display panel (100). The low potential wiring (VSL) may extend in a second direction (DR2) from the first area (A1). The low potential wiring (VSL) may include a first bend (CP1) that is bent from the second direction (DR2) to the first direction (DR1) from a non-display area (NDA) located on the bottom side of the display panel (100).

[0152] Additionally, the low potential wiring (VSL) may be placed in the lower side, left side, and non-display area (NDA) of the corner where the lower side and left side meet of the display panel (100). Additionally, the low potential wiring (VSL) may be placed in the lower side, right side, and non-display area (NDA) of the corner where the lower side and right side meet of the display panel (100). Additionally, the low potential wiring (VSL) may be placed in the upper side, the corner where the upper side and left side meet, and the non-display area (NDA) of the corner where the upper side and right side meet of the display panel (100).

[0153] High potential wiring (VDL) may be placed in a non-display area (NDA) and a first area (A1). High potential wiring (VDL) may be placed in a non-display area (NDA) located on the lower side of the display panel (100). High potential wiring (VDL) may extend in a first direction (DR1) from a non-display area (NDA) located on the lower side of the display panel (100). High potential wiring (VDL) may extend in a second direction (DR2) from the first area (A1). High potential wiring (VDL) may include a second bend (CP2) that is bent from the second direction (DR2) to the first direction (DR1) from a non-display area (NDA) located on the lower side of the display panel (100).

[0154] The first power connection wires (VSCL) can be placed in the bending area (BA). Each of the first power connection wires (VSCL) can be extended from the low potential wire (VSL).

[0155] The second power connection wires (VDCL) can be placed in the bending area (BA). Each of the second power connection wires (VDCL) can be connected to the high potential wire (VDL) through the power connection hole (VDH).

[0156] Display power wiring (DDL) can be placed in the display area (DA). Display power wiring (DDL) can be connected to high potential wiring (VDL) in the non-display area (NDA) located at the bottom of the display panel (100).

[0157] Display power lines (DDL) can be arranged in a mesh (or grid) shape in the display area (DA). As a result, high potential voltage can be applied more uniformly to the subpixels (SPX) of the display area (DA).

[0158] Touch wires (SL) may be placed in a non-display area (NDA) and a first area (A1). Each touch wire (SL) may extend in a first direction (DR1) from a non-display area (NDA) placed on the lower side of the display panel (100). Each touch wire (SL) may extend in a second direction (DR2) from the first area (A1). Each touch wire (SL) may include a third bend (CP3) that is bent from the second direction (DR2) to the first direction (DR1) from a non-display area (NDA) placed on the lower side of the display panel (100). Each touch wire (SL) may overlap with at least one of a low potential wire (VDL) and a high potential wire (VSL) in a non-display area (NDA) placed on the lower side of the display panel (100).

[0159] FIG. 14 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 13.

[0160] Referring to FIG. 14, a fan-out wiring area (FLA) may be placed between a display area (DA) and a dam area (DMA). Data fan-out wiring (DFL) and scan fan-out wiring (SFL) may be placed in the fan-out wiring area (FLA).

[0161] Data fan-out lines (DFLs) may include first data fan-out lines (DFL1) disposed on a first gate insulating film (130) and second data fan-out lines (DFL2) disposed on a first interlayer insulating film (141). Additionally, scan fan-out lines (SFLs) may include first scan fan-out lines (SFL1) disposed on a first gate insulating film (130) and second scan fan-out lines (SFL2) disposed on a first interlayer insulating film (141).

[0162] The first data fan-out lines (DFL1) and the first scan fan-out lines (SFL1) are placed on the same layer as the first gate electrode (G1) and the first capacitor electrode (CAE1) and may contain the same material. Additionally, the second data fan-out lines (DFL2) and the second scan fan-out lines (SFL2) are placed on the same layer as the second capacitor electrode (CAE2) and may contain the same material.

[0163] The first data fan-out lines (DFL1) and the second data fan-out lines (DFL2) can be arranged alternately in the second direction (DR2). That is, the first data fan-out lines (DFL1) and the second data fan-out lines (DFL2) can be arranged in the order of the first data fan-out line (DFL1), the second data fan-out line (DFL2), the first data fan-out line (DFL1), and the second data fan-out line (DFL2) in the second direction (DR2).

[0164] The first scan fan-out wires (SFL1) and the second scan fan-out wires (SFL2) can be arranged alternately in the second direction (DR2). That is, the first scan fan-out wires (SFL1) and the second scan fan-out wires (SFL2) can be arranged in the order of the first scan fan-out wire (SFL1), the second scan fan-out wire (SFL2), the first scan fan-out wire (SFL1), and the second scan fan-out wire (SFL2) in the second direction (DR2).

[0165] The dam area (DMA) may be an area where at least one dam (DAM1, DAM2, DAM3) is placed. Although FIG. 14 describes the dam area (DMA) with the placement of the first dam (DAM1), the second dam (DAM2), and the third dam (DAM3), the number of dams placed in the dam area (DMA) is not limited to this.

[0166] The first dam (DAM1), the second dam (DAM2), and the third dam (DAM3) may be placed apart from each other. The first dam (DAM1) may be placed closest to the display area (DA), and the third dam (DAM3) may be placed furthest from the display area (DA). The second dam (DAM2) may be placed between the first dam (DAM1) and the third dam (DAM3).

[0167] Each of the first dam (DAM1) and the second dam (DAM2) may include a first sub-dam (SDAM1 / SDAM1') and a second sub-dam (SDAM2 / SDAM2') disposed on the first sub-dam (SDAM1 / SDAM1'). The first sub-dam (SDAM1 / SDAM1') may include the same material as the bank (190). The thickness of the first sub-dam (SDAM1 / SDAM1') and the thickness of the bank (190) may be substantially the same. The second sub-dam (SDAM2 / SDAM2') may include the same material as the spacer (191). The thickness of the second sub-dam (SDAM2 / SDAM2') and the thickness of the spacer (191) may be substantially the same.

[0168] The third dam (DAM3) may include a first sub-dam (SDAM1), a second sub-dam (SDAM2) disposed on the first sub-dam (SDAM1), and a third sub-dam (SDAM3) disposed on the second sub-dam (SDAM2). The thickness of the third dam (DAM3) may be greater than the thickness of the first dam (DAM1) and the thickness of the second dam (DAM2).

[0169] The first sub-dam (SDAM1) may contain the same material as the second flattening film (180). The second sub-dam (SDAM2) may contain the same material as the bank (190). The thickness of the second sub-dam (SDAM2) and the thickness of the bank (190) may be substantially the same. The third sub-dam (SDAM3) may contain the same material as the spacer (191). The thickness of the third sub-dam (SDAM3) and the thickness of the spacer (191) may be substantially the same.

[0170] The inorganic encapsulation region (CVDA) can be placed between the dam region (DMA) and the mask support region (MSA). The inorganic encapsulation region (CVDA) may be a region where only an inorganic film is placed and no organic film is placed. That is, as shown in FIG. 14, a barrier film (BR), a first gate insulating film (130), a first interlayer insulating film (141), a second interlayer insulating film (142), a second low-potential wiring (VSL2), a first encapsulated inorganic film (TFE1), and a second encapsulated inorganic film (TFE3) may be placed in the inorganic encapsulation region (CVDA). The inorganic encapsulation region (CVDA) can prevent oxygen or moisture from penetrating into the light-emitting elements (LEL).

[0171] The mask support area (MSA) may be positioned far from the marking area (DA) compared to the dam area (DMA) and the weapon encapsulation area (CVDA). The mask support area (MSA) may include a mask support structure (MSS). The mask support structure (MSS) may include a first structure (MSS1), a second structure (MSS2) positioned on the first structure (MSS1), a third structure (MSS3) positioned on the second structure (MSS2), and a fourth structure (MSS4) positioned on the third structure (MSS3). The thickness of the mask support structure (MSS) may be greater than the thickness of the third dam (DAM3).

[0172] The first structure (MSS1) may include the same material as the first flattening film (160). The thickness of the first structure (MSS1) may be substantially the same as the thickness of the first flattening film (160). The second structure (MSS2) may include the same material as the second flattening film (180). The thickness of the second structure (MSS2) may be substantially the same as the thickness of the second flattening film (180). The third structure (MSS3) may include the same material as the bank (190). The thickness of the third structure (MSS3) and the thickness of the bank (190) may be substantially the same. The fourth structure (MSS4) may include the same material as the spacer (191). The thickness of the fourth structure (MSS4) and the thickness of the spacer (191) may be substantially the same.

[0173] The low potential wiring (VSL) may include a first low potential wiring (VSL1) and a second low potential wiring (VSL2). The first low potential wiring (VSL1) is placed in the dam area (DMA), and the second low potential wiring (VSL2) may be placed in the fan-out wiring area (FLA), the dam area (DMA), the inorganic encapsulation area (CVDA), and the mask support area (MSA).

[0174] The first low potential wiring (VSL1) may be placed on the second interlayer insulating film (142) in the dam area (DMA). The first low potential wiring (VSL1) may contain the same material as the first anode connecting electrode (ANDE1).

[0175] The second low potential wiring (VSL2) may be placed on the first planarization film (160) in the fan-out wiring region (FLA). The second low potential wiring (VSL2) may be placed on the first low potential wiring (VSL1) and the first sub-dam (SDAM1) of the third dam (DAM3) in the dam region (DMA). The second low potential wiring (VSL2) may be in contact with the first low potential wiring (VSL1) in the dam region (DMA). The second low potential wiring (VSL2) may be placed on the second interlayer insulating film (142) in the inorganic encapsulation region (CVDA). The second low potential wiring (VSL2) may be placed on the first structure (MSS1) in the mask support region (MSA). The second low potential wiring (VSL2) may comprise the same material as the second anode connection electrode (ANDE2).

[0176] The high potential wiring (VDL) may include a first high potential wiring (VDL1) and a second high potential wiring (VDL2). The first high potential wiring (VDL1) and the second high potential wiring (VDL2) may be placed in a fan-out wiring area (FLA).

[0177] The first high potential wiring (VDL1) may be placed on the second interlayer insulating film (142) in the fan-out wiring area (FLA). The first high potential wiring (VDL1) may include the same material as the first low potential wiring (VSL1) and the first anode connecting electrode (ANDE1).

[0178] The second high potential wiring (VDL2) may be placed on the first planarization film (160) in the fan-out wiring region (FLA). The second high potential wiring (VDL2) may include the same material as the second low potential wiring (VSL2) and the second anode connection electrode (ANDE2).

[0179] The first encapsulating inorganic membrane (TFE1) and the second encapsulating inorganic membrane (TFE3) may be placed in the fan-out wiring area (FLA), dam area (DMA), inorganic encapsulating area (CVDA), and mask support area (MSA). The encapsulating organic membrane (TFE2) may be placed in the fan-out wiring area (FLA) and the dam area (DMA).

[0180] The first encapsulating inorganic membrane (TFE1) may be placed on the second flattening membrane (180) in the fan-out wiring area (FLA). The first encapsulating inorganic membrane (TFE1) may be placed on the first dam (DAM1), the second dam (DAM2), and the third dam (DAM3) in the dam area (DMA). Additionally, the first encapsulating inorganic membrane (TFE1) may be placed on the second low-potential wiring (VSL2) between the first dam (DAM1) and the second dam (DAM2) in the dam area (DMA), and between the second dam (DAM2) and the third dam (DAM3). The first encapsulating inorganic membrane (TFE1) may be placed on the second low-potential wiring (VSL2) in the inorganic encapsulating area (CVDA). The first encapsulating inorganic membrane (TFE1) may be placed on the mask support structure (MSS) in the mask support area (MSA).

[0181] The encapsulating organic film (TFE2) may be placed on the first encapsulating inorganic film (TFE1) in the fan-out wiring area (FLA) and the dam area (DMA). FIG. 14 illustrates the encapsulating organic film (TFE2) being placed in the dam area (DMA) to cover a portion of the first dam (DAM1) and the second dam (DAM2) but not the third dam (DAM3), but embodiments of this specification are not limited thereto. For example, the encapsulating organic film (TFE2) may be placed to cover a portion of the first dam (DAM1), the second dam (DAM2), and the third dam (DAM3). Alternatively, the encapsulating organic film (TFE2) may be placed to cover a portion of the first dam (DAM1) but not the second dam (DAM2) and the third dam (DAM3).

[0182] The second encapsulating inorganic membrane (TFE3) may be placed on the encapsulating organic membrane (TFE2) in the fan-out wiring region (FLA). The second encapsulating inorganic membrane (TFE3) may be placed on the first encapsulating inorganic membrane (TFE1) and the encapsulating organic membrane (TFE3) in the dam region (DMA). The second encapsulating inorganic membrane (TFE3) may be placed on the first encapsulating inorganic membrane (TFE1) in the inorganic encapsulating region (CVDA). The second encapsulating inorganic membrane (TFE3) may be placed on the first encapsulating inorganic membrane (TFE1) in the mask support region (MSA).

[0183] Touch wiring (SL) can be placed on the second encapsulating inorganic film (TFE3) in the fan-out wiring area (FLA) and the dam area (DMA).

[0184] Meanwhile, referring to FIGS. 12 to 14, the low potential wiring (VSL) and the high potential wiring (VDL) may be spaced apart from each other in the non-display area (NDA) located on the lower side of the display panel (100). That is, the low potential wiring (VSL) and the high potential wiring (VDL) extending in the first direction (DR1) from the non-display area (NDA) located on the lower side of the display panel (100) may not overlap each other.

[0185] At least one of the touch wires (SL) may be positioned between the low potential wire (VSL) and the high potential wire (VDL) extending in the first direction (DR1) from the non-display area (NDA) located at the bottom of the display panel (100). As a result, the touch wire (SL) and at least one of the data fan-out wires (DFL) may overlap. Therefore, a parasitic capacitance may be formed between the touch wire (SL) and the data fan-out wire (DFL). Due to the parasitic capacitance, the touch driving signal or touch detection signal of the touch wire (SL) may be affected by the data voltage of the data fan-out wire (DFL).

[0186] Alternatively, at least one of the touch wiring (SL) and the scan fan-out wiring (SFL) may overlap. Therefore, a parasitic capacitance may be formed between the touch wiring (SL) and the scan fan-out wiring (SFL). Due to the parasitic capacitance, the touch driving signal or touch detection signal of the touch wiring (SL) may be affected by the scan control signal of the scan fan-out wiring (SFL).

[0187] Therefore, if the touch driving signal or touch detection signal of the touch wiring (SL) is affected by the data voltage of the data fan-out wiring (DFL) or by the scan control signal of the scan fan-out wiring (SFL), a touch detection error may occur. For example, touch detection errors may include errors where a touch occurs but is not recognized, and errors where a touch is recognized even though no touch occurs.

[0188] FIG. 15 is a layout diagram showing a non-display area of ​​a display panel according to another embodiment. FIG. 16 is a layout diagram showing in detail another example of area C of FIG. 15. FIG. 17 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 16. FIG. 18 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16.

[0189] The embodiments of FIGS. 15 to 18 differ from the embodiments of FIGS. 12 to 14 in that the low potential wiring (VSL) overlaps with the high potential wiring (VDL), so that the low potential wiring (VSL) or the high potential wiring (VDL) is positioned between the touch wiring (SL) and the data fan-out wiring (DFL) or the scan fan-out wiring (SFL). In FIGS. 15 to 18, descriptions that overlap with FIGS. 12 to 14 are omitted.

[0190] Referring to FIGS. 15 to 18, the low potential wiring (VSL) and the high potential wiring (VDL) can overlap each other in the non-display area (NDA) located on the lower side of the display panel (100). That is, the low potential wiring (VSL) and the high potential wiring (VDL) extending in the first direction (DR1) in the non-display area (NDA) located on the lower side of the display panel (100) can overlap each other. For example, in the fan-out wiring area (FLA), the second low potential wiring (VSL2) and the first high potential wiring (VDL1) can overlap each other as shown in FIG. 17. Alternatively, in the fan-out wiring area (FLA), the first low potential wiring (VSL1) and the second high potential wiring (VDL2) can overlap each other as shown in FIG. 18.

[0191] In the non-display area (NDA) located on the lower side of the display panel (100), the low potential wiring (VSL) and the high potential wiring (VDL) overlap each other, so the low potential wiring (VSL) or the high potential wiring (VDL) can be placed between the touch wiring (SL) and the data fan-out wiring (DFL) or the scan fan-out wiring (SFL). Therefore, it is possible to prevent parasitic capacitance from forming between the touch wiring (SL) and the data fan-out wiring (DFL) and between the touch wiring (SL) and the scan fan-out wiring (SFL). Accordingly, it is possible to prevent the touch driving signal or touch detection signal of the touch wiring (SL) from being affected by the data voltage of the data fan-out wiring (DFL) or by the scan control signal of the scan fan-out wiring (SFL), thereby preventing touch detection errors from occurring.

[0192] FIG. 19 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 20 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 21 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16.

[0193] The embodiments of FIGS. 19 to 21 differ from the embodiments of FIGS. 11, 17, and 18 in that the display panel (100) further includes a third planarization film (181) and a third anode connection electrode (ANDE3). In FIGS. 19 to 21, descriptions that overlap with the embodiments of FIGS. 11, 17, and 18 are omitted.

[0194] Referring to FIGS. 19 to 21, a third anode connecting electrode (ANDE3) may be disposed on a second planarization film (180). The third anode connecting electrode (ANDE3) may be connected to a second anode connecting electrode (ANDE2) through a third connecting contact hole (ANCT3) that penetrates the second planarization film (180). The third anode connecting electrode (ANDE3) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0195] A third planarization film (181) may be disposed on the third anode connection electrode (ANDE3). The third planarization film (181) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0196] The light-emitting elements (LELs) and the bank (190) can be placed on the third planarization film (181). The pixel electrode (171) of each light-emitting element (LEL) can be placed on the third planarization film (181). The pixel electrode (171) can be connected to the third anode connection electrode (ANDE3) through a fourth connection contact hole (ANCT4) that penetrates the third planarization film (181).

[0197] The mask support structure (MSS) may include a first structure (MSS1), a second structure (MSS2) disposed on the first structure (MSS1), a third structure (MSS3) disposed on the second structure (MSS2), and a fourth structure (MSS4) disposed on the third structure (MSS3). The first structure (MSS1) may include the same material as the first flattening film (160). The thickness of the first structure (MSS1) may be substantially the same as the thickness of the first flattening film (160). The second structure (MSS2) may include the same material as the second flattening film (180). The thickness of the second structure (MSS2) may be substantially the same as the thickness of the second flattening film (180). The third structure (MSS3) may include the same material as the third flattening film (181). The thickness of the third structure (MSS3) may be substantially the same as the thickness of the third flattening film (181). The fourth structure (MSS4) may contain the same material as the bank (190). The thickness of the fourth structure (MSS4) and the thickness of the bank (190) may be substantially the same. The fifth structure (MSS5) may contain the same material as the spacer (191). The thickness of the fifth structure (MSS5) and the thickness of the spacer (191) may be substantially the same.

[0198] The low potential wiring (VSL) may include a first low potential wiring (VSL1), a second low potential wiring (VSL2), and a third low potential wiring (VSL3). The first low potential wiring (VSL1) and the second low potential wiring (VSL2) are placed in the dam area (DMA), and the third low potential wiring (VSL3) may be placed in the fan-out wiring area (FLA), the dam area (DMA), the inorganic encapsulation area (CVDA), and the mask support area (MSA).

[0199] The first low potential wiring (VSL1) may be placed on the second interlayer insulating film (142) in the dam area (DMA). The first low potential wiring (VSL1) may contain the same material as the first anode connecting electrode (ANDE1).

[0200] The second low-potential wiring (VSL2) may be placed on the first low-potential wiring (VSL1) in the dam area (DMA). The second low-potential wiring (VSL2) may be placed to cover the first low-potential wiring (VSL1). That is, the second low-potential wiring (VSL2) may be placed on the top surface and sides of the first low-potential wiring (VSL1). The second low-potential wiring (VSL2) may contain the same material as the second anode connection electrode (ANDE2).

[0201] The third low potential wiring (VSL3) may be placed on the second planarization film (180) in the fan-out wiring region (FLA). The third low potential wiring (VSL3) may be placed on the first sub-dam (SDAM1) of the second low potential wiring (VSL2) and the third dam (DAM3) in the dam region (DMA). The third low potential wiring (VSL3) may be in contact with the upper and side surfaces of the second low potential wiring (VSL2) in the dam region (DMA). The third low potential wiring (VSL3) may be placed on the second interlayer insulating film (142) in the inorganic encapsulation region (CVDA). The third low potential wiring (VSL3) may be placed on the second structure (MSS2) in the mask support region (MSA). The third low potential wiring (VSL3) may comprise the same material as the third anode connection electrode (ANDE3).

[0202] The high potential wiring (VDL) may include a first high potential wiring (VDL1) and a second high potential wiring (VDL2). The first high potential wiring (VDL1) and the second high potential wiring (VDL2) may be placed in a fan-out wiring area (FLA).

[0203] The first high potential wiring (VDL1) may be placed on the second interlayer insulating film (142) in the fan-out wiring area (FLA). The first high potential wiring (VDL1) may include the same material as the first low potential wiring (VSL1) and the first anode connecting electrode (ANDE1).

[0204] The second high potential wiring (VDL2) is placed on the first flattening film (160) in the fan-out wiring region (FLA), in which case it may contain the same material as the second low potential wiring (VSL2) and the second anode connecting electrode (ANDE2). Alternatively, the second high potential wiring (VDL2) is placed on the second flattening film (180) in the fan-out wiring region (FLA), in which case it may contain the same material as the third low potential wiring (VSL3) and the third anode connecting electrode (ANDE3).

[0205] In the fan-out wiring area (FLA), the third low-potential wiring (VSL3) and the first high-potential wiring (VDL1) can overlap each other as shown in FIG. 20. As shown in FIG. 20, the first flattening film (160) and the second flattening film (180) are arranged between the third low-potential wiring (VSL3) and the first high-potential wiring (VDL1) in the third direction (DR3), whereas as shown in FIG. 17, the first flattening film (160) can be arranged between the second low-potential wiring (VSL2) and the first high-potential wiring (VDL1) in the third direction (DR3). As shown in FIG. 17, when only the first flattening film (160) is placed between the second low potential wiring (VSL2) and the first high potential wiring (VDL1) in the third direction (DR3), since the distance between the first high potential wiring (VDL1) and the second low potential wiring (VSL2) is short, a burnt defect may occur depending on the potential difference between the high potential voltage of the first high potential wiring (VDL1) and the low potential voltage of the second low potential wiring (VSL2). However, as shown in FIG. 20, when the distance between the third low potential wire (VSL3) and the first high potential wire (VDL1) in the third direction (DR3) is greater than the distance between the second low potential wire (VSL2) and the first high potential wire (VDL1) in the third direction (DR3) as shown in FIG. 17, the occurrence of burnt failures due to the potential difference between the high potential voltage of the first high potential wire (VDL1) and the low potential voltage of the third low potential wire (VSL3) can be reduced.

[0206] Alternatively, in the fan-out wiring area (FLA), the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) may overlap each other as shown in FIG. 21. As shown in FIG. 21, the first flattening film (160) and the second flattening film (180) are arranged between the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) in the third direction (DR3), whereas as shown in FIG. 18, the first flattening film (160) may be arranged between the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) in the third direction (DR3). As shown in FIG. 18, when only the first flattening film (160) is placed between the first low potential wiring (VSL1) and the second high potential wiring (VDL2) in the third direction (DR3), since the distance between the first low potential wiring (VSL1) and the second high potential wiring (VDL2) is short, a burnt defect may occur depending on the potential difference between the high potential voltage of the second high potential wiring (VDL2) and the low potential voltage of the first low potential wiring (VSL1). However, as shown in FIG. 21, when the distance between the first low potential wire (VSL1) and the second high potential wire (VDL2) in the third direction (DR3) is greater than the distance between the first low potential wire (VSL1) and the second high potential wire (VDL2) in the third direction (DR3) as shown in FIG. 18, the occurrence of burnt failures due to the potential difference between the high potential voltage of the first high potential wire (VDL1) and the low potential voltage of the second low potential wire (VSL2) can be reduced.

[0207] In the non-display area (NDA) located on the lower side of the display panel (100), the low potential wiring (VSL) and the high potential wiring (VDL) overlap each other, so the low potential wiring (VSL) or the high potential wiring (VDL) can be placed between the touch wiring (SL) and the data fan-out wiring (DFL) or the scan fan-out wiring (SFL). Therefore, it is possible to prevent parasitic capacitance from forming between the touch wiring (SL) and the data fan-out wiring (DFL) and between the touch wiring (SL) and the scan fan-out wiring (SFL). Accordingly, it is possible to prevent the touch driving signal or touch detection signal of the touch wiring (SL) from being affected by the data voltage of the data fan-out wiring (DFL) or by the scan control signal of the scan fan-out wiring (SFL), thereby preventing touch detection errors from occurring.

[0208] FIG. 22 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 23 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 24 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16.

[0209] The embodiments of FIGS. 22 to 24 differ from the embodiments of FIGS. 11, 17, and 18 in that the display panel (100) further comprises a second thin-film transistor (TFT2) having a second active layer (ACT2) and a second gate electrode (G2), a second gate insulating film (131), a third interlayer insulating film (150), a first connecting electrode (BE1), a second connecting electrode (BE2), a third data fan-out wiring (DFL3), and a third scan fan-out wiring (SFL3). In FIGS. 19 to 21, descriptions that overlap with the embodiments of FIGS. 11, 17, and 18 are omitted.

[0210] Referring to FIGS. 22 to 24, a second thin-film transistor (TFT2) may be disposed on the second interlayer insulating film (142). The second thin-film transistor (TFT2) may be any one of the first transistor (ST1) and the third transistor (ST3) shown in FIGS. 6 to 8, and the fourth transistor (ST4) shown in FIG. 8. The second thin-film transistor (TFT2) may include a second active layer (ACT2) and a second gate electrode (G2).

[0211] A second active layer (ACT2) of a second thin-film transistor (TFT2) may be disposed on the second interlayer insulating film (142). The second active layer (ACT2) may include an oxide semiconductor. For example, the second active layer (ACT2) may include IGZO (Indium (In), Gallium (Ga), Zinc (Zn) and Oxygen (O)), IGZTO (Indium (In), Gallium (Ga), Zinc (Zn), Tin (Sn) and Oxygen (O)), or IGTO (Indium (In), Gallium (Ga), Tin (Sn) and Oxygen (O)).

[0212] The second active layer (ACT2) may include a second channel region (CHA2), a second source region (S2), and a second drain region (D2). The second channel region (CHA2) may be a region that overlaps with the second gate electrode (G2) in the third direction (DR3). The second source region (S2) may be disposed on one side of the second channel region (CHA2), and the second drain region (D2) may be disposed on the other side of the second channel region (CHA2). The second source region (S2) and the second drain region (D2) may be regions that do not overlap with the second gate electrode (G2) in the third direction (DR3). The second source region (S2) and the second drain region (D2) may be regions that have conductivity by doping ions or impurities into an oxide semiconductor.

[0213] A second gate insulating film (131) may be disposed on the second active layer (ACT2) of the second thin-film transistor (TFT2). The second gate insulating film (131) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0214] A second gate electrode (G2) of a second thin-film transistor (TFT2) may be disposed on the second gate insulating film (132). The second gate electrode (G2) may overlap with the second active layer (ACT2) in the third direction (DR3). The second gate electrode (G2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0215] A third interlayer insulating film (150) may be disposed on the second gate electrode (G2) of the second thin-film transistor (TFT2). The third interlayer insulating film (150) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The third interlayer insulating film (150) may be formed of a plurality of inorganic films.

[0216] A first anode connection electrode (ANDE1), a first connection electrode (BE1), and a second connection electrode (BE2) may be disposed on the third interlayer insulating film (150). The first anode connection electrode (ANDE1) may be connected to a first drain region (D) of the first active layer (ACT1) through a first anode contact hole (ANCT1) penetrating the first interlayer insulating film (141), the second interlayer insulating film (142), the second gate insulating film (131), and the third interlayer insulating film (150). The first connection electrode (BE1) may be connected to a second source region (S2) of the second active layer (ACT2) through a first connection contact hole (BCT1) penetrating the third interlayer insulating film (150). The second connecting electrode (BE2) can be connected to the second drain region (D2) of the second active layer (ACT2) through a second connecting contact hole (BCT2) penetrating the third interlayer insulating film (150). The first anode connecting electrode (ANDE1), the first connecting electrode (BE1), and the second connecting electrode (BE2) can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0217] Data fan-out lines (DFLs) may include first data fan-out lines (DFL1) disposed on a first gate insulating film (130), second data fan-out lines (DFL2) disposed on a first interlayer insulating film (141), and third data fan-out lines (DFL3) disposed on a second gate insulating film (131). Additionally, scan fan-out lines (SFLs) may include first scan fan-out lines (SFL1) disposed on a first gate insulating film (130), second scan fan-out lines (SFL2) disposed on a first interlayer insulating film (141), and third scan fan-out lines (SFL3) disposed on a second gate insulating film (131).

[0218] The first data fan-out lines (DFL1) and the first scan fan-out lines (SFL1) are placed on the same layer as the first gate electrode (G1) and the first capacitor electrode (CAE1) and may contain the same material. Additionally, the second data fan-out lines (DFL2) and the second scan fan-out lines (SFL2) are placed on the same layer as the second capacitor electrode (CAE2) and may contain the same material. Additionally, the third data fan-out lines (DFL3) and the third scan fan-out lines (SFL3) are placed on the same layer as the second gate electrode (G2) and may contain the same material.

[0219] The first data fan-out lines (DFL1), the second data fan-out lines (DFL2), and the third data fan-out lines (DFL3) can be arranged alternately in the second direction (DR2). That is, the first data fan-out lines (DFL1), the second data fan-out lines (DFL2), and the third data fan-out lines (DFL3) can be arranged in the order of the first data fan-out line (DFL1), the second data fan-out line (DFL2), the third data fan-out line (DFL3), the first data fan-out line (DFL1), the second data fan-out line (DFL2), and the third data fan-out line (DFL3) in the second direction (DR2).

[0220] The first scan fan-out wires (SFL1), the second scan fan-out wires (SFL2), and the third scan fan-out wires (SFL3) can be arranged alternately in the second direction (DR2). That is, the first scan fan-out wires (SFL1), the second scan fan-out wires (SFL2), and the third scan fan-out wires (SFL3) can be arranged in the order of the first scan fan-out wire (SFL1), the second scan fan-out wire (SFL2), the third scan fan-out wire (SFL3), the first scan fan-out wire (SFL1), the second scan fan-out wire (SFL2), and the third scan fan-out wire (SFL3) in the second direction (DR2).

[0221] In the fan-out wiring area (FLA), the second low-potential wiring (VSL2) and the first high-potential wiring (VDL1) can overlap each other as shown in FIG. 23. Alternatively, in the fan-out wiring area (FLA), the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) can overlap each other as shown in FIG. 24.

[0222] In the non-display area (NDA) located on the lower side of the display panel (100), the low potential wiring (VSL) and the high potential wiring (VDL) overlap each other, so the low potential wiring (VSL) or the high potential wiring (VDL) can be placed between the touch wiring (SL) and the data fan-out wiring (DFL) or the scan fan-out wiring (SFL). Therefore, it is possible to prevent parasitic capacitance from forming between the touch wiring (SL) and the data fan-out wiring (DFL) and between the touch wiring (SL) and the scan fan-out wiring (SFL). Accordingly, it is possible to prevent the touch driving signal or touch detection signal of the touch wiring (SL) from being affected by the data voltage of the data fan-out wiring (DFL) or by the scan control signal of the scan fan-out wiring (SFL), thereby preventing touch detection errors from occurring.

[0223] FIG. 25 is a cross-sectional view showing another example of a display panel cut along B-B' of FIG. 10. FIG. 26 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16. FIG. 27 is a cross-sectional view showing another example of a display panel cut along D-D' of FIG. 16.

[0224] The embodiments of FIGS. 25 to 27 differ from the embodiments of FIGS. 19 to 21 in that the display panel (100) further includes a second thin-film transistor (TFT2) having a second active layer (ACT2) and a second gate electrode (G2), a second gate insulating film (131), a third interlayer insulating film (150), a first connecting electrode (BE1), a second connecting electrode (BE2), a third data fan-out wiring (DFL3), and a third scan fan-out wiring (SFL3). In FIGS. 25 to 27, the second thin-film transistor (TFT2) having a second active layer (ACT2) and a second gate electrode (G2), the second gate insulating film (131), the third interlayer insulating film (150), the first connecting electrode (BE1), the second connecting electrode (BE2), the third data fan-out wiring (DFL3), and the third scan fan-out wiring (SFL3) may be substantially the same as described in conjunction with FIGS. 22 to 24.

[0225] In the fan-out wiring area (FLA), the third low-potential wiring (VSL3) and the first high-potential wiring (VDL1) can overlap each other as shown in FIG. 26. As shown in FIG. 26, the first flattening film (160) and the second flattening film (180) are arranged between the third low-potential wiring (VSL3) and the first high-potential wiring (VDL1) in the third direction (DR3), whereas as shown in FIG. 17, the first flattening film (160) can be arranged between the second low-potential wiring (VSL2) and the first high-potential wiring (VDL1) in the third direction (DR3). As shown in FIG. 26, when the distance between the third low potential wire (VSL3) and the first high potential wire (VDL1) in the third direction (DR3) is greater than the distance between the second low potential wire (VSL2) and the first high potential wire (VDL1) in the third direction (DR3) as shown in FIG. 17, the occurrence of burnt failures due to the potential difference between the high potential voltage of the first high potential wire (VDL1) and the low potential voltage of the third low potential wire (VSL3) can be reduced.

[0226] Alternatively, in the fan-out wiring area (FLA), the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) may overlap each other as shown in FIG. 27. As shown in FIG. 27, the first flattening film (160) and the second flattening film (180) are arranged between the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) in the third direction (DR3), whereas as shown in FIG. 18, the first flattening film (160) may be arranged between the first low-potential wiring (VSL1) and the second high-potential wiring (VDL2) in the third direction (DR3). As shown in FIG. 27, when the distance between the first low potential wire (VSL1) and the second high potential wire (VDL2) in the third direction (DR3) is greater than the distance between the first low potential wire (VSL1) and the second high potential wire (VDL2) in the third direction (DR3) as shown in FIG. 18, the occurrence of burnt failures due to the potential difference between the high potential voltage of the first high potential wire (VDL1) and the low potential voltage of the second low potential wire (VSL2) can be reduced.

[0227] In the non-display area (NDA) located on the lower side of the display panel (100), the low potential wiring (VSL) and the high potential wiring (VDL) overlap each other, so the low potential wiring (VSL) or the high potential wiring (VDL) can be placed between the touch wiring (SL) and the data fan-out wiring (DFL) or the scan fan-out wiring (SFL). Therefore, it is possible to prevent parasitic capacitance from forming between the touch wiring (SL) and the data fan-out wiring (DFL) and between the touch wiring (SL) and the scan fan-out wiring (SFL). Accordingly, it is possible to prevent the touch driving signal or touch detection signal of the touch wiring (SL) from being affected by the data voltage of the data fan-out wiring (DFL) or by the scan control signal of the scan fan-out wiring (SFL), thereby preventing touch detection errors from occurring.

[0228] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0229] 10: Display device 100: Display panel 200: Display driving circuit 300: Circuit board

Claims

Claim 1 A display device comprising: a substrate including a display area and a non-display area; touch electrodes disposed in the display area; touch wiring disposed in the non-display area and connected to the touch electrodes; low potential wiring disposed in the non-display area and including a first low potential wiring to which a low potential voltage is applied and a second low potential wiring disposed on the first low potential wiring; high potential wiring disposed in the non-display area and to which a high potential voltage higher than the low potential voltage is applied; a dam disposed on the first low potential wiring and the second low potential wiring; a mask support structure; and an inorganic encapsulation area between the dam and the mask support structure; wherein any one of the touch wirings overlaps with at least one of the low potential wiring and the high potential wiring, the low potential wiring overlaps with the high potential wiring, and the second low potential wiring overlaps with the inorganic encapsulation area and the mask support structure. Claim 2 In claim 1, the touch wiring is a display device that overlaps with the low potential wiring and the high potential wiring. Claim 3 In claim 1, the touch wiring is a display device that overlaps with the low-potential wiring. Claim 4 A display device according to claim 1, further comprising: data wiring disposed in the display area; and data fan-out wiring disposed in the non-display area and connected to the data wiring, wherein any one of the data fan-out wirings overlaps with at least one of the low-potential wiring and the high-potential wiring. Claim 5 In claim 4, the data fan-out wiring is a display device that overlaps with the touch wiring. Claim 6 A display device according to claim 1, further comprising: scan lines disposed in the display area; a scan driving unit disposed in the non-display area and applying scan signals to the scan lines; and scan fan-out lines disposed in the non-display area and connected to the scan driving unit, wherein any one of the scan fan-out lines overlaps with at least one of the low potential line and the high potential line. Claim 7 In claim 6, the scan fan-out wiring is a display device that overlaps with the touch wiring. Claim 8 A display device according to claim 1, wherein the high potential wiring comprises a first high potential wiring disposed on the substrate and a second high potential wiring disposed on the first high potential wiring. Claim 9 In claim 8, the second low-potential wiring is a display device that overlaps with the first high-potential wiring. Claim 10 In claim 8, the first low-potential wiring is a display device that overlaps with the second high-potential wiring. Claim 11 A display device according to claim 8, wherein the first low-potential wiring and the first high-potential wiring comprise the same material, and the second low-potential wiring and the second high-potential wiring comprise the same material. Claim 12 In claim 8, the display device further comprises a third low-potential wiring disposed on the second low-potential wiring. Claim 13 In claim 12, the third low-potential wiring is a display device that overlaps with the first high-potential wiring. Claim 14 In claim 12, the first low-potential wiring is a display device that overlaps with the second high-potential wiring. Claim 15 A display device according to claim 14, wherein the first low-potential wiring and the first high-potential wiring comprise the same material, and the third low-potential wiring and the second high-potential wiring comprise the same material. Claim 16 Substrate; a first active layer disposed on the substrate and including a channel region; a first gate insulating film disposed on the first active layer; a first gate electrode disposed on the first gate insulating film and overlapping with the channel region of the first active layer; a first interlayer insulating film disposed on the first gate electrode; a capacitor electrode disposed on the first interlayer insulating film and overlapping with the first gate electrode; a second interlayer insulating film disposed on the capacitor electrode; a first low-potential wiring and a first high-potential wiring disposed on the second interlayer insulating film; a second low-potential wiring disposed on the first low-potential wiring; a second high-potential wiring disposed on the first high-potential wiring; a dam disposed on the first low-potential wiring and the second low-potential wiring; a mask support structure; A display device comprising: an inorganic bag region between the dam and the mask support structure; wherein at least one of the first low-potential wiring and the second low-potential wiring overlaps with at least one of the first high-potential wiring and the second high-potential wiring, and the second low-potential wiring overlaps with the inorganic bag region and the mask support structure. Claim 17 A display device according to claim 16, further comprising: a first flattening film disposed between the first high-potential wiring and the second high-potential wiring; and a second flattening film disposed on the second high-potential wiring. Claim 18 Substrate; a first active layer disposed on the substrate and including a channel region; a first gate insulating film disposed on the first active layer; a first gate electrode disposed on the first gate insulating film and overlapping with the channel region of the first active layer; a first interlayer insulating film disposed on the first gate electrode; a capacitor electrode disposed on the first interlayer insulating film and overlapping with the first gate electrode; a second interlayer insulating film disposed on the capacitor electrode; a first low-potential wiring and a first high-potential wiring disposed on the second interlayer insulating film; a second low-potential wiring disposed on the first low-potential wiring; a second high-potential wiring disposed on the first high-potential wiring; a third low-potential wiring disposed on the second low-potential wiring; a dam disposed on the first low-potential wiring, the second low-potential wiring, and the third low-potential wiring; a mask support structure; A display device comprising: an inorganic bag region between the dam and the mask support structure; wherein at least one of the first low-potential wiring and the third low-potential wiring overlaps with at least one of the first high-potential wiring and the second high-potential wiring, and the third low-potential wiring overlaps with the inorganic bag region and the mask support structure. Claim 19 A display device according to claim 18, further comprising: a first flattening film disposed between the first high-potential wiring and the second high-potential wiring; a second flattening film disposed on the second high-potential wiring; and a third flattening film disposed on the third low-potential wiring. Claim 20 In claim 19, a sealing layer disposed on the third flattening film and comprising a first sealing inorganic film, a sealing organic film, and a second sealing inorganic film; and a dam for preventing overflow of the sealing organic film, wherein the first low-potential wiring, the second low-potential wiring, and the third low-potential wiring overlap with the dam.

Images