Display device

Abstract

A display device is provided. A display device according to one embodiment comprises at least: a display panel including a substrate, a light-emitting element disposed on an upper surface of the substrate, and an overcoat layer disposed on the light-emitting element; a film member disposed on the overcoat layer of the display panel; a conductive layer disposed between the overcoat layer and the film member; a chassis member disposed on a lower surface of the substrate of the display panel; and a sealing member covering a side of the display panel, wherein the sealing member can electrically connect the conductive layer and the chassis member.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] A device for displaying images of a display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, as a light-emitting display panel, it may include a light-emitting element; for example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0004] Inorganic light-emitting diodes that use inorganic semiconductors as fluorescent materials have the advantage of durability even in high-temperature environments and higher efficiency of blue light compared to organic light-emitting diodes. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device capable of discharging static electricity that may occur on the surface of a display.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to one embodiment for solving the above problem comprises at least: a display panel including a substrate, a light-emitting element disposed on an upper surface of the substrate, and an overcoat layer disposed on the light-emitting element; a film member disposed on the overcoat layer of the display panel; a conductive layer disposed between the overcoat layer and the film member; a chassis member disposed on a lower surface of the substrate of the display panel; and a sealing member covering a side of the display panel, wherein the sealing member can electrically connect the conductive layer and the chassis member.

[0008] A display device according to another embodiment for solving the above problem is a display device in which at least a display area and a non-display area surrounding the display area are defined, and comprises: a display panel defining the display area; a film member disposed on the upper surface of the display panel and having a width greater than that of the display panel; a conductive layer disposed between the display panel and the film member and having a width greater than that of the display panel; a chassis member disposed on the lower surface of the display panel and having a width greater than that of the display panel and smaller than that of the film member; and a sealing member covering the side of the display panel, wherein the chassis member and the film member are spaced apart from each other in the non-display area, and the sealing member is interposed in the spaced-apart space between the chassis member and the film member and can come into direct contact with the upper surface of the chassis member. Effects of the invention

[0009] A display device according to one embodiment can discharge static electricity that may occur on the surface of a display.

[0010] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0011] FIG. 1 is a plan view illustrating a display device according to one embodiment. FIG. 2 is a schematic plan view illustrating a film member, a display panel, and a chassis member included in a display device according to an embodiment of FIG. 1. Figure 3 is a schematic cross-sectional view showing a cross-section cut along the line X1-X1` of Figure 2. Figure 4 is a structural diagram schematically illustrating the connection relationship between the circuit layer and the light-emitting element of Figure 3. Figure 5 is a schematic diagram illustrating a light-emitting element. FIG. 6 is a schematic cross-sectional view of a section cut along the line X2-X2' of FIG. 2. Figure 7 is a schematic cross-sectional view of a section cut along the line X3-X3` of Figure 2. Figure 8 is an enlarged view of the Q1 region of Figure 7. Figure 9 is a diagram illustrating the path of electrostatic discharge occurring in a film member. FIG. 10 is a schematic plan view illustrating a chassis member of a display device according to another embodiment. FIG. 11 schematically illustrates a cross-section cut along the line X4-X4' of FIG. 10, specifically schematically illustrating the appearance of a sealing member of a display device according to the embodiment of FIG. 10. FIG. 12 is a schematic diagram illustrating the appearance of a sealing member of a display device according to another embodiment. FIG. 13 is a schematic plan view illustrating a chassis member of a display device according to another embodiment. FIG. 14 schematically illustrates a cross-section cut along the line X5-X5' of FIG. 13, specifically schematically illustrating the appearance of a sealing member of a display device according to the embodiment of FIG. 13. FIG. 15 is a schematic diagram illustrating the appearance of a sealing member of a display device according to another embodiment. FIG. 16 is a schematic plan view illustrating a chassis member of a display device according to another embodiment. Specific details for implementing the invention

[0012] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0013] When an element or layer is referred to as "above" another element or layer, it includes cases where another layer or element is interposed directly above or in the middle of another element. Likewise, when referred to as "below," "left," and "right," they include cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0014] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0015] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0016] Specific embodiments will be described below with reference to the attached drawings.

[0017] FIG. 1 is a plan view illustrating a display device according to one embodiment.

[0018] In FIG. 1, a first direction (DR1), a second direction (DR2), and a third direction (DR3) are defined. The first direction (DR1) and the second direction (DR2) may be perpendicular to each other, and the first direction (DR1) and the third direction (DR3) may be perpendicular to each other. The first direction (DR1) may be understood to mean the horizontal direction in the drawing, the second direction (DR2) may mean the vertical direction in the drawing, and the third direction (DR3) may be understood to mean the upper and lower directions in the drawing. In the following specification, unless otherwise specified, "direction" may refer to both directions extending along that direction. Additionally, if it is necessary to distinguish between the two "directions" extending to both sides, one side will be referred to as "direction one side" and the other side as "direction other side," respectively. Based on FIG. 1, the direction in which the arrow points is referred to as the first side, and the opposite direction is referred to as the other side.

[0019] In the following description, for convenience of explanation, when referring to the surfaces of the display device (1) or each component constituting the display device (1), the surface facing in the direction in which the image is displayed is referred to as the upper surface, and the surface opposite to the upper surface is referred to as the lower surface. However, this is not limited thereto, and the upper surface and the other surface of the component may be referred to as the front surface and the back surface, or as the first surface or the second surface, respectively.

[0020] Referring to FIG. 1, the display device (1) displays a video or a still image. The display device (1) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Program Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (1).

[0021] The display device (1) includes a display panel (300, see FIG. 2) that provides a display screen. Examples of the display panel (300) include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following, an example of the display panel (300) is given in which an inorganic light-emitting diode display panel is applied, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0022] The shape of the display device (1) can be varied in many ways. For example, the display device (1) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a square with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area (DA) of the display device (1) may also be similar to the overall shape of the display device (1). In FIG. 1, a display device (1) with a rectangular shape having a long length in the first direction (DR1) is exemplified.

[0023] The display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) is an area where a screen can be displayed, and the non-display area (NDA) is an area where a screen is not displayed. The display area (DA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DA) may generally occupy the center of the display device (1), but is not limited thereto.

[0024] A non-display area (NDA) may be placed around a display area (DA). In other words, the non-display area (NDA) may be placed to surround the edges of the display area (DA). In some embodiments, the display area (DA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to four sides of the display area (DA), but is not limited thereto. The non-display area (NDA) may form the bezel of the display device (1). In each non-display area (NDA), wiring or circuit drivers included in the display device (1) may be placed, or external devices may be mounted.

[0025] The display area (DA) and non-display area (NDA) of the display device (1) may also be applied to the components included in the display device (1). Below, the components included in the display device (1) will be described.

[0026] FIG. 2 is a schematic plan view illustrating a film member, a display panel, and a chassis member included in a display device according to an embodiment of FIG. 1.

[0027] Referring to FIG. 2, the display device (1) may include a film member (100), a display panel (300), and a chassis member (500). Although a stacked structure is not shown in FIG. 2, the display device (1) may be configured by stacking the chassis member (500), the display panel (300), and the film member (100) in the order of the third direction (DR3). For convenience of explanation, the film member (100), the display panel (300), and the chassis member (500) will be described in that order.

[0028] The film member (100) can serve to protect the display device (1) from the outside. The film member (100) can be placed at the top of the display device (1) to protect the display panel (300) placed below the film member (100). In other words, the film member (100) can be placed on the upper surface of the display panel (300).

[0029] The area of ​​the film member (100) may be larger than the area of ​​the display panel (300) and larger than the area of ​​the chassis member (500). In other words, the film member (100) may completely cover the display panel (300) and the chassis member (500), and may be positioned to extend beyond the display panel (300) and the chassis member (500). A detailed description of the structure of the film member (100) will be provided later.

[0030] The display panel (300) can serve to display a screen. The display panel (300) can define a display area (DA) of the display device (1). The display area (DA) of the display panel (300) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto. For example, the shape of each pixel (PX) may be a rhombus shape with each side tilted in one direction.

[0031] Each of the plurality of pixels (PX) may include a plurality of light-emitting regions that emit light of a specific wavelength range. For example, a pixel (PX) may include a first light-emitting region (LA1), a second light-emitting region (LA2), and a third light-emitting region (LA3). The first light-emitting region (LA1) may emit light of a first color, the second light-emitting region (LA2) may emit light of a second color, and the third light-emitting region (LA3) may emit light of a third color. For example, the first color light may be red light having a peak wavelength in the range of 610 nm to 650 nm, the second color light may be green light having a peak wavelength in the range of 510 nm to 550 nm, and the third color light may be blue light having a peak wavelength in the range of 440 nm to 480 nm, but is not limited thereto.

[0032] Each of the plurality of pixels (PX) of the display area (DA) of the display panel (300) may include a light-blocking area (BA) located between a plurality of adjacent light-emitting areas (LA1, LA2, LA3). For example, the light-blocking area (BA) may be positioned between the first light-emitting area (LA1) and the second light-emitting area (LA2), or between the second light-emitting area (LA2) and the third light-emitting area (LA3).

[0033] A detailed description of the structure of the display panel (300) will be provided later.

[0034] The chassis member (500) can serve to improve mechanical strength by supporting the bottom surface of the display panel (300). The chassis member (500) can be placed on the bottom surface of the display panel (300). To ensure mechanical strength, the chassis member (500) may include a metal such as SUS304 or aluminum, as a material having rigidity.

[0035] A flexible printed circuit board (COF) may be placed on one side of a display panel (300) and may serve to supply a driving signal to a pixel of the display panel (300). Multiple flexible printed circuit boards (COF) may be placed and spaced apart from each other. Although the electrical connection between the pixel and the flexible printed circuit board (COF) is not illustrated, it may be electrically connected to the pixel of the display panel (300). As described later, the flexible printed circuit board (COF) may be attached to the bottom surface of the chassis member (500) by extending from one side of the display panel (300) to the chassis member (500) (see FIG. 6). A detailed explanation of this will be provided later.

[0036] The structure of each component constituting the display device (1) will be described below.

[0037] FIG. 3 is a schematic cross-sectional view taken along the line X1-X1' of FIG. 2. FIG. 4 is a structural diagram schematically illustrating the connection relationship between the circuit layer and the light-emitting element of FIG. 3. FIG. 5 is a schematic drawing of the light-emitting element.

[0038] Referring to FIG. 3, each of the pixels (PX) of the display device (1) may include a plurality of subpixels (SPXn). For example, one pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. As an example, the first color light may be red light having a peak wavelength in the range of 610 nm to 650 nm, the second color light may be green light having a peak wavelength in the range of 510 nm to 550 nm, and the third color light may be blue light having a peak wavelength in the range of 440 nm to 480 nm. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. In one embodiment, each subpixel (SPXn) may emit blue light. Although the drawing illustrates one pixel (PX) comprising three subpixels (SPXn), it is not limited thereto, and the pixel (PX) may comprise a larger number of subpixels (SPXn).

[0039] Each subpixel (SPXn) of the display device (1) may include a light-emitting region and a non-light-emitting region. The light-emitting region may be an area where a light-emitting element (ED) is placed and light of a specific wavelength range is emitted. The non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach and is not emitted.

[0040] The light-emitting region may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) through which light emitted from the light-emitting element (ED) is emitted. For example, the light-emitting region may also include an area where light emitted from the light-emitting element (ED) is reflected or refracted by another component and emitted. A plurality of light-emitting elements (ED) are placed in each subpixel (SPXn), and a light-emitting region may be formed by including the area where they are placed and an area adjacent thereto.

[0041] In FIGS. 2 and 3, the light-emitting regions of each subpixel (SPXn) are illustrated as having a uniform area, but are not limited thereto. In some embodiments, each light-emitting region of each subpixel (SPXn) may have a different area depending on the color or wavelength range of light emitted from the light-emitting element (ED) placed in the corresponding subpixel. For convenience of explanation, the structure of the display panel (300) will be described first below.

[0042] Referring to FIG. 4 and FIG. 5 in conjunction with FIG. 3, the display panel (300) may include a substrate (SUB), a circuit layer (CCL), a first overcoat layer (OC1), bank patterns (BP1, BP2), a first insulating layer (PAS1), a plurality of electrodes (RME), a bank layer (BNL), a second insulating layer (PAS2), a light-emitting element (ED), a connecting electrode (CNE), a third insulating layer (PAS3), a fourth insulating layer (PAS4), an upper bank layer (UBN), a color control structure (WCL1, WCL2, TPL), a first capping layer (CPL1), a low-refractive index layer (LRL), a second capping layer (CPL2), a second overcoat layer (OC2), a color filter layer (CFL), and a third overcoat layer (OC3).

[0043] The substrate (SUB) can serve as the base of the display panel (300). The substrate (SUB) may be made of an insulating material such as glass, quartz, or polymer resin. Additionally, the substrate (SUB) may be a rigid substrate (SUB), but it may also be a flexible substrate (SUB) capable of bending, folding, rolling, etc. The bottom surface of the substrate (SUB) may be the bottom surface of the display panel (300).

[0044] A circuit layer (CCL) may be disposed on a substrate (SUB). Various wirings that transmit electrical signals to a light-emitting element disposed on the substrate (SUB) may be disposed on the circuit layer (CCL). As shown in FIG. 4, the circuit layer (CCL) may include a plurality of conductive layers, such as a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer, and may include a plurality of insulating layers, such as a buffer layer (BL), a first gate insulating layer (GI), a first interlayer insulating layer (IL1), and a first protective layer (PVL).

[0045] The first conductive layer may be disposed on a substrate (SUB). The first conductive layer includes a lower metal layer (BML), and the lower metal layer (BML) is disposed to overlap with the active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the first active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0046] A buffer layer (BL) can be disposed on a lower metal layer (BML) and a substrate (SUB). The buffer layer (BL) is formed on the substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0047] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0048] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0049] In the drawing, a first transistor (T1) and a second transistor (T2) are shown arranged in a subpixel (SPXn) of a display device (1), but the display device (1) is not limited thereto and may include a larger number of transistors.

[0050] The first gate insulating layer (GI) is placed on the semiconductor layer in the display area (DA). The first gate insulating layer (GI) can serve as the gate insulating film for each transistor (T1, T2). In the drawings, the first gate insulating layer (GI) is illustrated as being patterned together with the gate electrodes (G1, G2) of the second conductive layer described later, and partially placed between the second conductive layer and the active layer (ACT1, ACT2) of the semiconductor layer. However, it is not limited thereto. In some embodiments, the first gate insulating layer (GI) may be placed entirely on the buffer layer (BL).

[0051] A second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction.

[0052] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0053] The third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a first voltage wiring (VL1) and a second voltage wiring (VL2) disposed in a display area (DA), a first conductive pattern (CDP1), and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2).

[0054] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) can be applied to the first voltage line (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) can be applied to the second voltage line (VL2). A portion of the first voltage line (VL1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole that penetrates the first interlayer insulating layer (IL1). The first voltage line (VL1) can serve as the first drain electrode (D1) of the first transistor (T1). The second voltage line (VL2) can be directly connected to the second electrode (RME2) described later.

[0055] The first conductive pattern (CDP1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The first conductive pattern (CDP1) can contact the lower metal layer (BML) through another contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The first conductive pattern (CDP1) can serve as the first source electrode (S1) of the first transistor (T1). Additionally, the first conductive pattern (CDP1) can be connected to the first electrode (RME1) or the first connection electrode (CNE1) described later. The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0056] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1).

[0057] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0058] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the inorganic layers are stacked alternately.

[0059] A first overcoat layer (OC1) may be disposed on the circuit layer (CCL). Specifically, the first overcoat layer (OC1) may be disposed on the first protective layer of the circuit layer (CCL). The first overcoat layer (OC1) may include an organic insulating material, such as polyimide (PI), to compensate for step differences caused by various wirings within the circuit layer (CCL) and to form a flat upper surface. However, in some embodiments, the first overcoat layer (OC1) may be omitted.

[0060] A plurality of bank patterns (BP1, BP2) may be disposed on the first overcoat layer (OC1). For example, the bank patterns (BP1, BP2) may be disposed directly on the first overcoat layer (OC1) and may have a structure in which at least a portion protrudes with respect to the upper surface of the first overcoat layer (OC1). The protruding portion of the bank patterns (BP1, BP2) may have a side that is inclined or bent with a certain curvature, and light emitted from the light-emitting element (ED) may be reflected from the electrode (RME) disposed on the bank patterns (BP1, BP2) and emitted in the direction of the upper portion of the first overcoat layer (OC1). The bank patterns (BP1, BP2) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0061] A plurality of electrodes (RME; RME1, RME2) may be disposed on bank patterns (BP1, BP2) and a first overcoat layer (OC1). For example, the first electrode (RME1) and the second electrode (RME2) may be disposed on at least the inclined side of the bank patterns (BP1, BP2). The width of the plurality of electrodes (RME) measured in the second direction (DR2) may be smaller than the width of the bank patterns (BP1, BP2) measured in the second direction (DR2), and the spacing between the first electrode (RME1) and the second electrode (RME2) in the second direction (DR2) may be narrower than the spacing between the bank patterns (BP1, BP2). At least some regions of the first electrode (RME1) and the second electrode (RME2) may be disposed directly on the first overcoat layer (OC1) so that they are disposed on the same plane.

[0062] A light-emitting element (ED) placed between bank patterns (BP1, BP2) emits light in both end directions, and the emitted light can be directed toward an electrode (RME) placed on the bank patterns (BP1, BP2).

[0063] The light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0064] A light-emitting element (ED) according to one embodiment may have a shape extending in one direction. In some embodiments, the light-emitting element (ED) may have a shape such as a cylinder, rod, wire, or tube, but is not limited thereto.

[0065] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0066] The first semiconductor layer (31) of the light-emitting element (ED) may be an n-type semiconductor. The first semiconductor layer (31) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, etc.

[0067] The second semiconductor layer (32) of the light-emitting element (ED) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0068] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a larger number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer.

[0069] The light-emitting layer (36) of the light-emitting device (ED) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electrical signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, if the light-emitting layer (36) has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN.

[0070] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0071] The electrode layer (37) of the light-emitting element (ED) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0072] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (1) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0073] The insulating film (38) of the light-emitting element (ED) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0074] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, the insulating film (38) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0075] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO₂ xIt may include at least one of ). In the drawings, the insulating film (38) is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0076] Each electrode (RME) may have a structure in which a portion disposed on the bank pattern (BP1, BP2) can reflect light emitted from the light-emitting element (ED). The first electrode (RME1) and the second electrode (RME2) are disposed to cover at least one side of the bank pattern (BP1, BP2) so as to reflect light emitted from the light-emitting element (ED).

[0077] Each electrode (RME) can directly contact the third conductive layer through electrode contact holes (CTD, CTS) in the portion overlapping with the bank layer (BNL). The first electrode contact hole (CTD) may be formed in the area where the bank layer (BNL) and the first electrode (RME1) overlap, and the second electrode contact hole (CTS) may be formed in the area where the bank layer (BNL) and the second electrode (RME2) overlap. The first electrode (RME1) can contact the first conductive pattern (CDP1) through the first electrode contact hole (CTD) penetrating the first overcoat layer (OC1) and the first protective layer (PV1). The second electrode (RME2) can contact the second voltage wiring (VL2) through the second electrode contact hole (CTS) penetrating the first overcoat layer (OC1) and the first protective layer (PV1). The first electrode (RME1) may be electrically connected to the first transistor (T1) through the first conductive pattern (CDP1) to apply the first power supply voltage, and the second electrode (RME2) may be electrically connected to the second voltage wiring (VL2) to apply the second power supply voltage. However, it is not limited thereto. In other embodiments, each electrode (RME1, RME2) may not be electrically connected to the voltage wiring (VL1, VL2) of the third conductive layer, and the connecting electrode (CNE) described below may be directly connected to the third conductive layer.

[0078] Multiple electrodes (RMEs) may include a highly reflective conductive material. For example, the electrodes (RMEs) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), an alloy such as aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) is stacked with said alloy. In some embodiments, the electrodes (RMEs) may be composed of a double layer or a multilayer structure in which an alloy containing aluminum (Al) and at least one metal layer consisting of titanium (Ti), molybdenum (Mo), and niobium (Nb) are stacked.

[0079] Each electrode (RME) may further include a transparent conductive material, without being limited thereto. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including them. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrodes (RME) are electrically connected to the light-emitting element (ED) and may reflect some of the light emitted from the light-emitting element (ED) toward the upper direction of the substrate (SUB).

[0080] The first insulating layer (PAS1) is disposed on the front surface of the display area (DA) and may be disposed on the first overcoat layer (OC1) and a plurality of electrodes (RME). The first insulating layer (PAS1) may include an insulating material to protect the plurality of electrodes (RME) while simultaneously insulating different electrodes (RME) from each other. Since the first insulating layer (PAS1) is disposed to cover the electrodes (RME) before the bank layer (BNL) is formed, the electrodes (RME) can be prevented from being damaged during the process of forming the bank layer (BNL). Additionally, the first insulating layer (PAS1) may prevent the light-emitting element (ED) disposed thereon from being damaged by direct contact with other components.

[0081] In an exemplary embodiment, the first insulating layer (PAS1) may have a step formed such that a portion of its upper surface is recessed between electrodes (RME) spaced apart in the second direction (DR2). A light-emitting element (ED) is disposed on the upper surface of the first insulating layer (PAS1) where the step is formed, and a space may be formed between the light-emitting element (ED) and the first insulating layer (PAS1).

[0082] Although not illustrated in the drawings, the first insulating layer (PAS1) may include contact portions. Each contact portion may be positioned to overlap with a different electrode (RME). For example, the contact portions may include first contact portions positioned to overlap with the first electrode (RME1) and second contact portions positioned to overlap with the second electrode (RME2). The first contact portions and the second contact portions may penetrate the first insulating layer (PAS1) to expose a portion of the upper surface of the first electrode (RME1) or the second electrode (RME2) below it. The first contact portions and the second contact portions may each further penetrate some of the other insulating layers positioned on the first insulating layer (PAS1). The electrode (RME) exposed by each contact portion may come into contact with the connecting electrode (CNE).

[0083] A bank layer (BNL) may be disposed on a first insulating layer (PAS1). The bank layer (BNL) includes a portion extending in a first direction (DR1) and a second direction (DR2) and may surround each subpixel (SPXn). The bank layer (BNL) may surround each subpixel (SPXn) and distinguish them, and may surround the outermost edge of a display area (DA) and distinguish the display area (DA) from a non-display area (NDA).

[0084] The light-emitting elements (ED) can be electrically connected to the electrode (RME) and the conductive layer under the first overcoat layer (OC1) by contacting the connecting electrodes (CNE: CNE1, CNE2), and can emit light of a specific wavelength range when an electrical signal is applied.

[0085] The bank layer (BNL) may have a certain height similar to the bank pattern (BP1, BP2). In some embodiments, the height of the upper surface of the bank layer (BNL) may be higher than that of the bank pattern (BP1, BP2), and its thickness may be equal to or greater than that of the bank pattern (BP1, BP2). The bank layer (BNL) can prevent ink from overflowing into adjacent subpixels (SPXn) during the inkjet printing process in the manufacturing process of the display device (1). The bank layer (BNL) may include an organic insulating material such as polyimide, similar to the bank pattern (BP1, BP2).

[0086] A second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED), a first insulating layer (PAS1), and a bank layer (BNL). The second insulating layer (PAS2) includes a pattern portion that extends in a first direction (DR1) between bank patterns (BP1, BP2) and is disposed on a plurality of light-emitting elements (ED). The pattern portion is disposed to partially cover the outer surface of the light-emitting element (ED), and may not cover both sides or both ends of the light-emitting element (ED). The pattern portion may form a linear or island pattern within each subpixel (SPXn) in a planar view. The pattern portion of the second insulating layer (PAS2) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting elements (ED) during the manufacturing process of the display device (1). Additionally, the second insulating layer (PAS2) may be disposed to fill the space between the light-emitting element (ED) and the first insulating layer (PAS1) below it. In addition, a portion of the second insulating layer (PAS2) may be placed on top of the bank layer (BNL).

[0087] Although not illustrated in the drawing, the second insulating layer (PAS2) may include contact portions. The second insulating layer (PAS2) may include a first contact portion arranged to overlap with the first electrode (RME1), and a second contact portion arranged to overlap with the second electrode (RME2). The contact portions may penetrate the second insulating layer (PAS2) in addition to the first insulating layer (PAS1). A plurality of first contact portions and second contact portions may each expose a portion of the upper surface of the first electrode (RME1) or the second electrode (RME2) below them.

[0088] A plurality of connecting electrodes (CNE; CNE1, CNE2) may be disposed on a plurality of electrodes (RME) and bank patterns (BP1, BP2). A first connecting electrode (CNE1) may be disposed on a first electrode (RME1) and a first bank pattern (BP1). The first connecting electrode (CNE1) may partially overlap with the first electrode (RME1) and be disposed to extend beyond the bank layer (BNL) from the light-emitting region. A second connecting electrode (CNE2) may be disposed on a second electrode (RME2) and a second bank pattern (BP2). The second connecting electrode (CNE2) may partially overlap with the second electrode (RME2) and be disposed to extend beyond the bank layer (BNL) from the light-emitting region.

[0089] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each disposed on the second insulating layer (PAS2) and can come into contact with light-emitting elements (EDs). The first connecting electrode (CNE1) partially overlaps with the first electrode (RME1) and can come into contact with one end of the light-emitting elements (EDs). The second connecting electrode (CNE2) partially overlaps with the second electrode (RME2) and can come into contact with the other end of the light-emitting elements (EDs). The connecting electrodes (CNEs) come into contact with the light-emitting elements (EDs) and can be electrically connected to the third conductive layer. The first connecting electrode (CNE1) comes into contact with the first end of the light-emitting elements (EDs), and the second connecting electrode (CNE2) comes into contact with the second end of the light-emitting elements (EDs).

[0090] According to one embodiment, the display device (1) allows each connecting electrode (CNE) to contact an electrode (RME) through contact portions (CT1, CT2). The first connecting electrode (CNE1) can contact the first electrode (RME1) through a first contact portion (CT1) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3). The second connecting electrode (CNE2) can contact the second electrode (RME2) through a second contact portion (CT2) that penetrates the first insulating layer (PAS1) and the second insulating layer (PAS2). Each connecting electrode (CNE) can be electrically connected to the third conductive layer through each electrode (RME). The first connecting electrode (CNE1) is electrically connected to the first transistor (T1) so that the first power supply voltage is applied, and the second connecting electrode (CNE2) is electrically connected to the second voltage wiring (VL2) so that the second power supply voltage can be applied. Each connecting electrode (CNE) can contact the light-emitting element (ED) in the light-emitting region to transmit the power supply voltage to the light-emitting element (ED).

[0091] Connecting electrodes (CNEs) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connecting electrode (CNE) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the connecting electrode (CNE) and be emitted.

[0092] A third insulating layer (PAS3) is disposed on the second connecting electrode (CNE2) of the first connecting electrode layer and on the second insulating layer (PAS2). The third insulating layer (PAS3) is disposed entirely on the second insulating layer (PAS2) to cover the second connecting electrode (CNE2), and the first connecting electrode (CNE1) of the second connecting electrode layer may be disposed on the third insulating layer (PAS3). The third insulating layer (PAS3) can insulate the first connecting electrode (CNE1) from the second connecting electrode (CNE2) so that they do not come into direct contact with each other.

[0093] The third insulating layer (PAS3) may include first contact portions. The first contact portions may penetrate the third insulating layer (PAS3) in addition to the first insulating layer (PAS1) and the second insulating layer (PAS2). A plurality of first contact portions may expose a portion of the upper surface of the first electrode (RME1) below them.

[0094] The fourth insulating layer (PAS4) may be disposed on the third insulating layer (PAS3), the connecting electrodes (CNE1, CNE2), and the bank layer (BNL). The fourth insulating layer (PAS4) may protect the layers disposed on the substrate (SUB). However, the fourth insulating layer (PAS4) may be omitted.

[0095] An upper bank layer (UBN), a color control structure (TPL, WCL1, WCL2), a color pattern (CP1, CP2, CP3), and a color filter layer (CFL1, CFL2, CFL3) may be disposed on the fourth insulating layer (PAS4). Between the color control structure (TPL, WCL1, WCL2) and the color filter layer (CFL1, CFL2, CFL3), a plurality of capping layers (CPL1, CPL2), a low refractive index layer (LRL), and a second overcoat layer (OC2) may be disposed, and an overcoat layer (OC) may be disposed on the color filter layer (CFL1, CFL2, CFL3).

[0096] The first insulating layer (PAS1), second insulating layer (PAS2), third insulating layer (PAS3), and fourth insulating layer (PAS4) described above may each comprise an inorganic insulating material or an organic insulating material. In an exemplary embodiment, the first insulating layer (PAS1), second insulating layer (PAS2), third insulating layer (PAS3), and fourth insulating layer (PAS4) are each silicon oxide (SiO₂). x ), silicon nitride (SiN x ), and silicon oxynitride (SiO₂ x N yIt may be any one of the following. The first insulating layer (PAS1), the second insulating layer (PAS2), the third insulating layer (PAS3), and the fourth insulating layer (PAS4) may be made of the same material, some may be made of the same material and some may be made of different material, or each may be made of different material.

[0097] The upper bank layer (UBN) may be arranged to overlap with the bank layer (BNL) on the fourth insulating layer (PAS4). The upper bank layer (UBN) may be arranged in a grid pattern including portions extending in the first direction (DR1) and the second direction (DR2). The upper bank layer (UBN) may surround a portion where light-emitting regions or light-emitting elements (ED) are arranged. The upper bank layer (UBN) may form a region where color control structures (TPL, WCL1, WCL2) are arranged.

[0098] Color control structures (TPL, WCL1, WCL2) may be placed within the area surrounded by the upper bank layer (UBN) on the fourth insulating layer (PAS4). The color control structures (TPL, WCL1, WCL2) may be placed in the light-emitting areas (LA1, LA2, LA3) surrounded by the upper bank layer (UBN) to form an island-shaped pattern in the display area (DA). However, not limited thereto, the color control structures (TPL, WCL1, WCL2) may each extend in one direction and be placed across a plurality of subpixels (SPXn) to form a linear pattern.

[0099] In an embodiment in which the light-emitting element (ED) of each subpixel (SPXn) emits blue light of a third color, the color control structure (TPL, WCL1, WCL2) may include a first wavelength conversion layer (WCL1) disposed in the first subpixel (SPX1) corresponding to a first light-emitting region (LA1), a second wavelength conversion layer (WCL2) disposed in the second subpixel (SPX2) corresponding to a second light-emitting region (LA2), and a light-transmitting layer (TPL) disposed in the third subpixel (SPX3) corresponding to a third light-emitting region (LA3).

[0100] The first wavelength conversion layer (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) disposed within the first base resin (BRS1). The second wavelength conversion layer (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) disposed within the second base resin (BRS2). The first wavelength conversion layer (WCL1) and the second wavelength conversion layer (WCL2) convert and transmit the wavelength of the third color blue light incident from the light-emitting element (ED). The first wavelength conversion layer (WCL1) and the second wavelength conversion layer (WCL2) further include a scatterer (SCP) contained in each base resin, and the scatterer (SCP) can increase the wavelength conversion efficiency.

[0101] The light-transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) disposed within the third base resin (BSR3). The light-transmitting layer (TPL) transmits the third color blue light incident from the light-emitting element (ED) while maintaining its wavelength. The scatterer (SCP) of the light-transmitting layer (TPL) may serve to regulate the emission path of light emitted through the light-transmitting layer (TPL). The light-transmitting layer (TPL) may not contain a wavelength conversion material.

[0102] The scattering body (SCP) may be a metal oxide particle or an organic particle. Examples of the metal oxide may include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle material may include acrylic resin or urethane resin.

[0103] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a transparent organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may be composed of an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be composed of the same material, but are not limited thereto.

[0104] The first wavelength conversion material (WCP1) may be a material that converts third-color blue light into first-color red light, and the second wavelength conversion material (WCP2) may be a material that converts third-color blue light into second-color green light. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0105] In some embodiments, the color control structures (TPL, WCL1, WCL2) may be formed through an inkjet printing process or a photoresist process. The color control structures (TPL, WCL1, WCL2) may be formed through a drying or exposure and development process after the material constituting them is sprayed or applied within the area surrounded by the upper bank layer (UBN). For example, in an embodiment where the color control structures (TPL, WCL1, WCL2) are formed by an inkjet printing process, the upper surface of each layer of the color control structures (TPL, WCL1, WCL2) may be formed curved in the drawings so that the edge portion adjacent to the upper bank layer (UBN) is higher than the center. However, this is not limited thereto. In an embodiment where the color control structure (TPL, WCL1, WCL2) is formed by a photoresist process, the upper surface of each layer of the color control structure (TPL, WCL1, WCL2) may be formed flat so that the edge portion adjacent to the upper bank layer (UBN) is parallel to the upper surface of the upper bank layer (UBN), or, unlike the drawing, the center of the color control structure (TPL, WCL1, WCL2) may be formed higher.

[0106] The light-emitting element (ED) of each subpixel (SPXn) can emit the same third color of blue light, and the light emitted from each subpixel (SPXn) can be of different colors. For example, light emitted from the light-emitting element (ED) placed in the first subpixel (SPX1) is incident on the first wavelength conversion layer (WCL1), light emitted from the light-emitting element (ED) placed in the second subpixel (SPX2) is incident on the second wavelength conversion layer (WCL2), and light emitted from the light-emitting element (ED) placed in the third subpixel (SPX3) is incident on the light-transmitting layer (TPL). The light incident on the first wavelength conversion layer (WCL1) is converted into red light, the light incident on the second wavelength conversion layer (WCL2) is converted into green light, and the light incident on the light-transmitting layer (TPL) can be transmitted as the same blue light without wavelength conversion. Even if each subpixel (SPXn) includes light-emitting elements (ED) that emit light of the same color, it can emit light of different colors depending on the arrangement of the color control structures (TPL, WCL1, WCL2) placed above it.

[0107] The first capping layer (CPL1) may be disposed on a plurality of color control structures (TPL, WCL1, WCL2) and an upper bank layer (UBN). The first capping layer (CPL1) can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the color control structures (TPL, WCL1, WCL2). The first capping layer (CPL1) may include an inorganic insulating material.

[0108] A low refractive index layer (LRL) can be placed on the first capping layer (CPL1). The low refractive index layer (LRL) is an optical layer that recycles light passing through the color control structure (TPL, WCL1, WCL2) and can improve the light emission efficiency and color purity of the display device (1). The low refractive index layer (LRL) can be made of an organic material having a low refractive index and can compensate for the step difference formed by the color control structure (TPL, WCL1, WCL2) and the upper bank layer (UBN).

[0109] The second capping layer (CPL2) is placed on the low-refractive index layer (LRL) and can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the low-refractive index layer (LRL). The second capping layer (CPL2) may include an inorganic insulating material similar to the first capping layer (CPL1).

[0110] The second overcoat layer (OC2) can be placed across the entire front of the display area (DA) and non-display area (NDA) on the second capping layer (CPL2). The second overcoat layer (OC2) overlaps with the color control structures (TPL, WCL1, WCL2) in the display area (DA), and overlaps with the dam structure ('DAM' in FIG. 8) and valley section ('VA' in FIG. 8) described later in the non-display area (NDA).

[0111] The second overcoat layer (OC2) protects the members disposed on the substrate (SUB) in addition to the plurality of capping layers (CPL1, CPL2) and the low-refractive index layer (LRL), and can partially compensate for the step difference caused by them. In particular, the second overcoat layer (OC2) compensates for the step difference formed by the lower color control structures (TPL, WCL1, WCL2) and the upper bank layer (UBN) and bank layer (BNL) in the display area (DA), so that the color filter layers (CFL1, CFL2, CFL3) disposed thereon can be formed on a flat surface.

[0112] A plurality of color filter layers (CFL1, CFL2, CFL3) may be disposed on a second overcoat layer (OC2). Each of the color filter layers (CFL1, CFL2, CFL3) may be disposed in a light-emitting region (LA1, LA2, LA3), and a portion thereof may be disposed in a light-blocking region (BA). The color filter layers (CFL1, CFL2, CFL3) may overlap with other color filter layers (CFL1, CFL2, CFL3) or color patterns (CP1, CP2, CP3) in the light-blocking region (BA). The part where the color filter layer (CFL1, CFL2, CFL3) does not overlap with other color filter layers (CFL1, CFL2, CFL3) is a light-emitting region (LA1, LA2, LA3) where light is emitted, and the part where different color filter layers (CFL1, CFL2, CFL3) overlap or where color patterns (CP1, CP2, CP3) are arranged may be a light-blocking region (BA) where the emission of light is blocked.

[0113] The color filter layers (CFL1, CFL2, CFL3) may include a first color filter layer (CFL1) disposed in a first subpixel (SPX1), a second color filter layer (CFL2) disposed in a second subpixel (SPX2), and a third color filter layer (CFL3) disposed in a third subpixel (SPX3). The color filter layers (CFL1, CFL2, CFL3) may be formed as a linear pattern disposed in a plurality of light-emitting regions (LA1, LA2, LA3). However, they are not limited thereto. The color filter layers (CFL1, CFL2, CFL3) may be disposed corresponding to each light-emitting region (LA1, LA2, LA3) and may form an island-shaped pattern.

[0114] The color filter layers (CFL1, CFL2, CFL3) may include a colorant, such as a dye or pigment, that absorbs light of a wavelength other than that of a specific wavelength. The color filter layers (CFL1, CFL2, CFL3) are arranged for each subpixel (SPXn) and may transmit only a portion of the light incident from the corresponding subpixel (SPXn) to the color filter layers (CFL1, CFL2, CFL3). In each subpixel (SPXn) of the display device (1), only the light transmitted by the color filter layers (CFL1, CFL2, CFL3) may be selectively displayed. In an exemplary embodiment, the first color filter layer (CFL1) may be a red color filter layer, the second color filter layer (CFL2) may be a green color filter layer, and the third color filter layer (CFL3) may be a blue color filter layer. Lights emitted from the light-emitting element (ED) can pass through the color control structure (TPL, WCL1, WCL2) and be emitted through the color filter layer (CFL1, CFL2, CFL3).

[0115] Color patterns (CP1, CP2, CP3) may be placed on a second overcoat layer (OC2) or a color filter layer (CFL1, CFL2, CFL3). Color patterns (CP1, CP2, CP3) may be placed in a light-blocking area (BA) containing the same material as the color filter layer (CFL1, CFL2, CFL3). In the light-blocking area (BA), color patterns (CP1, CP2, CP3) and color filter layers (CFL1, CFL2, CFL3) different from each other are stacked and disposed, and the transmission of light can be blocked in the area where they are stacked.

[0116] The first color pattern (CP1) may be placed in a light-blocking area (BA) containing the same material as the first color filter layer (CFL1). The first color pattern (CP1) may be placed directly on the second overcoat layer (OC2) in the light-blocking area (BA) and may not be placed in the light-blocking area (BA) adjacent to the first light-emitting area (LA1) of the first subpixel (SPX1). The first color pattern (CP1) may be placed in the light-blocking area (BA) between the second subpixel (SPX2) and the third subpixel (SPX3). The first color filter layer (CFL1) may be placed in the light-blocking area (BA) around the first subpixel (SPX1).

[0117] The second color pattern (CP2) may be placed in a light-blocking area (BA) containing the same material as the second color filter layer (CFL2). The second color pattern (CP2) may be placed directly on the second overcoat layer (OC2) in the light-blocking area (BA) and may not be placed in the light-blocking area (BA) adjacent to the second light-emitting area (LA2) of the second subpixel (SPX2). The second color pattern (CP2) may be placed in the light-blocking area (BA) between the first subpixel (SPX1) and the third subpixel (SPX3), or at the boundary between the outermost subpixel (SPXn) of the display area (DA) and the non-display area (NDA). The second color filter layer (CFL2) may be placed in the light-blocking area (BA) around the second subpixel (SPX2).

[0118] Similarly, the third color pattern (CP3) may be placed in the light-blocking region (BA) and may contain the same material as the third color filter layer (CFL3). The third color pattern (CP3) may be placed directly on the second overcoat layer (OC2) in the light-blocking region (BA) and may not be placed in the light-blocking region (BA) adjacent to the third light-emitting region (LA3) of the third subpixel (SPX3). The third color pattern (CP3) may be placed in the light-blocking region (BA) between the first subpixel (SPX1) and the second subpixel (SPX2). The third color filter layer (CFL3) may be placed in the light-blocking region (BA) around the third subpixel (SPX3).

[0119] In the display device (1), the area overlapping with the bank layer (BNL) and the upper bank layer (UBN) becomes a light-blocking area (BA), and in the light-blocking area (BA), each of the first color pattern (CP1), the second color pattern (CP2), and the third color pattern (CP3) may be arranged to overlap with at least one of the color filter layers (CFL1, CFL2, CFL3) containing different color materials. For example, the first color pattern (CP1) may be arranged to overlap with the second color filter layer (CFL2) and the third color filter layer (CFL3), the second color pattern (CP2) may be arranged to overlap with the first color filter layer (CFL1) and the third color filter layer (CFL3), and the third color pattern (CP3) may be arranged to overlap with the first color filter layer (CFL1) and the second color filter layer (CFL2). The light-blocking region (BA) can block the transmission of light by overlapping color patterns (CP1, CP2, CP3) containing different color materials and color filter layers (CFL1, CFL2, CFL3) with each other.

[0120] Multiple color patterns (CP1, CP2, CP3) have a stacked structure with color filter layers (CFL1, CFL2, CFL3), and can prevent color mixing between adjacent regions by using materials containing different color materials.

[0121] The third overcoat layer (OC3) may be placed on the color filter layers (CFL1, CFL2, CFL3) and the color patterns (CP1, CP2, CP3). The third overcoat layer (OC3) is placed across the entire front surface of the display area (DA), and a portion may also be placed in the non-display area (NDA). The third overcoat layer (OC3) may include an organic insulating material to protect the components placed in the display area (DA) from the outside. The upper surface of the third overcoat layer (OC3) may be the upper surface of the display panel (300).

[0122] A film member (100) and a conductive layer (200) may be disposed on a third overcoat layer (OC3). Specifically, the film member (100) is disposed on the third overcoat layer (OC3), and the conductive layer (200) is disposed between the film member (100) and the third overcoat layer (OC3). An adhesive layer (ADH) is interposed between the conductive layer (200) and the third overcoat layer so that the third overcoat layer (OC3) and the conductive layer (200) can be bonded to each other. Additionally, although not shown in the drawings, a separate adhesive member may also be interposed between the conductive layer (200) and the film member (100) so that the film member (100) and the conductive layer (200) can be bonded to each other.

[0123] As described above, the film member (100) can serve to protect the upper surface of the display device (1). The film member (100) may include an anti-fingerprint film (110) and a base film (130) placed at the top.

[0124] The anti-fingerprint film (110) of the film member (100) can serve to prevent fingerprints from being left on the display device (1) by a user. Since the structure of the anti-fingerprint film (110) is widely known in the art, a detailed description thereof will be omitted.

[0125] The base film (130) of the film member (100) can serve as the base of the film member (100). The base film (130) may include a material having a certain degree of rigidity. In some embodiments, the base film (130) may include triacetyl cellulose (TAC), but is not limited thereto. As described above, the base film (130) can protect the outside of the display device (1) by having a certain degree of rigidity.

[0126] Meanwhile, the film member (100) is a part that is directly touched by the hand of the user of the display device (1), and static electricity may be generated on the film member (100) due to the user's handling. However, if there is no means to discharge the static electricity generated on the film member (100), the static electricity generated on the film member (100) may cause damage to the display panel (300). Accordingly, it is necessary to provide a means to discharge the static electricity generated on the film member (100).

[0127] The conductive layer (200) can serve to provide a path for discharging static electricity generated in the film member (100). The conductive layer (200) may be placed on the bottom surface of the film member (100). The conductive layer (200) may have substantially the same area and width as the film member (100) and may completely overlap with the film member (100), but is not limited thereto. For example, the conductive layer (200) may have a smaller area compared to the film member (100). For convenience of explanation, the following description will focus on the case where the area of ​​the film member (100) and the conductive layer (200) are substantially the same.

[0128] The conductive layer (200) may include a transparent material having conductivity. Accordingly, a path can be secured to discharge static electricity generated in the film member (100) without blocking the transmission of light in the display area (DA). In some embodiments, the conductive layer (200) may include a transparent metal oxide such as indium tin oxide (ITO), but is not limited thereto.

[0129] As described above, the chassis member (500) can serve to increase mechanical strength by supporting the bottom surface of the display panel (300). The chassis member (500) can be placed on the bottom surface of the display panel (300), that is, on the bottom surface of the substrate (SUB) of the display panel (300). The chassis member (500) may include a conductive metal.

[0130] A heat dissipation layer (GP) may be disposed between the chassis member (500) and the display panel (300). The heat dissipation layer (GP) may serve to shield electromagnetic waves emitted from the display panel (300). In some embodiments, the heat dissipation layer (GP) may include graphite, but is not limited thereto.

[0131] The chassis member (500) can be electrically connected to the conductive layer (200) by the sealing member (700) as described below. Accordingly, static electricity transmitted to the conductive layer (200) can pass through the sealing member (700) and be discharged from the chassis member (500). The sealing member (700) will be described in detail below.

[0132] FIG. 6 is a schematic cross-sectional view taken along the line X2-X2' of FIG. 2. FIG. 7 is a schematic cross-sectional view taken along the line X3-X3' of FIG. 2. FIG. 8 is an enlarged view of the Q1 region of FIG. 7.

[0133] Referring to FIGS. 6 and 7, a display device (1) according to one embodiment has a second direction (DR2) width of a film member (100), a second direction (DR2) width of a chassis member (500), and a second direction (DR2) width of a display panel (300) in that order, and the step difference in the second direction (DR2) width of each member is formed in a non-display area (NDA). In the non-display area (NDA), the film member (100), the display panel (300), and the chassis member (500) are spaced apart from each other to form a spaced-apart space, and may further include a sealing member (700) interposed in the spaced-apart space to cover the side of the display panel (300). In some embodiments, the second direction (DR2) width of the film member (100) and the second direction (DR2) width of the conductive layer (200) may be substantially the same, but are not limited thereto. For convenience of explanation, the following description will focus on the fact that the second direction (DR2) width of the conductive layer (200) is substantially the same as the second direction (DR2) width of the film member (100).

[0134] The sealing member (700) can cover the side of the display panel (300), bond the film member (100) and the chassis member (500) to increase mechanical stability, and receive static electricity from the conductive layer (200) and transmit it to the chassis member (500). The sealing member (700) may include a conductive material. The sealing member (700) can be electrically connected by directly contacting the bottom surface of the conductive layer (200) in an area where the flexible printed circuit board (COF) is not placed.

[0135] In the area where the flexible printed circuit board (COF) is placed, the sealing member (700) may also be interposed on one side of the flexible printed circuit board (COF) as shown in FIG. 6, so as to cover a portion of one side of the flexible printed circuit board (COF). The flexible printed circuit board (COF) may be placed at the end of the substrate (SUB) of the display panel (300), bent toward the chassis member (500), and attached to the bottom surface of the chassis member (500). A driving chip (DC) that generates a driving signal may be mounted on the flexible printed circuit board (COF). In some embodiments, the driving chip (DC) may be placed on one side of the flexible printed circuit board (COF) and positioned to face the outside of the display device (1), but is not limited thereto. A resin (RP) may be interposed between the side of the substrate (SUB) of the flexible printed circuit board (COF) and the display panel (300). The resin (RP) can compensate for the second direction (DR2) step difference between the display panel (300) and the chassis member (500) to relieve stress that may be applied to the flexible printed circuit board (COF) due to the bending of the flexible printed circuit board (COF).

[0136] The sealing member (700) can come into direct contact with the upper surface of the chassis member (500) as shown in FIG. 7 in the spaced-apart space (see FIG. 2) between a plurality of flexible printed circuit boards (COF). As the second direction (DR2) width of the chassis member (500) and the second direction (DR2) width of the conductive layer (200) (or the second direction (DR2) width of the film member (100)) are larger than the second direction (DR2) width of the display panel (300), a portion exposed from the display panel (300) to the third direction (DR3) in the non-display area (NDA) is defined, so that the film member (100) and the chassis member (500) are spaced apart from each other to form a spaced-apart space, and the sealing member (700) is interposed in the spaced-apart space between the film member (100) and the chassis member (500) and can come into direct contact with the bottom surface of the conductive layer (200) and the top surface of the chassis member (500).

[0137] Meanwhile, various members disposed on the substrate (SUB) of the display panel (300) can define a step difference by forming a slope that tilts toward the bottom surface of the display panel (300) near the boundary between the display area (DA) and the non-display area (NDA). Accordingly, the film member (100), the conductive layer (200), and the substrate (SUB) of the display panel (300) can be spaced apart from each other with the sealing member (700) in between. Below, the shape of the sealing member (700) interposed near the boundary between the non-display area (NDA) and the display area (DA), and the part where the conductive layer (200) and the sealing member (700) begin to come into direct contact will be described.

[0138] FIG. 8 is an enlarged view of the Q1 region of FIG. 7. FIG. 9 is a diagram illustrating the path of electrostatic discharge occurring in the film member.

[0139] Referring to FIG. 8, a display panel (300) according to one embodiment does not include a light-emitting element in a non-display area (NDA), so the width of the third direction (DR3) of the non-display area (NDA) may be smaller than the width of the third direction (DR3) of the display area (DA) compared to the display area (DA).

[0140] Specifically, the non-display area (NDA) is an area that does not display a screen and does not have a light-emitting element (ED) placed therein, so various elements adjacent to the light-emitting element (ED), such as bank patterns (BP1, BP2), first electrode (RME1), second electrode (RME2), first connecting electrode (CNE1), second connecting electrode (CNE2), color control material (WCL1, WCL2, TPL), etc., may not be placed therein. Instead, in the non-display area (NDA) of the display panel (300), a dam (DAM) is placed on the first overcoat layer (OC1) to prevent the low-refractive index layer (LRL) from flooding into the non-display area (NDA), and a valley (VA) penetrating the first overcoat layer (OC1) may be placed near the boundary between the non-display area (NDA) and the display area (DA) of the display panel (300). Accordingly, the first overcoat layer (OC1) has a shape that is concavely recessed toward the other side of the third direction (DR3) near the boundary between the non-display area (NDA) and the display area (DA), and the low-refractive index layer (LRL) fills the valley portion (VA) during the formation process to form a step, and is not flooded into the non-display area (NDA) by the dam portion (DAM).

[0141] As described above, between the film member (100) and the display panel (300), a step is formed in the display panel (300) so that they are spaced apart from each other in the non-display area (NDA). Therefore, a sealing member (700) can be interposed in the spaced-out area between the display panel (300) and the film member (100) to fill the spaced-out area.

[0142] The adhesive layer (ADH) bonding the third overcoat layer (OC3) and the conductive layer (200) may extend to the non-display area (NDA) and may not extend further in the non-display area (NDA). Accordingly, the bottom surface of the conductive layer (200) may be partially exposed in the non-display area (NDA). Therefore, the sealing member (700) that fills the gap space between the display panel (300) and the film member (100) in the non-display area (NDA) may come into direct contact with the bottom surface of the conductive layer (200).

[0143] In the configuration described above, static electricity generated in the film member (100) is transferred to the sealing member (700) along the conductive layer (200) as shown in FIG. 9, and the sealing member (700) transfers the static electricity to the chassis member (500), and the chassis member (500) can discharge the received static electricity. Accordingly, the display device (1) according to one embodiment can protect various elements placed on the display panel (300) from static electricity that may be generated from the film member (100).

[0144] Other embodiments of the display device (1) according to one embodiment will be described below. In the following embodiments, components identical to those in the previously described embodiment will be referred to by the same reference numerals, and redundant descriptions will be omitted or simplified, with the focus on the differences.

[0145] FIG. 10 is a schematic plan view illustrating a chassis member of a display device according to another embodiment. FIG. 11 is a schematic cross-section cut along the line X4-X4' of FIG. 10, specifically a schematic drawing illustrating the appearance of a sealing member of a display device according to the embodiment of FIG. 10.

[0146] Referring to FIGS. 10 and 11, the chassis member (501) of the display device (1_1) according to the present embodiment is exemplified as having a plurality of holes (HA) formed through the chassis member (501), and a sealing member (701) may be interposed through the plurality of holes (HA). In some embodiments, the planar shape of each of the plurality of holes (HA) may have a rectangular shape, but is not limited thereto. For example, the planar shape of each of the plurality of holes (HA) may be circular.

[0147] Specifically, the sealing member (701) according to the present embodiment may include a main part (701a) interposed in the space between the film member (100) and the chassis member (501), and a through part (701b) interposed in the hole (HA) of the chassis member (501). The through part (701b) is fastened to the hole (HA) of the chassis member (501) so that the bonding strength with the chassis member (501) can be further improved.

[0148] As the connection between the sealing member (701) and the chassis member (501) is strengthened in the non-display area (NDA) by the configuration described above, the mechanical stability between the film member (100) and the chassis member (501) can be further improved.

[0149] FIG. 12 is a schematic diagram illustrating the appearance of a sealing member (700) of a display device (1) according to another embodiment.

[0150] Referring to FIG. 12, the display device (1_2) according to the present embodiment differs from the display device (1_1) according to FIG. 11 in that the sealing member (702) penetrates the hole (HA) and can be interposed even to a part of the bottom surface of the chassis member (501), and other configurations are substantially the same or similar.

[0151] Specifically, the sealing member (702) according to the present embodiment may further include a main part (702a) interposed in the spaced-apart space between the film member (100) and the chassis member (501), a through part (702b) interposed in the hole (HA) of the chassis member (501), and a fixing part (702c) extending from the through part (702b) and interposed on the bottom surface of the chassis member (500). The width of the second direction (DR2) of the fixing part (702c) may be greater than the width of the second direction (DR2) of the through part (702b).

[0152] As the connection between the sealing member (702) and the chassis member (501) is strengthened in the non-display area (NDA) by the configuration described above, the mechanical stability between the film member (100) and the chassis member (501) can be further improved.

[0153] FIG. 13 is a schematic plan view illustrating a chassis member of a display device according to another embodiment. FIG. 14 is a schematic cross-section cut along the line X5-X5' of FIG. 13, specifically a schematic drawing illustrating the appearance of a sealing member of a display device according to the embodiment of FIG. 13.

[0154] Referring to FIGS. 13 and 14, the chassis member (503) of the display device (1_3) according to the present embodiment is illustrated as having irregularities formed in a second direction (DR2). Specifically, the chassis member (503) according to the present embodiment may have a structure in which a plurality of contact portions (CT) that are concave in the second direction (DR2) and a plurality of protrusion portions (PT) that protrude in the second direction (DR2) are alternately arranged.

[0155] The sealing member (703) according to the present embodiment can directly contact the upper surface of the chassis member (503) at the protrusion (PT) and directly contact the side of the chassis member (503) in the second direction (DR2) at the contact portion (CT). In other words, the sealing member (703) may include a main portion (703a) that directly contacts the upper surface of the chassis member (503) and a fastening portion (703b) that is fastened to the contact portion (CT) of the chassis member (503) and directly contacts the side of the chassis member (503) in the second direction (DR2). Since protrusions (PT) can be arranged on both sides of the first direction (DR1) of the contact portion (CT), the fastening portion (703b) of the sealing member (703) can be fastened by being surrounded by the protrusions (PT).

[0156] As the connection between the sealing member (703) and the chassis member (503) is strengthened in the non-display area (NDA) by the configuration described above, the mechanical stability between the film member (100) and the chassis member (503) can be further improved.

[0157] FIG. 15 is a schematic diagram illustrating the appearance of a sealing member of a display device according to another embodiment.

[0158] Referring to FIG. 15, the display device (1_4) according to the present embodiment differs from the display device (1_3) according to FIG. 14 in that the sealing member (704) can extend beyond the contact portion (CT) to a portion of the bottom surface of the chassis member (503), and other configurations are substantially the same or similar.

[0159] Specifically, the sealing member (704) according to the present embodiment may further include a main part (704a) that directly contacts the upper surface of the chassis member (503) and a fastening part (704b) that is connected to the contact part (CT) of the chassis member (503) and directly contacts the second direction (DR2) side of the chassis member (503), as well as a fixing part (704c) that is interposed on the lower surface of the chassis member (503) beyond the contact part (CT).

[0160] As the connection between the sealing member (704) and the chassis member (503) is strengthened in the non-display area (NDA) by the configuration described above, the mechanical stability between the film member (100) and the chassis member (503) can be further improved.

[0161] FIG. 16 is a schematic plan view illustrating a chassis member of a display device according to another embodiment.

[0162] Referring to FIG. 16, the chassis member (505) of the display device (1_5) according to the present embodiment is exemplified in that a contact portion (CT5) is formed at the corner of the chassis member (505), and a protrusion (PT5) can be formed between the contact portions.

[0163] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0164] 100: Film absence 200: Conductive layer 300: Display panel 500: Chassis component 700: Sealing member

Claims

Claim 1 A display device comprising: a substrate, a light-emitting element disposed on the upper surface of the substrate, and an overcoat layer disposed on the light-emitting element; a film member disposed on the overcoat layer of the display panel; a conductive layer disposed between the overcoat layer and the film member; a chassis member disposed on the lower surface of the substrate of the display panel; and a sealing member covering the side of the display panel, wherein the sealing member electrically connects the conductive layer and the chassis member, the sealing member comprises a conductive material, the chassis member comprises a conductive metal material, the width of the film member is greater than the width of the display panel and the width of the chassis member, and the width of the chassis member is greater than the width of the display panel. Claim 2 delete Claim 3 delete Claim 4 A display device according to claim 1, wherein the chassis member and the film member are spaced apart from each other with the display panel in between, and the sealing member is interposed in the spaced-out space between the film member and the chassis member. Claim 5 A display device according to claim 4, wherein the bottom surface of the conductive layer is in direct contact with the sealing member, and the top surface of the chassis member is in direct contact with the sealing member. Claim 6 A display device according to claim 5, further comprising an adhesive layer disposed between the conductive layer and the overcoat layer to bond the conductive layer and the overcoat layer, wherein the adhesive layer exposes a portion of the conductive layer and the sealing member is in direct contact with the portion of the conductive layer exposed by the adhesive layer. Claim 7 In claim 6, the conductive layer completely covers the bottom surface of the film member and is a display device comprising a transparent metal oxide. Claim 8 A display device according to claim 6, further comprising a wavelength conversion layer disposed between the overcoat layer and the light-emitting element and a color filter layer disposed between the wavelength conversion layer and the overcoat layer. Claim 9 A display device according to claim 1, further comprising a heat dissipation layer disposed between the chassis member and the substrate. Claim 10 In claim 9, the heat dissipation layer comprises graphite in the display device. Claim 11 In claim 1, the film member comprises a base film and an anti-fingerprint film disposed on the base film, forming a display device. Claim 12 In claim 11, the base film is a display device comprising triacetyl cellulose. Claim 13 A display device comprising: a display panel defining the display area and a non-display area surrounding the display area; a film member disposed on the upper surface of the display panel and having a width greater than that of the display panel; a conductive layer disposed between the display panel and the film member and having a width greater than that of the display panel; a chassis member disposed on the lower surface of the display panel and having a width greater than that of the display panel and smaller than that of the film member; and a sealing member covering the side of the display panel, wherein the chassis member and the film member are spaced apart from each other in the non-display area, and the sealing member is interposed in the spaced-apart space between the chassis member and the film member and is in direct contact with the upper surface of the chassis member. Claim 14 In paragraph 13, the chassis member comprises a conductive metal, the sealing member comprises a conductive material, and the sealing member is a display device in direct contact with the bottom surface of the conductive layer. Claim 15 In claim 14, the display panel comprises a substrate and a light-emitting element disposed on the substrate, and further comprises a heat dissipation layer disposed between the chassis member and the substrate. Claim 16 A display device according to claim 15, further comprising a plurality of flexible printed circuit boards disposed on the substrate of the display panel, wherein one side of each of the plurality of flexible printed circuit boards is disposed on the upper surface of the substrate, and the other side of each of the plurality of flexible printed circuit boards is disposed on the lower surface of the chassis member. Claim 17 In claim 16, a display device in which resin is interposed between the flexible printed circuit board and the substrate. Claim 18 In claim 14, the chassis member includes a hole penetrating the chassis member, and the sealing member is a display device interposed through the hole. Claim 19 In paragraph 18, the sealing member is a marking device that penetrates the hole and covers a portion of the bottom surface of the chassis member. Claim 20 In claim 14, the chassis member has a plurality of contact portions concave toward the inside of the chassis member and a plurality of protrusion portions protruding toward the outside of the chassis member alternately arranged, and the sealing member is fastened to each of the plurality of contact portions and interposed therein, forming a display device.

Images