Memory device and method for determining start point and end point of verification operation of target state during programming

Abstract

A memory device and a programming method thereof are disclosed for determining the start and end points of a verification operation of a target state during programming. In a programming operation of a first page and a second page disposed adjacently at the same height from a substrate within a three-dimensional memory cell array, the programming of the second page is based on a verification offset in which the magnitude of the shift of the threshold voltage dispersion corresponding to the first target state of the first page is divided by the voltage increment of the program voltage, and the program of the second page.

Description

Technology Field

[0001] The present invention relates to semiconductor memory devices, and more specifically, to a memory device and a programming method thereof that determines the starting point of a verification operation related to a target state during programming. Background Technology

[0002] Systems using semiconductor chips widely use Dynamic Random Access Memory (DRAM) as operating memory or main memory to store data or instructions used by a host within the system and / or to perform computational operations, and use storage devices as storage media. Storage devices include non-volatile memory. As the capacity of the storage device increases, the number of memory cells and word lines stacked on the substrate of the non-volatile memory increases, and the number of bits of data stored in the memory cells also increases. To improve the storage capacity and integration density of the memory, non-volatile memory devices that stack memory cells in a three-dimensional structure, such as 3D NAND flash memory devices, are being studied.

[0003] In a 3D NAND flash memory device, multiple program loops may be executed until the program is completed according to Incremental Step Pulse Programming (hereinafter referred to as "ISPP"). As the program loop increases, a program voltage is applied to the memory cell in a series of pulses, and the size of the program pulses increases by a predetermined step size. In the intervals between the program pulses, verification operations (or verification read operations) are performed. That is, verification operations are performed on the data state of the memory cell to determine whether the memory cell has reached a verification level related to its data.

[0004] To increase capacity per unit area, one or more bits may be programmed into a memory cell. Depending on the number of bits stored in the memory cell, the memory cell may be classified as SLC, MLC, TLC, or QLC. Depending on the number of bits stored in the memory cell, the memory cell may have multiple programmed states. Multiple programmed states may be defined by a range of threshold voltages. As multi-level cells (e.g., 4-state MLC, 8-state MLC, 16-state MLC) are employed, the programming time becomes increasingly longer. In particular, the number of verification operations increases in proportion to the number of programmed states, and this verification time accounts for a large proportion of the total programming time. An example in which the number of verification operations increases in proportion to the number of programmed states is described in US Patent 7584391.

[0005] Meanwhile, the ideal data state of programmed multi-level cells should maintain a predetermined voltage interval with adjacent data states so that a sufficient read margin can be secured. However, during the programming operation of multi-level cells, the threshold voltage of each data state may be deformed into a non-ideal form due to the effects of coupling caused by high voltages repeatedly applied to the selected memory cell or adjacent memory cells.

[0006] If verification operations can be omitted until verification start points corresponding to each program state are reached, it would be beneficial to improve program speed and performance by minimizing the number of verification operations. The problem to be solved

[0007] The objective of the present invention is to provide a memory device and a programming method thereof that determine the start and end points of a verification operation related to a target state during programming. means of solving the problem

[0008] A method for programming a memory device according to embodiments of the present invention comprises: using program loops including a program section and a verification section to cause threshold voltages of memory cells formed in three-dimensional arrays of the memory device to have target states, and a step of programming the memory cells of a first word line, wherein the first word line constitutes a first page associated with a first string selection line, and a first program loop count of the first target state associated with the memory cells of the first page being programmed to a first target state is stored; and a step of programming the memory cells of a second word line, wherein the second word line constitutes a second page associated with a second string selection line adjacent to the first string selection line, and the second word line is disposed adjacent to the same position as the first word line from the substrate of the three-dimensional array, and when performing a verification operation to determine whether the memory cells of the second page are programmed to the first target state, the first program loop count of the first target state of the first page is applied as the termination loop of the verification operation.

[0009] A method for programming a memory device according to embodiments of the present invention utilizes program loops including a program section and a verification section to cause threshold voltages of memory cells formed in three-dimensional arrays of the memory device to have target states, and programs the memory cells of a first word line, wherein the first word line constitutes a first page associated with a first string selection line, and stores the number of first program loops of the first target state associated with the memory cells of the first page being programmed into a first target state; The method includes the step of programming the memory cells of the second word line into the first target state, wherein the second word line constitutes a second page associated with the second string selection line adjacent to the first string selection line, and the second word line is positioned at the same location as the first word line from the substrate of the three-dimensional array, and a verification offset is calculated based on the magnitude of the shift of the threshold voltage dispersion corresponding to the first target state of the second page and the voltage increment of the program voltage to be applied in the program loops, and the start loop of the verification operation that determines whether the memory cells of the second page have been programmed into the first target state among the program loops that program the memory cells of the second page into the first target state is adjusted according to the relationship between the first program loop count and the verification offset.

[0010] A memory device according to embodiments of the present invention comprises a memory cell array including memory cells in which 3 bits are programmed per memory cell, wherein the memory cell array is formed as a three-dimensional array of memory cells; and a control circuit that controls a programming operation so that the threshold voltages of the memory cells of a first page and a second page disposed adjacent to the same position as the first page from the substrate of the three-dimensional array have target states. The programming operation is performed by programming loops based on a voltage increment of the programming voltage, and each of the programming loops includes a programming section and a verification section. The control circuit stores the number of programming loops of the first target state associated with the memory cells of the first page being programmed to the first target state, and determines the start loop and end loop of the verification operation among the programming loops based on the number of programming loops of the first target state of the first page and the voltage increment of the programming voltage when programming the memory cells of the second page to the first target state. Effects of the invention

[0011] A memory device according to the present invention can improve program speed and program performance by determining a start loop and an end loop of a verification operation corresponding to each program state based on pass loop information obtained from the previous page program procedure of a selected word line and a minimum number of verifications according to the ISPP of each program state, and by omitting verification operations until reaching the start loop of a verification operation corresponding to a target state. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 2 is a block diagram illustrating a memory device according to embodiments of the present invention. FIG. 3 is a diagram illustrating the structure of a memory device according to embodiments of the present invention. Figure 4 shows an equivalent circuit diagram of the memory block of Figure 2. FIGS. 5a to 5c are drawings for explaining a programming method according to embodiments of the present invention. FIGS. 6a to 7b are drawings for explaining a programming method according to embodiments of the present invention. FIG. 8 is a diagram showing program bias conditions according to embodiments of the present invention. FIGS. 9 and FIGS. 10 are drawings for illustrating a programming method according to embodiments of the present invention. FIGS. 11 and 12 are drawings for illustrating a programming method in which program verification is partially omitted for at least some of the loops among a plurality of program loops according to embodiments of the present invention. FIG. 13 is a drawing illustrating a system to which a memory system according to embodiments of the present invention is applied. Specific details for implementing the invention

[0013] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention.

[0014] Referring to FIG. 1, the memory system (100) may include a memory controller (110) and at least one memory device (120). In this embodiment, a number of conceptual hardware configurations included in the memory system (100) are illustrated, but are not limited thereto and other configurations are also possible. The memory controller (110) may control the memory device (120) to write data to the memory device (120) in response to a write request from a host, or control the memory device (120) to read data stored in the memory device (120) in response to a read request from a host.

[0015] In some embodiments, the memory system (100) may be an internal memory embedded in an electronic device. For example, the memory system (100) may be an embedded Universal Flash Storage (UFS) memory device, an embedded Multi-Media Card (eMMC), or a Solid State Drive (SSD). In some embodiments, the memory system (100) may be an external memory that is removable from the electronic device. For example, the memory system (100) may include at least one of a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), Extreme Digital (xD), and Memory Stick.

[0016] The memory device (120) can perform erase, program, or read operations, etc., under the control of the memory controller (110). The memory device (120) receives a command (CMD) and an address (ADDR) from the memory controller (110) through an input / output line, and transmits and receives data (DATA) for a program operation or a read operation with the memory controller (110). Additionally, the memory device (120) can receive a control signal (CTRL) through a control line. The memory device (120) may include a memory cell array (122) and a control circuit (124).

[0017] The memory cell array (122) includes a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the present invention will be described in detail with the example of the case where the plurality of memory cells are NAND flash memory cells. The memory cell array (122) may include a three-dimensional memory cell array including a plurality of cell strings, and this will be described in detail with reference to FIGS. 3 and FIGS. 4.

[0018] A three-dimensional memory cell array is monolithically formed at at least one physical level of memory cell arrays having an active region disposed on a silicon substrate and a circuit formed on or within the substrate as a circuit related to the operation of memory cells. The term "monolithic" means that the layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array. In one embodiment according to the technical concept of the present invention, the three-dimensional memory cell array includes cell strings arranged vertically such that at least one memory cell is positioned on top of another memory cell. The at least one memory cell may include a charge trap layer. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 describe suitable configurations for a three-dimensional memory array in which the three-dimensional memory array is composed of multiple levels and word lines and / or bit lines are shared between the levels, and are incorporated herein by reference.

[0019] The control circuit (124) may include a register (128) and a verification offset calculation unit (129). The control circuit (124) may control the program operation so that the threshold voltages of memory cells of a first page and a second page, which are placed adjacently at the same location on the substrate of the three-dimensional memory cell array (122), have a plurality of target states. The program operation is performed by program loops based on the voltage increment of the program voltage, and each of the program loops may include a program section and a verification section.

[0020] The control circuit (124) can store in the register (128) the number of program loops of the first target state associated with the memory cells of the first page being programmed into, for example, the first target state. The control circuit (124) can calculate a verification offset based on the magnitude of the shift of the threshold voltage spread corresponding to the first target state of the second page and the voltage increment of the program voltage to be applied in the program loops using the verification offset calculation unit (129).

[0021] The control circuit (124) can determine the start loop and end loop of the verification operation among the program loops based on the number of program loops of the first target state of the first page and the voltage increase of the program voltage when programming the memory cells of the second page to the first target state.

[0022] When the control circuit (124) programs the memory cells of the second page into a first target state, it may apply the number of program loops of the first target state of the first page stored in the register (128) as the termination loop of the verification operation of the first target state of the second page. When the control circuit (124) programs the memory cells of the second page into a first target state, it may apply the lowest program loop of the program loops corresponding to the number of verification offsets among the program loops prior to the termination loop of the verification operation as the start loop of the verification operation. The control circuit (124) may perform the verification operation of the first target state of the second page from the start loop of the verification operation until it reaches the termination loop of the verification operation. The control circuit (124) may omit the verification operation of the first target state of the second page among the program loops prior to the termination loop of the verification operation until it reaches the start loop of the verification operation.

[0023] FIG. 2 is a block diagram illustrating a memory device according to embodiments of the present invention.

[0024] Referring to FIGS. 1 and 2, the memory device (120) may include a memory cell array (122), a row decoder (394), a control circuit (124), a page buffer section (393), an input / output circuit section (126), and a voltage generation section (127). Although not illustrated, the memory device (120) may further include an input / output interface.

[0025] The memory cell array (122) can be connected to word lines (WL), string select lines (SSL), ground select lines (GSL), and bit lines (BL). The memory cell array (122) can be connected to a row decoder (394) via the word lines (WL), string select lines (SSL), and ground select lines (GSL), and can be connected to a page buffer (393) via the bit lines (BL). The memory cell array (122) may include a plurality of memory blocks (BLK1 to BLKn).

[0026] Each memory block (BLK1 to BLKn) may include a plurality of memory cells and a plurality of select transistors. The memory cells may be connected to word lines (WL), and the select transistors may be connected to string select lines (SSL) or ground select lines (GSL). The memory cells of each memory block (BLK1 to BLKn) may be composed of single-level cells that store 1-bit data or multi-level cells that store M-bit data (where M is an integer greater than or equal to 2).

[0027] The row decoder (394) can select one of the multiple memory blocks (BLK1 to BLKn) of the memory cell array (122), select one of the word lines (WL) of the selected memory block, and select one of the multiple string selection lines (SSL).

[0028] The control circuit (124) can output various internal control signals to perform programming, reading, and erasing operations on the memory cell array (122) based on the command (CMD), address (ADDR), and control signal (CTRL) transmitted from the memory controller (110). The control circuit (124) can provide a row address (R_ADDR) to the row decoder (394), provide a column address to the input / output circuit unit (126), and provide a voltage control signal (CTRL_VOL) to the voltage generation unit (127).

[0029] The control circuit (124) can control the program operation so that the threshold voltages of the memory cells of the first page (or previous page) and the second page (or next page), which are positioned adjacently at the same height from the substrate within the memory cell array (122), have a plurality of target states.

[0030] The control circuit (124) can store in a register (128) the number of program loops of the first target state associated with the memory cells of the previous page being programmed into, for example, the first target state. The control circuit (124) can calculate a verification offset based on the magnitude of the shift of the threshold voltage spread corresponding to the first target state of the next page and the voltage increment of the program voltage to be applied in the program loops using a verification offset calculation unit (129). When programming the memory cells of the next page into the first target state, the control circuit (124) can determine the start loop and end loop of the verification operation among the program loops based on the number of program loops of the first target state of the previous page and the voltage increment of the program voltage of the next page.

[0031] When the control circuit (124) programs the memory cells of the next page into a first target state, it may apply the number of program loops of the first target state of the previous page stored in the register (128) as the termination loop of the verification operation of the first target state of the next page. When the control circuit (124) programs the memory cells of the next page into a first target state, it may apply the lowest program loop of the program loops corresponding to the number of verification offsets among the program loops prior to the termination loop of the verification operation as the start loop of the verification operation. The control circuit (124) may perform the verification operation of the first target state of the next page from the start loop of the verification operation until it reaches the termination loop of the verification operation. The control circuit (124) may omit the verification operation of the first target state of the next page among the program loops prior to the termination loop of the verification operation until it reaches the start loop of the verification operation.

[0032] The page buffer unit (393) can operate as a write driver or a sense amplifier depending on the operation mode. During a read operation, the page buffer unit (393) can sense the bit line (BL) of a selected memory cell under the control of the control circuit (124). The sensed data can be stored in latches provided inside the page buffer unit (393). The page buffer unit (393) can dump the data stored in the latches to the input / output circuit unit (126) through the data line (DL) under the control of the control circuit (124).

[0033] The input / output circuit section (126) can temporarily store a command (CMD), an address (ADDR), and data (DATA) provided from outside the non-volatile memory device (120) through an input / output line (I / O). The input / output circuit section (126) can temporarily store read data of the non-volatile memory device (120) and output it to the outside through an input / output line (I / O) at a designated time.

[0034] The voltage generation unit (127) can generate various types of voltages to perform program, read, and erase operations on the memory cell array (122) based on the voltage control signal (CTRL_VOL). Specifically, the voltage generation unit (127) can generate wordline voltages (VWL), for example, program voltage, verification voltage, read voltage, pass voltage, erase voltage, erase verification voltage, etc.

[0035] FIG. 3 is a diagram illustrating the structure of a memory device according to embodiments of the present invention.

[0036] Referring to FIG. 3, the memory device (120) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell region (CELL) on a first wafer, fabricating a lower chip containing a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0037] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (120) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0038] The peripheral circuit region (PERI) may include a first substrate (210), an interlayer insulating layer (215), a plurality of circuit elements (220a, 220b, 220c) formed on the first substrate (210), a first metal layer (230a, 230b, 230c) connected to each of the plurality of circuit elements (220a, 220b, 220c), and a second metal layer (240a, 240b, 240c) formed on the first metal layer (230a, 230b, 230c). In one embodiment, the first metal layer (230a, 230b, 230c) may be formed of tungsten, which has a relatively high electrical resistivity, and the second metal layer (240a, 240b, 240c) may be formed of copper, which has a relatively low electrical resistivity.

[0039] In this specification, only the first metal layer (230a, 230b, 230c) and the second metal layer (240a, 240b, 240c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (240a, 240b, 240c). At least some of the one or more metal layers formed on the upper part of the second metal layer (240a, 240b, 240c) may be formed of aluminum or the like, having an electrical resistivity lower than that of copper forming the second metal layer (240a, 240b, 240c).

[0040] The interlayer insulating layer (215) is disposed on a first substrate (210) to cover a plurality of circuit elements (220a, 220b, 220c), a first metal layer (230a, 230b, 230c), and a second metal layer (240a, 240b, 240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0041] A lower bonding metal (271b, 272b) may be formed on the second metal layer (240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (271b, 272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (371b, 372b) of the cell region (CELL) by a bonding method, and the lower bonding metal (271b, 272b) and the upper bonding metal (371b, 372b) may be formed of aluminum, copper, or tungsten, etc.

[0042] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (310) and a common source line (320). On the second substrate (310), a plurality of word lines (331-338; 330) may be stacked along a direction perpendicular to the upper surface of the second substrate (310) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (330), respectively, and a plurality of word lines (330) may be disposed between the string selection lines and the ground selection lines.

[0043] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (310) (Z-axis direction) and penetrate word lines (330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (350c) and a second metal layer (360c). For example, the first metal layer (350c) may be a bitline contact, and the second metal layer (360c) may be a bitline. In one embodiment, the bitline (360c) may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (310).

[0044] In one embodiment illustrated in FIG. 3, the area where the channel structure (CH) and bit line (360c) are placed may be defined as a bit line bonding area (BLBA). The bit line (360c) may be electrically connected to circuit elements (220c) that provide a page buffer section (393) in the peripheral circuit area (PERI) in the bit line bonding area (BLBA). For example, the bit line (360c) may be connected to an upper bonding metal (371c, 372c) in the peripheral circuit area (PERI), and the upper bonding metal (371c, 372c) may be connected to a lower bonding metal (271c, 272c) that is connected to the circuit elements (220c) of the page buffer section (393).

[0045] In the wordline bonding area (WLBA), wordlines (330) may be extended along a second direction (X-axis direction) perpendicular to the first direction and parallel to the upper surface of the second substrate (310), and may be connected to a plurality of cell contact plugs (341-347; 340). The wordlines (330) and the cell contact plugs (340) may be connected to each other at pads provided by extending at least some of the wordlines (330) along the second direction at different lengths. A first metal layer (350b) and a second metal layer (360b) may be connected in sequence to the upper portion of the cell contact plugs (340) connected to the wordlines (330). The cell contact plugs (340) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (371b, 372b) of the cell area (CELL) and the lower bonding metal (271b, 272b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0046] Cell contact plugs (340) may be electrically connected to circuit elements (220b) that provide a row decoder (394) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (220b) forming the row decoder (394) may be different from the operating voltage of the circuit elements (220c) forming the page buffer section (393). For example, the operating voltage of the circuit elements (220c) forming the page buffer section (393) may be greater than the operating voltage of the circuit elements (220b) forming the row decoder (394).

[0047] A common source line contact plug (380) may be disposed in the external pad bonding area (PA). The common source line contact plug (380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to the common source line (320). A first metal layer (350a) and a second metal layer (360a) may be sequentially laminated on top of the common source line contact plug (380). For example, the area where the common source line contact plug (380), the first metal layer (350a), and the second metal layer (360a) are disposed may be defined as the external pad bonding area (PA).

[0048] Meanwhile, input / output pads (205, 305) may be disposed in the external pad bonding area (PA). Referring to FIG. 3, a lower insulating film (201) covering the lower surface of the first substrate (210) may be formed on the lower surface of the first substrate (210), and a first input / output pad (205) may be formed on the lower insulating film (201). The first input / output pad (205) is connected to at least one of a plurality of circuit elements (220a, 220b, 220c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (203), and may be separated from the first substrate (210) by the lower insulating film (201). Additionally, a side insulating film is disposed between the first input / output contact plug (203) and the first substrate (210) to electrically separate the first input / output contact plug (203) and the first substrate (210).

[0049] In FIG. 3, an upper insulating film (301) covering the upper surface of the second substrate (310) may be formed on the upper surface of the second substrate (310), and a second input / output pad (305) may be disposed on the upper insulating film (301). The second input / output pad (305) may be connected to at least one of a plurality of circuit elements (220a, 220b, 220c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (303). In one embodiment, the second input / output pad (305) may be electrically connected to the circuit element (220a).

[0050] According to the embodiments, the second substrate (310) and common source line (320), etc., may not be placed in the area where the second input / output contact plug (303) is placed. Additionally, the second input / output pad (305) may not overlap with the word lines (330) in the third direction (Z-axis direction). Referring to FIG. 3, the second input / output contact plug (303) is separated from the second substrate (310) in a direction parallel to the upper surface of the second substrate (310) and may be connected to the second input / output pad (305) by penetrating the interlayer insulating layer (315) of the cell area (CELL).

[0051] According to embodiments, the first input / output pad (205) and the second input / output pad (305) may be formed optionally. For example, the memory device (120) may include only the first input / output pad (205) disposed on the upper part of the first substrate (210), or only the second input / output pad (305) disposed on the upper part of the second substrate (310). Alternatively, the memory device (120) may include both the first input / output pad (205) and the second input / output pad (305).

[0052] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0053] The memory device (120) may form a lower metal pattern (273a) of the same shape as the upper metal pattern (372a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (372a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (273a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern (372a) of the same shape as the lower metal pattern (273a) of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern (273a) formed on the upper metal layer of the peripheral circuit region (PERI).

[0054] A lower bonding metal (271b, 272b) may be formed on the second metal layer (240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (271b, 272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (371b, 372b) of the cell region (CELL) by a bonding method.

[0055] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (392) of the same shape as the lower metal pattern (252) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (252) formed on the upper metal layer of the peripheral circuit area (PERI). A contact may not be formed on the upper metal pattern (392) formed on the upper metal layer of the cell area (CELL).

[0056] FIG. 4 shows an equivalent circuit diagram of the memory block of FIG. 2. The memory block illustrated in FIG. 4 is an example of one of the plurality of memory blocks (BLK1 to BLKn) described with reference to FIG. 2, and shows a first memory block (BLK1). Hereinafter, embodiments of the present invention will be described in detail using the first memory block (BLK1) as an example. The first memory block (BLK1) represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. A plurality of memory cell strings included in the first memory block (BLK1) may be formed in a direction perpendicular to the substrate.

[0057] Referring to FIG. 4, the first memory block (BLK1) may include NAND strings (NS11–NS33), word lines (WL1–WL8), bit lines (BL1–BL3), ground select lines (GSL1–GSL3), string select lines (SSL1–SSL3), and a common source line (CSL). FIG. 4 is illustrated such that each of the cell strings (NS11–NS33) includes eight memory cells (MCs) connected to eight word lines (WL1–WL8), but the present invention is not limited thereto.

[0058] Each cell string (e.g., NS11) may include a string select transistor (SST), a plurality of memory cells (MC), and a ground select transistor (GST) connected in series. The string select transistor (SST) is connected to a corresponding string select line (SSL1). The plurality of memory cells (MC) are each connected to a corresponding word line (WL1–WL8). The ground select transistor (GST) is connected to a corresponding ground select line (GSL1). The string select transistor (SST) is connected to a corresponding bit line (BL1–BL3), and the ground select transistor (GST) is connected to a common source line (CSL).

[0059] According to an embodiment, in each cell string, one or more dummy memory cells may be provided between the string select transistor (SST) and the memory cells (MC). In each cell string, one or more dummy memory cells may be provided between the ground select transistor (GST) and the memory cells (MC). In each cell string, one or more dummy memory cells may be provided between the memory cells (MC). The dummy memory cells have the same structure as the memory cells (MC) and may not be programmed (e.g., programmed forbidden) or may be programmed differently from the memory cells (MC). For example, when the memory cells (MC) are programmed to have two or more threshold voltage spreads, the dummy memory cells may be programmed to have one threshold voltage spread range or fewer threshold voltage spreads than the memory cells (MC).

[0060] FIGS. 5a through 5c are drawings illustrating a programming method according to embodiments of the present invention. Before the description, let us assume that a memory device according to an exemplary embodiment of the present invention stores 3-bit data per memory cell and performs a programming operation according to a 2-step programming method. A programming method according to the 2-step programming method will be described below.

[0061] First, the first page data will be stored simultaneously in the memory cells of the selected word line. As shown in FIG. 5a, the memory cells belonging to the threshold voltage range corresponding to the erase state (E) will be programmed to have threshold voltages belonging to the threshold voltage ranges corresponding to the program state (Q1) according to the data to be programmed.

[0062] Next, 2-page data, that is, the second and third page data, will be stored simultaneously in the memory cells of the selected word line. As shown in FIG. 5b, memory cells belonging to the threshold voltage range corresponding to the erase state (E) will be programmed to have threshold voltages belonging to threshold voltage ranges corresponding to the respective program states (P1'3') according to the data to be programmed. Memory cells belonging to the threshold voltage range corresponding to the program state (Q1) of FIG. 5a will be programmed to have threshold voltages belonging to the respective program voltage ranges corresponding to the respective program states (P4'*?*) according to the data to be programmed.

[0063] Here, the verification voltages (VP1'–VP7') used to determine the threshold voltage spreads (P1'–P7') are lower than the verification voltages (VP1–VP7) used to determine the final threshold voltage spreads (P1–P7) (see FIG. 5c). For example, the verification voltage (VP1') used to determine the threshold voltage spread (P1') is lower than the verification voltage (VP1) used to determine the corresponding final threshold voltage spread (P1). The operation of programming memory cells to have the threshold voltage spreads shown in FIG. 5b is called a coarse program operation, and memory cells belonging to the threshold voltage spreads (P1'–P7') are programmed to have the final threshold voltage spreads (P1–P7). This operation is called a fine program operation (or reprogram operation).

[0064] The programming methods described in FIGS. 5a, 5b, and 5c, respectively, will include verification operations to determine whether memory cells are programmed to have threshold voltages of desired threshold voltage spreads. This will be described in detail below.

[0065] FIGS. 6a to 7b are drawings illustrating a programming method according to embodiments of the present invention. FIGS. 6a and 7a show examples of the occurrence of a programming voltage (Vpgm) applied in each program loop according to an ISPP programming scheme. FIG. 6a illustrates a case where a first voltage increment (△V1) is applied to each program loop according to an ISPP programming scheme, and FIG. 7a illustrates an exemplary case where a second voltage increment (△V2) greater than the first voltage increment (△V1) is applied to each program loop. FIGS. 6b and 7b show threshold voltage dispersions according to the ISPP programming scheme of FIGS. 6a and 7a.

[0066] Referring to FIGS. 6a and 6b, memory cells can be programmed from a first threshold voltage spread (20) to a second threshold voltage spread (30) by a plurality of step pulse voltages having a first voltage increment (△V1). The shift in threshold voltage induced by each step pulse voltage can be performed by FN tunneling in the case of NAND flash memory. By providing a pulse voltage that increases by a constant amount equal to the first voltage increment (△V1) to the word line of the selected memory cells, the spread of the memory cells moves sequentially in the order 20->21->22->23->24->25->26-> ... -> 30. Ideally, the threshold voltage spread of the cells finally formed after the program ends will maintain reference number 30.

[0067] Referring to FIGS. 7a and 7b, memory cells can be programmed from a third threshold voltage spread (70) by a plurality of step pulse voltages having a second voltage increment (△V2) to move to a fourth threshold voltage spread (80). By providing a pulse voltage that increases by a constant amount equal to the second voltage increment (△V2) to the word line of the selected memory cells, the spread of memory cells moves sequentially in the order 70->71->72->73-> ... ->80. Ideally, the threshold voltage spread of the cells finally formed after the program ends will maintain reference number 80.

[0068] Referring to FIGS. 6b and FIGS. 7b, the second voltage increment (△V2) used to generate multiple step pulse voltages is greater than the first voltage increment (△V1). Therefore, the voltage shift in each program loop when the second voltage increment (△V2) is applied is greater than the voltage shift when the first voltage increment (△V1) is applied. On the other hand, for the same voltage shift, the number of program loops required when the second voltage increment (△V2) is applied is less than the number of program loops required when the first voltage increment (△V1) is applied.

[0069] Here, a small number of required program loops means that the program is fast because the number of program repetitions is small. Conversely, a large number of required program loops means that the program is slow because the number of program repetitions is large.

[0070] According to an exemplary embodiment, the programming method described in FIGS. 6a and 6b may be applied when programming memory cells belonging to a threshold voltage spread corresponding to the erase state (E) described in FIGS. 5a through 5c into program states (P1' to P3'). That is, it may be applied when programming memory cells with a relatively slow programming speed. For example, the threshold voltage spread (20) in FIG. 6b represents the shift size of the P2' threshold voltage spread, and the threshold voltage spread (30) may correspond to the P2 threshold voltage spread after programming. The value (W1 / △V1) obtained by dividing the window size (W1) of the P2' threshold voltage spread by the first voltage increment (△V1) may be determined as the minimum number of verification operations. In FIG. 6b, at least six verification operations may be required to determine whether the P2 threshold voltage spread has been programmed to have threshold voltages.

[0071] According to an exemplary embodiment, the programming method described in FIGS. 7a and 7b may be applied when programming memory cells belonging to a threshold voltage spread corresponding to the programming state (Q1) described in FIGS. 5a through 5c into programming states (P4' to P7'). That is, it may be applied when programming memory cells with a relatively fast programming speed. For example, the threshold voltage spread (70) in FIG. 7b represents the shift size of the P7' threshold voltage spread, and the threshold voltage spread (30) may correspond to the P7 threshold voltage spread after programming. The value (W2 / △V2) obtained by dividing the window size (W2) of the P7' threshold voltage spread by the second voltage increment may be determined as the minimum number of verification operations. In FIG. 7b, at least three verification operations may be required to determine whether the P7 threshold voltage spread has been programmed to have threshold voltages.

[0072] Meanwhile, when memory cells belonging to the threshold voltage spread corresponding to the erase state (E) described in FIGS. 5a to 5c are programmed into program states (P1' to P3'), the magnitude of the shift in the threshold voltage spread may vary. The magnitude of the shift in the threshold voltage spread is smallest when moving from the erase state (E) to the data state of P1', and the magnitude of the shift in the threshold voltage spread is largest when moving to the data state of P3'. At this time, the degree of threshold voltage variation that may occur will be greatest in the data state of P3' and smallest in the data state of P1'.

[0073] Likewise, when memory cells belonging to the threshold voltage spread corresponding to the Q1 data state described in FIGS. 5a to 5c are programmed into program states (P4' to P7'), the magnitude of the shift in the threshold voltage spread may vary. The magnitude of the shift in the threshold voltage spread is smallest when moving from the Q1 data state to the P4' data state, and the magnitude of the shift in the threshold voltage spread is largest when moving to the P7' data state. The degree of threshold voltage variation that may occur at this time will be greatest in the P7' data state and smallest in the P4' data state.

[0074] The minimum number of verifications for program states (P1–P7) may vary depending on the magnitude of the shift in the threshold voltage spread described in FIGS. 6b and 7b, the voltage increment of the program voltage to be applied in each program loop, and the degree of variation of the threshold voltage. This difference in the number of verifications may be referred to as a verification offset. For example, the P2 threshold voltage spread may have a verification offset of 7, as shown in FIG. 10, and the P7 threshold voltage spread may have a verification offset of 6.

[0075] During the program operation described in FIGS. 5a through 7b, the verification start point (or verification start loop) of the program state may be determined according to the verification offset for the program states (P1*) and / or the number of program loops required by the program. The number of program loops required by the program may be determined by pass loop information obtained from the previous page program procedure of the selected word line. As the verification start loop is determined, the program verification prior to the verification start loop for the program loops of the program states (P1*) may be partially omitted.

[0076] FIG. 8 is a diagram showing program bias conditions according to embodiments of the present invention. For convenience, FIG. 8 illustrates cell strings (NS11, NS21) connected to the first bit line (BL1) and cell strings (NS12, NS22) connected to the second bit line (BL2) among the cell strings (NS11~NS33, FIG. 4) of the first memory block (BLK1).

[0077] Referring to FIG. 8, the first bit line (BL1) is a program-allowed bit line to which a relatively low program-allowed voltage (VPER, FIG. 9), for example, ground voltage (VSS), is applied, and the second bit line (BL2) is a program-unallowed bit line to which a relatively high program-unallowed voltage (VINH, FIG. 9), for example, power supply voltage (VDD), is applied.

[0078] Assuming that the NS21 cell string is selected among the cell strings (NS11, NS21) connected to the first bit line (BL1), during the program operation (PROGRAM, FIG. 9), a turn-off voltage at the ground voltage (VSS) level is applied to the first string selection line (SSL1) connected to the NS11 cell string, and a turn-on voltage, such as a power supply voltage (VDD), greater than or equal to the threshold voltage (Vth) of each string selection transistor (SST), can be applied to the second string selection line (SSL2) connected to the NS21 cell string.

[0079] A turn-off voltage at the ground voltage (VSS) level is applied to the first and second ground select lines (GSL1, GSL2). A third precharge voltage (VPC, FIG. 9) higher than the ground voltage (VSS) may be applied to the source line (CSL). A program voltage (VPGM, FIG. 9) (e.g., 18 V) is applied to the select word line (e.g., WL3), and a pass voltage (VPASS1, FIG. 9) (e.g., 8 V) is applied to the non-select word line (e.g., WL2, WL4).

[0080] Under these program bias conditions, 18V is applied to the gate of memory cell (A) and the channel voltage is 0V. Since a strong electric field is formed between the gate and the channel of memory cell (A), memory cell (A) is programmed. Meanwhile, the channel voltage of memory cell (B) is the power supply voltage (VDD) and since a weak electric field is formed between the gate and the channel of memory cell (B), memory cell (B) is not programmed. Since the channels of memory cells (C, D) are in a floating state, the channel voltage rises to a boosting level by the pass voltage (VPASS1), and memory cells (C, D) are not programmed.

[0081] FIGS. 9 and FIGS. 10 are drawings for illustrating a programming method according to embodiments of the present invention. FIG. 9 may be used interchangeably with respect to a memory cell (A) programmed in the NS21 cell string of FIG. 8, where the selected word line (WLs) refers to the WL3 word line, the unselected word lines (WLu) refer to the WL2 and WL4 word lines, the selected string selection line (SSL) refers to the SSL2 string selection line, the unselected string selection line (SSL) refers to the SSL1 string selection line, the selected ground selection line (GSL) refers to the GSL2 ground selection line, the unselected ground selection line (GSL) refers to the GSL1 ground selection line, the program allow bit line (BL) refers to the BL1 bit line, and the program prohibit bit line (BL) refers to the BL2 bit line.

[0082] Referring to FIG. 9, for memory cells connected to selected word lines (WLs), a plurality of program loops (LOOP1, LOOP2, LOOP3, ) can be sequentially executed according to ISPP until programming is completed. As the program loops are repeated, the program voltages (VPGM1, VPGM2, VPGM3, ) can be increased stepwise. Each program loop (LOOPi, i is a natural number) may include a program section (PROGRAM) that applies a program voltage (VPGM) to the selected word lines (WLs) to program the selected memory cells, and a verification section (VERIFY) that applies a verification voltage (VVFY) to the selected word lines (WLs) to verify whether programming is successful.

[0083] The program section (PRGOGRAM) may include a channel precharge and bitline setup section (PBLS), a string select line setup section (PSSLS), a program execution section (PEXE), and a program recovery section (PRCV).

[0084] The channel precharge and bitline setup section (PBLS) can perform initialization or precharge (hereinafter referred to as USIP (Unselect String Initial Precharge)) operations on the channels of multiple cell strings before the program loop by utilizing the Gate Induced Drain Leakage (GIDL) phenomenon. In the channel precharge and bitline setup section (PBLS), a power supply voltage (VDD), which is a program-prohibition voltage (VINH), may be applied to the program-prohibition bitline (BL), and a ground voltage (VSS), which is a program-prohibition voltage level, may be applied to the program-enabled bitline (BL). A first turn-on voltage (VSSL1) may be applied to the select string select line (SSL), and a turn-off voltage, i.e., a ground voltage (VSS), may be applied to the non-select string select line (SSL). A turn-on voltage (VGSL) may be applied to the ground select lines (GSL), and a power supply voltage (VDD) may be applied to the source line (CSL) as a precharge voltage. The channels of multiple cell strings may be initialized according to a GIDL phenomenon induced through a select string select transistor (SST) connected to a select string select line (SSL), and may be initialized according to a GIDL phenomenon induced through a ground select transistor (GST) connected to the ground select lines (GSL).

[0085] The string select line setup section (PSSLS) may maintain a first turn-on voltage (VSSL1) on the selected string select line (SSL), apply a turn-off voltage to the unselected string select lines (SSL), and apply a ground voltage (VSS) to the source line (CSL) and ground select lines (GSL). The program execution section (PEXE) may apply a program pass voltage to the selected word line (WLs) and unselected word lines (WLu), and after a certain period of time has elapsed, apply a program voltage (VPGM) to the selected word line (WLs). The program recovery section (PRCV) may recover the bit lines (BL), string select lines (SSL), selected word line (WLs), and unselected word line (WLu) to the ground voltage (VSS).

[0086] The verification section (VERIFY) may include a verification read section (RD) and a read recovery section (RRCV). The verification read section (RD) may apply a read pass voltage (VPASS2) to the non-selected word line (WLu) so that the memory cell can always be turned on regardless of the program state of the memory cell, apply a verification voltage (VVFY) to the selected word line (WLs), apply a turn-on voltage (NGSL) to the selected ground select line (GSL), and apply a turn-off voltage, i.e., a ground voltage (VSS), to the non-selected ground select line (GSL). The read recovery section (RRCV) may recover the bit lines (BL), string select lines (SSL), selected word line (WLs), and non-selected word line (WLu) to the ground voltage (VSS).

[0087] As a result of the program operation for memory cells connected to a WL3 word line connected to an SSL2 selection string line performed by the program methods described in FIG. 5a to 9, pass loop information to program states (P1-7) can be obtained as shown in FIG. 10. For example, to explain a program method in which program verification is partially omitted for program loops for memory cells connected to a WL3 word line connected to an SSL3 selection string line of FIG. 4, the programmed WL3 word line of the SSL2 string selection line is referred to as the previous page, and the WL3 word line to be programmed of the SSL3 string selection line is referred to as the next page.

[0088] Referring to FIG. 10, in the program operation of the previous page, the program would have been passed after 10 program loops were executed to obtain the P1 program state. The P2 program state would have been passed after 12 program loops, the P3 program state after 13 program loops, the P4 program state after 15 program loops, the P5 program state after 16 program loops, the P6 program state after 18 program loops, and the P7 program state after 20 program loops. Each pass loop of the program states (P1*) can be stored in the register (128) of the control circuit (124). The control circuit (124) can determine the number of pass loops of each program state (P1*) of the previous page stored in the register (128) as the end loop of the verification operation that determines whether each program state (P1*) of the next page is programmed.

[0089] By the verification offset calculation unit (129) of the control circuit (124), the P2 threshold voltage spread in the program operation of the next page may have 7 verification offsets. Each of the P3 and P4 threshold voltage spreads may be calculated to have 7 verification offsets, and each of the P5 to P7 threshold voltage spreads may have 6 verification offsets.

[0090] The control circuit (124) can skip program verification for the beginning of program loops corresponding to the value obtained by subtracting the verification offset calculated by the verification offset calculation unit (129) from the number of pass loops of the previous page (P1) stored in the register (128). For example, in the case of the P2 program state, program verification can be skipped for 5 program loops (LOOP1, LOOP2, , LOOP5), which is the value obtained by subtracting the verification offset 7 from the number of pass loops of the previous page 12. Accordingly, program verification can be performed in program loops 6, 7, 8, 9, 10, 11, 12 (LOOP6, LOOP7, LOOP8, LOOP9, LOOP10, LOOP11, LOOP12).

[0091] For example, in the case of the P3 program state, program verification can be omitted in 6 program loops (LOOP1, LOOP2, , LOOP6) starting from the program start loop (LOOP1), which is the value of 6 minus the verification offset 7 from the pass loop count 13 of the previous page. Accordingly, program verification can be performed in program loops 7, 8, 9, 10, 11, 12, and 13 (LOOP7, LOOP8, LOOP9, LOOP10, LOOP11, LOOP12, LOOP13). Likewise, in the case of the P7 program state, program verification can be omitted in 14 program loops (LOOP1, LOOP2, , LOOP14) starting from the program start loop (LOOP1), which is the value of 14 minus the verification offset 6 from the pass loop count 20 of the previous page. Accordingly, program verification can be performed in program loops 15, 16, 17, 18, 19, and 20 (LOOP15, LOOP16, LOOP17, LOOP18, LOOP19, LOOP20).

[0092] FIGS. 11 and 12 are drawings for illustrating a programming method in which program verification is partially omitted for at least some of the loops among a plurality of program loops according to embodiments of the present invention.

[0093] Referring to FIGS. 10 and 11, a method for programming to the target program state (P2) for the next page is shown. For example, when programming to the target program state (P2), the 12-pass loop information of the previous page may be applied as the end point of the program operation or the end program loop. Then, according to the ISPP program scheme, a first voltage increment (△V1) is applied to each program loop, and a minimum verification count or verification offset 7, calculated by dividing the shift size of the P2 threshold voltage spread by the first voltage increment (△V1), may be applied.

[0094] Program verification can be omitted in 5 program loops (LOOP1, LOOP2, LOOP5) starting from the program start loop (LOOP1), which is the value of 5 minus the verification offset 7 from the 12 end program loops applied to programming to the target program state (P2). Program verification for the target program state (P2) can be performed in 7 program loops corresponding to the number of verification offsets among the 12 end program loops, namely program loops 6, 7, 8, 9, 10, 11, and 12 (LOOP6, LOOP7, LOOP8, LOOP9, LOOP10, LOOP11, LOOP12). In the 7 program loops (LOOP6, LOOP7, LOOP8, LOOP9, LOOP10, LOOP11, LOOP12), a verification voltage (VP2) can be applied to verify whether programming to the target program state (P2) is successful.

[0095] Referring to FIGS. 10 and 12, a method for programming to the target program state (P7) for the next page is shown. For example, when programming to the target program state (P7), the 20-pass loop information of the previous page may be applied as the end point of the program operation or the end program loop. Then, according to the ISPP program scheme, a second voltage increment (△V2) may be applied to each program loop, and a minimum verification count or verification offset 6 may be applied, which is calculated by dividing the shift size of the P7 threshold voltage spread by the second voltage increment (△V2).

[0096] Program verification can be omitted in 14 program loops (LOOP1, LOOP2, LOOP14) starting from the program start loop (LOOP1), which is the value of 14, obtained by subtracting the verification offset 6 from the 20 end program loops applied to programming to the target program state (P7). Program verification for the target program state (P7) can be performed in 6 program loops corresponding to the number of verification offsets among the 20 end program loops, namely 15, 16, 17, 18, 19, and 20 program loops (LOOP15, LOOP16, LOOP17, LOOP18, LOOP19, LOOP20). In the 6 program loops (LOOP15, LOOP16, LOOP17, LOOP18, LOOP19, LOOP20), a verification voltage (VP7) can be applied to verify whether programming to the target program state (P7) is successful.

[0097] FIG. 13 is a drawing illustrating a system to which a memory system according to embodiments of the present invention is applied. The system (1000) of FIG. 13 may basically be a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IoT (Internet of Things) device. However, the system (1000) of FIG. 13 is not necessarily limited to a mobile system and may be an automotive device such as a personal computer, a laptop computer, a server, a media player, or a navigation system.

[0098] Referring to FIG. 13, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0099] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0100] The main processor (1100) may include one or more CPU cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator block (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator block (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0101] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0102] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a memory controller (1310a, 1310b) and a non-volatile memory (NVM) device (1320a, 1320b) that stores data under the control of the memory controller (1310a, 1310b). The NVM device (1320a, 1320b) may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0103] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a memory card and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as UFS (universal flash storage) are applied, but it is not necessarily limited thereto.

[0104] The storage device (1300a, 1300b) may include the memory system (100) described in FIGS. 1 to 12. The memory controller (1310a, 1310b) corresponds to the memory controller (110), and the NVM device (1320a, 1320b) may correspond to the memory device (120). The NVM device (1320a, 1320b) includes a control circuit that controls the operation modes of the NVM device (1320a, 1320b), and the control circuit may control the programming operation so that the threshold voltages of the memory cells of the next page to be programmed have a plurality of target states using a programmed previous page that is placed adjacent to the same height from the substrate in the three-dimensional memory cell array. The control circuit can store the number of program loops of the first target state associated with the memory cells of the previous page being programmed into, for example, the first target state, and calculate the verification offset of the next page based on the magnitude of the shift of the threshold voltage spread corresponding to the first target state of the next page and the voltage increment of the program voltage to be applied in the program loops. When programming the memory cells of the next page into the first target state, the control circuit can determine the start loop and end loop of the verification operation among the program loops based on the number of program loops of the first target state of the previous page and the voltage increment of the program voltage of the next page.

[0105] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0106] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, keypad, keyboard, mouse and / or microphone, etc.

[0107] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope, etc.

[0108] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0109] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0110] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0111] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0112] Although the present invention has been described in relation to a limited number of embodiments illustrated in the drawings, this is merely illustrative and those skilled in the art will recognize that various modifications and variations and equivalent other embodiments are possible therefrom. Accordingly, the appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

Claim 1 A method for programming a memory device, wherein program loops including a program section and a verification section are used to cause threshold voltages of memory cells formed in three-dimensional arrays of the memory device to have target states, and a step of programming the memory cells of a first word line, wherein the first word line constitutes a first page associated with a first string selection line, and a first program loop count of the first target state associated with the memory cells of the first page being programmed to a first target state is stored; and a step of programming the memory cells of a second word line, wherein the second word line constitutes a second page associated with a second string selection line adjacent to the first string selection line, and the second word line is disposed adjacent to the same position as the first word line from the substrate of the three-dimensional array, and when performing a verification operation to determine whether the memory cells of the second page are programmed to the first target state, the first program loop count of the first target state of the first page is applied as the termination loop of the verification operation;and includes the step of calculating a verification offset by dividing the voltage increment of the program voltage to be applied in the program loops by the shift size of the threshold voltage spread corresponding to the first target state of the second page, and applying the lowest program loop of the program loops corresponding to the number of verification offsets among the program loops prior to the termination loop of the verification operation as the start loop of the verification operation, and the step of programming the memory cells of the first and second word lines programs first to third data constituting 3 bits per memory cell according to a 2-step programming method, and by the first step program, memory cells belonging to the threshold voltage spread corresponding to the erase state are programmed to have threshold voltages belonging to threshold voltage spreads corresponding to the first program state according to the first data to be programmed, and by the second step program, memory cells belonging to the threshold voltage spread corresponding to the erase state are programmed to have threshold voltages belonging to threshold voltage spreads corresponding to the second to fourth program states respectively according to the second and third data to be programmed, and memory cells belonging to the threshold voltage spread corresponding to the first program state A method programmed to have threshold voltages belonging to threshold voltage dispersions corresponding to each of the 5th to 8th programmed states according to the second and third data to be programmed.; Claim 2 delete Claim 3 In claim 1, the verification operation of the first target state of the second page is performed from the start loop of the verification operation until the end loop of the verification operation is reached. Claim 4 A method in which, in the first paragraph, the verification operation of the first target state of the second page is omitted until the start loop of the verification operation is reached among the program loops prior to the end loop of the verification operation. Claim 5 A method according to claim 1, wherein the third word line constitutes a third page adjacent to the first word line and associated with the first string selection line, and the second program loop count of the first target state associated with the memory cells of the third page being programmed to the first target state is stored; and the fourth word line constitutes a fourth page associated with the second string selection line, the second word line is placed at the same location as the third word line from the substrate of the three-dimensional array, and when performing a verification operation to determine whether the memory cells of the fourth page are programmed to the first target state, the second program loop count of the first target state of the third page is applied as the termination loop of the verification operation. Claim 6 In paragraph 5, the method wherein the termination loop of the verification operation on page 2 and the termination loop of the verification operation on page 4 are set differently from each other. Claim 7 delete Claim 8 A method for programming a memory device comprises using program loops including a program section and a verification section to cause threshold voltages of memory cells formed of three-dimensional arrays of the memory device to have target states, and a step of programming the memory cells of a first word line, wherein the first word line constitutes a first page associated with a first string selection line, and a first program loop count of the first target state associated with the memory cells of the first page being programmed to a first target state is stored;The method includes the step of programming the memory cells of the second word line into the first target state, wherein the second word line constitutes a second page associated with a second string selection line adjacent to the first string selection line, the second word line is positioned at the same location as the first word line on the substrate of the three-dimensional array, and a verification offset is calculated based on the magnitude of shift of the threshold voltage spread corresponding to the first target state of the second page and the voltage increment of the program voltage to be applied in the program loops, and among the program loops that program the memory cells of the second page into the first target state, a verification operation start loop that determines whether the memory cells are programmed into the first target state is adjusted according to the relationship between the number of first program loops and the verification offset, and the step of programming the memory cells of the first and second word lines programs first to third data constituting three bits per memory cell according to a 2-step programming method, and according to the first data to which memory cells belonging to the threshold voltage spread corresponding to the erase state are programmed by the first step programming A method in which a memory cell belonging to a threshold voltage dispersion corresponding to a program state is programmed to have threshold voltages belonging to threshold voltage dispersions corresponding to the second to fourth program states, respectively, according to the second and third data to be programmed by a second step program, and a memory cell belonging to a threshold voltage dispersion corresponding to the first program state is programmed to have threshold voltages belonging to threshold voltage dispersions corresponding to the fifth to eighth program states, respectively, according to the second and third data to be programmed. Claim 9 A memory cell array comprising memory cells in which 3 bits are programmed per memory cell, wherein the memory cell array is formed as a three-dimensional array of the memory cells; The control circuit includes a first page and a second page disposed adjacent to the same position as the first page on the substrate of the three-dimensional array, and controls a program operation so that the threshold voltages of the memory cells have target states, wherein the program operation is performed by program loops based on a voltage increment of the program voltage, and each of the program loops includes a program section and a verification section, wherein the control circuit stores the number of program loops of the first target state associated with the memory cells of the first page being programmed to the first target state, and determines the start loop and end loop of the verification operation among the program loops based on the number of program loops of the first target state of the first page and the voltage increment of the program voltage when programming the memory cells of the second page to the first target state, and the control circuit calculates a verification offset by dividing the voltage increment of the program voltage to be applied in the program loops by the magnitude of the shift of the threshold voltage dispersion corresponding to the first target state of the second page, and among the program loops prior to the end loop of the verification operation, the lowest program loop of the program loops corresponding to the number of verification offsets is the Applying as a start loop for a verification operation, the control circuit programs first to third data constituting the three bits per memory cell according to a 2-step programming method, and by the first step program, memory cells belonging to a threshold voltage range corresponding to an erase state are programmed to have threshold voltages belonging to threshold voltage ranges corresponding to the first program state according to the first data to be programmed, and by the second step program,A memory device in which memory cells belonging to a threshold voltage dispersion corresponding to the erase state are programmed to have threshold voltages belonging to threshold voltage dispersions corresponding to the second to fourth program states, respectively, according to the second and third data to be programmed, and memory cells belonging to a threshold voltage dispersion corresponding to the first program state are programmed to have threshold voltages belonging to threshold voltage dispersions corresponding to the fifth to eighth program states, respectively, according to the second and third data to be programmed. Claim 10 delete

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