Memory device and method for controlling row hammer

Abstract

A row hammer control method and a memory device are disclosed. The memory device includes a memory cell array comprising a plurality of counter memory cells that store a word line and an access count value of the word line, and a control logic circuit that monitors a row address accessing the word line during a row hammer monitoring time frame and determines the row address as a row hammer address and stores it in an address storage unit when the number of accesses to the word line is greater than or equal to a threshold. The control logic circuit holds a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit.

Description

Technology Field

[0001] The present invention relates to semiconductor memory devices, and more specifically, to a memory device and a method of operation thereof that controls a row hammer so that row hammer address information is not evicted by holding the next row hammer address determination operation until the row hammer address is targeted refreshed. Background Technology

[0002] Systems using semiconductor chips widely utilize Dynamic Random Access Memory (DRAM) as operational memory or main memory to store data or instructions used by a host within the system and / or to perform computational operations. Generally, DRAM writes data or reads out written data under the control of the host. When performing computational operations, the host retrieves instructions and / or data from DRAM and uses the data to execute instructions and / or perform computational operations. If the result of a computational operation exists, the host writes the result back to the DRAM. Accordingly, the host may require the Reliability, Availability, and Serviceability (RAS) features of the DRAM chips.

[0003] DRAM cell sizes are decreasing to increase DRAM capacity and density. Some DRAM-based systems occasionally experience intermittent failures due to heavy workloads. These failures are traced to repetitive access to a single memory cell row, also known as row hammer. Repetitive access to a specific row can cause an increased rate of decay in adjacent rows (e.g., victim rows) due to electromagnetic coupling between rows. Additionally, memory cells connected to the victim rows may become disturbed, leading to data corruption where memory cell data is flipped.

[0004] To control the row hammer, the DRAM can monitor the row hammer address(s) that are intensively accessed among the access addresses for a certain period of time. The DRAM stores the row hammer address(s) in a limited register(s) of the address storage unit, generates hammer refresh address(s) representing the addresses of memory cell row(s) that are physically adjacent to the memory cell row(s) corresponding to the row hammer address(s), and can target refresh the memory cells connected to the victim memory cell row corresponding to the hammer refresh address.

[0005] However, generally, DRAM uses a limited number of register(s) (or latches) to control row hammer, and the number of row hammer address(s) is determined by the number of historical accesses over a certain period of time, and furthermore, can be determined by the number of register(s) storing the accesses. As a new row hammer address is stored in a register(s), the row hammer address(s) previously stored in the register(s) are evicted from the register(s), and the monitored row hammer address may become missing. There is a problem in that victim rows adjacent to the missing row hammer address may decay faster than the timing of the auto-refresh operation, making them vulnerable to row hammer.

[0006] Accordingly, in order to satisfy the RAS expectation, a memory device and a method of operation thereof are required to control so that the row hammer information is not evicted until the memory cell row associated with the row hammer information is targeted refreshed. The problem to be solved

[0007] The objective of the present invention is to provide a memory device and a method of operation thereof that controls a row hammer so that row hammer address information is not evicted by holding the next row hammer address determination operation until the row hammer address is targeted refreshed. means of solving the problem

[0008] A memory device according to embodiments of the present invention comprises a memory cell array including a word line and a plurality of counter memory cells, wherein the plurality of counter memory cells store an access count value of the word line; and a control logic circuit that monitors a row address accessing the word line during a row hammer monitoring time frame, and determines the row address as a row hammer address and stores it in an address storage unit when the number of accesses to the word line is greater than or equal to a threshold. The control logic circuit holds a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit.

[0009] A control logic circuit according to embodiments of the present invention comprises: a counter that counts the number of accesses of a row address accessed during a row hammer monitoring time frame; the counter reads the access count value of a word line from a plurality of counter memory cells connected to a word line accessed by the row address, increases the read access count value by +1 and outputs the output value of the counter as the number of accesses of the row address; a comparator that determines whether the row address is a row hammer address by comparing the output value of the counter with a threshold value; and a latch circuit that stores the row address in an address storage unit based on the determination of the comparator and activates a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit, and is configured such that the output value of the counter associated with the next row address is not provided to the comparator by the activated latch pull signal.

[0010] A method of operating a memory device comprising a plurality of memory cell rows according to embodiments of the present invention comprises: monitoring a row address that accesses a word line during a row hammer monitoring time frame; determining the row address as a row hammer address when the number of accesses to the word line is greater than or equal to a threshold; storing the row hammer address in an address storage unit; activating a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit; and holding a determination operation for the next row hammer address based on the activation of the latch pull signal. Effects of the invention

[0011] A memory device according to the present invention can provide an enhanced RAS function by preventing the row hammer address from being evicted from registers by holding the next row hammer address determination operation until the row hammer address is targeted refreshed. Brief explanation of the drawing

[0012] FIG. 1 is a drawing illustrating a system including a memory device for controlling a row hammer according to exemplary embodiments of the present invention. FIGS. 2 and FIGS. 3 are block diagrams illustrating a memory device according to embodiments of the present invention. Figure 4 is a diagram illustrating the refresh operation of the memory device of Figure 2. FIG. 5 is a block diagram illustrating a row hammer control circuit according to embodiments of the present invention. FIG. 6 is a diagram illustrating a row hammer control operation according to embodiments of the present invention. FIG. 7 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIG. 8 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIG. 9 is a drawing illustrating a memory device for controlling a row hammer according to an exemplary embodiment of the present invention. FIG. 10 is a block diagram showing a system including a memory device for controlling a row hammer according to embodiments of the present invention. Specific details for implementing the invention

[0013] FIG. 1 is a diagram illustrating a system including a memory device for controlling a row hammer according to exemplary embodiments of the present invention.

[0014] Referring to FIG. 1, the system (100) may include a host device (110) and a memory device (120). The host device (110) may be communicatively connected to the memory device (120) through a memory bus (130).

[0015] The host device (110) may be, for example, a computing system such as a computer, laptop, server, workstation, portable communication terminal, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), smartphone, or wearable device. Or the host device (110) may be some of the components included in a computing system such as a graphics card.

[0016] The host device (110) is a functional block that performs general computer operations within the system (100) and may correspond to a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), or an Application Processor (AP). The host device (110) may include a memory controller (112) that controls the transmission and reception of data to and from a memory device (120).

[0017] A memory controller (112) can access a memory device (120) in response to a memory request from a host device (110). The memory controller (112) may include a Memory Physical Layer Interface (Memory PHY) for interfacing with the memory device (120), such as selecting rows and columns corresponding to memory locations, writing data to memory locations, or reading written data. The Memory PHY may include physical or electrical layers and logical layers provided for signals, frequencies, timings, drives, detailed operation parameters, and functionality required for efficient communication between the memory controller (112) and the memory device (120). The Memory PHY may support features of the DDR and / or LPDDR protocols of the JEDEC (Joint Electron Device Engineering Council) standard.

[0018] A memory controller (112) and a memory device (120) can be connected via a memory bus (130). For the sake of brevity in the drawing, the clock (CK), command / address (CA), and data (DQ) are each shown as being provided through a single signal line between the memory controller (112) and the memory device (120) on the memory bus (130), but in reality, they may be provided through multiple signal lines or buses. The signal lines between the memory controller (112) and the memory device (120) may be connected via connectors. The connectors may be implemented as pins, balls, signal lines, or other hardware components.

[0019] A clock (CK) signal can be transmitted from the memory controller (112) to the memory device (120) through the clock signal line of the memory bus (130). A command / address (CA) signal can be transmitted from the memory controller (112) to the memory device (120) through the command / address (CA) bus of the memory bus (130). A chip select (CS) signal can be transmitted from the memory controller (112) to the memory device (120) through the chip select (CS) line of the memory bus (130). For example, a signal transmitted through the command / address (CA) bus while the chip select (CS) signal is activated to logic high can indicate that it is a command. Data (DQ) can be transmitted from the memory controller (112) to the memory device (120) or from the memory device (120) to the memory controller (112) through a data (DQ) bus composed of bidirectional signal lines of the memory bus (130).

[0020] The memory device (120) can write data (DQ), read data (DQ), and perform refresh operations under the control of the memory controller (112). For example, the memory device (120) may be a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) device. However, the scope of the present invention is not limited thereto, and the memory device (120) may be any one of volatile memory devices such as LPDDR (Low Power Double Data Rate) SDRAM, Wide I / O DRAM, HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), etc. The memory device (120) may include a memory cell array (200) and a low hammer control circuit (210).

[0021] The memory cell array (200) may include a plurality of word lines and a plurality of bit lines, and a plurality of memory cells formed at the intersection of the word lines and bit lines. The memory cells of the memory cell array (200) may be volatile memory cells, for example, DRAM cells.

[0022] The memory cell array (200) may include counter memory cells (202) connected to each word line. The counter memory cells (202) may store the number of accesses to the corresponding word line. The row hammer control circuit (210) monitors a row address accessing a word line during a row hammer monitoring time frame, and when the number of accesses to the word line is above a threshold, it may determine the row address as a row hammer address and store it in an address storage unit. The row hammer control circuit (210) may hold a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit. Accordingly, the memory device (120) may provide an enhanced RAS function by preventing the row hammer address stored in the address storage unit from being evicted until a normal refresh and / or target refresh occurs, and by defending against row hammer attacks.

[0023] FIGS. 2 and FIGS. 3 are block diagrams illustrating a memory device according to embodiments of the present invention. FIG. 2 shows the memory device (120) of FIG. 1 implemented as a DRAM, and FIG. 3 shows the memory cell array (200) of FIG. 2. FIG. 3 is a diagram illustrating the refresh operation of the memory device of FIG. 2. It should be noted that the DRAM configuration shown in FIG. 2 is provided as an example and is not necessarily an actual DRAM configuration. Furthermore, the exemplary DRAM configuration shown in FIG. 2 does not imply or represent any limitation to the present disclosure.

[0024] Referring to FIGS. 1 and 2, the memory device (120) may include a memory cell array (200), a row decoder (204), a column decoder (206), an input / output gating circuit (208), a control logic circuit (220), an address buffer (230), a refresh control circuit (240), and an input / output circuit (250). Although not shown in FIG. 2, the memory device (120) may further include a clock buffer, a mode register set (MRS), bank control logic, a voltage generation circuit, etc.

[0025] The address buffer (230) can receive an address (ADDR) including a bank address, a row address (ROW_ADDR), and a column address (COL_ADDR) from the memory controller (112). The address buffer (230) can provide the received bank address to the bank control logic, provide the received row address (ROW_ADDR) to the row decoder (204), and provide the received column address (COL_ADDR) to the column decoder (206).

[0026] A memory cell array (200) includes a plurality of memory cells provided in the form of a matrix arranged in rows and columns. The memory cell array (200) includes a plurality of word lines (WL) and a plurality of bit lines (BL) connected to the memory cells. The plurality of word lines (WL) may be connected to the rows of the memory cells, and the plurality of bit lines (BL) may be connected to the columns of the memory cells. Data of the memory cells connected to the active word lines (WL) may be sensed and amplified by sense amplifiers connected to the bit lines (BL).

[0027] The memory cell array (200) may include first to fourth banks (BANK1 to BANK4). Bank control logic generates bank control signals in response to a bank address, and in response to the bank control signals, the row decoder (204) and column decoder (206) of the bank corresponding to the bank address among the first to fourth banks (BANK1 to BANK4) may be activated. Although an example of a memory device (120) including four banks is illustrated in this embodiment, depending on the embodiment, the memory device (120) may include any number of banks.

[0028] A row decoder (204) and a column decoder (206) are arranged corresponding to each of the first to fourth banks (BANK1~BANK4), and a row decoder (204) and a column decoder (206) connected to a bank corresponding to a bank address can be activated. The row decoder (204) can decode a row address (ROW_ADDR) received from an address buffer (230), select a word line (WL) corresponding to the row address (ROW_ADDR) among a plurality of word lines (WL), and connect to a word line driver that activates the selected word line (WL).

[0029] The column decoder (206) can select certain bit lines (BL) among a plurality of bit lines (BL) of the memory cell array (200). The column decoder (206) can generate a column selection signal by decoding a burst address that is incrementally increased by +1 based on the column address (COL_ADDR) in burst mode, and can connect the bit lines (BL) selected by the column selection signal to the input / output gating circuit (208). The burst address refers to the addresses of column locations that can be accessed in relation to the burst length (BL) for a read and / or write command.

[0030] The input / output gating circuit (208) may include read data latches that store read data of bit lines (BL) selected by a column selection signal, and a write driver for writing write data to the memory cell array (200). The input / output circuit (250) may include a data input buffer (260) and a data output buffer (270). Read data stored in the read data latches of the input / output gating circuit (208) may be provided to the data (DQ) bus through the data output buffer (270). Write data may be written to the memory cell array (200) through the data input buffer (260) connected to the data (DQ) bus and through the write driver of the input / output gating circuit (208).

[0031] The control logic circuit (220) can receive a clock (CK) signal and a command (CMD) and generate control signals to control the operation timing and / or memory operation of the memory device (120). The control logic circuit (220) can provide control signals to the circuits of the memory device (120) to operate as set in the operation and control parameters stored by the MRS. The control logic circuit (220) can use the control signals to read data from the memory cell array (200) and write data to the memory cell array (200). Although the control logic circuit (220) and the address buffer (230) are shown as separate components in FIG. 2, the control logic circuit (220) and the address buffer (230) may be implemented as an inseparable single component. Additionally, although FIG. 2 shows that the command (CMD) and address (ADDR) are provided as separate signals, the address can be considered to be included in the command, as presented in LPDDR standards, etc.

[0032] Among the first to fourth banks (BANK1~BANK4) of the memory cell array (200), the first bank (BANK1) is shown as a representative example in FIG. 3. Referring to FIG. 3, the first bank (BANK1) may include a plurality of word lines (WL1~WLm) and bit lines (BL1~BLn, BLx~BLz). In the first bank (BANK1), a plurality of memory cells (MC) may be located at the point where the word lines (WL1~WLm) and bit lines (BL1~BLn, BLx~BLz) intersect. In the first bank (BANK1), the memory cells (MC) connected to each word line (WL1~WLm) may be divided into first memory cells (201) and second memory cells (202).

[0033] The first memory cells (201) connected to each word line (WL1~WLm) and bit line (BL1~BLn) are memory cells that store data and may be referred to as data cells. The second memory cells (202) connected to each word line (WL1~WLm) and bit line (BLx~BLz) are memory cells that store the number of accesses of the corresponding word lines (WL1~WLm) and may include counter memory cells (C31, C32, C33, C3m). For convenience of explanation, the first memory cells (201) may be used interchangeably as data cells, and the second memory cells (202) may be used interchangeably as counter memory cells.

[0034] For example, the first counter memory cells (C31) connected to the first word line (WL1) can store the number of accesses that activate the memory cell row of the first word line (WL1). The second counter memory cells (C32) connected to the second word line (WL2) can store the number of accesses that activate the memory cell row of the second word line (WL2), and the third counter memory cells (C33) connected to the third word line (WL3) can store the number of accesses that activate the memory cell row of the third word line (WL3). Likewise, the m-th counter memory cells (C3m) can store the number of accesses that activate the memory cell row of the m-th word line (WLm).

[0035] Counter memory cells (C31, C32, C33, C3n) may be repeated in each of the second to fourth banks (BANK2~BANK4) of the memory cell array (200). The number and location of the counter memory cells (C31, C32, C33, C3n) may be reconfigured according to the maximum number of accesses expected by the memory controller (112). According to an embodiment, there may be between 8 and 24 counter memory cells along each word line. For example, the counter memory cells may be composed of 8, 12, 16, or 24. In other examples, more or fewer counter memory cells may be used.

[0036] In FIG. 2, the control logic circuit (220) can count the number of accesses for each of the memory cell rows in the memory cell array (200) and store the counted number of accesses in counter memory cells (202) connected to word lines. The control logic circuit (220) may include a row hammer control circuit (210) that determines the number of accesses of the memory cell rows that is greater than or equal to a threshold and identifies the memory cell row having the number of accesses greater than or equal to the threshold as a row hammer risk row.

[0037] A row hammer control circuit (210) may be configured to monitor row hammer for memory cell rows having access counts exceeding a threshold within a memory cell array (200) and to detect row hammer for a specific memory cell row. A specific memory cell row refers to a memory cell row having access counts exceeding a threshold during a predetermined time interval. The predetermined time interval may be set to a refresh window time (tREFw) of 32ms or 64ms defined in the JEDEC standard, as shown in FIG. 4. According to an embodiment, the predetermined time interval may be set to the default refresh rate time (tREFi) of FIG. 4. The default refresh rate is defined, for example, as the number of refresh commands (REFRESH) of about 8K within a 32ms refresh window. The predetermined time interval may be referred to as a row hammer monitor time frame or time window set by a memory controller (112).

[0038] According to an embodiment, the row hammer control circuit (210) may transmit information about the detected row hammer risk row to the memory controller (112). The memory controller (112) may issue a normal refresh command based on the row hammer risk row information. The memory controller (112) may transmit address signals of memory cell row(s) physically adjacent to the row hammer risk row to the memory device (120) along with the refresh command. The memory device (120) may refresh the memory cell row(s) physically adjacent to the row hammer risk row according to the normal refresh command.

[0039] According to an embodiment, the row hammer control circuit (210) may be configured to target refresh a memory cell row physically adjacent to a row hammer risk row. The row hammer control circuit (210) is a general term for a method of implementing hardware, firmware, software, or a combination thereof for controlling or managing a row hammer. In the following embodiments, the row hammer control circuit (210) will be described as controlling a row hammer that is accessed above a threshold during a row hammer monitoring time frame, but the embodiments of the present invention are not limited thereto. For example, the row hammer control circuit (210) may correspond to a configuration provided within a control logic circuit (220), and it may be described as the control logic circuit (220) controlling the row hammer.

[0040] The control logic circuit (220) can control the refresh control circuit (240) to perform a normal refresh operation by increasing the refresh counter value by +1 in response to a refresh command (CMD). Additionally, the control logic circuit (220) can control the refresh control circuit (240) to perform a target row refresh operation based on row hammer address(s) (RH_ADDR). The refresh control circuit (240) can generate a refresh address (REF_ADDR) corresponding to the memory cell row where the normal refresh operation and / or target row refresh operation will be performed.

[0041] FIG. 5 is a block diagram illustrating a row hammer control circuit according to embodiments of the present invention.

[0042] Referring to FIG. 5, the row hammer control circuit (210) may include a counter (510), a logic circuit (520), a comparator (530), a pulse generator (540), a latch circuit (550), and a row hammer address generator (560).

[0043] The counter (510), logic circuit (520), and comparator (530) can operate together to determine whether the number of accesses to a memory cell row associated with a row address (ROW_ADDR) applied together with an active command (ACT) is greater than or equal to a threshold (THRESHOLD). When a word line (WL) corresponding to the row address (ROW_ADDR) is accessed, the access count value (CNT) stored in the counter memory cells (202) connected to the word line (WL) can be read out to the counter (510). The access count value (CNT) stored in the counter memory cells (202) can be understood as the number of accesses to the word line (WL) corresponding to the row address (ROW_ADDR). The counter (510) can increase the read access count value (CNT) by +1 in consideration of the currently applied active command (ACT), and store the increased access count value (CNT+1) in the counter memory cells (202) connected to the word line (WL). Additionally, the counter (510) can output the increased access count value (CNT+1) as the output (XOUT) signal of the counter (510).

[0044] Meanwhile, the counter (510) can reset the output (XOUT) of the counter (510) to a zero (0) value by a reset signal (RST). The reset signal (RST) line of the counter (510) can be connected to the output (CO) signal line of the comparator (530). The comparator (530) can output a logic high-level output (CO) when the increased access count value (CNT+1) output from the counter (510), received through the logic circuit (520), is greater than or equal to a threshold (THRESHOLD). As the logic high-level output (CO) signal of the comparator (530) is provided as the reset signal (RST) of the counter (510), the output (XOUT) of the counter (510) can be reset to a zero (0) value.

[0045] The logic circuit (520) may include a first input (L1) that inputs the output (XOUT) signal of the counter (510), a second input (L2) that inputs the latch pull signal (LFULL) of the latch circuit (550), and an output (LO). The logic circuit (520) may be implemented as an AND gate. When the latch pull signal (LFULL) of the second input (L2) signal is at a logic low level, the logic circuit (520) may output the counter (510) output (XCNT) signal of the first input (L1) signal as an output (LO) signal. When the latch pull signal (LFULL) of the second input (L2) is at a logic high level, the logic circuit (520) may output a logic low level output (LO) signal. A latch pull signal (LFULL) is provided by a latch circuit (550). When the address storage unit (552) included in the latch circuit (550) is full and there is no empty space, the latch pull signal (LFULL) can be provided at a logic high level. By the logic high level latch pull signal (LFULL), the logic circuit (520) can block the counter (510) output (XCNT) signal from being provided to the comparator (530).

[0046] The comparison unit (530) may include a first input (C1) for inputting a threshold (THRESHOLD), a second input (C2) for inputting an output (LO) of a logic circuit (520), and an output (CO). The threshold (THRESHOLD) may be set by the memory controller (112) as a low hammer judgment criterion and provided from the MRS. The comparison unit (530) may compare the logic circuit (520) output (LO) signal of the second input (C2) signal with the threshold (THRESHOLD) of the first input (C1). When the counter (510) output (XCNT) signal having an increased access count value (CNT+1) output from the counter (510) is input as the second input (C2) signal, the comparison unit (530) may compare the increased access count value (CNT+1) with the threshold (THRESHOLD).

[0047] The pulse generator (540) may include an input (PIN) and an output (POUT) that input the output (CO) signal of the comparator (530). The pulse generator (540) may selectively output a pulse-shaped output (POUT) signal depending on the logic level of the output (CO) signal of the comparator (530). For example, the pulse generator (540) may output a pulse-shaped output (POUT) signal when the output (CO) signal of the comparator (530) is at a logic high level. When the output (CO) signal of the comparator (530) is at a logic low level, the output (POUT) signal of the pulse generator (540) may be output at a logic low level.

[0048] For example, when the comparison unit (530) compares the threshold (THRESHOLD) of the first input (C1) signal with the increased access count value (CNT+1) of the second input (C2) signal, and the increased access count value (CNT+1) is smaller than the threshold (THRESHOLD), the comparison unit (530) can output a logic low-level output (CO) signal. The logic low-level output (CO) signal of the comparison unit (530) can be provided to the pulse generator (540) and the counter (510). Depending on the logic low-level output (CO) signal of the comparison unit (530), the pulse generator (540) can output a logic low-level output (POUT) signal. Also, the logic low-level output (CO) signal of the comparison unit (530) is provided as a reset signal (RST) of the counter (510), which acts as an inactive signal for the reset operation of the counter (510). Accordingly, the counter (510) can continue counting operations without being reset by a logic low-level reset signal (RST). The counter (510) can read an access counter value (CNT) associated with the next active command (ACT) and the next row address (ROW_ADDR) from the counter memory cells (202), increase the read access counter value (CNT) by +1, store the increased access counter value (CNT+1) in the counter memory cells (202) connected to the word line (WL) corresponding to the next row address (ROW_ADDR), and provide the increased access counter value (CNT+1) to the logic circuit (520) as an output (XCNT) signal.

[0049] For example, when the comparison unit (530) compares the threshold (THRESHOLD) of the first input (C1) signal with the increased access count value (CNT+1) of the second input (C2) signal, and the increased access count value (CNT+1) is greater than or equal to the threshold (THRESHOLD), the comparison unit (530) can output a logic high-level output (CO) signal. The logic high-level output (CO) signal of the comparison unit (530) can be provided to the pulse generator (540) and the counter (510). The pulse generator (540) can output a pulse-shaped output (POUT) signal in response to the logic high-level output (CO) signal of the comparison unit (530). And, the logic high-level output (CO) signal of the comparator (530) is provided as a reset signal (RST) of the counter (510) and acts as an active signal for the reset operation of the counter (510) to reset the output (XOUT) of the counter (510) to a zero (0) value.

[0050] The latch circuit (550) and the row hammer address generator (560) can operate together to store a row address (ROW_ADDR) having an access count greater than or equal to a threshold (THRESHOLD), and to normal refresh and / or target row refresh as the stored row address (ROW_ADDR). The latch circuit (550) can store the row address (ROW_ADDR) in the address storage unit (552), and if there is no empty space in the address storage unit (552), it can activate the latch pull signal (LFULL) to a logic high level. The latch pull signal (LFULL) can be deactivated to a logic low level when the row address (ROW_ADDR) stored in the address storage unit (552) is transmitted to the row hammer address generator (560) in response to a refresh signal (REFRESH). The row hammer address generation unit (560) can provide the received row address (ROW_ADDR) to the refresh control circuit (240, FIG. 2) as the row hammer address (RH_ADDR) to enable normal refresh and / or target row refresh.

[0051] The latch circuit (550) includes a first input (EN) for inputting an output (POUT) signal of the pulse generator (540), a second input (LIN) for inputting a row address (ROW_ADDR) signal, and an output (LOUT), and can output a latch pull signal (LFULL) indicating that the address storage unit (552) within the latch circuit (550) is full. The latch circuit (550) can be enabled when the output (POUT) signal of the pulse generator (540) applied to the first input (EN) is applied in the form of a pulse. When the output (POUT) signal of the pulse generator (540) is applied at a logic low level, the latch circuit (550) is in a disabled state.

[0052] When a pulse-shaped output (POUT) signal of a pulse generator (540) is applied as a first input, the latch circuit (550) can store a row address (ROW_ADDR) input as a second input (LIN) signal in an address storage unit (552). The pulse-shaped output (POUT) signal of the pulse generator (540) indicates that the number of accesses to the row address (ROW_ADDR) corresponding to the active command (ACT) is greater than or equal to a threshold (THRESHOLD), and this row address (ROW_ADDR) corresponds to a row hammer address.

[0053] The latch circuit (550) can store a row address (ROW_ADDR) in the latch of the address storage unit (552) in response to a pulse-shaped pulse generator (540) output (POUT) signal and output a latch pull signal (LFULL) at a logic high level indicating that the address storage unit (552) is full. The logic high level latch pull signal (LFULL) can be provided to the logic circuit (520) to block the counter (510) output (XCNT) signal from being provided to the comparator (530). In this embodiment, the address storage unit (552) of the latch circuit (550) is described as including one latch. According to the embodiment, the address storage unit (552) of the latch circuit (550) may be configured to include two or more latches.

[0054] The latch circuit (550) can output a row address (ROW_ADDR) signal stored in the address storage unit (552) as an output (LOUT) signal. The output (LOUT) of the latch circuit (550) can be provided to the row hammer address generator (560). The row hammer address generator (560) may include a first input (EN) that inputs a refresh signal (REFRESH), a second input (D) that inputs the output (LOUT) signal of the latch circuit (550), and an output (O). The row hammer address generator (560) is enabled when a refresh signal (REFRESH) is applied to the first input (EN), and can output a row address (ROW_ADDR) signal stored in the address storage unit (552), which is the output (LOUT) signal of the latch circuit (550) of the second input (D), as an output (O) signal. The row hammer address generation unit (560) can output the row address (ROW_ADDR) signal stored in the address storage unit (552) as the row hammer address (RH_ADDR) signal in response to a refresh signal (REFRESH).

[0055] A row hammer address (RH_ADDR) is provided to a refresh control circuit (240), and the refresh control circuit (240) can generate a refresh address (REF_ADDR) based on the row hammer address (RH_ADDR). The refresh address (REF_ADDR) may refer to a memory cell row on which a normal refresh operation and / or a target row refresh operation is to be performed.

[0056] FIG. 6 is a diagram illustrating a row hammer control operation according to embodiments of the present invention.

[0057] Referring to FIGS. 2, 5, and 6, a row address (ROW_ADDR) may be applied to the memory device (120) along with an active command (ACT) at time T1. For convenience of explanation, the active command (ACT) applied along with the row address (ROW_ADDR) 300h at time T1 is referred to as the first active command (ACT1), the active command (ACT) applied along with the row address (ROW_ADDR) 300h at time T3 is referred to as the second active command (ACT2), and the active command (ACT) applied along with the row address (ROW_ADDR) 200h at time T6 is referred to as the third active command (ACT3). Furthermore, it is assumed that the threshold (THRESHOLD) applied to the first input (C1) of the comparator (530) is set to 200h, i.e., 512.

[0058] From time T1 to time T2, a row address (ROW_ADDR) 300h can be applied along with a first active command (ACT1). The counter (510) can read out an access count value (CNT) stored in counter memory cells (202) connected to a word line (WL) corresponding to the row address (ROW_ADDR) 300h of the memory cell array (200), and provide a counter (510) output (XCNT) value, e.g. 1FFh, i.e. 511, which is the value of the read access count value (CNT) increased by +1, to the second input (C2) of the comparator (530). Additionally, the counter (510) can store the counter (510) output (XCNT) value 1FFh, i.e. 511, in the counter memory cells (202) connected to a word line (WL) corresponding to the row address (ROW_ADDR) 300h. The comparator (530) can compare the threshold value (THRESHOLD) 200h of the first input (C1), i.e., 512, with the counter (510) output (XCNT) value 1FFh of the second input (C2), i.e., 511, and output a logic low-level output (CO) signal. Accordingly, the pulse generator (540) outputs a logic low-level output (POUT) signal, and the latch circuit (550) can output a logic low-level latch pull signal (LFULL).

[0059] From time T3 to time T5, a row address (ROW_ADDR) 300h can be applied along with a second active command (ACT2). At time T3, the counter (510) can read out an access count value (CNT) 1FFh, i.e., 511, stored in counter memory cells (202) connected to a word line (WL) corresponding to the row address (ROW_ADDR) 300h of the memory cell array (200), and provide a counter (510) output (XCNT) value 200h, i.e., 512, which is the value obtained by increasing the read access count value (CNT) by +1, as the second input (C2) of the comparator (530). Additionally, the counter (510) can store the counter (510) output (XCNT) value 200h, i.e., 512, in counter memory cells (202) connected to the word line (WL) corresponding to the row address (ROW_ADDR) 300h. The comparator (530) can compare the threshold (THRESHOLD) value 200h, i.e., 512 of the first input (C1) with the counter (510) output (XCNT) value 200h, i.e., 512 of the second input (C2), and output a logic high-level output (CO) signal.

[0060] At time T4, the output (XCNT) value of the counter (510) can be reset to 0h by the logic high-level output (CO) signal of the comparator (530). The counter (510) can store the counter (510) output (XCNT) value 0h, i.e., zero (0), in the counter memory cells (202) connected to the word line (WL) corresponding to the row address (ROW_ADDR) 300h. Accordingly, the second input (C2) of the comparator (530) can be output as the counter (510) output (XCNT) value 0h, i.e., zero (0). The comparison unit (530) can compare the threshold value (THRESHOLD) of the first input (C1) 200h, i.e., 512, with the counter (510) output (XCNT) value of the second input (C2) 0h, i.e., zero (0), and output a logic low-level output (CO) signal.

[0061] Between time points T3 and T4, the output (CO) signal of the comparator (530) can be output at a logic high level. The pulse generator (540) can output a pulse-shaped output (POUT) signal in response to the logic high level output (CO) signal of the comparator (530).

[0062] At time T4, the latch circuit (550) can store a row address (ROW_ADDR) corresponding to the second active command (ACT2) in the address storage unit (552) in response to a pulse-shaped pulse generator (540) output (POUT) signal. The latch circuit (550) can store the row address (ROW_ADDR) 300h in the latch of the address storage unit (552) and output a latch pull signal (LFULL) at a logic high level indicating that the address storage unit (552) is full. The logic high level latch pull signal (LFULL) can be provided to the logic circuit (520) to block the counter (510) output (XCNT) value from being provided to the comparison unit (530). Additionally, the latch circuit (550) can output the row address (ROW_ADDR) 300h stored in the address storage unit (552) as an output (LOUT) signal. The output (LOUT) signal 300h of the latch circuit (550) can be provided to the low hammer address generator (560). The low hammer address generator (560) can output the output (LOUT) signal 300h of the latch circuit (550) as a low hammer address (RH_ADDR) signal in response to a refresh signal (REFRESH). The low hammer address (RH_ADDR) 300h is provided to the refresh control circuit (240, FIG. 2), and a refresh address (REF_ADDR) can be generated based on the low hammer address (RH_ADDR) 300h.

[0063] At time T6, a row address (ROW_ADDR) 200h may be applied along with a third active command (ACT3). The counter (510) reads out an access count value (CNT) stored in counter memory cells (202) connected to a word line (WL) corresponding to the row address (ROW_ADDR) 200h of the memory cell array (200), and outputs a counter (510) output (XCNT) value that increases the read access count value (CNT) by +1, e.g., 200h, i.e., 512. Since the counter (510) output (XCNT) value 200h, i.e., 512 for the row address (ROW_ADDR) 200h is greater than or equal to the threshold (THRESHOLD) 200h, i.e., 512, it will correspond to a row hammer address.

[0064] However, the counter (510) output (XCNT) value 200h, i.e. 512, is not provided to the comparator (530) by the logic high-level latch pull signal (LFULL) provided to the logic circuit (520). This means that the next row hammer determination operation is held until the row hammer address (RH_ADDR) 300h is normal refreshed and / or target row refreshed by the refresh control circuit (240). Accordingly, the row hammer address (RH_ADDR) 300h is not evicted by the row address (ROW_ADDR) 200h, which will be determined as the next row hammer address. The row address (ROW_ADDR) 200h will be determined as the row hammer address (RH_ADDR) after the normal refresh operation and / or target row refresh operation for the row hammer address (RH_ADDR) 300h.

[0065] FIG. 7 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention.

[0066] Referring to FIG. 7 in conjunction with FIG. 1 to 6, in step S710, the system (100) can perform initialization. When the system (100) is powered up, the memory controller (112) and the memory device (120) can perform initial setup operations according to a predetermined method. In the initialization of the memory device (120), default operation parameters can be set. For example, a threshold (THRESHOLD) which is a low hammer judgment criterion can be set, and a low hammer monitor time frame (tREFi) can be set. Additionally, the address storage unit (552) within the latch circuit (550) of the low hammer control circuit (210) can be reset to an empty latch state.

[0067] In step S720, the control logic circuit (220) can perform the operation of monitoring the row hammer. The control logic circuit (220) can monitor the row address accessing the word line.

[0068] In step S730, the control logic circuit (220) can perform a counter-based latch-hold operation for the row hammer monitored in step S620. In step S730, the control logic circuit (220) can determine the corresponding row address as a row hammer address and store it in the address storage unit when the number of accesses to the word line is greater than or equal to a threshold. The control logic circuit (220) can hold a determination operation for the next row hammer address based on the activation of a latch-pull signal (LFULL) indicating that there is no empty space to store the row hammer address in the address storage unit (552). Step S730 will be described in detail in FIG. 8.

[0069] In step S740, the control logic circuit (220) can determine whether the low hammer monitor time frame (tREFi) has elapsed. If the low hammer monitor time frame (tREFi) has not elapsed (NO), the process can proceed to step S730. The control logic circuit (220) can perform a counter-based latch-hold operation on the low hammer address (RH_ADDR) to be obtained in step S730. If the low hammer monitor time frame (tREFi) has elapsed (YES), the process can proceed to step S750.

[0070] In step S750, the control logic circuit (220) may perform a normal refresh and / or target row refresh operation on the row hammer address (RH_ADDR) obtained in step S730. After performing the normal refresh and / or target row refresh operation on the row hammer address (RH_ADDR), the control logic circuit (220) may proceed to step S710. In step S710, the control logic circuit (220) may reset the address storage unit (552) of the latch circuit (550), which stored the row address (ROW_ADDR) corresponding to the row hammer address (RH_ADDR) for which the normal refresh and / or target row refresh operation was performed, to an empty latch state. Accordingly, the control logic circuit (220) may monitor the next row hammer address (RH_ADDR) and store it in the empty latch of the address storage unit (552).

[0071] FIG. 8 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIG. 8 is a flow diagram specifically illustrating a counter-based latch hold operation (step S730) for a monitored row hammer described in FIG. 7.

[0072] Referring to FIG. 8 in conjunction with FIGS. 1 to 7, at step S810, the control logic circuit (220) can receive a row address (ROW_ADDR) along with an active command (ACT). Since the row address (ROW_ADDR) is configured to access a word line (WL) corresponding to the row address (ROW_ADDR), for convenience of explanation, the row address (ROW_ADDR) may be used interchangeably with the word line (WL) address.

[0073] In step S820, the control logic circuit (220) can read out the access count value (CNT) stored in the counter memory cells (202) connected to the word line (WL) to the counter (510).

[0074] In step S830, the control logic circuit (220) can increase the access count value (CNT) read out in step S820 by +1 to the access count value of the word line (WL), i.e., the output value (XCNT) of the counter (510).

[0075] In step S840, the control logic circuit (220) can determine whether the output (XCNT) value of the counter (510) obtained in step S830 is greater than or equal to the threshold (THRESHOLD). As a result of the determination, if the output (XCNT) value of the counter (510) is greater than or equal to the threshold (THRESHOLD) (YES), the control logic circuit (220) moves to step S850, and if the output (XCNT) value of the counter (510) is not greater than or equal to the threshold (THRESHOLD) (NO), the control logic circuit (220) can move to step S880. In step S880, the control logic circuit (220) can store the output (XCNT) value of the counter (510) obtained in step S830 as the access count value (CNT) of the word line (WL) in the counter memory cells (202) connected to the word line (WL).

[0076] In step S850, the control logic circuit (220) can determine whether there is an empty latch in the address storage unit (552) within the latch circuit (550) of the row hammer control circuit (210). If the result of the determination is that there is an empty latch in the address storage unit (552), the control logic circuit (220) moves to step S860, and if there is no empty latch in the address storage unit (552), the control logic circuit (220) can move to step S880. In step S880, the control logic circuit (220) can store the output (XCNT) value of the counter (510) obtained in step S830 as the access count value (CNT) of the word line (WL) in the counter memory cells (202) connected to the word line (WL).

[0077] In step S860, the control logic circuit (220) can store a wordline (WL) address having an access count value greater than or equal to a threshold (THRESHOLD) in the latch of the address storage unit (552) of the latch circuit (550). The latch circuit (550) can store the wordline (WL) address in the latch of the address storage unit (552) and activate a latch pull signal (LFULL) to a logic high level to indicate that the address storage unit (552) is full.

[0078] In step S870, the control logic circuit (220) can reset the counter (510) output (XCNT) value to zero (0) based on the logic high-level latch pull signal (LFULL). In step S880, the control logic circuit (220) can store the counter (510) output (XCNT) value zero (0) obtained in step S870 as the access count value (CNT) of the word line (WL) in the counter memory cells (202) connected to the word line (WL).

[0079] After performing step S880, the control logic circuit (220) moves to step S740 of FIG. 7 to determine whether the low hammer monitor time frame (tREFi) has elapsed, and can perform a normal refresh and / or target low refresh operation for the low hammer address (RH_ADDR) of step S750.

[0080] FIG. 9 is a drawing illustrating a memory device for controlling a row hammer according to an exemplary embodiment of the present invention. FIG. 9 shows the memory device (120) of FIG. 1 implemented as HBM. It should be noted that the HBM configuration shown in FIG. 9 is provided as an example and is not necessarily an actual HBM configuration. Furthermore, the exemplary HBM configuration shown in FIG. 9 does not imply or suggest any limitation to the present disclosure. Hereinafter, subscripts attached to the same reference numeral in different drawings (e.g., a in 120a) are intended to distinguish multiple circuits having similar or identical functions. For convenience of explanation, the memory device (120a) may be used interchangeably with HBM (120a).

[0081] Referring to FIGS. 1 and 9, the HBM (120a) can be connected to a host device (110) via the JEDEC standard HBM protocol. The HBM protocol is a high-performance random access memory (RAM) interface for three-dimensional stacked memories (e.g., DRAM). The HBM (120a) generally achieves a wider bandwidth while consuming less power in a substantially smaller form factor than other DRAM technologies (e.g., DDR4, GDDR5, etc.).

[0082] HBM (120a) can have high bandwidth by including a plurality of channels (CH1–CH8) having independent interfaces. HBM (120a) may include a plurality of dies (910, 920), and as an example, may include a logic die (or buffer die) (910) and one or more core dies (920) stacked on top of the logic die (910). In the example of FIG. 9, an example is shown in which first to fourth core dies (921–924) are provided in HBM (120a), but the number of core dies (920) can be varied. The core dies (920) may be referred to as memory dies.

[0083] Each of the first to fourth core dies (921-924) may include one or more channels. In FIG. 9, an example is shown in which the HBM (120a) has eight channels (CH1-CH8) as each of the first to fourth core dies (921-924) includes two channels. For example, the first core die (921) may include a first channel and a third channel (CH1, CH3), the second core die (922) may include a second channel and a fourth channel (CH2, CH4), the third core die (923) may include a fifth channel and a seventh channel (CH5, CH7), and the fourth core die (924) may include a sixth channel and an eighth channel (CH6, CH8).

[0084] A logic die (910) may include an interface circuit (911) that communicates with a host device (110) and may receive commands / addresses and data from the host device (110) through the interface circuit (911). The host device (110) may transmit commands / addresses and data through bus(s) (130) arranged corresponding to channel(s) (CH1–CH8), and the bus (130) may be formed to be separated by channel, or some of the bus (130) may be shared by at least two channels. The interface circuit (911) may transmit commands / addresses and data to a channel where the host device (110) requests memory operation or computation processing. Additionally, according to an exemplary embodiment of the present invention, each of the core dies (920) or each of the channels may include a Processor In Memory (PIM) circuit.

[0085] The host device (110) may provide commands / addresses and data so that at least some of a number of computational operations or kernels can be performed in the HBM (120a), and computational processing may be performed in the PIM circuit of a channel designated by the host device (110). As an example, if the received command / address directs computational processing, the PIM circuit of the corresponding channel may perform computational processing using write data provided from the host device (110) and / or data read out from the corresponding channel. As another example, if the command / address received by the corresponding channel of the HBM (120a) directs memory operation, access operation for data may be performed.

[0086] According to an embodiment, each of the channels (CH1 to CH8) may include a plurality of banks, and the PIM circuit of each channel may be equipped with one or more processing elements. As an example, the number of processing elements in each channel may be equal to the number of banks, or as the number of processing elements is less than the number of banks, one processing element may be shared among at least two banks. The PIM circuit of each channel may execute a kernel offloaded by the host device (110).

[0087] According to an embodiment, each of the channels (CH1 to CH8) may include a row hammer control circuit (RHC) described with reference to FIGS. 1 to 8. Each of the channels (CH1 to CH8) includes a memory cell array comprising a word line and a plurality of counter memory cells and a control logic circuit, wherein the plurality of counter memory cells may store an access count value of the word line. The row hammer control circuit (RHC) monitors a row address accessing the word line during a row hammer monitoring time frame and, when the number of accesses to the word line is greater than or equal to a threshold, determines the row address as a row hammer address and stores it in an address storage unit. The row hammer control circuit (RHC) may hold a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit. Accordingly, each of the channels (CH1~CH8) can provide an enhanced RAS function by preventing the row hammer address stored in the address storage unit from being ejected until normal refresh and / or target refresh.

[0088] Meanwhile, the logic die (910) may further include a Through Silicon Via (TSV) region (912), an HBM Physical Layer Interface (HBM PHY) region (913), and a Serializer / Deserializer (SERDES) region (914). The TSV region (912) is a region where TSVs for communication with core dies (920) are formed, and where bus(s) (130) arranged corresponding to channel(s) (CH1~CH8) are formed. If each channel (CH1~CH8) has a bandwidth of 128 bits, the TSVs may include configurations for 1024 bits of data input / output.

[0089] The HBM PHY area (913) may include a plurality of input / output circuits for communication between the memory controller (112) and the channels (CH1–CH8), and as an example, the HBM PHY area (913) may include one or more interconnect circuits for connecting the memory controller (112) and the channels (CH1–CH8). The HBM PHY area (913) may include physical or electrical layers and logical layers provided for signals, frequencies, timings, drives, detailed operation parameters, and functionality required for efficient communication between the memory controller (112) and the channels (CH1–CH8). The HBM PHY area (913) may perform memory interfacing, such as selecting rows and columns corresponding to memory cells for the corresponding channels, writing data to memory cells, or reading written data. The HBM PHY area (913) may support features of the HBM protocol of the JEDEC standard.

[0090] The SERDES region (914) is a region that provides a SERDES interface according to the JEDEC (Joint Electron Device Engineering Council) standard as the processing throughput of the processor(s) of the host device (110) increases and as the demands for memory bandwidth increase. The SERDES region (914) may include a SERDES transmitter portion, a SERDES receiver portion, and a controller portion. The SERDES transmitter portion includes a parallel-to-serial circuit and a transmitter, and may receive a parallel data stream and serialize the received parallel data stream. The SERDES receiver portion includes a receiver amplifier, an equalizer, a clock and data recovery circuit and a serial-to-parallel circuit, and may receive a serial data stream and parallelize the received serial data stream. The controller portion may include an error detection circuit, an error correction circuit and registers such as a FIFO (First In First Out).

[0091] FIG. 10 is a block diagram showing a system (1000) including a memory device for controlling a row hammer according to embodiments of the present invention.

[0092] Referring to FIG. 10, the system (1000) may include a camera (1100), a display (1200), an audio processing unit (1300), a modem (1400), DRAMs (1500a, 1500b), flash memories (1600a, 1600b), I / O devices (1700a, 1700b), and an application processor (1800, hereinafter referred to as "AP"). The system (1000) may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an IoT (Internet of Things) device. Additionally, the system (1000) may be implemented as a server or a personal computer.

[0093] The camera (1100) can capture still images or video according to the user's control, and can store the captured image / video data or transmit it to a display (1200). The audio processing unit (1300) can process audio data included in flash memory devices (1600a, 1600b) or network content. The modem (1400) can modulate and transmit a signal for wired / wireless data transmission and reception, and can demodulate it to restore the original signal at the receiving end. The I / O devices (1700a, 1700b) may include devices that provide digital input and / or output functions, such as a USB (Universal Serial Bus), storage, a digital camera, an SD (Secure Digital) card, a DVD (Digital Versatile Disc), a network adapter, a touch screen, etc.

[0094] The AP (1800) can control the overall operation of the system (1000). The AP (1800) can control the display (1200) so that a portion of the content stored in the flash memory devices (1600a, 1600b) is displayed on the display (1200). When user input is received through the I / O devices (1700a, 1700b), the AP (1800) can perform a control operation corresponding to the user input. The AP (1800) may include an accelerator block, which is a dedicated circuit for AI (Artificial Intelligence) data computation, or may have an accelerator chip (1820) separate from the AP (1800). A DRAM (1500b) may additionally be mounted on the accelerator block or the accelerator chip (1820). An accelerator is a functional block that specializes in performing specific functions of the AP (1800). The accelerator may include a GPU, which is a functional block that specializes in graphic data processing; a Neural Processing Unit (NPU), which is a block that specializes in AI computation and inference; and a Data Processing Unit (DPU), which is a block that specializes in data transmission.

[0095] The system (1000) may include multiple DRAMs (1500a, 1500b). The AP (1800) may control the DRAMs (1500a, 1500b) through command and mode register (MRS) settings that conform to JEDEC (Joint Electron Device Engineering Council) standard specifications, or communicate by setting a DRAM interface protocol to use manufacturer-specific functions such as low voltage, high speed, and reliability, as well as CRC (Cyclic Redundancy Check) and ECC (Error Correction Code) functions. For example, the AP (1800) may communicate with the DRAM (1500a) using an interface that conforms to JEDEC standard specifications such as LPDDR4, LPDDR5, etc., and the accelerator block or accelerator chip (1820) may communicate by setting a new DRAM interface protocol to control the accelerator DRAM (1500b) which has a higher bandwidth than the DRAM (1500a).

[0096] Although only DRAMs (1500a, 1500b) are shown in FIG. 10, they are not limited thereto, and any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or Hybrid RAM can be used as long as it satisfies the bandwidth, response speed, and voltage conditions of the AP (1800) or accelerator chip (1820). The DRAMs (1500a, 1500b) have relatively smaller latency and bandwidth than the I / O devices (1700a, 1700b) or flash memories (1600a, 1600b). The DRAMs (1500a, 1500b) are initialized at the time of power-on of the system (1000), and the operating system and application data are loaded and used as a temporary storage location for the operating system and application data or as an execution space for various software codes.

[0097] Within the DRAMs (1500a, 1500b), arithmetic operations such as addition, subtraction, multiplication, and division, as well as vector operations, address operations, or Fast Fourier Transform (FFT) operations, may be performed. Additionally, within the DRAMs (1500a, 1500b), a function for performing inference may be performed. Here, inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training step for learning a model through various data and an inference step for recognizing data using the learned model. As an example, an image captured by a user through a camera (1100) is signal-processed and stored in the DRAM (1500b), and an accelerator block or accelerator chip (1820) may perform AI data operations to recognize data using the data stored in the DRAM (1500b) and the function used for inference.

[0098] The system (1000) may include a plurality of storage or a plurality of flash memories (1600a, 1600b) having a larger capacity than the DRAMs (1500a, 1500b). An accelerator block or accelerator chip (1820) may perform training steps and AI data computations using the flash memory devices (1600a, 1600b). In one embodiment, the flash memories (1600a, 1600b) may more efficiently perform training steps and inference AI data computations performed by the AP (1800) and / or the accelerator chip (1820) by using a computation device provided within the memory controller (1610). The flash memories (1600a, 1600b) may store photos taken through the camera (1100) or store data received via a data network. For example, Augmented Reality / Virtual Reality, HD (High Definition), or UHD (Ultra High Definition) content can be stored.

[0099] In the system (1000), DRAMs (1500a, 1500b) may include a row hammer control circuit as described with reference to FIGS. 1 through 8. The DRAMs (1500a, 1500b) include a memory cell array comprising a word line and a plurality of counter memory cells and a control logic circuit, wherein the plurality of counter memory cells may store an access count value of the word line. The DRAMs (1500a, 1500b) monitor a row address accessing the word line during a row hammer monitoring time frame, and when the number of accesses to the word line is greater than or equal to a threshold, the row address may be determined as a row hammer address and stored in an address storage unit. The DRAMs (1500a, 1500b) may hold a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit. Accordingly, the DRAMs (1500a, 1500b) can provide an enhanced RAS function by preventing the row hammer address stored in the address storage from being evicted until normal refresh and / or target refresh.

[0100] Although the present invention has been described in relation to a limited number of embodiments illustrated in the drawings, this is merely illustrative and those skilled in the art will recognize that various modifications and variations and equivalent other embodiments are possible therefrom. Accordingly, the appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

Claim 1 A memory device comprising a memory cell array including a word line and a plurality of counter memory cells, wherein the plurality of counter memory cells store an access count value of the word line; and a control logic circuit that monitors a row address accessing the word line during a row hammer monitoring time frame, and determines the row address as a row hammer address and stores it in an address storage unit when the number of accesses to the word line is greater than or equal to a threshold, wherein the control logic circuit holds a determination operation for the next row hammer address based on the activation of a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit. Claim 2 The memory device according to claim 1 further comprises a refresh control circuit that refreshes a victim memory cell row physically adjacent to a memory cell row corresponding to the row hammer address stored in the address storage unit during the row hammer monitoring time frame. Claim 3 A memory device according to claim 1, wherein the control logic circuit reads the access count value of the word line from the plurality of counter memory cells connected to the word line corresponding to the row address, outputs the read access count value by increasing it by +1 using a counter, and provides the output value of the counter as the number of accesses for the word line. Claim 4 In paragraph 3, the control logic circuit is a memory device that stores the output value of the counter in the plurality of counter memory cells connected to the word line. Claim 5 In paragraph 3, the control logic circuit resets the output value of the counter to zero (0) when the number of accesses to the word line is greater than or equal to the threshold, and stores the reset output value of the counter in the plurality of counter memory cells connected to the word line. Claim 6 A memory device according to claim 1, wherein the control logic circuit generates a pulse-shaped enable signal using a pulse generator when the number of accesses to the word line is greater than or equal to the threshold, and stores the row address as the row hammer address in the address storage unit in response to the enable signal. Claim 7 In paragraph 2, the control logic circuit is a memory device that provides the row hammer address stored in the address storage unit to the refresh control circuit in response to a refresh signal. Claim 8 In claim 7, the refresh signal is a memory device generated by a refresh command applied to the memory device. Claim 9 In claim 1, the control logic circuit is a memory device that resets the address storage unit to an empty space and disables the latch pull signal after the row hammer monitoring time frame has elapsed. Claim 10 In claim 1, the control logic circuit is a memory device that uses the basic refresh rate time (tREFi) specified in the memory device as the low hammer monitoring time frame. Claim 11 A counter for counting the number of accesses of a row address accessed during a row hammer monitoring time frame, wherein the counter reads an access count value of a word line from a plurality of counter memory cells connected to a word line accessed by the row address, increases the read access count value by +1 and outputs the output value of the counter as the number of accesses of the row address; a comparator for determining whether the row address is a row hammer address by comparing the output value of the counter with a threshold value; and a latch circuit for storing the row hammer address in an address storage unit based on the determination of the comparator and activating a latch pull signal indicating that there is no empty space to store the row hammer address in the address storage unit, wherein the output value of the counter related to the number of accesses of the next row address is not provided to the comparator by the activated latch pull signal. Claim 12 In claim 11, the counter is a control logic circuit that stores the output value of the counter in the plurality of counter memory cells connected to the word line. Claim 13 In claim 11, if the row address is determined to be the row hammer address by the comparison unit, the counter resets the output value of the counter to zero (0) and stores the reset output value of the counter in the plurality of counter memory cells connected to the word line. Claim 14 In claim 11, the control logic circuit further comprises a logic circuit including a first input for inputting the output value of the counter, a second input for inputting the latch pull signal, and an output that provides the output value of the counter to the comparator, wherein the logic circuit is a control logic circuit that does not provide the output value of the counter to the comparator when the latch pull signal is activated. Claim 15 In claim 11, the control logic circuit further comprises a pulse generator that inputs an output signal of the comparator and outputs a pulse-shaped output signal according to the logic level of the output signal of the comparator, and the latch circuit is a control logic circuit that stores the row address in the address storage unit in response to the pulse-shaped output signal of the pulse generator. Claim 16 In claim 11, the control logic circuit further comprises a row hammer address generating unit that outputs the row address stored in the address storage unit as the row hammer address in response to a refresh signal. Claim 17 In claim 16, the refresh signal is a control logic circuit generated by a refresh command applied to a memory device including the control logic circuit. Claim 18 In claim 11, the control logic circuit further comprises a refresh control circuit that refreshes a victim memory cell row physically adjacent to a memory cell row corresponding to the row hammer address. Claim 19 In claim 11, the control logic circuit is a control logic circuit that resets the address storage unit to an empty space after the low hammer monitoring time frame has elapsed. Claim 20 In claim 11, a control logic circuit in which a basic refresh rate time (tREFi) specified in a memory device including the control logic circuit is used as the low hammer monitoring time frame.

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