Display apparatus

Abstract

The present invention provides a display device capable of reducing the possibility of defects occurring during the manufacturing process, comprising a metal plate having an indentation recessed inwardly on one side and a display panel disposed on the upper side of the metal plate, wherein the display panel comprises a substrate having a display area and a peripheral area outside the display area; a metal wiring disposed on the upper side of the substrate and having a first portion that overlaps or is adjacent to the indentation when viewed from a direction perpendicular to the substrate; a driving unit disposed on the upper side of the substrate and overlaps with the metal plate and is disposed adjacent to the metal wiring when viewed from a direction perpendicular to the substrate; and a shielding unit interposed between the substrate and the metal wiring and that overlaps with at least a portion of the indentation when viewed from a direction perpendicular to the substrate.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a display device capable of reducing the possibility of defects occurring during the manufacturing process. Background Technology

[0002] Generally, a display device is manufactured by forming a display element on one side of a substrate and attaching a metal plate to the other side of the substrate. To attach the metal plate to the other side of the substrate, an indentation is located on one side of the metal plate, and an alignment key is formed on the other side of the substrate to which the metal plate is attached. The metal plate is attached to the other side of the substrate using this indentation and the alignment key. The problem to be solved

[0003] However, these conventional display devices had a problem in that defects could occur due to external light entering through the indentation during the manufacturing process.

[0004] The present invention aims to solve various problems, including those mentioned above, by providing a display device and a method for manufacturing the same that can reduce the possibility of defects occurring during the manufacturing process. However, these problems are exemplary and do not limit the scope of the present invention. means of solving the problem

[0005] According to one aspect of the present invention, a display device is provided comprising a metal plate having an indentation recessed inwardly on one side and a display panel disposed on the upper side of the metal plate, wherein the display panel comprises a substrate having a display area and a peripheral area outside the display area; a metal wiring disposed on the upper side of the substrate and having a first portion that overlaps or is adjacent to the indentation when viewed from a direction perpendicular to the substrate; a driving unit disposed on the upper side of the substrate and overlaps with the metal plate and is disposed adjacent to the metal wiring when viewed from a direction perpendicular to the substrate; and a shielding unit interposed between the substrate and the metal wiring and overlaps with at least a portion of the indentation when viewed from a direction perpendicular to the substrate.

[0006] The metal wiring extends from the first portion and has a second portion that overlaps with the metal plate when viewed from a direction perpendicular to the substrate, and the shielding portion may overlap with the second portion when viewed from a direction perpendicular to the substrate.

[0007] The metal wiring may extend along the outer side of the display area to surround at least a portion of the display area.

[0008] The above display panel may further comprise a shielding layer disposed on the upper surface of the substrate, an inorganic insulating layer covering the shielding layer, a semiconductor layer disposed on the inorganic insulating layer, a gate insulating layer covering the semiconductor layer, and a gate layer disposed on the gate insulating layer.

[0009] The above metal wiring can be disposed on the gate insulating layer.

[0010] The above display panel further comprises an interlayer insulating layer covering the gate layer and a conductive layer disposed on the interlayer insulating layer, and the metal wiring may be disposed on the interlayer insulating layer.

[0011] The metal wiring above may include the same material as the conductive layer.

[0012] The shielding portion may be disposed on the same layer as the shielding layer.

[0013] The shielding portion may include the same material as the shielding layer.

[0014] The above display panel may further include a driving voltage wiring located between the indentation and the driving part when viewed from a direction perpendicular to the substrate.

[0015] According to one aspect of the present invention, a display device is provided comprising a metal plate having an opening on one side and a display panel disposed on the upper side of the metal plate, wherein the display panel comprises a substrate having a display area and a peripheral area located outside the display area, a metal wiring disposed on the upper side of the substrate and having a first portion that overlaps or is adjacent to the opening when viewed from a direction perpendicular to the substrate, a driving unit disposed on the upper side of the substrate and overlaps with the metal plate and is disposed adjacent to the metal wiring when viewed from a direction perpendicular to the substrate, and a shielding unit interposed between the substrate and the metal wiring and overlaps with at least a portion of the opening when viewed from a direction perpendicular to the substrate.

[0016] The metal wiring extends from the first portion and has a second portion that overlaps with the metal plate when viewed from a direction perpendicular to the substrate, and the shielding portion may overlap with the second portion when viewed from a direction perpendicular to the substrate.

[0017] The metal wiring may extend along the outer side of the display area to surround at least a portion of the display area.

[0018] The above display panel may further comprise a shielding layer disposed on the upper surface of the substrate, an inorganic insulating layer covering the shielding layer, a semiconductor layer disposed on the inorganic insulating layer, a gate insulating layer covering the semiconductor layer, and a gate layer disposed on the gate insulating layer.

[0019] The above metal wiring can be disposed on the gate insulating layer.

[0020] The above display panel further comprises an interlayer insulating layer covering the gate layer and a conductive layer disposed on the interlayer insulating layer, and the metal wiring may be disposed on the interlayer insulating layer.

[0021] The shielding portion may be disposed on the same layer as the shielding layer.

[0022] The shielding portion may include the same material as the shielding layer.

[0023] The above display panel may further include a driving voltage wiring located between the opening and the driving unit when viewed from a direction perpendicular to the substrate.

[0024] Other aspects, features, and advantages other than those described above will become clear from the specific details, claims, and drawings for implementing the invention below. Effects of the invention

[0025] According to one embodiment of the method for manufacturing a display device according to the present invention as described above, a display device and a method for manufacturing the same can be provided, which can reduce the possibility of defects occurring during the manufacturing process. Of course, the scope of the present invention is not limited by such effects. Brief explanation of the drawing

[0026] FIG. 1 is a perspective view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 2 is a plan view schematically illustrating a part of a display panel of a display device according to one embodiment of the present invention. Figure 3 is an equivalent circuit diagram of one pixel included in the display panel of Figure 2. FIG. 4 is a plan view schematically illustrating a display panel of a display device according to one embodiment of the present invention as viewed from below. FIG. 5 is a plan view schematically illustrating the first metal plate of a display device according to one embodiment of the present invention as viewed from above. FIG. 6 is a plan view schematically illustrating a display device according to one embodiment of the present invention as viewed from below. FIG. 7 is a plan view schematically illustrating a display device according to one embodiment of the present invention as viewed from below. FIG. 8 is a cross-sectional view schematically illustrating a cross section taken along the line I-I' of FIG. 1. FIG. 9 is a cross-sectional view schematically illustrating a cross section taken along the line II-II' of FIG. 1. FIG. 10 is a diagram illustrating the inflow of external light in a display device according to a comparative example. FIG. 11 is a drawing for explaining the external light shielding effect of a display device according to one embodiment of the present invention. FIG. 12 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 14 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 15 is a diagram illustrating the inflow of external light in a display device according to a comparative example. FIG. 16 is a drawing for explaining the external light shielding effect of a display device according to one embodiment of the present invention. FIG. 17 is a plan view schematically illustrating the second metal plate of a display device according to one embodiment of the present invention as viewed from above. FIG. 18 is a plan view schematically illustrating a display device according to one embodiment of the present invention as viewed from below. FIG. 19 is a plan view schematically illustrating a display device according to one embodiment of the present invention as seen from below. FIG. 20 is a conceptual diagram schematically illustrating part A of FIG. 2. FIG. 21 is a cross-sectional view schematically illustrating a cross section taken along the line III-III' of FIG. 20. Specific details for implementing the invention

[0027] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0029] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0030] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0031] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0032] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0033] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0034] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0035] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0036] FIG. 1 is a perspective view schematically illustrating a part of a display device (1) according to one embodiment of the present invention. As shown in FIG. 1, the display device (1) according to the present embodiment includes a display panel (10) and a metal plate (700) supporting the display panel (10). The display device (1) can be any device that includes the display panel (10). For example, the display device (1) can be a variety of products such as a smartphone, tablet, laptop, television, or billboard.

[0037] A display panel (10) includes a substrate (100, see FIG. 2) having a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion for displaying an image, and a plurality of pixels may be arranged in the display area (DA). When viewed from a direction approximately perpendicular to the display panel (10) (z-axis direction), the display area (DA) may have various shapes, such as a circle, an ellipse, a polygon, or a specific geometric shape. FIG. 1 illustrates that the display area (DA) has a shape of an approximately rectangular shape with rounded corners.

[0038] A peripheral area (PA) may be positioned outside the display area (DA). The peripheral area (PA) is a portion that does not display an image and may surround the display area (DA) entirely or partially. A driving unit, etc., for providing electrical signals or power to pixel circuits corresponding to each of a plurality of pixels may be positioned in the peripheral area (PA). A pad, which is an area where electronic components or printed circuit boards can be electrically connected, may be positioned in the peripheral area (PA).

[0039] A metal plate (700) is positioned at the bottom of a display panel (10) and can serve to support the display panel (10). The metal plate (700) may be a plate made of a metallic material. That is, the metal plate (700) may include a metal or an alloy of at least two metals. For example, the metal plate (700) may include aluminum (Al), copper (Cu), iron (Fe), or chromium (Cr), etc. However, the present invention is not limited thereto. An adhesive layer may be interposed between the metal plate (700) and the display panel (10). This adhesive layer can serve to mutually bond the metal plate (700) and the display panel (10).

[0040] FIG. 2 is a plan view schematically illustrating a part of a display panel (10) of a display device (1) according to one embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of a pixel (P) included in the display panel (10) of FIG. 2. Specifically, FIG. 2 is a plan view illustrating the view of the display panel (10) from the top (+z direction).

[0041] As described above, the display panel (10) includes a substrate (100). The substrate (100) may include various materials having flexible or bendable properties. For example, the substrate (100) may include glass, metal, or polymer resin. Additionally, the substrate (100) may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the substrate (100) may have a multilayer structure including two layers each containing such a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride) interposed between the layers, and various other variations are possible.

[0042] As illustrated in FIG. 2, a pixel (P) is located in the display area (DA) of the substrate (100). The pixel (P) refers to a sub-pixel and may include a display element (280, see FIG. 8) such as an organic light-emitting diode (OLED). The pixel (P) may emit light, for example, red, green, blue, or white.

[0043] The pixel (P) can be electrically connected to embedded circuits placed in the peripheral area (PA). A gate driver (DV) and a pad (PD), etc., can be placed in the peripheral area (PA).

[0044] A gate driver (DV) can provide signals to a pixel (P) through a signal line (SL). Specifically, the gate driver (DV) can be electrically connected to the signal line (SL). By extending the signal line (SL) along a first direction (x-axis direction) and electrically connecting it to the pixel (P), the gate driver (DV) can provide signals such as a scan signal or a light emission control signal to the pixel (P). The gate driver (DV) can be positioned on both sides of a display area (DA). Some of the pixels (P) positioned in the display area (DA) can be electrically connected to the gate driver (DV) positioned on the left, and the rest can be electrically connected to the gate driver (DV) positioned on the right. Although FIG. 2 illustrates the gate driver (DV) being positioned on both sides of the display area (DA), the present invention is not limited thereto. For example, the gate driver (DV) may be placed on only one side of the display area (DA).

[0045] The pad portion (PD) is electrically connected to a control portion (not shown) to provide a signal or voltage to the gate driver portion (DV). Specifically, the terminals of the pad portion (PD) are exposed without being covered by an insulating layer and can be electrically connected to the terminals of the printed circuit board (360, see FIG. 21). The printed circuit board (360) transmits the signal or power from the control portion to the display panel (10). For example, a control signal generated by the control portion can be transmitted to the gate driver portion (DV) through the printed circuit board (360). Additionally, the control portion can transmit a driving voltage (ELVDD) to the driving voltage wiring (PL) and provide a common voltage (ELVSS) to the electrode power supply wiring. The common voltage (ELVSS) can be transmitted to the opposing electrode (283, see FIG. 8) of the pixel (P) through the electrode power supply wiring.

[0046] Meanwhile, a data driver (not shown) generates a data signal, and the generated data signal can be transmitted to a pixel (P) through a data line (DL). The data line (DL) crosses the display area (DA) and extends to the surrounding area (PA). The data signal from the data driver can be applied to the data line (DL) through a pad (PD).

[0047] A metal wiring (400) may be located in the peripheral area (PA) of the substrate (100). Specifically, the metal wiring (400) may surround at least a portion of the display area (DA) and may be located outside the gate driver (DV). The metal wiring (400) may be used to check whether a crack has occurred in the display panel. A detailed description of the metal wiring (400) will be provided later.

[0048] As illustrated in FIG. 3, a pixel (P) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) electrically connected thereto.

[0049] The pixel circuit (PC) may include a plurality of thin-film transistors (T1 to T7) and a storage capacitor (Cst) as illustrated in FIG. 3. The plurality of thin-film transistors (T1 to T7) and the storage capacitor (Cst) may be connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2), and a driving voltage line (PL). At least one of these lines, for example, the driving voltage line (PL), may be shared among neighboring pixels (P).

[0050] A plurality of thin-film transistors (T1 to T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), and a second initialization transistor (T7).

[0051] An organic light-emitting diode (OLED) may include a first electrode (e.g., a pixel electrode) and a second electrode (e.g., a counter electrode), wherein the first electrode of the organic light-emitting diode (OLED) is connected to a driving transistor (T1) via a light-emitting control transistor (T6) to receive a driving current, and the second electrode may receive a common voltage (ELVSS). The organic light-emitting diode (OLED) may generate light of brightness corresponding to the driving current.

[0052] Some of the plurality of thin-film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the remainder may be PMOS (p-channel MOSFETs). For example, among the plurality of thin-film transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the remainder may be PMOS (p-channel MOSFETs). Alternatively, among the plurality of thin-film transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS and the remainder may be PMOS. Alternatively, all of the plurality of thin-film transistors (T1 to T7) may be NMOS or all may be PMOS. The plurality of thin-film transistors (T1 to T7) may include amorphous silicon or polysilicon. If necessary, the thin-film transistors that are NMOS may include oxide semiconductors. For convenience, the following description explains the case where the compensation transistor (T3) and the first initialization transistor (T4) are NMOS (n-channel MOSFET) containing oxide semiconductor, and the rest are PMOS (p-channel MOSFET).

[0053] The signal wiring may include a first scan wiring (SL1) that transmits a first scan signal (Sn), a second scan wiring (SL2) that transmits a second scan signal (Sn'), a previous scan wiring (SLp) that transmits a previous scan signal (Sn-1) to a first initialization transistor (T4), a subsequent scan wiring (SLn) that transmits a subsequent scan signal (Sn+1) to a second initialization transistor (T7), a light emission control wiring (EL) that transmits a light emission control signal (En) to an operation control transistor (T5) and a light emission control transistor (T6), and a data wiring (DL) that intersects with the first scan wiring (SL1) and transmits a data signal (Dm).

[0054] The driving voltage line (PL) transmits a driving voltage (ELVDD) to the driving transistor (T1), the first initialization voltage line (VL1) transmits a first initialization voltage (Vint1) that initializes the driving transistor (T1), and the second initialization voltage line (VL2) transmits a second initialization voltage (Vint2) that initializes the first electrode of the organic light-emitting diode (OLED).

[0055] The driving gate electrode of the driving transistor (T1) is connected to the storage capacitor (Cst) through the second node (N2), and either the source region or the drain region of the driving transistor (T1) is connected to the driving voltage line (PL) via the operation control transistor (T5) through the first node (N1), and the other of the source region or the drain region of the driving transistor (T1) can be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED) via the light emission control transistor (T6) through the third node (N3). The driving transistor (T1) can receive a data signal (Dm) according to the switching operation of the switching transistor (T2) and supply a driving current to the organic light-emitting diode (OLED). That is, the driving transistor (T1) can control the amount of current flowing from the first node (N1), which is electrically connected to the driving voltage wiring (PL), to the organic light-emitting diode (OLED) in response to the voltage applied to the second node (N2) which changes according to the data signal (Dm).

[0056] The switching gate electrode of the switching transistor (T2) is connected to the first scan line (SL1) that transmits the first scan signal (Sn), and either the source region or the drain region of the switching transistor (T2) is connected to the data line (DL), and the other of the source region and the drain region of the switching transistor (T2) can be connected to the driving transistor (T1) through the first node (N1) and connected to the driving voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) can transmit the data signal (Dm) from the data line (DL) to the first node (N1) in response to the voltage applied to the first scan line (SL1). That is, the switching transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first scan line (SL1) and transmits the data signal (Dm) transmitted through the data line (DL) to the driving transistor (T1) through the first node (N1).

[0057] The compensation gate electrode of the compensation transistor (T3) is connected to the second scan line (SL2). Either the source region or the drain region of the compensation transistor (T3) can be connected to the first electrode of the organic light-emitting diode (OLED) via the third node (N3) and the light-emitting control transistor (T6). The other source region or the drain region of the compensation transistor (T3) can be connected to the first capacitor electrode (CE1) of the storage capacitor (Cst) and the driving gate electrode of the driving transistor (T1) via the second node (N2). This compensation transistor (T3) can be turned on according to the second scan signal (Sn') received through the second scan line (SL2) to diode-connect the driving transistor (T1).

[0058] The first initialization gate electrode of the first initialization transistor (T4) can be connected to the previous scan line (SLp). Either the source region or the drain region of the first initialization transistor (T4) can be connected to the first initialization voltage line (VL1). The other of the source region and the drain region of the first initialization transistor (T4) can be connected to the first capacitor electrode (CE1) of the storage capacitor (Cst) and the driving gate electrode of the driving transistor (T1), etc., through the second node (N2). The first initialization transistor (T4) can apply the first initialization voltage (Vint1) from the first initialization voltage line (VL1) to the second node (N2) in response to the voltage applied to the previous scan line (SLp). That is, the first initialization transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan wiring (SLp) to transmit the first initialization voltage (Vint1) to the driving gate electrode of the driving transistor (T1) and perform an initialization operation to initialize the voltage of the driving gate electrode of the driving transistor (T1).

[0059] The operation control gate electrode of the operation control transistor (T5) is connected to the light emission control wire (EL), and either the source region or the drain region of the operation control transistor (T5) is connected to the driving voltage wire (PL), while the other can be connected to the driving transistor (T1) and the switching transistor (T2) through the first node (N1).

[0060] The light-emitting control gate electrode of the light-emitting control transistor (T6) is connected to the light-emitting control wiring (EL), and either the source region or the drain region of the light-emitting control transistor (T6) is connected to the driving transistor (T1) and the compensation transistor (T3) through the third node (N3), and the other of the source region and the drain region of the light-emitting control transistor (T6) can be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED).

[0061] The operation control transistor (T5) and the light emission control transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control wiring (EL), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current flows through the organic light-emitting diode (OLED).

[0062] The second initialization gate electrode of the second initialization transistor (T7) is subsequently connected to the scan wiring (SLn), and either the source region or the drain region of the second initialization transistor (T7) is connected to the first electrode (pixel electrode) of the organic light-emitting diode (OLED), and the other of the source region or the drain region of the second initialization transistor (T7) is connected to the second initialization voltage wiring (VL2) to receive the second initialization voltage (Vint2). The second initialization transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan wiring (SLn) to initialize the first electrode (pixel electrode) of the organic light-emitting diode (OLED). The scan wiring (SLn) may be the same as the first scan wiring (SL1). In this case, the scan line can transmit the same electrical signal with a time difference to function as a first scan line (SL1) and as a subsequent scan line (SLn). That is, the subsequent scan line (SLn) may be a first scan line of a pixel electrically connected to a data line (DL) as a pixel adjacent to the pixel (P) shown in FIG. 3.

[0063] The second initialization transistor (T7) can be connected to the scan line (SLn) as shown in FIG. 3. However, the present invention is not limited thereto, and the second initialization transistor (T7) may be connected to the light emission control line (EL) and driven according to the light emission control signal (En).

[0064] The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) of the storage capacitor (Cst) is connected to the driving gate electrode of the driving transistor (T1) through the second node (N2), and the second capacitor electrode (CE2) of the storage capacitor (Cst) is connected to the driving voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to the difference between the driving gate electrode voltage of the driving transistor (T1) and the driving voltage (ELVDD).

[0065] The specific operation of each pixel (P) according to one embodiment is as follows.

[0066] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0067] During the data programming period, when the first scan signal (Sn) and the second scan signal (Sn') are supplied through the first scan line (SL1) and the second scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward-biased. Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the driving gate electrode (G1) of the driving transistor (T1). A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0068] During the light emission period, the operation control transistor (T5) and the light emission control transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control wiring (EL). A driving current is generated according to the voltage difference between the voltage of the driving gate electrode (G1) of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current is supplied to the organic light-emitting diode (OLED) through the light emission control transistor (T6).

[0069] As described above, some of the plurality of thin-film transistors (T1 to T7) may include oxide semiconductors. For example, the compensation transistor (T3) and the first initialization transistor (T4) may include oxide semiconductors.

[0070] Since polysilicon has high reliability, it can be controlled to ensure that the intended current flows accurately. Therefore, the driving transistor (T1), which directly affects the brightness of the display device, can be configured to include a semiconductor layer composed of polysilicon with high reliability, thereby enabling the implementation of a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so the voltage drop is not significant even if the driving time is long. That is, in the case of oxide semiconductors, the color change of the image due to voltage drop is not significant even during low-frequency driving, so low-frequency driving is possible. Therefore, the compensation transistor (T3) and the first initialization transistor (T4) can be configured to include oxide semiconductors, thereby preventing the occurrence of leakage current and enabling the implementation of a display device (1) with reduced power consumption.

[0071] Meanwhile, such oxide semiconductors are sensitive to light, so fluctuations in current amount, etc. may occur due to light from the outside. Therefore, a metal layer can be placed below the oxide semiconductor to absorb or reflect light from the outside. Accordingly, as shown in FIG. 3, the compensation transistor (T3) and the first initialization transistor (T4), each containing the oxide semiconductor, may have gate electrodes located above and below the oxide semiconductor layer, respectively. That is, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the metal layer located below the oxide semiconductor may overlap with the oxide semiconductor.

[0072] FIG. 4 is a schematic plan view illustrating the view of a display panel (10) of a display device (1) according to an embodiment of the present invention as seen from the bottom (-z direction), and FIG. 5 is a schematic plan view illustrating the view of a first metal plate (710) of a display device (1) according to an embodiment of the present invention as seen from the top (+z direction). The display panel (10) may include an upper surface (+z direction) and a lower surface (-z direction). The metal plate (700) may include the first metal plate (710), and the first metal plate (710) may include an upper surface (+z direction) and a lower surface (-z direction). As shown in FIG. 4, a plurality of alignment keys (AK) may be arranged on the lower surface (-z direction) of the display panel (10). When the upper surface of the first metal plate (710) is attached to the lower surface of the display panel (10), the first metal plate (710) can be attached to a preset position of the display panel (10) using alignment keys (AK). Of course, the plurality of alignment keys (AK) provided by the display panel (10) may be formed on the lower surface (in the -z direction) of the display panel (10), but the present invention is not limited thereto. For example, when forming a metal layer on the entire surface of the substrate (100) and then patterning it to form wiring or electrodes, alignment keys (AK) such as those shown in FIG. 4 may be formed simultaneously with such wiring or electrodes. This is also true for the embodiments and variations thereto described later.

[0073] As illustrated in FIG. 5, the first metal plate (710) may include a plurality of indentations (711). In this specification, "indentation" refers to a portion that is concavely indented from the edge of the first metal plate (710) toward the inside of the first metal plate (710).

[0074] The indentations (711) can be formed to be indented inward from one side of the first metal plate (710). For example, the indentations (711) can be formed on one side of the first metal plate (710) by cutting a portion of the first metal plate (710) using a laser beam. Some of the indentations (711) may be placed on one side of the first metal plate (710), and the remainder of the indentations (711) may be placed on the other side. Specifically, each indentation (711) may be symmetrically arranged with respect to the centerline (CL) of the first metal plate (710) or arranged with a similar spacing. By arranging the display panel (10) and the first metal plate (710) so that each of the plurality of alignment keys (AK) corresponds to each of the plurality of indentations (711), the first metal plate (710) can be attached to a preset position on the display panel (10).

[0075] FIGS. 6 and FIGS. 7 are plan views illustrating a display device (1) according to an embodiment of the present invention as viewed from below (-z direction). In FIG. 6, metal wiring (400) is also illustrated for convenience of explanation. As shown in FIG. 6, when the upper surface (+z direction) of the first metal plate (710) is attached to the lower surface (-z direction) of the display panel (10), a portion of the metal wiring (400) of the display panel (10) overlaps with the indentation (711) of the first metal plate (710). Specifically, the metal wiring (400) may include a first part (410) that overlaps with the indentation (711) when viewed from a direction perpendicular to the substrate (100) (z-axis direction), and a second part (420) that extends from the first part (410) and overlaps with the first metal plate (710) when viewed from a direction perpendicular to the substrate (100) (z-axis direction).

[0076] These metal wiring (400) can be shielded by a shielding part (800). In FIG. 7, the shielding part (800) is shown together for convenience of explanation. As shown in FIG. 7, when the upper surface (+z direction) of the first metal plate (710) is attached to the lower surface (-z direction) of the display panel (10), a part of the shielding part (800) of the display panel (10) overlaps with the indentation (711) of the first metal plate (710). Specifically, the part of the shielding part (800) that overlaps with the indentation (711) also overlaps with the first part (410) of the metal wiring (400). In addition, the remaining part of the shielding part (800) overlaps with the second part (420) of the metal wiring (400). Thus, the metal wiring (400) can be shielded by the shielding part (800). In FIG. 6, the shielding portion (800) is shown to overlap with the first portion (410) and the second portion (420), but the present invention is not limited thereto. For example, the shielding portion (800) may overlap only with the first portion (410).

[0077] Meanwhile, the first portion (410) of the metal wiring (400) may be positioned adjacent to the indentation (711) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). In this case, the metal wiring (400) may include a second portion (420) that extends from the first portion (410) and overlaps with the first metal plate (710) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). In this case as well, a part of the shielding portion (800) overlaps with the indentation (711), and the remaining part of the shielding portion (800) may overlap with the second portion (420) of the metal wiring (400).

[0078] FIG. 8 is a cross-sectional view schematically illustrating a cross-section taken along the line I-I' of FIG. 1, and is a cross-sectional view within the display area (DA). As shown in FIG. 8, a display panel (10) is disposed on the upper surface of a metal plate (700). A buffer layer (111) comprising silicon oxide, silicon nitride, or silicon oxynitride can be formed on the substrate (100) of the display panel (10). The buffer layer (111) can serve to increase the smoothness of the upper surface of the substrate (100), and the buffer layer (111) can prevent metal atoms or impurities from the substrate (100) from diffusing to the first semiconductor layer (210) located above it. The buffer layer (111) may be a single layer or a multilayer comprising silicon oxide, silicon nitride, or silicon oxynitride.

[0079] A transistor (TFT) may be formed on the buffer layer (111). As shown in FIG. 8, the transistor (TFT) may include a shielding layer (200), a first semiconductor layer (210), a first gate layer (220), a conductive layer (230), a second semiconductor layer (240), and a second gate layer (250).

[0080] A shielding layer (200) may be placed on a buffer layer (111). The shielding layer (200) may have a shape corresponding to a driving transistor (T1) and may serve as a lower protective metal to protect the first semiconductor layer (210). The shielding layer (200) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the shielding layer (200) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The shielding layer (200) may have a multilayer structure, for example, the shielding layer (200) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo. The inorganic insulating layer (112) covers the shielding layer (200) and may be placed on the buffer layer (111). The inorganic insulating layer (112) may include an insulating material. For example, the inorganic insulating layer (112) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0081] The first semiconductor layer (210) may be disposed on the inorganic insulating layer (112). The first semiconductor layer (210) may include a silicon semiconductor. For example, the first semiconductor layer (210) may include amorphous silicon or polysilicon. Specifically, the first semiconductor layer (210) may include polysilicon crystallized at low temperature. If necessary, ions may be implanted in at least a portion of the first semiconductor layer (210). The first gate insulating layer (113) covers the first semiconductor layer (210) and may be disposed on the inorganic insulating layer (112). The first gate insulating layer (113) may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0082] The first gate layer (220) may be disposed on the first gate insulating layer (113). The first gate layer (220) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate layer (220) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This first gate layer (220) may have a multilayer structure, for example, the first gate layer (220) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo. The first interlayer insulating layer (114) covers the first gate layer (220). The first interlayer insulating layer (114) may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0083] A conductive layer (230) may be disposed on the first interlayer insulating layer (114). The conductive layer (230) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the conductive layer (230) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The conductive layer (230) may have a multilayer structure, for example, the conductive layer (230) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo. The second interlayer insulating layer (115) covers the conductive layer (230). The second interlayer insulating layer (115) may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0084] The second semiconductor layer (240) may be disposed on the second interlayer insulating layer (115). The second semiconductor layer (240) may include an oxide semiconductor. The second gate insulating layer (116) covers the second semiconductor layer (240). The second gate insulating layer (116) may be an inorganic insulating layer comprising an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0085] The second gate layer (250) may be disposed on the second gate insulating layer (116). The second gate layer (250) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second gate layer (250) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This second gate layer (250) may have a multilayer structure, for example, the second gate layer (250) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo. The third interlayer insulating layer (117) covers the second gate layer (250). The third interlayer insulating layer (117) may be an inorganic insulating layer comprising inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0086] A first connecting electrode layer (260) including a source electrode (261) and a drain electrode (262) may be disposed on the third interlayer insulating layer (117). The first connecting electrode layer (260) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first connecting electrode layer (260) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This first connecting electrode layer (260) may have a multilayer structure, for example, the first connecting electrode layer (260) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0087] The first planarization layer (118) covers the first connecting electrode layer (260). The first planarization layer (118) may include an organic insulating material. For example, the first planarization layer (118) may include a photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0088] A second connecting electrode layer (270) may be disposed on the first flattening layer (118). The second connecting electrode layer (270) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second connecting electrode layer (270) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This second connecting electrode layer (270) may have a multilayer structure, for example, the second connecting electrode layer (270) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0089] The second planarization layer (119) covers the second connecting electrode layer (270). The second planarization layer (119) may include an organic insulating material. For example, the second planarization layer (119) may include a photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0090] In the display areas (DA), a display element (280) having a pixel electrode (281), a counter electrode (283), and an intermediate layer (282) interposed therebetween may be disposed on the second flattening layer (119). The pixel electrode (281) may be electrically connected to a transistor (TFT) by contacting either a source electrode (261) or a drain electrode (262) through the first connecting electrode layer (260) and the second connecting electrode layer (270) as shown in FIG. 8.

[0091] A pixel defining film (120) may be disposed on the second planarization layer (119). This pixel defining film (120) serves to define pixels by having openings corresponding to each subpixel, that is, openings that expose at least the central part of the pixel electrode (281). In addition, the pixel defining film (120) serves to prevent arcs from occurring at the edge of the pixel electrode (281) by increasing the distance between the edge of the pixel electrode (281) and the opposing electrode (283) above the pixel electrode (281). Such a pixel defining film (120) may be formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane).

[0092] The intermediate layer (282) of the organic light-emitting diode may include low-molecular-weight or high-molecular-weight materials. When including low-molecular-weight materials, the structure may have a stacked structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure, and may include various organic materials including copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed by vacuum deposition.

[0093] When the intermediate layer (282) includes a polymer material, it may generally have a structure including a hole transport layer (HTL) and an emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the emitting layer may include polymer materials such as PPV (Poly-Phenylenevinylene) and Polyfluorene. This intermediate layer (282) can be formed by screen printing, inkjet printing, or laser induced thermal imaging (LITI).

[0094] Of course, the intermediate layer (282) is not necessarily limited to this and may have various structures. Also, the intermediate layer (282) may include a layer that is integral across a plurality of pixel electrodes (281), or may include a layer patterned to correspond to each of the plurality of pixel electrodes (281).

[0095] The counter electrode (283) is positioned above the display area (DA), and can be positioned to cover the display area (DA) as shown in FIG. 8. That is, the counter electrode (283) can be formed integrally with a plurality of organic light-emitting elements and correspond to a plurality of pixel electrodes (281).

[0096] Since these organic light-emitting elements can be easily damaged by moisture or oxygen from the outside, an encapsulation layer (290) can cover and protect these organic light-emitting elements. The encapsulation layer (290) covers the display area (DA) and can extend to the outside of the display area (DA). This encapsulation layer (290) may include a first inorganic encapsulation layer (291), an organic encapsulation layer (292), and a second inorganic encapsulation layer (293), as shown in FIG. 8.

[0097] The first inorganic sealing layer (291) covers the counter electrode (283) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. Of course, other layers such as a capping layer may be interposed between the first inorganic sealing layer (291) and the counter electrode (283) as needed. Since this first inorganic sealing layer (291) is formed along the structure below it, its upper surface is not flat as shown in FIG. 8. The organic sealing layer (292) covers this first inorganic sealing layer (291), and unlike the first inorganic sealing layer (291), its upper surface can be made approximately flat. Specifically, the upper surface of the organic sealing layer (292) can be made approximately flat in the portion corresponding to the display area (DA). This organic encapsulation layer (292) may include one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second inorganic encapsulation layer (293) covers the organic encapsulation layer (292) and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. This second inorganic encapsulation layer (293) may prevent the organic encapsulation layer (292) from being exposed to the outside by contacting the first inorganic encapsulation layer (291) at the magnetic edge located outside the display area (DA).

[0098] In this way, the bag layer (290) includes a first inorganic bag layer (291), an organic bag layer (292), and a second inorganic bag layer (293). Through this multilayer structure, even if a crack occurs within the bag layer (290), such cracks can be prevented from connecting between the first inorganic bag layer (291) and the organic bag layer (292), or between the organic bag layer (292) and the second inorganic bag layer (293). This prevents or minimizes the formation of a path for moisture or oxygen from the outside to penetrate into the display area (DA).

[0099] FIG. 9 is a cross-sectional view schematically illustrating a cross section taken along the line II-II' of FIG. 1. As shown in FIG. 9, a metal wiring (400) and a gate driver (DV) may be disposed in the peripheral area (PA). A shielding part (800) may be disposed below the metal wiring (400).

[0100] As described above, the metal wiring (400) may overlap with the indentation (711) of the first metal plate (710) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). Additionally, the metal wiring (400) may be placed on the same layer as the conductive layer (230) included in the transistor (TFT). That is, the metal wiring (400) may be placed on the first interlayer insulating layer (114). The metal wiring (400) may be simultaneously formed with the same material as the conductive layer (230) included in the transistor (TFT). Accordingly, the metal wiring (400) may include the same material as the conductive layer (230).

[0101] The gate driver (DV) may overlap with the first metal plate (710) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). Additionally, the gate driver (DV) may be positioned adjacent to the metal wiring (400). The gate driver (DV) may include various electronic elements such as transistors and / or capacitors, but for convenience, FIG. 9 only shows a portion of the electrode or wiring that such electronic elements may include. The gate driver (DV) may include, for example, a first layer (210a), a second layer (220a), a third layer (260a), and a fourth layer (270a).

[0102] The first layer (210a) may be placed on the inorganic insulating layer (112), and the second layer (220a) may be placed on the first gate insulating layer (113). The first layer (210a) may be formed simultaneously with the same material when forming the first semiconductor layer (210) included in the transistor (TFT) located within the display area (DA), and the second layer (220a) may be formed simultaneously with the same material when forming the first gate layer (220) included in the transistor (TFT) located within the display area (DA). Meanwhile, the third layer (260a) may be placed on the third interlayer insulating layer (117), and the fourth layer (270a) may be placed on the first flattening layer (118). The third layer (260a) can be formed simultaneously with the same material when forming the first connection electrode layer (260) included in the transistor (TFT) located within the display area (DA), and the fourth layer (270a) can be formed simultaneously with the same material when forming the second connection electrode layer (270) included in the transistor (TFT) located within the display area (DA). In this way, the transistor included in the gate driver (DV) can be formed simultaneously with the same material when forming the transistor (TFT) located within the display area (DA).

[0103] The shielding portion (800) may be interposed between the substrate (100) and the metal wiring (400). Specifically, the shielding portion (800) may be placed on the same layer as the shielding layer (200) included in the transistor (TFT). That is, the shielding portion (800) may be placed on the buffer layer (111). The shielding portion (800) may be simultaneously formed with the same material as the shielding layer (200) included in the transistor (TFT). Accordingly, the shielding portion (800) may include the same material as the shielding layer (200). Meanwhile, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the shielding portion (800) may overlap with at least a part of the indentation (711) of the first metal plate (710). Specifically, since the shielding portion (800) overlaps with the recess (711) and the metal wiring (400) also overlaps with the recess (711), the shielding portion (800) can be located below the metal wiring (400). Accordingly, the shielding portion (800) can shield the metal wiring (400) from external light entering the display panel (10) through the recess (711) of the first metal plate (710).

[0104] Light introduced through the indentation (711) of the first metal plate (710) may include light incident obliquely on the lower surface (in the -z direction) of the shielding part (800). As shown in FIG. 10, which is a drawing for explaining the introduction of external light in a display device according to a comparative example, when the shielding part (800) is not located below the metal wiring (400), light (L1) introduced through the indentation (711) of the first metal plate (710) may reach the gate driving part (DV). Specifically, light (L1) incident obliquely on the lower surface (in the -z direction) of the metal wiring (400) is reflected from the lower surface (in the -z direction) of the metal wiring (400), and the light path is changed. The reflected light (L1) is incident obliquely on the upper surface (+Z direction) of the first metal plate (710) and is reflected from the upper surface (+Z direction) of the first metal plate (710), changing the light path. Subsequently, the light (L1) reaches the first layer (210a) of the gate driver (DV).

[0105] The gate driver (DV) may include electronic elements such as transistors and / or capacitors arranged along a second direction (y-axis direction). The gate driver (DV) includes a portion adjacent to the indentation (711) and a remainder portion. As described above, when light introduced through the indentation (711) reaches the portion of the gate driver (DV) adjacent to the indentation (711), a difference occurs between the threshold voltage of the transistor located in the portion of the gate driver (DV) adjacent to the indentation (711) and the threshold voltage of the transistor located in the remainder portion of the gate driver (DV). Accordingly, even if the same electrical signal is applied to the transistor located in the part of the gate driver (DV) adjacent to the indentation (711) and the transistor located in the remaining part of the gate driver (DV), the electrical signal applied to the pixel electrically connected to the part of the gate driver (DV) adjacent to the indentation (711) may be different from the electrical signal applied to the pixel electrically connected to the remaining part of the gate driver (DV). As a result, even if the brightness of the pixel electrically connected to the part of the gate driver (DV) adjacent to the indentation (711) and the brightness of the pixel electrically connected to the remaining part of the gate driver (DV) are intended to be the same, the brightness may be different. This may result in stains appearing on the image displayed by the display device (1).

[0106] However, in the case of the display device (1) according to the present embodiment, a shielding part (800) is located below the metal wiring (400). As shown in FIG. 11, which is a drawing for explaining the external light shielding effect of the display device (1) according to one embodiment of the present invention, light (L2) incident obliquely on the lower surface (in the -z direction) of the shielding part (800) is reflected from the lower surface (in the -z axis direction) of the shielding part (800), changing the light path, and the reflected light (L2) can be extracted to the outside of the display panel (10) through the indentation (711) of the first metal plate (710). That is, by causing light (L2) incident obliquely on the lower surface (in the -z direction) of the shielding part (800) to be reflected from the shielding part (800) located at the bottom of the metal wiring (400), it is possible to prevent the light (L2) incident in this way from being reflected from the lower surface (in the -z direction) of the metal wiring (400). Through this, it is possible to prevent or minimize the light (L2) from being incident on the upper surface (in the +z direction) of the first metal plate (710) and reaching the gate driving part (DV).

[0107] Meanwhile, in FIG. 9, the metal wiring (400) is shown to overlap with the indentation (711) when viewed from a direction perpendicular to the substrate (100) (z-axis direction), but the metal wiring (400) may be placed adjacent to the indentation (711). Even in this case, since the shielding portion (800) overlaps with at least a part of the indentation (711), the metal wiring (400) can be shielded from external light entering the display panel (10) through the indentation (711) of the first metal plate (710).

[0108] Although FIG. 11 illustrates that the metal wiring (400) is disposed on the same layer as the conductive layer (230) included in the transistor (TFT), the present invention is not limited thereto. For example, as shown in FIG. 12, which is a cross-sectional view schematically illustrating a part of a display device (1) according to one embodiment of the present invention, the metal wiring (400) may be disposed on the same layer as the first gate layer (220) included in the transistor (TFT). That is, the metal wiring (400) may be disposed on the first gate insulating layer (113). The metal wiring (400) may be simultaneously formed with the same material as the first gate layer (220). Accordingly, the metal wiring (400) may include the same material as the first gate layer (220).

[0109] Even when the metal wiring (400) is placed on the same layer as the first gate layer (220), as shown in FIG. 12, the shielding portion (800) is located below the metal wiring (400). Accordingly, the shielding portion (800) can shield the metal wiring (400) from external light entering the display panel (10) through the indentation (711) of the first metal plate (710). Specifically, just like light (L2), light (L3) incident obliquely on the lower surface (in the -z direction) of the shielding portion (800) is reflected from the lower surface (in the -z axis direction) of the shielding portion (800), changing the light path, and the reflected light (L3) can be extracted to the outside of the display panel (10) through the indentation (711) of the first metal plate (710). That is, by causing light (L3) incident obliquely on the lower surface (in the -z direction) of the shielding part (800) to be reflected from the shielding part (800) located at the bottom of the metal wiring (400), it is possible to prevent the light (L3) incident in this way from being reflected from the lower surface (in the -z direction) of the metal wiring (400). Through this, it is possible to prevent or minimize the light (L3) from being incident on the upper surface (in the +z direction) of the first metal plate (710) and reaching the gate driving part (DV).

[0110] In FIGS. 9, 11, and 12, both one side of the metal wiring (400) and one side of the shielding part (800) are shown as being spaced apart from one side of the substrate (100), but the present invention is not limited thereto. For example, as shown in FIG. 13, which is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), one side of the metal wiring (400) is spaced apart from one side of the substrate (100), but one side of the shielding part (800) may overlap with one side of the substrate (100). In this case, the shielding part (800) can more easily shield the metal wiring (400) from external light entering the display panel (10) through the indentation (711) of the first metal plate (710).

[0111] FIG. 14 is a cross-sectional view schematically illustrating a part of a display device (1) according to an embodiment of the present invention. As shown in FIG. 14, a metal wiring (400) and a gate driving unit (DV) may be disposed in a peripheral area (PA). A shielding unit (800) may be disposed below the metal wiring (400).

[0112] Meanwhile, a driving voltage wiring (PL) may be disposed between the metal wiring (400) and the gate driving unit (DV). The driving voltage wiring (PL) is located outside the gate driving unit (DV), specifically between one side of the display panel (10) and the gate driving unit (DV), and is electrically connected to a pixel (P) to provide a driving voltage (ELVDD). When viewed from a direction perpendicular to the substrate (100) (z-axis direction), the driving voltage wiring (PL) is disposed between the indentation (711) and the gate driving unit (DV), and the driving voltage wiring (PL) may overlap with the first metal plate (710). The driving voltage wiring (PL) may include, for example, a first layer (260b) and a second layer (270b). The first layer (260b) may be placed on the third interlayer insulating layer (117), and the second layer (270b) may be placed on the first flattening layer (118). The first layer (260b) may be formed simultaneously with the same material when forming the first connection electrode layer (260) included in the transistor (TFT), and the second layer (270b) may be formed simultaneously with the same material when forming the second connection electrode layer (270) included in the transistor (TFT).

[0113] As illustrated in FIG. 15, which is a drawing for explaining the inflow of external light in a display device according to a comparative example, when a shielding part (800) is not located below the metal wiring (400), light introduced through the indentation (711) of the first metal plate (710) can reach the gate driving part (DV). Specifically, light (L4) incident obliquely on the lower surface (in the -z direction) of the metal wiring (400) is reflected from the lower surface (in the -z direction) of the metal wiring (400), changing the light path. The reflected light (L4) is incident obliquely on the upper surface (in the +Z direction) of the first metal plate (710), and is reflected from the upper surface (in the +Z direction) of the first metal plate (710), changing the light path. Subsequently, light (L4) is incident obliquely on the lower surface (in the -z direction) of the first layer (260b) of the driving voltage wiring (PL), and is reflected from the lower surface (in the -z direction) of the first layer (260b), thereby changing the light path. Finally, light (L4) is reflected from the upper surface (in the +Z direction) of the first metal plate (710), thereby changing the light path, and thus light (L4) reaches the first layer (210a) of the gate driving unit (DV).

[0114] As described above, when light introduced through the indentation (711) reaches the part of the gate driving unit (DV) adjacent to the indentation (711), a difference occurs between the threshold voltage of the transistor located in the part of the gate driving unit (DV) adjacent to the indentation (711) and the threshold voltage of the transistor located in the remaining part of the gate driving unit (DV). Accordingly, even if the same electrical signal is applied to the transistor located in the part of the gate driving unit (DV) adjacent to the indentation (711) and the transistor located in the remaining part of the gate driving unit (DV), the electrical signal applied to the pixel electrically connected to the part of the gate driving unit (DV) adjacent to the indentation (711) may be different from the electrical signal applied to the pixel electrically connected to the remaining part of the gate driving unit (DV). As a result, even if it is intended that the brightness of a pixel electrically connected to the part of the gate driver (DV) adjacent to the indentation (711) and the brightness of a pixel electrically connected to the rest of the gate driver (DV) are the same, the brightness may differ. This may result in stains appearing on the image displayed by the display device (1).

[0115] However, as illustrated in FIG. 16, which is a drawing for explaining the external light shielding effect of a display device (1) according to one embodiment of the present invention, in the case of a display device (1) according to this embodiment, a shielding part (800) is located below the metal wiring (400). Accordingly, just like light (L2), light (L5) incident obliquely on the lower surface (in the -z direction) of the shielding part (800) is reflected from the lower surface (in the -z axis direction) of the shielding part (800), changing the light path, and the reflected light (L5) can be extracted to the outside of the display panel (10) through the indentation (711) of the first metal plate (710). That is, by causing light (L5) incident obliquely on the lower surface (in the -z direction) of the shielding part (800) to be reflected from the shielding part (800) located at the bottom of the metal wiring (400), it is possible to prevent the light (L5) incident in this way from being reflected from the lower surface (in the -z direction) of the metal wiring (400). Through this, it is possible to prevent or minimize the light (L5) from being incident on the upper surface (in the +z direction) of the first metal plate (710) and reaching the gate driving part (DV).

[0116] In FIGS. 14 and 16, both one side of the metal wiring (400) and one side of the shielding part (800) are shown as being spaced apart from one side of the substrate (100), but the present invention is not limited thereto. For example, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), one side of the metal wiring (400) is spaced apart from one side of the substrate (100), but one side of the shielding part (800) may overlap with one side of the substrate (100). In this case, the shielding part (800) can more easily shield the metal wiring (400) from external light entering the display panel (10) through the indentation (711) of the first metal plate (710).

[0117] FIG. 17 is a plan view schematically illustrating a second metal plate (720) of a display device (1) according to an embodiment of the present invention as viewed from above (+z direction). A metal plate (700) may include a second metal plate (720), and the second metal plate (720) may include an upper surface (+z direction) and a lower surface (-z direction). As shown in FIG. 16, the second metal plate (720) may include a plurality of openings (721). Some of the openings (721) may be placed on one side of the second metal plate (720), and the remainder of the openings (721) may be placed on the other side. Specifically, each opening (721) may be symmetrically arranged with respect to the centerline (CL) of the second metal plate (720) or arranged with similar spacing. By arranging the alignment keys (AK) such that each of the plurality of alignment keys (AK) shown in FIG. 4 corresponds to each of the plurality of openings (721), the second metal plate (720) is attached to a preset position of the display panel (10).

[0118] FIGS. 18 and 19 are schematic plan views illustrating a display device (1) according to an embodiment of the present invention as viewed from below (in the -z direction). However, for convenience of explanation, the metal wiring (400) is also shown in FIG. 18. As shown in FIG. 18, when the upper surface (in the +z direction) of the second metal plate (720) is attached to the lower surface (in the -z direction) of the display panel (10), a portion of the metal wiring (400) of the display panel (10) overlaps with the opening (721) of the second metal plate (720). Specifically, the metal wiring (400) may include a third part (430) that overlaps with an opening (721) when viewed from a direction perpendicular to the substrate (100) (z-axis direction), and a fourth part (440) that extends from the third part (430) and overlaps with a second metal plate (720) when viewed from a direction perpendicular to the substrate (100) (z-axis direction).

[0119] These metal wiring (400) can be shielded by a shielding part (800). In FIG. 19, the shielding part (800) is shown together for convenience of explanation. As shown in FIG. 19, when the upper surface (+z direction) of the second metal plate (720) is attached to the lower surface (-z direction) of the display panel (10), a part of the shielding part (800) of the display panel (10) overlaps with the opening (721) of the second metal plate (720). Specifically, the part of the shielding part (800) that overlaps with the opening (721) also overlaps with the third part (430) of the metal wiring (400). In addition, the remaining part of the shielding part (800) overlaps with the fourth part (440) of the metal wiring (400). Thus, the metal wiring (400) can be shielded by the shielding part (800). In FIG. 19, the shielding portion (800) is shown to overlap with the third portion (430) and the fourth portion (440), but the present invention is not limited thereto. For example, the shielding portion (800) may overlap only with the third portion (430).

[0120] Meanwhile, the third portion (430) of the metal wiring (400) may be positioned adjacent to the opening (721) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). In this case, the metal wiring (400) may include a fourth portion (440) that extends from the third portion (430) and overlaps with the second metal plate (720) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). In this case as well, a portion of the shielding portion (800) overlaps with the opening (721), and the remaining portion of the shielding portion (800) may overlap with the fourth portion (440) of the metal wiring (400). The effect that occurs when the shielding part (800) shields the metal wiring (400), which partially overlaps with the indentation (711), from external light also occurs when the shielding part (800) shields the metal wiring (400), which partially overlaps with the opening (721), from external light; therefore, for convenience, details that overlap with the content described above with reference to FIGS. 1 to 16 are omitted. That is, the content described above with reference to FIGS. 1 to 16 can be applied as is to the display device (1) according to the present embodiment, except that the metal plate (700) has an opening (721) rather than an indentation (711).

[0121] FIG. 20 is a conceptual diagram schematically illustrating part A of FIG. 2, and FIG. 21 is a cross-sectional view schematically illustrating a cross section taken along line III-III' of FIG. 20. As described above, the metal wiring (400) may be located outside the display area (DA) so as to surround at least a portion of the display area (DA). That is, the metal wiring (400) may extend along the outside of the display area (DA) to surround the display area (DA).

[0122] As illustrated in FIG. 20, the display device (1) according to the present embodiment has a plurality of test thin-film transistors (TT) located in a peripheral area (PA), specifically a pad portion (PD), and a plurality of pads (310, 320, 330, 340).

[0123] Test thin-film transistors (TT) are thin-film transistors used to verify whether pixels of a display area (DA) operate normally during the manufacturing process. Each of the multiple test thin-film transistors (TT) includes a semiconductor layer (421), a gate electrode (422), a source electrode (423), and a drain electrode (424), as illustrated in FIGS. 20 and 21. The semiconductor layer (421) of the test thin-film transistor (TT) may contain the same material as the first semiconductor layer (210) included in the aforementioned transistor (TFT) and may be located on the same layer. The gate electrode (422) of the test thin-film transistor (TT) may contain the same material as the first gate layer (220) included in the aforementioned transistor (TFT) and may be located on the same layer. The source electrode (423) and drain electrode (424) of the test thin-film transistor (TT) may have the same material as the conductive layer (230) included in the aforementioned transistor (TFT) and may be located on the same layer. For example, to ensure insulation between the semiconductor layer (421) and the gate electrode (422), a first gate insulating layer (113) may be interposed between the semiconductor layer (421) and the gate electrode (422). Additionally, the source electrode (423) and drain electrode (424) may be placed on the first interlayer insulating layer (114).

[0124] For reference, in FIG. 20, the first gate insulating layer (113) and the first interlayer insulating layer (114) are omitted for convenience, and only the positional relationship of the semiconductor layer (421), gate electrode (422), source electrode (423), and drain electrode (424) is shown. Of course, FIG. 20 also shows various other wirings and pads. A buffer layer (111) may be interposed between the test thin-film transistor (TT) and the substrate (100).

[0125] The gate electrodes (422) of these multiple test thin-film transistors (TT) are electrically connected to each other, and a first wiring (W1), which is a bridge wiring, makes this possible. That is, the first wiring (W1), which is placed on a layer different from the layer on which the gate electrodes (422) are placed, electrically connects the gate electrodes (422) that are spaced apart from each other. For example, the first wiring (W1) is located on the first interlayer insulating layer (114), and the first wiring (W1) can directly contact the gate electrodes (422) through contact holes formed in the first interlayer insulating layer (114) interposed between the first wiring (W1) and the gate electrodes (422), thereby electrically connecting the gate electrodes (422) that are spaced apart from each other. Accordingly, at least a portion of the first wiring (W1) and the gate electrodes (422) can be positioned on a virtual straight line (extended along the x-axis) as shown in FIG. 20.

[0126] Each of the test thin-film transistors (TT) includes a source electrode (423) and a drain electrode (424). The first wiring (W1) may include the same material as the source electrode (423) and the drain electrode (424), such as a metal like titanium, copper, or aluminum, and may have a single layer or a multilayer structure. If it has a multilayer structure, the first wiring (W1) may have a three-layer structure of titanium / aluminum / titanium. Furthermore, the first wiring (W1) may be placed on the same layer as the source electrode (423) and the drain electrode (424), that is, on the first interlayer insulating layer (114). Accordingly, the first wiring (W1) may be connected to the lower gate electrodes (422) through a contact hole formed in the first interlayer insulating layer (114).

[0127] Multiple data lines (DL) extend across the display area (DA) to the surrounding area (PA). Each of the multiple test thin-film transistors (TT) is electrically connected to a corresponding one of the multiple data lines (DL). Accordingly, when electrical signals are simultaneously applied to the gate electrodes (422) of the multiple test thin-film transistors (TT) that are electrically connected to each other, channels are simultaneously formed in the semiconductor layers (421) of the multiple test thin-film transistors (TT). When the multiple test thin-film transistors (TT) are turned on simultaneously in this manner, an electrical signal from the second line (W2), which is a test signal line, is transmitted to the multiple data lines (DL). Accordingly, pixels in the display area (DA) that are electrically connected to the multiple data lines (DL) emit light, allowing for the inspection of whether the pixels within the display area (DA) are defective.

[0128] When the display device is used after the manufacturing of the display device is completed, the test thin-film transistors (TT) are turned off. For example, if the test thin-film transistors (TT) are P-type thin-film transistors, the test thin-film transistors (TT) are turned off by applying a VGH bias voltage (positive bias voltage) to the first wiring (W1). Accordingly, a signal from the driving chip (350), which will be described later, can be applied to the data wiring (DL) through the first pads (320).

[0129] The gate electrodes (422) may include a metal such as molybdenum or aluminum, for example, and may have a single layer or a multilayer structure. If they have a multilayer structure, the gate electrodes (422) may have a three-layer structure of molybdenum / aluminum / molybdenum. These gate electrodes (422) may be located on the first gate insulating layer (113) as described above.

[0130] As described above, a plurality of data lines (DL) extend across the display area (DA) and into the peripheral area (PA). These plurality of data lines (DL) may include the same material as the source electrode (423) and drain electrode (424) of the test thin-film transistor (TT), such as a metal like titanium, copper, or aluminum, and may have a single-layer or multi-layer structure. If they have a multi-layer structure, the plurality of data lines (DL) may have a three-layer structure of titanium / aluminum / titanium. Furthermore, the plurality of data lines (DL) may be placed on the same layer as the layer on which the source electrode (423) and drain electrode (424) are placed. Each of the plurality of test thin-film transistors (TT) is electrically connected to a corresponding one of these plurality of data lines (DL), which can be achieved by intermediate lines (425). That is, the intermediate wires (425) connect multiple data wires (DL) and multiple test thin-film transistors (TT).

[0131] These intermediate wires (425) may contain the same material as the gate electrodes (422), such as a metal like molybdenum or aluminum, and may have a single layer or a multilayer structure. If they have a multilayer structure, the intermediate wires (425) may have a three-layer structure of molybdenum / aluminum / molybdenum. Furthermore, the intermediate wires (425) may be placed in the same layer as the layer where the gate electrodes (422) are placed. Of course, the end of the intermediate wire (425) in the direction of the data wire (DL) is connected to the upper data wire (DL) through a contact hole formed in the first interlayer insulating layer (114), and the end of the intermediate wire (425) in the direction of the test thin-film transistor (TT) is connected to the upper drain electrode (424) through a contact hole formed in the first interlayer insulating layer (114). Meanwhile, the source electrodes (423) of the test thin-film transistors (TT) are connected to a second-second wiring (W2-2) (having a portion extended in the x-axis direction) which is part of the second wiring (W2) that is a test signal line, and specifically, the source electrodes (423) may be integral with the second-second wiring (W2-2).

[0132] Meanwhile, as illustrated in FIGS. 20 and 21, the display device (1) may have a plurality of first pads (310, 320, 330). Each of the first pads (320) located in the direction of the display area (DA) (+y direction) centered on the plurality of test thin-film transistors (TT) among the plurality of first pads (310, 320, 330) is located above the corresponding intermediate wiring (425) and can make contact with the corresponding intermediate wiring (425). Each of these plurality of first pads (310, 320, 330) may include a metal such as titanium, copper, or aluminum, which is the same material as the source electrode (423) and drain electrode (424) of the test thin-film transistor (TT), and may have a single layer or a multilayer structure. In the case of a multilayer structure, the plurality of first pads (310, 320, 330) may have a three-layer structure of titanium / aluminum / titanium. Furthermore, the plurality of first pads (310, 320, 330) may be placed on the same layer as the layer where the source electrode (423) and the drain electrode (424) are placed. Accordingly, the plurality of first pads (310, 320, 330) may be connected to the lower intermediate wiring (425) through a contact hole formed in the first interlayer insulating layer (114).

[0133] Some of the first pads (310, 320, 330) may be dummy pads that are not connected to other electrical components formed on the substrate (100). At this time, it is necessary to ensure that the height from the bottom surface of the substrate (100) to the top surface of the first pads (320) electrically connected to the data wiring (DL) is approximately the same as the height from the bottom surface of the substrate (100) to the top surface of the dummy first pad (310). To achieve this, since intermediate wiring (425) is located below the first pads (320) electrically connected to the data wiring (DL), a step adjustment part (427) may be located below the dummy first pad (310) in the direction of the substrate (100). These step adjustment parts (427) may include the same material as the intermediate wiring (425), that is, the same material as the gate electrodes (422), such as a metal such as molybdenum or aluminum, and may have the same layer structure as the intermediate wiring (425).

[0134] Among the plurality of first pads (310, 320, 330), the first pads (320) are located in the direction of the display area (DA) (+y direction) centered on the plurality of test thin-film transistors (TT), and among the plurality of first pads (310, 320, 330), the first pads (330) are located in the opposite direction of the display area (DA) (-y direction) centered on the plurality of test thin-film transistors (TT). These first pads (320) and first pads (330) can be connected to a driving chip (350) equipped with a display device through an anisotropic conductive film (not shown for convenience), as shown in FIG. 21.

[0135] A plurality of first pads (310, 320, 330) are located on a first interlayer insulating layer (114) covering a peripheral area (PA) as described above. Additionally, a first flattening layer (118) is located on the first interlayer insulating layer (114) in the peripheral area (PA). Of course, the first interlayer insulating layer (114) and the first flattening layer (118) may also exist within a display area (DA) as shown in FIG. 2. The first flattening layer (118) may include an organic material such as, for example, acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane). This first flattening layer (118) has an opening (118-1) that exposes a plurality of first pads (310, 320, 330).

[0136] The driving chip (350) is provided with output terminals (351) and input terminals (352) located on both sides of the body (353). Since FIG. 21 is a cross-sectional view, only one output terminal (351) and one input terminal (352) of the driving chip (350) are shown, but the driving chip (350) may be provided with multiple output terminals (351) and multiple input terminals (352) (arranged along the x-axis direction). Such a driving chip (350) may be, for example, an IC chip.

[0137] The first pads (330) exposed by the opening (118-1) of the first flattening layer (118) are connected to the input terminals (352) of the driving chip (350), and the first pads (320) are connected to the output terminals (351) of the driving chip (350). Accordingly, when driving an actual display device rather than a test, an electrical signal from the driving chip (350) is transmitted from the output terminals (351) of the driving chip (350) to the data lines (DL) via the first pads (320) and intermediate lines (425), and consequently, can be transmitted to multiple pixels within the display area (DA).

[0138] Of course, information regarding an image to be implemented in a display area (DA) can be input to the driving chip (350) through the input terminals (352) of the driving chip (350). To this end, the display device may be provided with a printed circuit board (360) including a plate (362) and output terminals (361). Although only one output terminal (361) of the printed circuit board (360) is shown in FIG. 21 as it is a cross-sectional view, the printed circuit board (360) may be provided with a plurality of output terminals (361) (arranged along the x-axis direction).

[0139] The display device (1) is provided with second pads (340) located in the opposite direction (-y direction) of the display area (DA) direction centered on the first pad (330). Each of the second pads (340) may contain the same material as the source electrode (423) and drain electrode (424) of the test thin-film transistor (TT), such as a metal like titanium, copper, or aluminum, and may have a single layer or a multilayer structure. If it has a multilayer structure, the second pads (340) may have a three-layer structure of titanium / aluminum / titanium. Furthermore, the second pads (340) may be placed on the same layer as the layer on which the source electrode (423) and drain electrode (424) are placed. That is, the second pads (340) may be located on the first interlayer insulating layer (114).

[0140] These second pads (340) can be electrically connected to the corresponding first pads (330) by second connecting wires (426). The second connecting wires (426) may include the same material as the gate electrodes (422), such as a metal like molybdenum or aluminum, and may have a single layer or a multilayer structure. If they have a multilayer structure, the second connecting wires (426) may have a three-layer structure of molybdenum / aluminum / molybdenum. Furthermore, the second connecting wires (426) may be placed in the same layer as the layer where the gate electrodes (422) are placed. That is, the second connecting wires (426) may be located between the first gate insulating layer (113) and the first interlayer insulating layer (114). The end of the second connecting wire (426) in the direction of the display area (DA) is connected to the upper first pad (330) through a contact hole formed in the first interlayer insulation layer (114), and the opposite end of the second connecting wire (426) is connected to the upper second pad (340) through a contact hole formed in the first interlayer insulation layer (114).

[0141] As described above, information regarding an image to be implemented in a display area (DA) can be input to the driving chip (350) through the input terminals (352) of the driving chip (350). To this end, the output terminals (361) of the printed circuit board (360) are electrically connected to the second pads (340) through an anisotropic conductive film (not shown), the second pads (340) are electrically connected to the first pads (330) by the second connecting wires (426), and the first pads (330) can be electrically connected to the input terminals (352) of the driving chip (350).

[0142] Meanwhile, as the input terminals (352) of the driving chip (350) are connected to the first pads (330) through an anisotropic conductive film, etc. and the output terminals (351) of the driving chip (350) are connected to the first pads (320) through anisotropic conductive film, etc., the driving chip (350) is positioned on top of the test thin-film transistors (TT) as shown in FIG. 21. In this process, the first pad (310), which is a dummy pad not connected to other electrical components formed on the substrate (100), is also connected to the input terminal (352) of the driving chip (350) through anisotropic conductive film, etc.

[0143] As described above, a step adjustment part (427) is located at the lower side of the substrate (100) in the direction of the dummy pad, the first pad (310), so that the height from the bottom surface of the substrate (100) to the upper surface of the first pads (320) electrically connected to the data wiring (DL) and the height from the bottom surface of the substrate (100) to the upper surface of the dummy pad, the first pad (310) are approximately similar or identical. Therefore, the driving chip (350) can be positioned stably.

[0144] As illustrated in FIG. 20, the metal wiring (400) includes a first metal wiring (401) and a second metal wiring (402). The first metal wiring (401) is positioned to cross the opening (118-1) of the first flattening layer (118) in the peripheral region (PA) of the substrate (100) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). The first metal wiring (401) may be located on the first interlayer insulating layer (114). This first metal wiring (401) may include the same material as the first pads (310, 320, 330), source electrode (423), and drain electrode (424), such as a metal like titanium, copper, or aluminum, and may have the same layer structure as the first pads (310, 320, 330), source electrode (423), and drain electrode (424). That is, the first metal wiring (401) may have a single layer or a multilayer structure. If it has a multilayer structure, the first metal wiring (401) may have a three-layer structure of titanium / aluminum / titanium.

[0145] The first metal wiring (401) can be connected to the lower second metal wiring (402) through a contact hole formed in the first interlayer insulating layer (114). The second metal wiring (402) is located below the first interlayer insulating layer (114), specifically on the first gate insulating layer (113). Accordingly, the second metal wiring (402) may contain the same material as the gate electrodes (422), such as a metal like molybdenum or aluminum, and may have the same layer structure as the gate electrodes (422). That is, the second metal wiring (402) may have a single layer or a multilayer structure. If it has a multilayer structure, the second metal wiring (402) may have a three-layer structure of molybdenum / aluminum / molybdenum. Furthermore, the second metal wiring (402) can be placed on the same layer as the layer where the gate electrodes (422) are placed.

[0146] This second metal wiring (402) can be connected to a first pad (331), which is one of the first pads (330). That is, the second metal wiring (402) can be extended to the lower part of the first pad (331) and connected to the first pad (331) above it through a contact hole formed in the first interlayer insulation layer (114). Additionally, the first pad (331) can be connected to a second pad (341), which is one of the second pads (340), through a second connecting wiring (426).

[0147] For reference, FIG. 20 illustrates that among the first pads (330), the first pad (332), the first pad (333), and the first pad (334) are not connected to other wiring, etc. in the direction of the display area (DA) (+y direction). However, this is illustrated as such for convenience, and the first pad (332), the first pad (333), or the first pad (334) may also be connected to other wiring. Such other wiring may be wiring located between the first gate insulating layer (113) and the first interlayer insulating layer (114), or wiring located on the first interlayer insulating layer (114). This is also true for the embodiments and variations thereof described later.

[0148] As illustrated in FIG. 20, the display device (1) according to the present embodiment may include a first wiring (W1). The first wiring (W1) may be positioned to cross the opening (118-1) of the first flattening layer (118) in the peripheral region (PA) of the substrate (100) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). Additionally, as illustrated in FIG. 20, the first metal wiring (401) may include an adjacent portion parallel to at least a portion of the first wiring (W1).

[0149] The first wiring (W1) is a bridge wiring as described above and electrically connects the gate electrodes (422) that are spaced apart from each other. The first wiring (W1) can directly contact the gate electrodes (422) through contact holes formed in the first interlayer insulating layer (114) interposed between the first wiring (W1) and the gate electrodes (422), thereby electrically connecting the gate electrodes (422) that are spaced apart from each other.

[0150] Meanwhile, as described above, the display device (1) according to the present embodiment may include a second wiring (W2) which is a test signal line. The second wiring (W2) may be positioned to cross the opening (118-1) of the first flattening layer (118) in the peripheral area (PA) of the substrate (100) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). Additionally, as shown in FIG. 20, the second wiring (W2) may include an adjacent portion that is parallel to at least a part of the first wiring (W1).

[0151] The second wiring (W2), which is a test signal line, is connected to the source electrodes (423) of the test thin-film transistors (TT). Specifically, the second wiring (W2) may be integral with the source electrodes (423). That is, the second wiring (W2) may be located on the first interlayer insulating layer (114). This second wiring (W2) may include the same material as the first pads (310, 320, 330), the source electrode (423), and the drain electrode (424), such as a metal like titanium, copper, or aluminum, and may have the same layer structure as the first pads (310, 320, 330), the source electrode (423), and the drain electrode (424). That is, the second wiring (W2) may have a single layer or a multilayer structure. In the case of a multilayer structure, the second wiring (W2) may have a three-layer structure of titanium / aluminum / titanium.

[0152] As described above, the plurality of test thin-film transistors (TT) are test thin-film transistors used to verify whether the pixels of the display area (DA) operate normally during the manufacturing process. The first wiring (W1) and the second wiring (W2) are electrically connected to these plurality of test thin-film transistors (TT) and are wirings for applying a test signal to the data wiring (DL). That is, a test gate signal can be applied to the plurality of test thin-film transistors (TT) through the first wiring (W1), and a test data signal can be transmitted to the plurality of data wiring (DL) through the second wiring (W2).

[0153] Meanwhile, as illustrated in FIG. 20, the display device according to the present embodiment may include a third wiring (W3). The third wiring (W3) may be positioned to cross the opening (118-1) of the first flattening layer (118) in the peripheral region (PA) of the substrate (100) when viewed from a direction perpendicular to the substrate (100) (z-axis direction). Additionally, as illustrated in FIG. 20, the third wiring (W3) may include an adjacent portion that is parallel to at least a part of the second wiring (W2).

[0154] The third wiring (W3) may be located on the first interlayer insulation layer (114). This third wiring (W3) may contain the same material as the first metal wiring (401), such as a metal like titanium, copper, or aluminum, and may have the same layer structure as the first metal wiring (401). That is, the third wiring (W3) may have a single layer or a multilayer structure. If it has a multilayer structure, the third wiring (W3) may have a three-layer structure of titanium / aluminum / titanium.

[0155] This third wiring (W3) may be a wiring that applies an inspection signal to the source electrodes (423) of test thin-film transistors (TT) that are not connected to the second wiring (W2) in a portion not shown in FIG. 20, similar to the second wiring (W2), and applies an inspection signal to the data wiring (DL) that is electrically connected to the test thin-film transistors (TT).

[0156] FIG. 20 schematically illustrates part A of FIG. 2, and part B of FIG. 2 has the shape of FIG. 20 flipped horizontally.

[0157] As described above, the metal wiring (400) can be used to check whether a crack has occurred in the display panel (10). One end of the metal wiring (400) surrounding the display area (DA) is electrically connected to the first pad (331) in part A, and the other end of the metal wiring (400) is electrically connected to the pad in part B as well. Therefore, by applying an electrical signal between the first pad (331) in part A and the pad corresponding to the first pad (331) in part B and measuring the voltage and / or current, it is possible to check whether a crack has occurred in the display panel (10). This is because if a crack occurs at the edge of the display panel (10) during the manufacturing process, the metal wiring (400) is severed by the crack, and consequently, the electrical signal detected between the first pad (330) in part A and the corresponding pad in part B becomes different from the normal case. After the manufacturing of the display device (1) is completed, a DC bias voltage is applied to the metal wiring (400) from the power supply of the display device (1).

[0158] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0159] DA: Display area PA: Surrounding area 1: Display device 10: Display panel 100: Substrate 400: Metal wiring 410: Part 1 430: Part 3 710: First metal plate 711: Inlet 720: Second metal plate 721: Opening 800: Shielding part DV: Gate driver

Claims

Claim 1 A display device comprising: a metal plate having an indentation recessed inwardly on one side; and a display panel disposed on the upper side of the metal plate; wherein the display panel comprises: a substrate having a display area and a peripheral area outside the display area; a metal wiring disposed on the upper side of the substrate and having a first portion that overlaps or is adjacent to the indentation when viewed from a direction perpendicular to the substrate; a gate driving portion disposed on the upper side of the substrate and overlaps with the metal plate when viewed from a direction perpendicular to the substrate and is disposed adjacent to the metal wiring; and a shielding portion interposed between the substrate and the metal wiring and overlaps with at least a portion of the indentation when viewed from a direction perpendicular to the substrate. Claim 2 A display device according to claim 1, wherein the metal wiring has a second portion that extends from the first portion and overlaps with the metal plate when viewed from a direction perpendicular to the substrate, and the shielding portion overlaps with the second portion when viewed from a direction perpendicular to the substrate. Claim 3 A display device according to claim 1, wherein the metal wiring extends along the outer side of the display area to surround at least a portion of the display area. Claim 4 A display device according to claim 1, wherein the display panel further comprises: a shielding layer disposed on the upper surface of the substrate; an inorganic insulating layer covering the shielding layer; a semiconductor layer disposed on the inorganic insulating layer; a gate insulating layer covering the semiconductor layer; and a gate layer disposed on the gate insulating layer. Claim 5 In paragraph 4, the metal wiring is disposed on the gate insulating layer, forming a display device. Claim 6 A display device according to claim 4, wherein the display panel further comprises: an interlayer insulating layer covering the gate layer; and a conductive layer disposed on the interlayer insulating layer, and the metal wiring disposed on the interlayer insulating layer. Claim 7 A display device according to claim 6, wherein the metal wiring comprises the same material as the conductive layer. Claim 8 In paragraph 4, the shielding portion is a display device disposed on the same layer as the shielding layer. Claim 9 In paragraph 4, the display device wherein the shielding portion comprises the same material as the shielding layer. Claim 10 A display device according to claim 1, wherein the display panel further comprises a driving voltage wiring located between the indentation and the driving part when viewed from a direction perpendicular to the substrate. Claim 11 A display device comprising: a metal plate having an opening on one side; and a display panel disposed on the upper side of the metal plate; wherein the display panel comprises: a substrate having a display area and a peripheral area located outside the display area; a metal wiring disposed on the upper side of the substrate and having a third portion that overlaps or is adjacent to the opening when viewed from a direction perpendicular to the substrate; a driving part disposed on the upper side of the substrate and overlaps with the metal plate when viewed from a direction perpendicular to the substrate and is disposed adjacent to the metal wiring; and a shielding part interposed between the substrate and the metal wiring and that overlaps with at least a portion of the opening when viewed from a direction perpendicular to the substrate. Claim 12 A display device according to claim 11, wherein the metal wiring has a fourth part that extends from the third part and overlaps with the metal plate when viewed from a direction perpendicular to the substrate, and the shielding part overlaps with the fourth part when viewed from a direction perpendicular to the substrate. Claim 13 A display device according to claim 11, wherein the metal wiring extends along the outer side of the display area to surround at least a portion of the display area. Claim 14 A display device according to claim 11, wherein the display panel further comprises: a shielding layer disposed on the upper surface of the substrate; an inorganic insulating layer covering the shielding layer; a semiconductor layer disposed on the inorganic insulating layer; a gate insulating layer covering the semiconductor layer; and a gate layer disposed on the gate insulating layer. Claim 15 In paragraph 14, the metal wiring is disposed on the gate insulating layer, in a display device. Claim 16 In claim 14, the display panel further comprises: an interlayer insulating layer covering the gate layer; and a conductive layer disposed on the interlayer insulating layer; and the metal wiring disposed on the interlayer insulating layer, the display device. Claim 17 In paragraph 16, the display device wherein the metal wiring comprises the same material as the conductive layer. Claim 18 In paragraph 14, the shielding portion is a display device disposed on the same layer as the shielding layer. Claim 19 In paragraph 14, the display device wherein the shielding portion comprises the same material as the shielding layer. Claim 20 A display device according to claim 11, wherein the display panel further comprises a driving voltage wiring located between the opening and the driving part when viewed from a direction perpendicular to the substrate.

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