Method for cleaning chamber components having metal etching residues

Abstract

A residue cleaning method is provided for a ruthenium (Ru) residue on at least one surface of a component of a semiconductor processing chamber. The residue is exposed to a Ru cleaning composition comprising at least one of hypochlorite and O3-based chemicals, and the Ru cleaning composition removes the Ru residue.

Description

Technology Field

[0001] The present disclosure relates to a method for cleaning metal residues from components of a plasma processing chamber. Background Technology

[0002] During semiconductor wafer processing, features may be etched through a metal-containing layer. In the formation of magnetic random access memories (MRAM) or resistive random-access memory (RRAM) devices, a plurality of thin metal layers or films may be etched sequentially. For MRAM, a plurality of thin metal layers may be used to form magnetic tunnel junction stacks. The thin metal layers may contain ruthenium (Ru) and other metals, such as cobalt (Co), iron (Fe), palladium (Pd), nickel (Ni), boron (B), platinum (Pt), tantalum (Ta), molybdenum (Mo), titanium (Ti), manganese (Mn), magnesium (Mg), chromium (Cr), iridium (Ir), tungsten (W), copper (Cu), aluminum (Al), hafnium (Hf), indium (In), tin (Sn), gold (Au) and silver (Ag).

[0003] These metal-containing layers may be etched in a plasma processing chamber. Etched metal residues may be deposited on the plasma-facing surfaces of components in the plasma processing chamber during the plasma etching process. Excessive residue can alter the performance of the chamber, generate contaminants, and render components unusable. Changes in component performance may cause non-uniformities. Contaminants may cause failures in the fabricated devices. If a component becomes unusable and must be replaced, the replacement component may be costly.

[0004] The description of the background art provided in this specification is intended to provide the general context of the present disclosure. The information described in this background art section, as well as aspects of the present art that may not otherwise be recognized as prior art at the time of filing, are not explicitly or implicitly acknowledged as prior art to the present disclosure.

[0005] Cross-reference regarding related applications

[0006] This application claims the benefit of priority of U.S. Patent Application No. 63 / 139,231, filed January 19, 2021, which is incorporated herein by reference for all purposes.

[0007] To achieve the foregoing and according to the purpose of the present disclosure, a residue cleaning method is provided for a ruthenium (Ru) residue on at least one surface of a component of a semiconductor processing chamber. The residue is exposed to a Ru cleaning composition comprising at least one of hypochlorite and O3-based chemicals, and the Ru cleaning composition removes the Ru residue.

[0008] In another aspect, a method for cleaning residues including noble metal residues from components of a semiconductor processing chamber is provided. The noble metal residues are exposed to a noble metal cleaning composition comprising thionyl chloride and pyridine, and the noble metal cleaning composition removes the noble metal residues.

[0009] These and other features of the present disclosure will be described in more detail below together with the detailed description of the present disclosure and the drawings below. Brief explanation of the drawing

[0010] The present disclosure is illustrated by the drawings of the attached drawings, in which similar reference numbers refer to similar elements, as an example rather than a limitation. Figure 1 is a high-level flowchart of one embodiment. FIGS. 2A and FIGS. 2B are schematic diagrams of a stack processed in one embodiment. Figure 3 is a schematic diagram of an etching reactor that may be used for etching. FIG. 4a is an enlarged cross-sectional view of a part of a component of a plasma processing chamber having a residue layer. FIG. 4b is an enlarged cross-sectional view of a part of the component after the residue layer has been removed. Figure 5 is a schematic diagram of the components in a wet bath. Specific details for implementing the invention

[0011] The present disclosure will now be described in detail with reference to some preferred embodiments of the disclosure as illustrated in the accompanying drawings. In the description below, numerous specific details are provided to provide a complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other examples, known process steps and / or structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0012] During semiconductor wafer processing, features may be etched through a metal-containing layer. In the formation of magnetic random access memories (MRAM) or resistive random-access memory (RRAM) devices, a plurality of thin metal layers or films may be etched sequentially. For MRAM, a plurality of thin metal layers may be used to form magnetic tunnel junction stacks. The thin metal layers may contain ruthenium (Ru) and other metals, such as cobalt (Co), iron (Fe), palladium (Pd), nickel (Ni), boron (B), platinum (Pt), tantalum (Ta), molybdenum (Mo), titanium (Ti), manganese (Mn), magnesium (Mg), chromium (Cr), iridium (Ir), tungsten (W), copper (Cu), aluminum (Al), hafnium (Hf), indium (In), tin (Sn), gold (Au), and silver (Ag). In various embodiments, the thin metal layers may include Group III, Group IV, and Group V elemental metals (Group III to V metals).

[0013] These metal-containing layers may be processed, for example, etched in a plasma processing chamber. After metal plasma etching, the plasma chamber components are contaminated with multiple etching species, including metals in both metallic and compound forms, and silicon species from process wafers or mask materials. Contaminants on the chamber walls will cause serious issues in integrated circuit (IC) manufacturing by affecting chamber plasma conditions and, consequently, wafer-to-wafer repeatability. To etch most metals in MRAM magnetic tunnel junctions (MTJs), halogen chemicals are applied to evaluate etching efficiency. Metal-containing residues from wafer processing are redeposited onto the chamber walls. X-ray photoelectron spectroscopy analysis of the chamber wall surfaces reveals that the metals are mostly in compound forms, such as metal fluorides (MFx, M: metal). In addition, the chamber wall surfaces are also coated with silicon oxide layers from the process wafer, hard mask materials, or etching chemicals. Mixtures of metals / metal compounds and silicon oxide form contamination layers inside the chamber. This contamination causes several issues, including the flaking off of metal particles onto wafers and process drift caused by the release of multiple atoms from the chamber walls during wafer processing. Excessive residue can alter chamber performance, generate contaminants, and render components unusable. Changes in component performance can lead to non-uniformities. Contaminants can cause the failure of fabricated devices. If a component becomes unusable and requires replacement, the replacement component can be costly.

[0014] If residues cannot be cleaned from the component, the component must be discarded and replaced. Some of these residues are noble metal residues. Noble metals are metals that are highly resistant to chemical attack. Noble metals include Pd, Au, Ru, Pt, rhodium (Rh), osmium (Os), and iridium (Ir).

[0015] The embodiments provide a method for cleaning components having at least Ru metal residues and other precious metal residues. For ease of understanding, FIG. 1 is a high-level flowchart of the process used in one embodiment. Various embodiments may have more or fewer steps. In addition, in various embodiments, the steps may be performed in different orders or simultaneously. Metal layers are processed in a chamber (104). One exemplary chamber may be a plasma processing chamber. For example, metal layers may form a stack on a wafer to provide MRAM, RRAM, cobalt interconnects, etc. FIG. 2a is a schematic cross-sectional view of an exemplary MRAM stack (200) on a process wafer processed in one embodiment. The stack (200) is on a substrate having a silicon or silicon oxide (Si / SiO2) layer (204). A first tantalum (Ta) layer (208) is on the Si / SiO2 layer (204). A platinum (Pt) layer (212) is on top of a first Ta layer (208). A cobalt platinum alloy (CoPt) layer (216) is on top of the Pt layer (212). A magnesium oxide (MgO) layer (220) is on top of the CoPt layer (216). A cobalt iron boron (CoFeB) layer (224) is on top of the MgO layer (220). A second Ta layer (228) is on top of the CoFeB layer (224). A ruthenium (Ru) layer (232) is on top of the second Ta layer (228). A patterned mask is formed on top of the stack (200). In this embodiment, the patterned mask includes a titanium nitride layer (236) under the Ru layer (244) and under the SiO2 layer (240).

[0016] The stack (200) may be processed so that one or more of the metal-containing layers are etched. To do so, the stack may undergo one or more etching processes. FIG. 2b is a schematic cross-sectional view of the stack (200) after an exemplary process has been completed on the stack (200). As illustrated, the processing of the stack etched the first Ta layer (208), the Pt layer (212), the CoPt layer (216), the MgO layer (220), the CoFeB layer (224), the second Ta layer (228), and the Ru layer (232). Some of the patterned masks may also be etched.

[0017] As a result of processing the stack (200), materials from the Ru layer, SiO2 layer, TiN layer, CoFeB layer, MgO layer, CoPt layer, Pt layer, and / or Ta layer may be deposited on the plasma-facing surfaces of the plasma processing chamber. For example, as a result of etching, residues of tantalum, beryllium, platinum, manganese, cobalt, iron, ruthenium, magnesium, titanium, and silicon are deposited on the plasma-facing surfaces of the chamber. After processing, the stack may be removed. This may be accomplished by removing the wafer from the chamber. Subsequently, another stack on the wafer may be placed in the process chamber for processing. As each stack is etched, an additional coating of residue will be formed on the plasma-facing surfaces of the chamber. In some embodiments, more than a thousand wafers are processed in the chamber.

[0018] In one embodiment, all processing may be performed in a single plasma etching chamber. In other embodiments, processing may be performed in different chambers. FIG. 3 schematically illustrates an example of a processing chamber system (300) that may be used in one embodiment. The processing chamber system (300) includes a plasma reactor (302) having a plasma processing chamber (304) inside. A plasma power supply (306) tuned by a power matching network (308) supplies power to a transformer coupled plasma (TCP) coil (310) located near a dielectric inductive power window (312) to generate plasma (314) within the plasma processing chamber (304) by providing inductively coupled power. A pinnacle (372) extends from the chamber wall (376) of the plasma processing chamber (304) to the dielectric induction power window (312) to form a pinnacle ring. The pinnacle (372) is angled with respect to the chamber wall (376) and the dielectric induction power window (312). For example, the inner angle between the pinnacle (372) and the chamber wall (376) and the inner angle between the pinnacle (372) and the dielectric induction power window (312) may each be greater than 90° and less than 180°. As illustrated, the pinnacle (372) provides an angled ring near the top of the plasma processing chamber (304). A TCP coil (top power source) (310) may be configured to create a uniform diffusion profile within the plasma processing chamber (304). For example, the TCP coil (310) may be configured to generate a toroidal power distribution in the plasma (314).A dielectric induction power window (312) is provided to separate the TCP coil (310) from the plasma processing chamber (304) while allowing energy to pass from the TCP coil (310) to the plasma processing chamber (304). A wafer bias voltage power supply (316), tuned by a bias matching network (318), provides power to the electrode (320) to set the bias voltage when the stack is placed on the electrode (320). A cover (366) is placed over the electrode (320). In this embodiment, the cover (366) is a bare silicon wafer. A controller (324) controls the plasma power supply (306) and the wafer bias voltage power supply (316).

[0019] The plasma power supply (306) and the wafer bias voltage power supply (316) may be configured to operate at specific radio frequencies, for example, 13.56 MHz (megahertz), 27 MHz, 2 MHz, 60 MHz, 400 kHz (kilohertz), 2.54 GHz (gigahertz), or combinations thereof. The plasma power supply (306) and the wafer bias voltage power supply (316) may be appropriately sized to supply various powers to achieve the desired process performance. For example, in one embodiment, the plasma power supply (306) may supply power in the range of 50 to 5000 W, and the wafer bias voltage power supply (316) may supply a bias voltage in the range of 20 to 2000 V. In addition, the TCP coil (310) and / or electrode (320) may be composed of two or more sub-coils or sub-electrodes. The sub-coils or sub-electrodes may be powered by a single power supply or by multiple power supplies.

[0020] As illustrated in FIG. 3, the processing chamber system (300) further comprises a gas source / gas supply mechanism (330). The gas source (330) is in fluid connection with the plasma processing chamber (304) through a gas inlet, such as a gas injector (340). The gas injector (340) may be located at any advantageous position within the plasma processing chamber (304) and may take any shape to inject gas. However, preferably, the gas inlet may be configured to create a "tunable" gas injection profile. A tunable gas injection profile allows for independent adjustment of the flow of gases to each of the multiple zones within the semiconductor processing chamber (304). More preferably, the gas injector is mounted on a dielectric induction power window (312). The gas injector may be mounted on the power window, may be mounted within the power window, or may form part of the power window. Process gases and byproducts are removed from the plasma processing chamber (304) via a pressure control valve (342) and a pump (344). The pressure control valve (342) and the pump (344) also serve to maintain a specific pressure within the plasma processing chamber (304). The pressure control valve (342) can maintain a pressure of less than 1 torr during processing. An edge ring (360) is placed around the upper portion of the electrode (320). The gas source / gas supply mechanism (330) is controlled by a controller (324). For example, the Kiyo manufactured by Lam Research Corp. of Fremont, CA ® Tools may be used to implement one embodiment.

[0021] When the performance of the component has sufficiently degraded, or after a specified number of wafers have been processed, or after a specified usage time has elapsed, the component is removed from the chamber for cleaning (step (108)). For example, the component may be removed after 300 radio frequency (RF) hours. RF hours are the amount of time that RF power is applied to the plasma chamber. FIG. 4a is an enlarged cross-sectional view of a portion of the component of the plasma processing chamber (304) shown in FIG. 3, such as the induced power window (312) after the component is removed. In this embodiment, processing the stacks deposits a residue layer (408) on the plasma-facing surfaces of the component. In this embodiment, the residue layer (408) comprises residues of tantalum, beryllium, platinum, manganese, cobalt, iron, ruthenium, magnesium, titanium, and silicon oxide. Among these residues, ruthenium and platinum are precious metals. In some embodiments, the residue layer (408) may be formed by thin layers of residues of different materials.

[0022] After the component is removed from the plasma processing chamber (304), a Ru cleaning process is provided (step (112)). In one embodiment, the component is cleaned using at least one of hypochlorite and ozone (O3). In various embodiments, the hypochlorite may be at least one of sodium hypochlorite (NaClO), ammonium hypochlorite (NH4ClO), and hydrogen hypochlorite (HClO). In some embodiments, the cleaning process may be a wet cleaning process, such as using a wet cleaning bath. For example, the wet cleaning bath may be an aqueous solution containing at least one of hypochlorite and ozone. In addition, the wet cleaning bath may further contain ammonia. Although Ru is described in this example, the composition may be used to clean residues containing other materials alternatively or additionally. In some embodiments, cleaning may be performed while the component is inside the chamber.

[0023] FIG. 5 is a schematic diagram of a component (312) in an exemplary Ru wet cleaning bath (500). The Ru wet cleaning bath contains a Ru wet cleaning solution (504) containing an aqueous solution of at least one of hypochlorite and ozone (O3) together with ammonia in a container (508). A residue layer (408) is exposed to the Ru wet cleaning solution (504). In this embodiment, transducers (512) are provided. The transducers (512) provide ultrasonic or megasonic energy to increase residue removal. The Ru wet cleaning bath (500) removes at least some of the Ru residue. The component is removed from the Ru wet cleaning bath (500). The component (312) is removed from the Ru wet cleaning bath (500).

[0024] Precious metal cleaning is provided (step (116)). In one embodiment, the component is cleaned using a precious metal cleaning composition comprising a mixture of thionyl chloride and pyridine. In some embodiments, the cleaning process may be a wet cleaning process, such as using a wet cleaning bath. For example, the wet cleaning bath may be an aqueous solution containing thionyl chloride and pyridine in a solvent. A solution of a mixture of thionyl chloride and pyridine in a solvent is known as organic aqua regia. Organic aqua regia is known to dissolve some precious metals, such as palladium, gold, and platinum. However, organic aqua regia does not dissolve ruthenium, rhodium, iridium, and osmium. In some embodiments, the solvent may be at least one of acetonitrile (CH3CN), dimethyl sulfoxide (DMSO), and dimethylformamide (DMF). Examples of precious metal wet cleaning baths may be similar to Ru wet cleaning baths (500), but the difference is that the precious metal wet cleaning bath contains a precious metal wet cleaning solution of a mixture of thionyl chloride and pyridine in a solvent such as water. The residue layer (408) is exposed to the precious metal cleaning composition. The precious metal cleaning composition removes Pd and Pt-containing residues. The component (312) is removed from the precious metal cleaning composition.

[0025] Silicon oxide cleaning is provided (step (120)). In one embodiment, the component is placed in a silicon oxide wet cleaning bath containing an acid and a passivating solution. In this example, the acid may be at least one of hydrofluoric acid (HF) and ammonium fluoride (NH4F). The passivating solution may be an organic solvent generally selected from at least one of the group of amines, alcohols, glycols, and acetone. For example, the passivating solution may be at least one of methylamine, ethyleneamine, ethylenediamine, diethylenetriamine, ethylene glycol, propylene glycol, and acetylacetone. The acid removes silicon oxide-containing residues. The passivating solution protects the surface of the component. The silicon oxide wet cleaning bath may be similar to the Ru wet cleaning bath (500), but the difference is that the silicon oxide wet cleaning bath contains a silicon oxide wet cleaning solution. The residue layer (408) is exposed to a silicon oxide wet cleaning solution. The silicon oxide wet cleaning removes silicon oxide-containing residues. The passivating solution passivates the surface of the component and prevents damage to the texture applied to the parts. The component is removed from the silicon oxide wet cleaning bath.

[0026] In this embodiment, the silicon oxide wet cleaning bath further includes other acids to remove other metals. The other acids may be one or more of hydrochloric acid (HCl), nitric acid (HNO3), and sulfuric acid (H2SO4). These acids may be used to remove one or more of Ta, Ni, Co, Cr, Hf, and III-V metals. In other embodiments, one or more separate baths of HCl, HNO3, and H2SO4 may be used to remove one or more of Ta, Ni, Co, Cr, Hf, and III-V metals before providing the silicon oxide wet cleaning bath.

[0027] The step of providing Ru wet cleaning (step (112)), the step of providing precious metal wet cleaning (step (116)), and the step of providing silicon oxide wet cleaning (step (120)) may be repeated multiple times during multiple cycles (step (124)). The residue layer (408) may comprise alternating layers of different residues. The alternating layers may be caused by different wafers being etched sequentially for many different wafers. FIG. 4b is an enlarged cross-sectional view of a portion of component (312) after the residue layer (408) shown in FIG. 4a has been removed.

[0028] Next, the component (312) is mounted inside a plasma processing chamber (step (128)). The plasma processing chamber is used to process metal-containing layers, for example, to etch metal-containing layers (step (132)).

[0029] The ability to clean metal containing residues from the component allows the component (312) to be reused instead of requiring the disposal of the component. Reusing the component (312) reduces costs and waste, reduces contamination of the devices to be processed, and increases device uniformity. Various embodiments use organic aqua regia instead of ordinary aqua regia to reduce damage to the surface of the component.

[0030] In some embodiments, additional cleaning steps may be provided. For example, a deionized water rinse may be provided after any wet cleaning steps. In other embodiments, additional wet cleaning steps may be provided. Other cleaning processes may be added in other embodiments. For example, scrubbing or beam blasting may be provided in other embodiments.

[0031] In other embodiments, other steps may be provided after the component (312) is re-mounted in the plasma processing chamber (step (128)) and before using the component in the plasma processing chamber (step (132)). For example, the plasma process may be used to condition or season the component (312).

[0032] In other embodiments, metal layers, such as a Ru-containing layer, may be used as a hard mask. These embodiments may not have a step of etching the metal-containing layer. However, residue from the Ru-containing layer may be deposited on parts of the plasma processing chamber. Other embodiments may have different metal-containing layers for different applications.

[0033] Although the present disclosure has been described in terms of several preferred embodiments, there are changes, substitutions, modifications, and various alternative equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Accordingly, the following appended claims are intended to be interpreted as including all such changes, substitutions, and various alternative equivalents that fall within the true spirit and scope of the present disclosure.

Claims

Claim 1 A residue cleaning method comprising ruthenium (Ru) residue, noble metal residue, and silicon oxide residue on at least one surface of a component of a semiconductor processing chamber, the method comprising: a step of exposing the residue to a Ru cleaning composition comprising at least one of hypochlorite and O3-based chemicals, wherein the Ru cleaning composition removes the Ru residue; a step of exposing the residue to a noble metal cleaning composition comprising thionyl chloride and pyridine in a solvent, wherein the noble metal cleaning composition removes the noble metal residue; and a step of exposing the residue to a silicon oxide wet cleaning solution comprising a passivating solution comprising an acid and an organic solvent, wherein the acid removes the silicon oxide residue and the passivating solution passivates at least one surface of the component. Claim 2 A residue cleaning method according to claim 1, wherein the step of exposing the residue comprises immersing the component in a bath of the Ru cleaning composition. Claim 3 A residue cleaning method according to claim 1, wherein the Ru cleaning composition further comprises ammonia. Claim 4 delete Claim 5 A residue cleaning method according to claim 1, wherein the solvent is an organic solvent. Claim 6 A residue cleaning method according to claim 5, wherein the organic solvent is at least one of dimethyl sulfoxide and dimethylformamide. Claim 7 delete Claim 8 A residue cleaning method according to claim 1, wherein the steps of exposing the residue to the Ru cleaning composition, exposing the residue to the precious metal cleaning composition, and exposing the residue to the silicon oxide wet cleaning solution are performed sequentially. Claim 9 A residue cleaning method according to claim 1, wherein the steps of exposing the residue to the Ru cleaning composition, exposing the residue to the precious metal cleaning composition, and exposing the residue to the silicon oxide wet cleaning solution are performed sequentially over a plurality of cycles. Claim 10 A residue cleaning method according to claim 1, wherein the steps of exposing the residue to the Ru cleaning composition, exposing the residue to the precious metal cleaning composition, and exposing the residue to the silicon oxide wet cleaning solution are performed simultaneously. Claim 11 A residue cleaning method according to claim 1, wherein at least two of the steps of exposing the residue to the Ru cleaning composition, exposing the residue to the precious metal cleaning composition, and exposing the residue to the silicon oxide wet cleaning solution are performed simultaneously. Claim 12 A residue cleaning method according to claim 1, wherein the acid of the silicon oxide wet cleaning solution comprises at least one of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Claim 13 A residue cleaning method according to claim 12, wherein the passivating solution comprises at least one of methylamine, ethyleneamine, ethylenediamine, diethylenetriamine, and acetylacetone. Claim 14 In claim 12, the residue cleaning method wherein the passivating solution comprises an organic solvent. Claim 15 A residue cleaning method according to claim 12, wherein the passivating solution comprises at least one of the group consisting of amines and acetone. Claim 16 A residue cleaning method according to claim 1, wherein the Ru cleaning composition further comprises water. Claim 17 A residue cleaning method comprising ruthenium (Ru) residue and precious metal residue from a component of a semiconductor processing chamber, the method comprising: a step of exposing the residue to a Ru cleaning composition comprising at least one of hypochlorite and O3-based chemicals, wherein the Ru cleaning composition removes the Ru residue; and a step of exposing the precious metal residue to a precious metal cleaning composition comprising thionyl chloride and pyridine, wherein the precious metal cleaning composition removes the precious metal residue. Claim 18 A residue cleaning method according to claim 17, wherein the precious metal cleaning composition further comprises an organic solvent. Claim 19 A residue cleaning method according to claim 18, wherein the organic solvent is at least one of dimethyl sulfoxide and dimethylformamide. Claim 20 In claim 17, the precious metal cleaning composition further comprises a solvent, a method for cleaning residues. Claim 21 A method for cleaning residues, including ruthenium (Ru) residues and silicon oxide residues, from at least one surface of a component of a semiconductor processing chamber, comprising: a step of exposing the residues to a Ru cleaning composition comprising at least one of hypochlorite and O3-based chemicals, wherein the Ru cleaning composition removes the Ru residues; and a step of exposing the residues to a silicon oxide wet cleaning solution comprising an acid and an organic solvent, wherein the acid removes the silicon oxide residues and the passivating solution passivates at least one surface of the component. Claim 22 A residue cleaning method according to claim 21, wherein the acid of the silicon oxide wet cleaning solution comprises at least one of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Claim 23 A residue cleaning method according to claim 22, wherein the passivating solution comprises at least one of methylamine, ethyleneamine, ethylenediamine, diethylenetriamine, and acetylacetone. Claim 24 In claim 22, the passivating solution comprises an organic solvent, a residue cleaning method. Claim 25 A residue cleaning method according to claim 22, wherein the passivating solution comprises at least one of the group consisting of amines and acetone.

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