Image sensor including spider routing

Abstract

The image sensor of the present disclosure includes a pixel array comprising a first column line and a second column line connected to pixels, and a reading circuit that receives pixel signals through the first column line and the second column line. The first column line includes a main wire, a first wire between one end of the main wire and a first interlayer connection area, and a second wire connected to the other end of the main wire, and the second column line includes a main wire, a first wire between one end of the main wire and a first interlayer connection area, and a second wire connected to the other end of the main wire. A first distance between the first column line and the second column line is longer than a second distance between the point where the first column line is connected to the first interlayer connection area and the point where the second column line is connected to the first interlayer connection area, and the length of the first wire of the first column line may be longer than the length of the second wire of the second column line.

Description

Technology Field

[0001] The present disclosure relates to an image sensor, and more specifically, to an image sensor comprising spider routing that prevents performance degradation due to differences in the time constant of a column line. Background Technology

[0002] Types of image sensors include CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors (CIS). A CMOS image sensor includes pixels composed of CMOS transistors, and converts light energy into electrical signals using photoelectric conversion elements included in each pixel. A CMOS image sensor acquires information regarding the captured image using the electrical signals generated from each pixel.

[0003] Recently, the rapid increase in the number of pixels in image sensors and the reduction in pixel size have made it possible to provide users with ultra-high-resolution (UHD) images. For example, to reduce chip size, analog-to-digital converters (ADCs) with a width narrower than the pixel array have been placed within the image sensor; this involves spider routing for the column lines through which pixel outputs are transmitted to the ADCs. However, spider routing causes differences in time constants between column lines, which degrades the performance of the image sensor. Therefore, providing routing that reduces these time constant differences between column lines has emerged as a critical issue. The problem to be solved

[0004] The technical concept of the present disclosure provides spider routing that prevents performance degradation due to differences in the time constants of the column lines of an image sensor. means of solving the problem

[0005] The image sensor of the present disclosure comprises a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line spaced apart from the first column line in a first direction, and a reading circuit that receives pixel signals through the first column line and the second column line connected to a first interlayer connection area, wherein the first column line includes a main wiring extending in a second direction perpendicular to the first direction, a first wiring between one end of the main wiring and the first interlayer connection area, and a second wiring connected to the other end of the main wiring, and the second column line includes a main wiring extending in the second direction, a first wiring between one end of the main wiring and the first interlayer connection area, and a second wiring connected to the other end of the main wiring, and the first distance between the first column line and the second column line is such that the point where the first column line is connected to the first interlayer connection area and the second column line is the first The distance between the point connected to the inter-layer connection area is longer than the second distance, and the length of the first wiring of the first column line may be greater than the length of the second wiring of the second column line. Effects of the invention

[0006] According to embodiments of the present disclosure, the performance of an image sensor can be improved by providing spider routing that causes the column lines of the image sensor to have the same time constant. Brief explanation of the drawing

[0007] FIG. 1 illustrates an exemplary configuration of an image sensor according to an embodiment of the present disclosure. Figure 2 illustrates an exemplary configuration of the image sensor of Figure 1. Figure 3 illustrates an exemplary circuit diagram of the pixel group of Figure 2. FIG. 4 illustrates a plan view of an image sensor of the present disclosure. FIG. 5 illustrates in detail an exemplary configuration of the column lines of the image sensor of FIG. 4. FIGS. 6a to 6c schematically illustrate the output of pixel signals according to the position of the column line. FIG. 7 illustrates a plan view of an image sensor of the present disclosure. FIG. 8 illustrates a plan view of an image sensor of the present disclosure. FIG. 9 illustrates an exemplary configuration of an image sensor according to an embodiment of the present disclosure. FIG. 10 illustrates a plan view of an image sensor of the present disclosure. FIG. 11 illustrates in detail an exemplary configuration of the column lines of the image sensor of FIG. 10. FIG. 12 shows a plan view of the image sensor of FIG. 1 or FIG. 9. FIG. 13 shows a cross-sectional view along the line II' of the image sensor of FIG. 12. FIG. 14 illustrates an exemplary configuration of an electronic device including a camera module in which the image sensor of the present disclosure is implemented. FIG. 15 illustrates an exemplary configuration of the camera module of FIG. 14. Specific details for implementing the invention

[0008] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0009] The components described by reference to terms such as part or unit, module, block, ~or, ~er used in the detailed description and the functional blocks illustrated in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0010] FIG. 1 illustrates an exemplary configuration of an image sensor according to an embodiment of the present disclosure. The image sensor (1) may include a first semiconductor chip (10) and a second semiconductor chip (20). The first semiconductor chip (10) may include a first interlayer connection area (111), a second interlayer connection area (112), a third interlayer connection area (113), and a pixel array (110). The second semiconductor chip (20) may include a fourth interlayer connection area (114), a fifth interlayer connection area (115), a sixth interlayer connection area (116), row drivers (120), analog-to-digital converters (130), a data bus (170), and a logic circuit (190).

[0011] Under the control of the logic circuit (190), the second semiconductor chip (20) can transmit a signal to the first semiconductor chip (10) to control the pixel array (110). For example, under the control of the logic circuit (190), the row driver (120) can transmit a control signal to control the pixels of the pixel array (110) to the pixel array (110) through the fifth interlayer connection area (115) and the second interlayer connection area (112), and / or through the sixth interlayer connection area (116) and the third interlayer connection area (113). The pixel array (110) can output a pixel signal, and the output pixel signal can be transmitted to analog-to-digital converters (130) through the first interlayer connection area (111) and the fourth interlayer connection area (114).

[0012] Analog-to-digital converters (130) and a logic circuit (190) can perform a correlated double sampling operation on a pixel signal, and the result of the correlated double sampling can be transmitted to the logic circuit (190) via a data bus (170). The logic circuit (190) may include a buffer for storing the result of the correlated double sampling, an Image Signal Processor Front End circuit, an ISP, etc. In this case, the logic circuit (190) can perform various processing operations on pixel data received from the analog-to-digital converters (130) via the data bus (170), such as crosstalk compensation, auto dark level compensation (ADLC) to remove fixed pattern noise (FPN), etc. Furthermore, the logic circuit (190) can further perform color interpolation, auto white balance, gamma correction, color saturation correction, formatting, bad pixel correction, hue correction, etc. on the pixel data.

[0013] In an embodiment, the length (s1) in the first direction (D1) of the pixel array (110) of the first semiconductor chip (10) may be greater than the length (s2) in the first direction (D1) of the first interlayer connection area (111). As a result, the lengths of the column lines through which the pixel outputs of the pixel array (110) are transmitted may differ from one another due to the difference in the length of the first wiring (a) of each column line. For example, the length of the column line placed in the middle of the pixel array (110) may be relatively short, and the length of the column line placed on the side of the pixel array (110) may be relatively long. Thus, the arrangement of column lines such that the distance between the first wirings is narrowed due to the difference between the length (s1) of the pixel array (110) and the length (s2) of the first interlayer connection area (111) may be referred to as spider routing.

[0014] In an embodiment, the length (s1) in the first direction (D1) of the row drivers (120) of the second semiconductor chip (20) and the analog-digital converters (130) may be generally (or substantially) the same as the length (S1) in the first direction (D1) of the pixel array (110) of the first semiconductor chip (10). That is, the length (s1) in the first direction (D1) of the pixel array (110) may be greater than the length (s2) in the first direction of the analog-digital converters (130). And, the length (s2) in the first direction of the analog-digital converters (130) may be generally (or substantially) the same as the length (s2) in the first direction (D1) of the fourth interlayer connection region (114).

[0015] Meanwhile, the difference in the length of the column lines due to the aforementioned spider routing results in differences in the resistance and capacitance values ​​of each column line, and results in differences in the time constant (RC constant). Furthermore, the difference in the time constant of the column lines may result in differences in the settling time of the pixel outputs output from the column lines. The image sensor (1) of the present disclosure may further include a second wiring (b) to solve the problem caused by the difference in the settling time of the pixel outputs. For example, the second wiring (b) may be part of the column line and may be provided in an area opposite to the area where the first wiring (a) is formed. As a result, by the wiring (b) additionally provided to the column line, the lengths of the column lines of the pixel array (110) may become equal to each other, and as a result, the time constants of each column line may become equal to each other.

[0016] FIG. 2 illustrates an exemplary configuration of the image sensor (1) of FIG. 1. The image sensor (100) may include a pixel array (110), a row driver (120), analog-to-digital converters (130), a timing controller (140), a ramp signal generator (150), a pixel boosting controller (160), a data bus (170), and a buffer (180). The pixel array (110), row driver (120), and analog-to-digital converters (130) of FIG. 2 may correspond to the pixel array (110), row drivers (120), and analog-to-digital converters (130) of FIG. 1, respectively. Also, the timing controller (140), ramp signal generator (150), pixel boosting controller (160), and buffer (180) of FIG. 2 may correspond to the logic circuit (190) of FIG. 1. And, analog-to-digital converters (130), timing controller (140), ramp signal generator (150), pixel boosting controller (160), and buffer (180) can be referred to as reading circuits.

[0017] A pixel array (110) may include a plurality of pixels (PX) arranged in a matrix form along rows and columns. Each of the plurality of pixels may include a photoelectric conversion element. Each of the plurality of pixels may detect light using the photoelectric conversion element and convert the detected light into an electrical signal (hereinafter, pixel signal). For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0018] A plurality of pixels constituting a pixel array (110) may include a plurality of pixel groups (PG). Each pixel group (PG) may include two or more pixels. For example, a pixel group (PG) may include nine pixels (PX) arranged in three rows and three columns, or four pixels (PX) arranged in two rows and two columns, but the number of pixels constituting a pixel group (PG) is not limited thereto.

[0019] Pixels constituting a pixel group (PG) may share at least one or more floating diffusion regions. For example, pixels constituting a pixel group (PG) may share only one floating diffusion region. In this case, the pixels of each pixel group (PG) may be commonly connected to one column line (e.g., CL1). Alternatively, pixels constituting a pixel group (PG) may share multiple floating diffusion regions. More specifically, pixels in the first column of a pixel group (PG) may share one floating diffusion region, pixels in the second column may share another floating diffusion region, and pixels in the third column may share yet another floating diffusion region. In this case, pixels in the first column of a pixel group (PG) illustrated in the drawing may be commonly connected to a column line (CL1), pixels in the second column may be commonly connected to a column line (CL2), and pixels in the third column may be commonly connected to a column line (CL3).

[0020] A pixel group (PG) may include pixels of the same type for outputting information related to the same color. For example, a pixel group (PG) may include red pixels (R) that convert light in the red spectrum region into an electrical signal, green pixels (Gr, Gb) that convert light in the green spectrum region into an electrical signal, or blue pixels (B) that convert light in the blue spectrum region into an electrical signal. To this end, a plurality of color filters may be formed on the pixel groups (PG) to form a multi-color filter array (Multi-CFA).

[0021] The row driver (120) can select and drive a row of the pixel array (110). The row driver (120) can decode an address and / or control signal generated by the timing controller (140) to generate control signals for selecting and driving a row of the pixel array (110). For example, the control signals may include a signal for selecting a pixel, a signal for resetting a floating diffusion region, a signal for selecting a column line, etc.

[0022] Analog-to-digital converters (130) can convert an analog signal (i.e., a pixel signal) output from a pixel array (110) into a digital signal. For example, the analog-to-digital converters (130) may include a plurality of analog-to-digital converters (130_1 to 130_n), and each analog-to-digital converter may include a comparator (COMP) and a counter (CNT). The comparator (COMP) can compare a pixel signal output through a column line (i.e., any one of CL1 to CLn) connected to the comparator (COMP) with a ramp signal (RAMP) received from a ramp signal generator (150) and output a comparison result. The comparator (COMP) may operate based on a correlated-double sampling (CDS) technique that acquires a reset signal and an image signal for the pixel signal and extracts the difference as a valid signal component. Each analog-to-digital converter may transmit the result of the correlated-double sampling to a buffer (180) via a data bus (170).

[0023] The counter (CNT) can count pulses of the corresponding comparator (COMP) output signal. For example, the counter (CNT) can be operated by various control signals, such as a counter clock signal generated by the timing controller (140), a counter reset signal that controls the reset of the counter (CNT), and an inversion signal that inverts the internal bits of the counter (CNT). The counter (CNT) can count comparison result signals according to the counter clock signal and output the counting result as a digital signal.

[0024] Counters (CNT) may include Up / Down Counters and Bit-wise Inversion Counters. Bit-wise Counters can perform operations similar to Up / Down Counters. For example, Bit-wise Counters can perform the function of performing only an Up count and the function of inverting all bits inside the counter to make them 1's complement when a specific signal is received. Bit-wise Counters can perform a reset count and then invert it to convert it into 1's complement, i.e., a negative value.

[0025] The timing controller (140) can generate control signals and / or clocks to control the operation and / or timing of each of the row driver (120), analog-to-digital converters (130), ramp signal generator (150), and pixel boosting controller (160).

[0026] The ramp signal generator (150) can generate a ramp signal (RAMP). The ramp signal generator (150) can operate under the control of the timing controller (140). For example, the ramp signal generator (150) can operate under control signals such as a ramp enable signal, a mode signal, etc. When the ramp enable signal is activated, the ramp signal generator (150) can generate a ramp signal (RAMP) having a slope set based on the mode signal.

[0027] The pixel boosting controller (160) can control the settling time of pixel signals output from column lines (CL1 to CLn). For example, the pixel boosting controller (160) can generate a signal to control the discharge of each column line so that the pixel signal output from each column line can be stabilized quickly.

[0028] The buffer (180) may include a set (182) of memories (MEMs) and a sensing amplifier (SA). Each memory (MEM) may receive a digital signal output from a corresponding analog-to-digital converter via a data bus (170) and store the received digital signal. The sensing amplifier (SA) may detect and amplify the stored digital signal. The sensing amplifier (SA) may output the amplified digital signal as image data (IDAT). For example, the image data (IDAT) may include information regarding the color of an object and information regarding the phase of an object.

[0029] FIG. 3 illustrates an exemplary circuit diagram of a pixel group (PG) of FIG. 2. The pixel group (PG) may include photoelectric conversion elements (PD1–PD4), transfer transistors (TG1–TG4), a dual conversion transistor (DCT), a reset transistor (RT), a driving transistor (DT), and a select transistor (ST). In addition to the configuration of the pixel group (PG), a switch (SW) and a current source (CS) for controlling the boosting of a pixel signal (PIX) are also illustrated. For example, the switch (SW) and the current source (CS) may be provided as part of the configuration of an analog-to-digital converter (130 in FIG. 2) or provided outside of the analog-to-digital converter.

[0030] The first pixel may include a first photoelectric conversion element (PD1) and a first transfer transistor (TG1). The second pixel may include a second photoelectric conversion element (PD2) and a second transfer transistor (TG2), and other pixels may each include similar components. Each of the first to fourth pixels may share a dual conversion transistor (DCT), a reset transistor (RT), a driving transistor (DT), a select transistor (ST), and a floating diffusion region (FD1).

[0031] Transfer transistors (TG1 to TG4) can transfer charges generated by photoelectric conversion elements (PD1 to PD4) to a first floating diffusion region (FD1). For example, during the period when the transfer transistor (TG1) is turned on by a transfer signal (VTG1) received from a low driver (120 in FIG. 2), charges provided from the photoelectric conversion element (PD1) can be accumulated in the first floating diffusion region (FD1). Transfer transistors (TG2 to TG4) can also operate in a similar manner so that charges provided from the photoelectric conversion elements (PD2 to PD4) can similarly be accumulated in the first floating diffusion region (FD1). One end of each of the transfer transistors (TG1 to TG4) can be connected to the photoelectric conversion elements (PD1 to PD4), and the other end can be connected in common to the first floating diffusion region (FD1).

[0032] The first floating diffusion region (FD1) can accumulate charges converted by at least one of the photoelectric conversion elements (PD1 to PD4). For example, the capacitance of the first floating diffusion region (FD1) is illustrated as the first capacitance (CFD1). The first floating diffusion region (FD1) can be connected to the gate terminal of a driving transistor (DT) operating as a source follower amplifier. As a result, a voltage potential corresponding to the charge accumulated in the first floating diffusion region (FD1) can be formed.

[0033] The reset transistor (RT) can be turned on by the reset signal (VRST) to provide a reset voltage (e.g., power supply voltage VDD) to the first floating diffusion region (FD1). As a result, the charge accumulated in the first floating diffusion region (FD1) moves to the power supply voltage (VDD) terminal, and the voltage of the first floating diffusion region (FD1) can be reset.

[0034] The driving transistor (DT) can amplify the change in electrical potential of the first floating diffusion region (FD1) and generate a corresponding voltage (i.e., pixel signal (PIX)). The select transistor (ST) can be driven by the select signal (VSEL) to select pixels to be read row by row. When the select transistor (ST) is turned on, the pixel signal (PIX) can be output through the column line (CL).

[0035] Meanwhile, under normal conditions, the first floating diffusion region (FD1) does not easily saturate, so there may not be a need to increase the capacitance (i.e., CFD1) of the first floating diffusion region (FD1). However, in a high-illumination environment, the first floating diffusion region (FD1) can easily saturate. Therefore, by turning on the dual conversion transistor (DCT) to prevent saturation, the first floating diffusion region (FD1) and the second floating diffusion region (FD2) can be electrically connected, and the capacitance of the floating diffusion regions (FD1, FD2) can be expanded to the sum of the first capacitance (CFD1) and the second capacitance (CFD2).

[0036] Furthermore, although not illustrated, the second floating diffusion region (FD2) may be electrically connected to the floating diffusion region of an adjacent pixel group (not illustrated) through a connection line (not illustrated), in which case the capacitance of the first floating diffusion region (FD1) may be further expanded. In this case, the pixel group (PG) may further include a switching element (e.g., a dual conversion transistor (DCT)) for electrically connecting the second floating diffusion region (FD2) to the floating diffusion region of an adjacent pixel group.

[0037] In an embodiment, when the image processing device operates in normal mode, pixel signals (PIX) output from each pixel constituting a pixel group (PG) can be used individually. That is, the timing controller (Fig. 2, 140) controls the transmission signals (VTG1 to VTG4) so ​​that each of the transmission transistors (TG1 to TG4) turns on at different timings, thereby allowing pixel signals (PIX) corresponding to charges converted by each photoelectric conversion element to be output at different timings through the column line (CL).

[0038] In an embodiment, when the image sensor (100) operates in binning mode, charges converted by pixels (PX1 to PX4) constituting a pixel group (PG) can be used simultaneously to generate a single pixel signal (PIX). For example, transfer transistors (TG1 to TG4) can be turned on simultaneously or at other times so that charges converted by pixels (PX1 to PX4) can be accumulated in a first floating diffusion region (FD1), and a pixel signal (PIX) corresponding to the sum of charges converted by photoelectric conversion elements (PD1 to PD4) can be output through a column line (CL).

[0039] Meanwhile, the potential of the column line (CL) can be increased by coupling between the transfer transistors (TG1~TG4) and the column line (CL), or by coupling between the reset transistor (RT) and the column line (CL), and a current source (CS) and a switch (SW) can be used to quickly lower the potential of the column line (CL). For example, a pixel boosting controller (Fig. 2, 160) can generate a boosting control signal to control the switch (SW), and the potential of the column line (CL) can be controlled by switching the switch (SW) according to the boosting control signal.

[0040] FIG. 4 illustrates a plan view of an image sensor of the present disclosure. FIG. 5 illustrates in detail an exemplary configuration of column lines (CL1, CL4) of the image sensor of FIG. 4. For example, FIG. 4 illustrates the top plate and bottom plate of the image sensor (1) illustrated in FIG. 1, and the pixel array is illustrated as including eight column lines (CL1 to CL8). Additionally, the first interlayer connection area (111) and the fourth interlayer connection area (114) are electrically connected by eight wires, and the fourth interlayer connection area (114) and the analog-to-digital converters (130) are also electrically connected by eight wires. Hereinafter, the configuration of the spider routing of the present disclosure will be described with reference to FIG. 4 and FIG. 5 together.

[0041] In an embodiment, column lines (CL1 to CL4) may be arranged across a main routing area (RT0), a first routing area (RT1), and a second routing area (RT2). For example, regarding the arrangement of the first column line (CL1), a main wiring extending in the second direction (D2) of the first column line (CL1) may be arranged on the main routing area (RT0). A first wiring (a1) of the first column line (CL1) may be connected between one end of the main wiring and the first inter-layer connection area (111) on the first routing area (RT1). Additionally, a second wiring (a2) of the first column line (CL1) may be connected to the other end of the main wiring on the second routing area (RT2). Similarly, another column line (e.g., CL4) may also include a main wiring positioned on a main routing area (RT0), a first wiring (a4) positioned on a first routing area (RT1), and a second wiring (b4) positioned on a second routing area (RT2).

[0042] In an embodiment, as the length of the first wiring (a1) of a specific column line (e.g., CL1) increases, the length of the second wiring (b1) may become shorter, and as the length of the first wiring (a1) decreases, the length of the second wiring (b1) may become longer. Also, due to the second wirings (e.g., b1, b4) placed on the second routing area (RT2), the lengths of the column lines (CL1, CL4) may become equal to each other. As a result, the resistance values ​​of the column lines (CL1, CL4) may become equal to each other, and the capacitance values ​​may also become equal to each other. Consequently, since the time constants of the column lines (CL1, CL4) become equal to each other, the settling time of the pixel signal output through the first column line (CL1) and the settling time of the pixel signal output through the fourth column line (CL4) may become equal to each other. This can be applied equally to other column lines (CL2~CL3, CL5~CL8).

[0043] In an embodiment, the distance (d0) between the main wires of two column lines (e.g., CL1, CL4) may be greater than the distance between the first wires (a1, a4) of the two column lines (CL1, CL4). Specifically, the distance (d0) between the points where each main wire of the column lines (CL1, CL4) and the first wire meet may be greater than the distance (d1) between the points where each first wire of the column lines (CL1, CL4) and the first interlayer connection area (111) meet.

[0044] In an embodiment, the distance (d0) between the main wires of two column lines (e.g., CL1, CL4) may be greater than the distance between the second wires (b1, b4) of the two column lines (CL1, CL4). Specifically, the distance (d0) between the points where the main wire of each column line (CL1, CL4) and the second wire meet may be greater than the distance (d2) between the points where the routing of each second wire of the column lines (CL1, CL4) ends. For example, the distance (d1) may be equal to or different from the distance (d2).

[0045] FIGS. 6a through 6c schematically illustrate the output of a pixel signal according to the position of a column line. Specifically, FIGS. 6a and 6b show the outputs of a pixel signal when wiring (e.g., FIG. 5, b1, b4) is not provided in the second routing area (Fig. 5, RT2) as in the present disclosure, and FIG. 6c shows the output of a pixel signal when wiring (Fig. 5, b1, b4) is provided in the second routing area (Fig. 5, RT2) of the present disclosure.

[0046] First, referring to FIGS. 1 to 5 and FIG. 6a, in order to control the voltage due to coupling between the transfer transistors (TG1 to TG4) and the column line, the pixel boosting controller (160) can apply a boosting control signal to the switch (SW) between t1 and t2. Then, in order to control the voltage due to coupling between the reset transistor (RT) and the column line, the pixel boosting controller (160) can apply a boosting control signal to the switch (SW) between t5 and t6.

[0047] However, if the pixel boosting controller (160) is optimized to settle the pixel output of a column line (e.g., CL4) placed in the center of the pixel array (110), a problem may occur with the settling time of a column line (e.g., CL1) placed at the edge of the pixel array (110), as shown in the graph in FIG. 6a.

[0048] Specifically, because the time constant of the pixel output of the first column line (CL1) is greater than the time constant of the pixel output of the fourth column line (CL4), the pixel output of the first column line (CL1) may not be completely settled even after t1 to t2, when the first boosting control signal is applied, has elapsed. Additionally, additional time (T1) may be required for the pixel output of the first column line (CL1) to be completely settled. Similarly, even after t5 to t6, when the second boosting control signal is applied, the pixel output of the first column line (CL1) may not be completely settled, and additional time (T2) may be required for the pixel output of the first column line (CL1) to be completely settled.

[0049] Conversely, even if the pixel boosting controller (160) is optimized to settle the pixel output of a column line (e.g., CL1) placed at the edge of the pixel array (110), a problem may occur with the settling time of a column line (e.g., CL4) placed at the center of the pixel array (110), as shown in the graph in FIG. 5b.

[0050] Specifically, since the time constant of the pixel output of the fourth column line (CL4) is smaller than the time constant of the pixel output of the first column line (CL1), when the first boosting control signal is applied, the pixel output of the fourth column line (CL4) may be discharged more than necessary. Therefore, additional time (T3) may be required for the pixel output of the first column line (CL4) to be completely settled. Similarly, when the second boosting control signal is applied, when the second boosting control signal is applied, the pixel output of the fourth column line (CL4) may be discharged more than necessary, and additional time (T4) may be required for the pixel output of the fourth column line (CL4) to be completely settled.

[0051] Consequently, if the lengths of the column lines of the pixel array (110) are different, additional times (T1, T2) may be required to completely settle the column line (CL1) placed at the edge of the pixel array (110), or additional times (T3, T4) may be required to completely settle the column line (CL4) placed at the center of the pixel array (110). Consequently, this may result in a decrease in the performance of the image sensor.

[0052] However, as in the embodiment of the present disclosure, by placing the second wiring in the second routing area (RT2), the time constants of each column line can be made equal to each other, and no additional time is required for the pixel boosting controller (160) to completely settle the pixel output regardless of the optimization of the pixel output of a specific column line. For example, referring to FIG. 6c, the pixel output of column lines (CL1, CL4) can be completely settled at t2 by a boosting control signal applied between t1 and t2, and the pixel output of column lines (CL1, CL4) can be completely settled at t6 by a boosting control signal applied between t5 and t6. Thus, the interval between t2 and t4 can be further reduced, thereby improving the operating speed of the image sensor.

[0053] FIG. 7 illustrates a plan view of an image sensor of the present disclosure. Similar to FIG. 4, FIG. 7 illustrates the top and bottom surfaces of the image sensor (1) illustrated in FIG. 1, and the pixel array is illustrated as including eight column lines (CL1 to CL8).

[0054] In an embodiment, the first column line (CL1) may include a first wiring (a1) connected to the first interlayer connection area (111) and may further include a second wiring (b1). For example, the second wiring (b1) may extend straight along the second direction (D2). Also, the fourth column line (CL4) may further include a second wiring (b4) in addition to the first wiring (a4) connected to the first interlayer connection area (111). For example, the second wiring (b4) may be arranged to form two right angles. Here, the second wiring (b4) may have a spiral shape as it is arranged to form two right angles. Due to the second wiring (b1, b4) placed at the other ends of the column lines (CL1, CL4), the time constants of the column lines (CL1, CL4) can be equal to each other, and the settling times of the pixel signals output through the column lines (CL1, CL4) can be equal to each other. This can be applied equally to other column lines (CL2~CL3, CL5~CL8).

[0055] FIG. 8 illustrates a plan view of an image sensor of the present disclosure. Since the embodiment of FIG. 8 is generally similar to the embodiment of FIG. 4 and FIG. 7, redundant descriptions are omitted.

[0056] In an embodiment, the first column line (CL1) may include a first wiring (a1) connected to the first interlayer connection area (111) and may further include a second wiring (b1) extending straight along the second direction (D2). Additionally, the fourth column line (CL4) may further include a second wiring (b4) in addition to the first wiring (a4) connected to the first interlayer connection area (111). For example, the second wiring (b4) may be arranged to form at least one protrusion, and, exemplarily, the second wiring (b4) is shown to include three protrusions. For example, the protrusions may extend in a direction different from the direction in which the second wiring (b4) extends (i.e., D2). Similarly, the second wiring of the second column line (CL2) is shown to include one protrusion, and the second wiring of the third column line (CL3) is shown to include two protrusions. By arranging the second wirings having the protrusions shown in FIG. 6, the settling times of pixel signals output through the column lines (CL1–CL4) can be equal to each other.

[0057] FIG. 9 illustrates an exemplary configuration of an image sensor according to an embodiment of the present disclosure. The image sensor (1) may include a first semiconductor chip (10) and a second semiconductor chip (20). The first semiconductor chip (10) may include a first interlayer connection area (111), a second interlayer connection area (112), a third interlayer connection area (113), and a pixel array (110). The second semiconductor chip (20) may include a fourth interlayer connection area (114), a fifth interlayer connection area (115), a sixth interlayer connection area (116), row drivers (120), analog-to-digital converters (130), a data bus (170), and a logic circuit (190). Hereinafter, since the image sensor of FIG. 9 is generally similar to the image sensor of FIG. 1, redundant descriptions are omitted.

[0058] The pixel array (110) can output a pixel signal, and the output pixel signal can be transmitted to analog-to-digital converters (130) through the first interlayer connection area (111) and the fourth interlayer connection area (114). Here, unlike the embodiment of FIG. 1, the length of the pixel array (110) of the first semiconductor chip (10) in the first direction (D1) and the length of the first interlayer connection area (111) in the first direction (D1) may be substantially (or generally) the same as s1. Also, the length of the first interlayer connection area (111) in the first direction (D1) and the length of the fourth interlayer connection area (114) may be substantially (or generally) the same as s1. Therefore, spider routing may not be formed between the pixel array (110) of the first semiconductor chip (10) and the first interlayer connection area (111).

[0059] In an embodiment, the length (s2) of the analog-to-digital converters (130) in the first direction (D1) may be smaller than the length (s1) of the fourth interlayer connection area (114) in the first direction (D1). As a result, the lengths of the column lines through which the pixel outputs of the pixel array (110) are transmitted may differ from one another due to the difference in the length of the third routing (c) of the column lines. For example, the length of the column line placed in the middle of the pixel array (110) may be relatively short, and the length of the column line placed on the side of the pixel array (110) may be relatively long. Thus, spider routing may be formed on the second semiconductor chip (20).

[0060] FIG. 10 illustrates a plan view of an image sensor of the present disclosure. FIG. 11 illustrates in detail an exemplary configuration of column lines (CL1, CL4) of the image sensor of FIG. 10. For example, FIG. 10 illustrates the top and bottom surfaces of the image sensor (1) illustrated in FIG. 9, and the pixel array is illustrated as including eight column lines (CL1 to CL8).

[0061] In an embodiment, the first column line (CL1) may include a main wire positioned on the main routing area (RT0) and having one end connected to the first inter-layer connection area (111), and a first wire (a1) positioned on the first routing area (RT1) and connected to the other end of the main wire. Additionally, the fourth column line (CL4) may include a main wire positioned on the main routing area (RT0) and having one end connected to the first inter-layer connection area (111), and a first wire (a4) positioned on the first routing area (RT1) and connected to the other end of the main wire.

[0062] In an embodiment, the fourth interlayer connection area (114) and the analog-to-digital converters (130) may be electrically connected by wiring placed on the second routing area (RT2). For example, wiring (b1) may be electrically connected to the first column line (CL1) through the interlayer connection areas (111, 114), and wiring (b4) may be electrically connected to the fourth column line (CL4) through the interlayer connection areas (111, 114).

[0063] In the embodiment, as the length of the wiring (b1) increases, the length of the first wiring (a1) of the first column line (CL1) may become shorter, and as the length of the wiring (b1) decreases, the length of the first wiring (a1) may become longer. Also, due to the first wirings (e.g., a1, a4) placed on the first routing area (RT1), the length of the wiring from the first column line (CL1) to the fourth interlayer connection area (114) and the length of the wiring from the fourth column line (CL4) to the fourth interlayer connection area (114) may become equal to each other. As a result, the resistance values ​​of the column lines (CL1, CL4) may become equal to each other, and the capacitance values ​​may also become equal to each other. As a result, since the time constants of the column lines (CL1, CL4) become equal to each other, the settling time of the pixel signal output through the first column line (CL1) and the settling time of the pixel signal output through the fourth column line (CL4) can become equal to each other. This can be applied equally to the other column lines (CL2~CL3, CL5~CL8).

[0064] In an embodiment, the distance (d0) between the main wires of two column lines (e.g., CL1, CL4) may be greater than the distance between the first wires (a1, a4) of the two column lines (CL1, CL4). Specifically, the distance (d0) between the points where each main wire of the column lines (CL1, CL4) and the first wire meet may be greater than the distance (d1) between the points where the routing of each first wire of the column lines (CL1, CL4) ends.

[0065] And, the distance (d0) between the main wires of the two column lines (e.g., CL1, CL4) may be greater than the distance between the two wires (b1, b4). Specifically, the distance (d0) between the column lines (CL1, CL4) may be greater than the distance (d2) between the points where each of the second wires (b1, b4) comes into contact with the corresponding analog-to-digital converter. For example, the distance (d1) may be equal to or different from the distance (d2).

[0066] Due to the first wiring (a1, a4) placed at the other ends of the column lines (CL1, CL4), the time constants of the column lines (CL1, CL4) can be equal to each other. Therefore, the settling times of the pixel signals output through the column lines (CL1, CL4) can be equal to each other. Meanwhile, although not shown in a separate drawing, the wiring shown in FIG. 7 and FIG. 8 can be derived by modifying the shape of the wiring (a1, a4) shown in FIG. 11.

[0067] FIG. 12 illustrates a plan view of the image sensor of FIG. 1 or FIG. 9. The image sensor (1) may include pixel groups (PG1 to PG4). Pixel groups (PG1 to PG4) may be repeatedly formed on the substrate of the image sensor along a first direction (D1) and a second direction (D2). Each of the pixel groups (PG1 to PG4) may include 2 x 2 pixels arranged along the first direction (D1) and the second direction (D2). Each pixel may include a photoelectric conversion element (PD).

[0068] Color filters (CF1 to CF4) for transmitting light of a specific wavelength band may be formed on each of the pixel groups (PG1 to PG4). For example, the first color filter (CF1) and the fourth color filter (CF4) may transmit green light, the second color filter (CF2) may transmit red light, and the third color filter (CF3) may transmit blue light. As illustrated, the second color filter (CF2) is adjacent to the first color filter (CF1) in the first direction (D1), and the third color filter (CF3) is adjacent to the fourth color filter (CF4) in the first direction (D1), thereby forming a Bayer pattern. Additionally, a microlens (ML) may be formed on the color filter formed on each pixel.

[0069] FIG. 13 illustrates a cross-sectional view along line I-I' of the image sensor of FIG. 12. The image sensor (1) may include a first semiconductor chip (10) and a second semiconductor chip (20). For example, the first semiconductor chip (10) may correspond to the first semiconductor chip (10) described through FIG. 1 to FIG. 11, and the second semiconductor chip (20) may correspond to the second semiconductor chip (20) described through FIG. 1 to FIG. 11.

[0070] The image sensor (1) may include a substrate (SUB) comprising a first surface (11a) and a second surface (11b) facing each other. The first substrate (SUB1) may include a single-crystal substrate or an epitaxial layer. The first substrate (SUB1) may include a region (11) doped with impurities of a first conductivity type (e.g., P-type) and a region (12) doped with impurities of a second conductivity type (e.g., N-type). The first doped region (11) and the second doped region (12) may constitute a photoelectric conversion element (PD) that constitutes each pixel. When light is incident on the photoelectric conversion element (PD) through a microlens (ML) and a color filter (any one of CF1 to CF4), electron-hole pairs (EHPs) corresponding to the intensity of the absorbed light may be generated.

[0071] A fixed charge film (13) may be formed on the first surface (11a) of the first substrate (SUB1). The fixed charge film (13) may include various types of metal oxides and / or metal fluorides. For example, the fixed charge film (13) may be Al2O3, HfO2 X (X is a natural number), may include at least one or more of SiO2 and SiN. An interlayer insulating film (16) may be formed on the second surface (11b) of the first substrate (SUB1). For example, the interlayer insulating film (16) may include multiple insulating films. For example, the interlayer insulating film (16) may be covered with a passivation film (not shown). For example, the passivation film may include a silicon nitride film.

[0072] Meanwhile, each of the pixels (PX1 to PX4) may include a floating diffusion region (FD) and a transfer transistor (TG). Furthermore, although not illustrated for the sake of illustration, each of the pixels (PX1 to PX4) may further include a reset transistor, a driving transistor, and a select transistor. The pixels (PX1 to PX4) may be separated from each other by a deep trench isolator (DTI). When a transfer signal is applied to the gate electrode of the transfer transistor (TG) and the transfer transistor (TG) is turned on, charges generated in the first doping region (11) and the second doping region (12) move to the floating diffusion region (FD). The charges in the floating diffusion region (FD) may be transferred to the outside (e.g., a second semiconductor chip, 20) through internal wiring (17) and vias (not illustrated) connecting the internal wiring (17).

[0073] A separation layer (14) may be formed on the fixed charge layer (13). The separation layers (14) may include tungsten, titanium, etc. The separation layers (14) may prevent crosstalk between adjacent pixels. In a planar view, the separation layers (14) may have a grid shape. Color filters (CF1~CF4) may be formed on the fixed charge layer (13) between the separation layers (14). Microlenses (ML) may be formed on the color filters (CF1~CF4).

[0074] The image sensor (1) may include a second substrate (SUB2). The image sensor (1) may include transistors (TR) formed on the second substrate (SUB2). The second substrate (SUB2) may be a p-type semiconductor substrate doped with impurities (e.g., a silicon substrate, a germanium substrate, or a silicon-germanium substrate).

[0075] The transistors (TR) formed on the second substrate (SUB2) can form the logic circuit (190) of FIG. 1 or FIG. 9. Active patterns (FN) may be formed on the second substrate (SUB2). Device isolation films (ST) that fill the spaces between the active patterns (FN) may be formed. For example, the device isolation films (ST) may include silicon oxide films. Each of the device isolation films (ST) may have a depth in a direction opposite to the third direction (D3). The third direction (D3) may be a direction perpendicular to the upper surface of the second substrate (SUB2).

[0076] Gate electrodes (GP) may be formed on an active pattern (FN) and extend in a second direction (D2) intersecting the active pattern (FN). The gate electrodes (GP) may be formed spaced apart from each other in a first direction (D1). A gate insulating pattern (GI) may be formed below each gate electrode (GP), and gate spacers (GS) may be formed on both sides of each gate electrode (GP). Furthermore, a capping pattern (CP) covering the upper surface of each gate electrode (GP) may be formed. An interlayer insulating film (21) covering the gate electrode (GP) may be formed.

[0077] The gate electrodes (GP) may include at least one of a doped semiconductor, a metal, and a conductive metal nitride. The gate insulation pattern (GI) may include a silicon oxide film, a silicon oxynitride film, or a high dielectric film having a dielectric constant higher than that of a silicon oxide film. The capping pattern (CP) and the gate spacers (GS) may each include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0078] Source / drain regions (SD) may be formed on active patterns (FN) located on both sides of each gate electrode (GP). The source / drain regions (SD) may be p-type or n-type impurity regions. The source / drain regions (SD) may be epitaxial patterns formed by an optional epitaxial growth process.

[0079] Source / drain regions (SD) may include semiconductor elements different from the second substrate (SUB2). For example, the source / drain regions (SD) may include semiconductor elements having a lattice constant greater than or smaller than the lattice constant of the semiconductor elements of the second substrate (SUB2). By the source / drain regions (SD) including semiconductor elements different from the second substrate (SUB2), compressive stress or tensile stress may be applied to the channel regions (AF) between the source / drain regions (SD).

[0080] For example, if the second substrate (SUB2) is a silicon substrate, the source / drain regions (SD) of the P-type MOSFET region may comprise silicon-germanium (embedded SiGe) or germanium. In this case, the source / drain regions (SD) may provide compressive stress to the channel regions (AF). As another example, if the second substrate (SUB2) is a silicon substrate, the source / drain regions (SD) of the N-type MOSFET region may comprise silicon carbide (SiC). In this case, tensile stress may be applied to the channel regions (AF). As a result, the mobility of carriers generated within the channel regions (AF) may be improved.

[0081] Source / drain contacts (CA) may be formed between gate electrodes (GP). The source / drain contacts (CA) are directly connected to source / drain regions (SD) and may be electrically connected to them. The source / drain contacts (CA) may be provided within the interlayer insulating film (21).

[0082] Gate contacts (CB) may be formed on the interlayer insulating film (21). Each gate contact (CB) may be directly connected to the gate electrode (GP) by penetrating the capping pattern (CP). The bottom surface of the gate contact (CB) may be located at a higher level than the bottom surface of the source / drain contact (CA). Furthermore, the bottom surface of the gate contact (CB) may be located at a higher level than the top surface of the source / drain region (SD).

[0083] An interlayer insulating film (22) may be formed on a second substrate (SUB). The interlayer insulating film (22) may include multiple insulating films. A signal processed by a logic circuit (e.g., FIG. 1, 190) composed of transistors (TR) may be transmitted to the outside of the image sensor (1) through internal wiring (23) and vias (not shown) connecting the internal wiring (23). Alternatively, charges of the floating diffusion region (FD) of the first semiconductor chip (10) may be transmitted to an analog-to-digital converter (Fig. 1, 130) composed of transistors (TR) through an insertion layer (30), internal wiring (23), and vias (not shown) connecting the internal wiring (23).

[0084] The insertion layer (30) can physically and / or electrically connect the first semiconductor chip (10) and the second semiconductor chip (20). For example, the insertion layer (30) can correspond to wiring that electrically connects the first interlayer connection region (111) and the fourth interlayer connection region (114) shown in FIG. 4.

[0085] The insertion layer (30) may include a first insulating film (31), a first conductive pattern (32), a second insulating film (33), and a second conductive pattern (34). The conductive patterns (32, 34) may be electrically connected by direct contact with each other, and the conductive patterns (32, 34) may electrically connect the internal wiring (17) of the first semiconductor chip (10) and the internal wiring (23) of the second semiconductor chip (20). The conductive patterns (32, 34) may be implemented using contact of conductive patterns such as copper or tungsten, TSV, BVS, etc. The first conductive pattern (32) and the second conductive pattern (34) may be provided within the first insulating film (31) and the second insulating film (33), respectively. For example, the first insulating film (31) and the second insulating film (33) may include silicon oxide films.

[0086] Furthermore, the insertion layer (30) may further include metal diffusion barrier layers (not shown) provided between the first semiconductor chip (10) and the first insulating layer (31), between the first insulating layer (31) and the second insulating layer (33), and between the second insulating layer (33) and the second semiconductor chip (20), respectively. In this case, the metal diffusion barrier layers may include SiN, SiCN, SiOCN, SiON, or SiC. The metal diffusion barrier layers can prevent metal components from diffusing from the connection portions (32, 34).

[0087] FIG. 14 illustrates an exemplary configuration of an electronic device including a camera module in which an image sensor of the present disclosure is implemented. FIG. 15 illustrates an exemplary configuration of the camera module of FIG. 14.

[0088] Referring to FIG. 14, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400).

[0089] The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although an electronic device including three camera modules (1100a, 1100b, 1100c) is illustrated as an example in the drawings, it is not limited thereto. In some embodiments, the camera module group (1100) may be modified to include only two camera modules. Also, in some embodiments, the camera module group (1100) may be modified to include n camera modules (n is a natural number greater than or equal to 4).

[0090] Hereinafter, with reference to FIG. 15, the detailed configuration of the camera module (1100b) will be described in more detail, but the following description may be applied equally to other camera modules (1100a, 1100b) according to the embodiment.

[0091] Referring to FIG. 15, the camera module (1100b) may include a prism (1105), an optical path folding element (OPFE) (1110), an actuator (1130), an image sensing device (1140), and a storage (1150).

[0092] The prism (1105) can modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material.

[0093] In some embodiments, the prism (1105) can change the path of light (L) incident in a first direction (X) to a second direction (Y) perpendicular to the first direction (X). Additionally, the prism (1105) can change the path of light (L) incident in the first direction (X) to a second direction (Y) perpendicular by rotating the reflective surface (1107) of the light-reflecting material in direction A around the central axis (1106) or by rotating the central axis (1106) in direction B. At this time, the OPFE (1110) can also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0094] In some embodiments, as illustrated, the maximum rotation angle of the prism (1105) in the A direction may be 15 degrees or less in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, but the embodiments are not limited thereto.

[0095] In some embodiments, the prism (1105) can move in the plus (+) or minus (-) B direction by about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be moved by the same angle in the plus (+) or minus (-) B direction, or by a nearly similar angle within a range of about 1 degree.

[0096] In some embodiments, the prism (1105) can move the reflective surface (1106) of the light-reflecting material in a third direction (e.g., Z direction) parallel to the extension direction of the central axis (1106).

[0097] OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The m lenses can be moved in a second direction (Y) to change the optical zoom ratio of the camera module (1100b). For example, when the basic optical zoom ratio of the camera module (1100b) is Z, moving the m optical lenses included in the OPFE (1110) may change the optical zoom ratio of the camera module (1100b) to 3Z or 5Z or an optical zoom ratio of 5Z or more.

[0098] The actuator (1130) can move the OPFE (1110) or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator (1130) can adjust the position of the optical lens so that the image sensor (1142) is positioned at the focal length of the optical lens for accurate sensing.

[0099] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) may sense an image of a sensing target using light (L) provided through an optical lens. The control logic (1144) may control the overall operation of the camera module (1100b) and may include the aforementioned logic circuit. For example, the control logic (1144) may control the operation of the camera module (1100b) according to a control signal provided through a control signal line (CSLb).

[0100] The memory (1146) can store information necessary for the operation of the camera module (1100b), such as calibration data (1147). The calibration data (1147) may include information necessary for the camera module (1100b) to generate image data using light (L) provided from the outside. The calibration data (1147) may include, for example, information regarding the degree of rotation described above, information regarding the focal length, information regarding the optical axis, etc. If the camera module (1100b) is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data (1147) may include focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing. Additionally, the memory (1146) may store information regarding the ROI necessary for the movement of the angle of view of the present disclosure.

[0101] Storage (1150) can store image data sensed through the image sensor (1142). Storage (1150) may be placed outside the image sensing device (1140) and may be implemented in a stacked form with the sensor chip constituting the image sensing device (1140). In some embodiments, storage (1150) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but embodiments are not limited thereto.

[0102] Referring to FIG. 14 and FIG. 15 together, in some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may include an actuator (1130). Accordingly, each of the plurality of camera modules (1100a, 1100b, 1100c) may include identical or different calibration data (1147) according to the operation of the actuator (1130) included therein.

[0103] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100b) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but the embodiments are not limited thereto.

[0104] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data provided from the depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0105] In some embodiments, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different viewing angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0106] Additionally, in some embodiments, the angle of view of each of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also be different from each other, but are not limited thereto.

[0107] In some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0108] Referring again to FIG. 14, the application processor (1200) may include an image sensor (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separately from a plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor (1200) and the plurality of camera modules (1100a, 1100b, 1100c) may be implemented separately from each other as separate semiconductor chips.

[0109] The image sensor (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216). The image sensor (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0110] Image data generated from each of the camera modules (1100a, 1100b, 1100c) can be provided to corresponding sub-image processors (1212a, 1212b, 1212c) through separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from the camera module (1100a) can be provided to the sub-image processor (1212a) through the image signal line (ISLa), image data generated from the camera module (1100b) can be provided to the sub-image processor (1212b) through the image signal line (ISLb), and image data generated from the camera module (1100c) can be provided to the sub-image processor (1212c) through the image signal line (ISLc). Such image data transmission can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but embodiments are not limited thereto.

[0111] Meanwhile, in some embodiments, a single sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor (1212a) and the sub-image processor (1212c) may not be implemented separately as illustrated, but rather integrated into a single sub-image processor, and image data provided from the camera module (1100a) and the camera module (1100c) may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0112] Image data provided to each sub-image processor (1212a, 1212b, 1212c) can be provided to an image generator (1214). The image generator (1214) can generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0113] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal.

[0114] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based, for example, on a mode selected by a user.

[0115] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different viewing angle, the image generator (1214) can perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, the image data output from the camera module (1100a) and the image data output from the camera module (1100c) are merged, and then an output image can be generated using the merged image signal and the image data output from the camera module (1100b) that was not used for merging.

[0116] If the zoom signal is a second signal different from the first signal, the image generator (1214) may not perform such image data merging and may generate an output image by selecting any one of the image data output from each camera module (1100a, 1100b, 1100c). However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0117] In some embodiments, the image generator (1214) receives multiple image data with different exposure times from at least one of a plurality of sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0118] The camera module controller (1216) can provide control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0119] One of the plurality of camera modules (1100a, 1100b, 1100c) may be designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a, 1100c) may be designated as slave cameras. This information may be included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0120] The camera module operating as a master and slave may be changed according to the zoom factor or operation mode signal. For example, if the field of view of the camera module (1100a) is wider than that of the camera module (1100b) and the zoom factor indicates a low zoom magnification, the camera module (1100b) may operate as a master and the camera module (1100a) may operate as a slave. Conversely, if the zoom factor indicates a high zoom magnification, the camera module (1100a) may operate as a master and the camera module (1100b) may operate as a slave.

[0121] In some embodiments, the control signal provided from the camera module controller (1216) to each camera module (1100a, 1100b, 1100c) may include a sync enable signal. For example, if the camera module (1100b) is a master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller (1216) may transmit a sync enable signal to the camera module (1100b). The camera module (1100b) that receives the sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules (1100a, 1100c) through a sync signal line (SSL). The camera module (1100b) and camera modules (1100a, 1100c) can be synchronized with this sync signal to transmit image data to the application processor (1200).

[0122] In some embodiments, a control signal provided from a camera module controller (1216) to a plurality of camera modules (1100a, 1100b, 1100c) may include mode information according to a mode signal. Based on this mode information, the plurality of camera modules (1100a, 1100b, 1100c) may operate in a first operation mode and a second operation mode with respect to the sensing speed.

[0123] A plurality of camera modules (1100a, 1100b, 1100c) can, in a first operating mode, generate an image signal at a first speed (e.g., generate an image signal at a first frame rate) and encode it at a second speed higher than the first speed (e.g., encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to an application processor (1200). At this time, the second speed may be 30 times or less of the first speed.

[0124] The application processor (1200) can store the received image signal, i.e., the encoded image signal, in a memory (1230) provided internally or in storage (1400) outside the application processor (1200), read the encoded image signal from the memory (1230) or storage (1400) and decode it, and display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image sensor (1210) can perform decoding, and can also perform image processing on the decoded image signal.

[0125] A plurality of camera modules (1100a, 1100b, 1100c) can generate an image signal at a third speed lower than a first speed in a second operation mode (e.g., generate an image signal at a third frame rate lower than a first frame rate) and transmit the image signal to an application processor (1200). The image signal provided to the application processor (1200) may be an unencoded signal. The application processor (1200) may perform image processing on the received image signal or store the image signal in memory (1230) or storage (1400).

[0126] The PMIC (1300) can supply power, such as power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0127] The PMIC (1300) can generate power corresponding to each of the plurality of camera modules (1100a, 1100b, 1100c) and adjust the power level in response to a power control signal (PCON) from the application processor (1200). The power control signal (PCON) may include power adjustment signals for each operating mode of the plurality of camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the power level being set. The power levels provided to each of the plurality of camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Additionally, the power level may be changed dynamically.

[0128] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention. Explanation of the symbols

[0129] 1: Image sensor 10: The first semiconductor chip 20: The second semiconductor chip

Claims

Claim 1 A pixel array comprising a first pixel connected to a first column line, and a second pixel connected to a second column line spaced apart from the first column line in a first direction; And a reading circuit that receives pixel signals through the first column line and the second column line connected to the first interlayer connection area, wherein the first column line includes a main wiring extending in a second direction perpendicular to the first direction, a first wiring between one end of the main wiring and the first interlayer connection area, and a second wiring connected to the other end of the main wiring, and the second column line includes a main wiring extending in the second direction, a first wiring between one end of the main wiring and the first interlayer connection area, and a second wiring connected to the other end of the main wiring, wherein the first distance between the main wiring of the first column line and the main wiring of the second column line is longer than the second distance between the point where the first column line is connected to the first interlayer connection area and the point where the second column line is connected to the first interlayer connection area, and the length of the first wiring of the first column line is of the first wiring of the second column line An image sensor having a length greater than that of the first column line, and the length of the second wiring of the first column line being smaller than the length of the second wiring of the second column line. Claim 2 In claim 1, the third distance between the point where the second wiring of the first column line ends and the point where the second wiring of the second column line ends is smaller than the first distance, in an image sensor. Claim 3 In claim 2, the second distance and the third distance are the same image sensor. Claim 4 An image sensor according to claim 1, wherein the pixel array and the first layer inter-connection region are formed on a first semiconductor chip, and the reading circuit is formed on a second semiconductor chip. Claim 5 In claim 4, the second semiconductor chip further comprises a second interlayer connection region electrically connected to the first interlayer connection region, and the reading circuit comprises: analog-to-digital converters that convert analog signals output from the first pixel and the second pixel and received through the second interlayer connection region into digital signals; and a logic circuit that processes the output of the analog-to-digital converters, an image sensor. Claim 6 In claim 5, the analog-to-digital converters include an image sensor comprising a current source for discharging charges of the first column line and a switch connecting the first column line and the current source. Claim 7 In claim 1, the second wiring of the second column line is an image sensor having a spiral shape. Claim 8 An image sensor according to claim 1, wherein the second wiring of the second column line comprises at least one protrusion formed in a direction different from the direction in which the second wiring of the second column line extends. Claim 9 A first semiconductor chip comprising a pixel array and a first interlayer connection region, wherein the pixel array comprises a first pixel connected to a first column line and a second pixel connected to a second column line spaced apart from the first column line in a first direction, and the first column line and the second column line are connected to the first interlayer connection region; and a second semiconductor chip comprising a reading circuit including analog-to-digital converters for processing the outputs of the first pixel and the second pixel, and a second interlayer connection region, wherein the first column line includes a main wiring extending in a second direction perpendicular to the first direction, a first wiring between one end of the main wiring and the first interlayer connection region, and a second wiring connected to the other end of the main wiring, and the second column line includes a main wiring extending in the second direction, a first wiring between one end of the main wiring and the first interlayer connection region, and a second wiring connected to the other end of the main wiring, wherein the first distance between the main wiring of the first column line and the main wiring of the second column line is longer than the second distance between the point where the first column line is connected to the first interlayer connection region and the point where the second column line is connected to the first interlayer connection region, and the length of the first wiring of the first column line is the second column An image sensor in which the length of the first wiring of the line is greater than the length of the second wiring of the first column line, the length of the second wiring of the second column line is smaller than the length of the second wiring of the second column line, and the first interlayer connection area and the second interlayer connection area are electrically connected. Claim 10 A first semiconductor chip comprising a pixel array and a first interlayer connection region, wherein the pixel array comprises a first pixel connected to a first column line and a second pixel connected to a second column line spaced apart from the first column line in a first direction, and the first column line and the second column line are connected to the first interlayer connection region; and a reading circuit comprising a first analog-to-digital converter for processing the output of the first pixel and a second analog-to-digital converter for processing the output of the second pixel, and a second semiconductor chip comprising a second interlayer connection region electrically connected to the first interlayer connection region, wherein the first column line includes a main wiring extending in a second direction perpendicular to the first direction and having one end connected to the first interlayer connection region, and a first wiring connected to the other end of the main wiring, and the second column line includes a main wiring extending in the second direction and having one end connected to the first interlayer connection region, and a second wiring connected to the other end of the main wiring, and the second semiconductor chip further includes a third wiring electrically connected to the first column and electrically connected to the first analog-to-digital converter through the first interlayer connection region and the second interlayer connection region, and the second semiconductor chip through the first interlayer connection region and the second interlayer connection region An image sensor further comprising a fourth wire electrically connected to a second column and electrically connected to a second analog-to-digital converter, wherein the first distance between the main wire of the first column line and the main wire of the second column line is longer than the second distance between the point where the third wire is connected to the first analog-to-digital converter and the point where the fourth wire is connected to the second analog-to-digital converter, and the length of the first wire is smaller than the length of the second wire.

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