Sequential read optimization of sequentially programmed memory subsystems

Abstract

The system includes volatile memory having buffers and a processing device. A command generation processor receives a read request from a host having a logical block address (LBA) and generates a first logical transfer unit (LTU) containing a first LBA to be mapped to a physical address. The command generation processor reads a flag to determine whether the first LTU is associated with a region of the LBA address space, which contains sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that instruct the processing device to retrieve data from a memory device and store the data in a set of buffers, wherein the command tags include a first command tag associated with a physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

Description

Technology Field

[0001] The embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to sequential read optimization of a sequentially programmed memory subsystem. Background Technology

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data in memory devices and retrieve data from memory devices. Brief explanation of the drawing

[0003] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present invention. FIG. 1a illustrates an exemplary computing system including a memory subsystem according to embodiments. FIG. 1b further illustrates in detail the memory subsystem of FIG. 1a according to one embodiment. FIG. 2 is a block diagram showing an example of a data structure configured to support zone-based mapping according to various embodiments. FIG. 3 is a block diagram of the interrelationships of a command generation processor, a conversion processor, and a command execution processor of a memory subsystem controller of FIG. 1a to 1b according to one embodiment. FIG. 4 is a flowchart of a sequential read optimization method according to one embodiment. FIG. 5 is a flowchart of a sequential read optimization method according to a related embodiment. FIG. 6 is a block diagram of an exemplary computer system in which embodiments of the present disclosure can be operated. Specific details for implementing the invention

[0004] An aspect of the present disclosure relates to the optimization of sequential reads of a memory subsystem that is programmed sequentially. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of a storage device and a memory module are described below together with FIG. 1a. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device that stores data. The host system may provide data to be stored in the memory subsystem and may request data to be retrieved from the memory subsystem.

[0005] A memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND (negative-and) memory device. Another example of a non-volatile memory device is described below with reference to Fig. 1a. A non-volatile memory device is a package of one or more dies. The dies in the package may be assigned to one or more channels to communicate with a memory subsystem controller. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). In some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of a memory device used to store data and may include a group of memory cells, a word line group, a word line, or individual memory cells.

[0006] Data operations can be performed in the memory subsystem. Data operations may be host-initiated operations. For example, the host system may initiate data operations (e.g., write, read, erase, etc.) in the memory subsystem. The host system may send access requests (e.g., write command, read command) to the memory subsystem to store data in a memory device of the memory subsystem and to read data from a memory device of the memory subsystem.

[0007] Data to be read or written as specified by a host request is hereinafter referred to as "host data." A host request may include logical address information for the host data (e.g., logical block address (LBA), namespace) which is a location that the host system associates with the host data. Logical address information (e.g., LBA, namespace) may be part of the metadata for the host data. The metadata may also include error handling data (e.g., ECC codeword, parity code), data version (e.g., used to distinguish the age of the written data), valid bitmap (this LBA or logical transport unit contains valid data), etc. For simplification, where "data" is referred to below, such data may be understood to refer to at least the host data, but may also refer to other data such as media management data and / or system data.

[0008] The cells (or simply "media") of a memory device can be organized hierarchically from the die (upper level) to planes, blocks, and pages (lower levels). A block set (also called a block stripe) can be a set of blocks arranged across planes of different dies so that the blocks are grouped together for data storage. Writing to block stripes allows for more host data to be written and read simultaneously from multiple dies. Multiple blocks of one or more block sets can be identified as a data group.

[0009] In various embodiments, the host file system may group host data by locality and write the host data sequentially to the memory subsystem. The file system may then write host data of different localities to the memory subsystem as parallel sequential streams, each stream having a unique locality, and, for example, different host applications may each write to their own stream. "Locality" may refer to temporal locality or spatial locality. Data grouped by temporal locality is host data that the processor tends to access repeatedly at the same memory device locations over a short period of time, for example, data that is written, overwritten, and trimmed at the same time. Trimming refers to the operating system's use of the trim command to inform the memory device of blocks of data that are no longer in use and can be internally erased, for example, through garbage collection. Data grouped by spatial locality captures data retrieval patterns when a specific storage location is referenced at a specific time and is likely to be referenced at a nearby memory location (on the memory device) in the near future. In this case, the processor may attempt to determine the size and shape of the region surrounding the currently referenced memory location that is worth preparing for faster access to locations referenced later. A reference to sequential locality is a special case of spatial locality that occurs when data elements are linearly aligned and accessed, such as when traversing the elements of a one-dimensional array.

[0010] A memory subsystem controller (e.g., including a processing device) typically writes randomly to the media from a portion of host data (e.g., 4KB) and then uses metadata to map the LBA space to the media's physical address space. However, when larger groups of host data (e.g., 100MB or more) are grouped by data locality and written, "data groups" may be written sequentially in larger chunks across one or more sets of blocks across multiple dies. To simplify the mapping of these data groups, LBAs of a zone (e.g., a logical address space associated with a data group) may be sequentially aligned within the LBA space and mapped to sequentially aligned physical addresses within the physical address space. That is, a data group may be associated with an LBA space zone having multiple sequential LBAs that are sequentially mapped to multiple sequential physical addresses. A memory subsystem capable of writing (e.g., programming) data zones and mapping zones at a time operates in a Zone Namespace (ZNS), where, for example, zones of logical addresses are named / identified as groups. Advantageously, the use of ZNS for logical to physical (LTP) address mapping significantly reduces the amount of metadata required to track LTP mappings.

[0011] In a memory subsystem, a read request (or read operation) typically issues one command tag at a time to a translation processor of the memory subsystem controller (e.g., converting a logical address to a physical address) to result in a random read at the granularity specified by the command tag. A command tag, also called a system tag (e.g., a systag), includes a logical transfer unit (LTU) number and a buffer address identifying a buffer (e.g., a slot or entry in volatile memory) where the content corresponding to the transfer unit is stored as if it were in a cache. In one embodiment, an LTU corresponding to a 4KB portion of data is a subset of multiple sequential LBAs that can be mapped to a physical address through a set of mapping data structures. Thus, to generate an LTU, the command generation processor of the memory subsystem controller may combine the LBA of the read request with sequential additional LBAs (which may also be received in the read request). Each LTU may be translated into a logical block or a logical page depending on the LTU type.

[0012] Since read requests are typically performed with one command tag at a time, each read request generates a command message (a mailbox message in one example) to the command generation processor of the memory subsystem controller (regardless of whether the read is sequential) and generates multiple (e.g., four) data structure lookups to map the read request's LBA to a physical location in the memory device, as described in detail. The command message can be used after fetching a non-volatile memory command, where the command generation processor notifies the translation processor of the command reception. These data structures (e.g., tables) can be stored in tightly coupled memory (TCM), static read-only memory (SRAM), or other volatile memory. This method of handling read requests increases latency, thereby increasing overhead and degrading overall performance, particularly when some read requests are issued sequentially to a sequentially written physical address space (e.g., ZNS). Therefore, the sequential data layout from sequential records is not utilized to limit the number of lookups that the memory subsystem controller (e.g., the translation processor of the memory subsystem controller) must perform to determine the physical addresses to retrieve data for performing a read request.

[0013] An aspect of the present disclosure addresses the above and other drawbacks by using a shared volatile memory (e.g., at least one volatile memory device) in which a translation processor of a processing device communicates a first physical address to a command execution processor of the processing device and sets a flag (e.g., a bit flag) indicating that the first physical address (mapped to a first LTU designated as a first command tag) is part of sequentially written data. A command generation processor of the processing device may determine a method for generating a set of command tags to include a first command tag to be issued as a group by accessing the physical address and flag in the volatile memory. The command generation processor may send a set of commands containing the command tags directly to the command execution processor of the processing device while bypassing any additional lookups by the translation processor in the mapping data structures. The command execution processor may read data from the physical addresses designated by the command tags into a set of buffers (e.g., slots in the volatile memory) allocated for this purpose.

[0014] In various embodiments, more specifically, this set of command tags may include a first command tag associated with a physical address as well as additional command tags associated with subsequent physical addresses sequentially numbered within a read window size (e.g., an offset value) starting from the first physical address. In this way, sequential data is read in a preview manner and stored in a set of buffers allocated to handle the capacity of data stored in the read preview of the first physical address and subsequent physical addresses, e.g., the offset value. Data requested by the host system read from a physical address is returned to the host system. If the host system requests data from a second or subsequent physical address within the offset value of the physical address, the command generation processor may quickly retrieve data from the set of buffers and send the data to the host system without further lookup or conversion.

[0015] The benefits of the present disclosure include, for example, improved read performance by allowing many read requests to be hit in buffers with a read preview operation, and avoiding the significant cost of suspending write operations to service many read requests (occurring more frequently than write operations). Additionally, the present disclosure describes a method for performing sequential read performance optimization to reduce latency for sequential read requests from a host system (even if such read requests are interspersed with write operations and / or read requests for other regions). These benefits leverage sequential writes performed on ZNS-enabled memory devices in a synergistic manner. Other benefits will be apparent to those skilled in the art of memory allocation and error optimization within the memory subsystem discussed later.

[0016] FIG. 1a illustrates a computing system (100) comprising a memory subsystem (110) according to some embodiments of the present disclosure. The memory subsystem (110) may include a medium such as volatile memory (e.g., memory device (140)), one or more non-volatile memory devices (e.g., memory device (130)), or a combination thereof. Each memory device (130 or 140) may be one or more memory component(s).

[0017] The memory subsystem (110) may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a Solid-State Drive (SSD), a flash drive, a Universal Serial Bus (USB) flash drive, an embedded multimedia controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0018] The computing system (100) may be a computing device or such a computing device including memory and processing devices, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, an unmanned aerial vehicle, a train, a car, or other means of transportation), an Internet of Things (IoT) capable device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device).

[0019] A computing system (100) may include a host system (120) coupled with one or more memory subsystems (110). In some embodiments, the host system (120) is coupled with different types of memory subsystems (110). FIG. 1a illustrates an example of a host system (120) coupled with one memory subsystem (110). In this specification, "coupled to" or "coupled with" generally refers to a connection between components or devices that may be an indirect communication connection, whether wired or wireless, or a direct communication connection (e.g., without intermediate components or devices), including connections such as electrical, optical, magnetic, etc.

[0020] The host system (120) may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system (120) uses the memory subsystem (110) to write data to the memory subsystem (110) and to read data from the memory subsystem (110).

[0021] A host system (120) may be coupled to a memory subsystem (110) via a physical host interface capable of communicating via a system bus. Examples of physical host interfaces include, but are not limited to, a SATA (Serial Advanced Technology Attachment) interface, a PCIe (Peripheral Component Interconnect Express) interface, a USB (universal serial bus) interface, a Fibre Channel, a SAS (Serial Attached SCSI), a DDR (double data rate) memory bus, a SCSI (Small Computer System Interface), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting DDR (Double Data Rate)), an ONFI (Open NAND Flash Interface), a DDR (Double Data Rate), a LPDDR (Low Power Double Data Rate) interface, or other interfaces. The physical host interface may be used to transmit data between the host system (120) and the memory subsystem (110). The host system (120) may further utilize an NVMe (NVM Express) interface to access components (e.g., memory device (130)) when the memory subsystem (110) is coupled to the host system (120) via a PCIe interface. A physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem (110) and the host system (120). FIG. 1a illustrates a memory subsystem (110) as an example. Generally, the host system (120) may access multiple memory subsystems through the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0022] The memory devices (130, 140) may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device (140)) may be random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM), but are not limited thereto.

[0023] Some examples of non-volatile memory devices (e.g., memory device (130)) include NAND (negative-and) type flash memory and write-in-place memory, such as 3D junction ("3D junction") memory. A junction array of non-volatile memory can perform bit storage based on changes in bulk resistance, together with a stackable junction grid data access array. Additionally, in contrast to many flash-based memories, junction non-volatile memory can perform write-in-place operations where non-volatile memory cells can be programmed without the non-volatile memory cells being erased in advance. For example, NAND type flash memory includes 2D NAND and 3D NAND.

[0024] Each of the memory devices (130) may include one or more arrays of memory cells. For example, a single-level cell (SLC), which is a type of memory cell, may store 1 bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices (130) may include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a specific memory device may include an SLC portion and an MLC portion, TLC portion, or QLC portion of memory cells. The memory cells of the memory devices (130) may be grouped into pages that can refer to the logical unit of the memory device used to store data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0025] Although nonvolatile memory components such as a 3D cross-section array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device (130) may be based on any other type of nonvolatile memory such as read-only memory (ROM), phase change memory (PCM), self-selection memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (negative-or) flash memory and electrically erasable programmable read-only memory (EEPROM).

[0026] A memory subsystem controller (115) (or a controller (115) for simplification) may communicate with memory devices (130) to perform operations such as reading data, writing data, erasing data, and other such operations on memory devices (130). The controller (115) may include hardware such as one or more integrated circuits and / or individual components, buffer memory, or a combination thereof. The hardware may include digital circuits having dedicated (e.g., hard-coded) logic for performing the operations described herein. The memory subsystem controller (115) may be a microcontroller, a special-purpose logic circuit (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

[0027] The memory subsystem controller (115) may include a processor (117) (e.g., a processing device) configured to execute instructions stored in local memory (119). In the illustrated example, the local memory (119) of the memory subsystem controller (115) includes an embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem (110), including handling communications between the memory subsystem (110) and the host system (120).

[0028] In some embodiments, the local memory (119) may include memory registers that store memory pointers, fetched data, etc. The local memory (119) may also include read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem (110) in FIG. 1a is shown to include a memory subsystem controller (115), in another embodiment of the present disclosure, the memory subsystem (110) may not include a memory subsystem controller (115) and instead may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0029] Generally, the memory subsystem controller (115) may receive commands or operations from the host system (120) and convert the commands or operations into instructions or appropriate commands to achieve desired access to the memory device (130). The memory subsystem controller (115) is responsible for other operations related to the memory devices (130), such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical block addresses (e.g., logical block address (LBA), namespace) and physical addresses (e.g., physical block address). The memory subsystem controller (115) may further include a host interface circuit for communicating with the host system (120) through a physical host interface. The host interface circuit can convert commands received from the host system into command instructions for accessing memory devices (130), as well as convert responses associated with memory devices into information about the host system (120).

[0030] The memory subsystem (110) may also include additional circuitry or components not shown. In some embodiments, the memory subsystem (110) may include an address circuitry (e.g., row decoder and column decoder) capable of receiving an address from the memory subsystem controller (115) and decoding an address for accessing memory devices (130), and a cache or buffer (e.g., DRAM).

[0031] In some embodiments, memory devices (130) include local media controllers (135) that operate with a memory subsystem controller (115) to perform operations on one or more memory cells of the memory device (130). An external controller (e.g., memory subsystem controller (115)) may manage the memory device (130) externally (e.g., perform media management operations on the memory device (130)). In some embodiments, the memory devices (130) are managed memory devices, which are raw memory devices coupled with a local controller (e.g., local media controller (135)) for memory management within the same memory device package or memory die. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] In some embodiments, the controller (115) includes an error correction code (ECC) encoder / decoder (111). The ECC encoder / decoder (111) may perform ECC encoding on data written to memory devices (130) and perform ECC decoding on data read from memory devices (130). ECC decoding may be performed to decode ECC codewords to correct errors in raw read data and, in many cases, to report the number of bit errors in raw read data.

[0033] FIG. 1b further illustrates in detail the memory subsystem (110) of FIG. 1a according to one embodiment. In the embodiment, the memory subsystem controller (115) (e.g., a processing device, referred to as the controller (115) for simplification) includes one or more registers (112), a command generation processor (122) including a buffer manager (113), a translation processor (123), a command execution processor (124), and a local memory (119). For example, the processor (117) (Fig. 1a) may include a command generation processor (123), a translation processor (123), and a command execution processor (124). The local memory (119) may store a zone map data structure (101) and a block set map data structure (107) among other ZNS mapping data structures, for example, as illustrated in FIG. 2. In one embodiment, the zone map data structure (101) includes multiple entries such that each entry has a block set entry identifier linked to an entry in the block set map data structure (107), which can in turn be linked to an entry in the page map data structure that finds a page in memory, and will be described in detail with reference to FIG. 2.

[0034] Additionally, as previously discussed with reference to one or more memory device(s) (130, 140), the physical address space of multiple dies (e.g., Die A and Die B) may be hierarchically organized by planes, blocks, and pages. Thus, for example, each Die A and Die B may include planes A and B, and each plane A and B may include blocks A and B. A block set (or block stripe) may be defined as a group of blocks arranged across the planes of the multiple dies of the memory device(s). As illustrated, a block set (144) may include block A of plane A of Die A, block A of plane B of Die B, etc., for example, plane C of Die C, and, if present and online, is arranged up to additional dies.

[0035] In various embodiments, the conversion processor (123) (and / or the dynamic data placer of the controller (115) coupled to the conversion processor (123)) dynamically determines a media layout to place data associated with logical addresses in the media units or memory components (also referred to as “IC dies” or “media”) of the memory devices (130, 140). The media layout specifies a mapping between the logical addresses used in commands received in the memory subsystem (110) (e.g., from the host system (120)) and physical memory locations in the media of the memory subsystem (110).

[0036] The conversion processor (123) may determine a media layout for a portion of the logical addresses in the LBA space for the placement of data at logical addresses associated with the physical addresses of the media of the memory device (130 or 140), based on the availability of media for writing, programming, storing, and committing data during input / output scheduling in the memory subsystem (110), for example. When the IC die(s), which contain media units within the IC die(s), are available for committing / programming data, a write command is scheduled for execution in the memory subsystem (110); and the conversion processor (123) generates a portion of the media layout for the write command and maps the logical address(s) used in the write command to memory locations within the IC die(s). Execution of the write command causes the memory subsystem (110) to commit / program the data associated with the write command to the IC die(s).

[0037] Depending on the availability of IC dies across the media and / or the application of a sequential mapping scheme, the controller (115) may sequentially write data groups (e.g., provided in a sequential stream of data-intensive data) to fill one IC die at a time, or, for example, sequentially write to multiple IC dies at a time in parallel to fill the IC dies of the media simultaneously. As discussed in more detail with reference to ZNS mapping data structures, the mapping of writes within regions of the LBA space may also be performed sequentially to simplify the calculations used to perform the mapping. When multiple IC dies are available, the logical addresses (e.g., LBAs) used in commands from multiple write streams may be mapped individually to multiple IC dies by a dynamically generated portion of the media layout so as not to cause media access conflicts during the execution of commands from multiple write streams.

[0038] In various embodiments, the conversion processor (123) accesses specific ZNS mapping data structures (e.g., zone map data structure (101) and block set map data structure (107)) to convert LBAs into physical block addresses (PBAs) of the physical address space. In the context of flash media (e.g., NOR or NAND flash memory), the conversion processor (123) may be referred to as a flash conversion layer (FTL). The mapping used by the conversion processor (123) may generally be assumed to include a type of block mapping, e.g., block level mapping or log block mapping. Where data locality is detected in a ZNS memory device, the conversion processor (123) may map groups of blocks forming regions, for example, within ZNS data structures, which may include mapping sequentially numbered LBAs to sequentially numbered PAs as previously discussed. The use of ZNS data structures and their interrelationships for mapping the LBA space of a region to the physical address space of the media are discussed in more detail with reference to FIG. 2.

[0039] In some embodiments, the memory subsystem (110) also includes a volatile memory device (140A) (e.g., shared volatile memory such as TCM, SRAM, DRAM, or a combination thereof) having allocated buffers used to store (e.g., cache) data in the fulfillment of read requests. Each buffer may be, for example, an addressed slot or entry of the volatile memory device (140A). The buffers may include a first buffer (142A), a second buffer (142B), a third buffer (142C), ... a Nth buffer (142N). Each buffer may store the page size of the data. In an alternative embodiment, although shown separately, the volatile memory device (140A) is actually part of the local memory (119) of the controller (115).

[0040] In various embodiments, the command generation processor (122) performs command processing to generate read commands and write commands based on read and write requests received individually from, for example, a host system (120) or other request agent. As part of the execution read requests, the buffer manager (113) of the command generation processor (122) may allocate a specific number (e.g., "set") of buffers having a capacity corresponding to the amount of data stored in subsequent physical addresses sequentially numbered after the first physical address within a first physical address (mapped by an LTU created to include the LBA of the read request) and, for example, an offset value defining the read window size of the memory device. In one embodiment, the offset value is 128 KB and allows for a read preview of an additional 124 KB of data beyond the first read request. Various other offset values ​​or read window sizes are conceived. For example, each subsequent physical address can be incremented by a page number across a reading window of a sequential physical address space defined by an offset value to determine subsequent physical addresses. By the buffer manager (113), the allocation and tracking of buffers facilitates the read preview operation.

[0041] In these embodiments, the command generation processor (122) may further generate a set of command tags used to instruct the command execution processor (124) of the processing device to retrieve data from the first address and subsequent addresses of the memory device (130 or 140), and store the data in a set of buffers. The command generation processor (122) may further transmit a group of commands containing the set of command tags to the command execution processor (124). In this way, each command tag of the set of command tags includes an LTU number identifying an LTU mapped to one of the individual sequential physical addresses.

[0042] In the relevant embodiments, the buffer manager (113) can track the use of the buffers, and host commands are responsible for locking or unlocking the buffers when hitting these buffers using any number of buffer management algorithms to track data cached in various buffers by a number of possible applications. Buffer management algorithms may include, for example, a 2-3 tree algorithm (also referred to as a 2-3 tree algorithm) in which buffers are sorted by LTU number (or LBA number), a linked list algorithm, or an N-way cache using a hash algorithm. For example, the buffer manager (113) may use a buffer index table that indexes sequentially read data cached in the buffers against discontinuous buffer numbers, as exemplified in Table 1.

[0043] Data index (e.g., for 64-byte data) Buffer index 0 0 1 3 2 4 ... ... ... ... 63 230

[0044] Metadata that may be used by these buffer management algorithms (e.g., for buffer allocation and usage tracking) includes LTU / LBA (as data is sorted), a buffer address indicating the buffer slot where data resides (or other buffer identifier used for indexing), and a buffer usage count that allows multiple users (e.g., host applications) on separate read or write paths to track together. In this way, the buffer manager (113) can manage multiple applications that write and read from multiple regions where any set of commands can write to or read from sequentially stored data, even though the allocated buffers may not be numbered sequentially as exemplified in Table 1. When data is tracked in buffers, hardware acceleration may be used to facilitate the tracking and management of data in buffers.

[0045] The buffer manager (113) may further use a flag (e.g., a bit flag) or counter to track whether any given buffer is being used in a read or write path. This allows for a fast search time (e.g., already being processed) to satisfy an inflight command for the buffer and a short search time to find a specific LBA, thus allowing the buffer to be checked for cache hits and direct transfer to the host system (120) instead of returning to the conversion processor (123) for mapping. Since data is retrieved from buffers acting like a cache, coherency should not be an issue as long as the zone map data structure (101) is checked first, which will continue to be performed within the sequential read optimization initiated by the command generation processor (122). In some embodiments, the controller (115) includes at least a part of the buffer manager (113). In other embodiments, or in combination, a controller and / or processing device of the host system (120) includes at least a portion of the buffer manager (113). For example, the controller (115) or the processing device of the host system (120) may be configured to execute instructions stored in memory to perform the operations of the buffer manager (113) described herein. In some embodiments, the buffer manager (113) is implemented in an integrated circuit chip placed in the memory subsystem (110). In other embodiments, the buffer manager (113) is part of the operating system, device driver, or application of the host system (120).

[0046] In these embodiments, the command execution processor (124) sequences write and read commands for memory device(s) (130, 140) within a channel of the data bus. In response to the reception of read commands, the command execution processor (124) may further retrieve data from a subsequent physical address of the memory device(s) (130, 140) pointed to by a first physical address and a set of command tags. It is recalled that each command tag includes an LTU that maps to a physical address and identifies a buffer address within buffers cached in a volatile memory device (140A). The command execution processor (124) may further store data (e.g., cache) for performing read commands in buffers allocated according to individual buffer addresses of the set of command tags, which is included within a group of commands generated by the command generation processor (122) and sent to the command execution processor (124). The command execution processor (124) can further perform error processing in a physical layer corresponding to a physical address space, for example.

[0047] The conversion processor (123) converts LTUs into physical addresses in the physical address space to facilitate the generation of commands to the command execution processor (124) by the command generation processor (122). Thus, the conversion processor (123) can act as an intermediary between the command generation processor (124) (which receives a memory request with an LBA and generates an LTU containing the LBA) and the command execution processor (124) which needs to know the physical address of the physical layer for executing the command. In the present disclosure, the regular use of the conversion processor (123) for indexing into various ZNS mapping data structures can be avoided in the read-pre operations of sequential read optimization.

[0048] FIG. 2 is a block diagram illustrating examples of data structures configured to support zone-based mapping according to various embodiments. A controller (115) may store the data structures illustrated in FIG. 2 in local memory (119), e.g., SRAM, or in memory components of a memory device (140), e.g., DRAM. The controller (115) may also use the data structures of FIG. 2 to configure or implement a media layout (e.g., a layout in which a data group of a region must be located within a physical address space). In FIG. 2, a zone map data structure (201) is configured to provide media layout information for a region in a namespace, e.g., an LBA space for ZNS operations. The zone map data structure (201) may be identical or similar to the zone map data structure (101) of FIG. 1b. The zone map data structure (201) may have multiple entries. In the zone map data structure (201), each zone entry identifies information about the zone, such as the zone's starting LBA address (211), the zone's block set identifier (213), the zone's zone cursor value (215), and the zone's status (217).

[0049] The host system (120) writes data to a zone starting from the LBA of the zone start LBA identifier (211). The host system (120) writes data sequentially to the zones of the LBA space. After a amount of data has been written to a zone, the current start LBA address for writing subsequent data is identified by the zone cursor value (215). Each write command for a zone moves the zone cursor value (215) to a new start LBA address for the next write command for the zone. The status (217) may have a value indicating that the zone is empty, full, implicitly open, explicitly open, closed, etc., to track the progress of writing the zone.

[0050] In FIG. 2, the logical-to-physical block map data structure (203) is configured to facilitate the conversion of LBA addresses from media to physical addresses. The logical-to-physical block map (203) may have multiple entries. An LBA may be used or converted as an index (e.g., LTU number) for an entry in the logical-to-physical block map (203). The index may be used to look up an entry for an LBA. Each entry in the logical-to-physical block map (203) identifies the physical address of a memory block in the media for the LBA. For example, the physical address of a memory block in the media may include a die identifier (233), a block identifier (235), a page map entry identifier (237), etc. The die identifier (233) identifies a specific IC die (e.g., die A or die B) of the memory device(s) (130, 140) of the memory subsystem (110). The block identifier (235) identifies a specific memory block (e.g., NAND flash memory) within the IC die identified using the die identifier (233). The page map entry identifier (237) identifies an entry of the page map data structure (205).

[0051] The page map data structure (205) may have multiple entries. Each entry in the page map (205) may include a page identifier (251) that identifies a page of memory cells within a block of memory cells (e.g., NAND memory cells). For example, the page identifier (251) may include a word line number for the page and a sub-block number for the page within a block of NAND memory cells. Additionally, an entry for a page may include a programming mode (253) for the page. For example, the page may be programmed in SLC mode, MLC mode, TLC mode, or QLC mode. When configured in SLC mode, each memory cell in the page stores 1 bit of data. When configured in MLC mode, each memory cell in the page stores 2 bits of data. When configured in TLC mode, each memory cell in the page stores 3 bits of data. When configured in QLC mode, each memory cell in the page stores 4 bits of data. Other pages on the integrated circuit die may have different modes for data programming.

[0052] In FIG. 2, the block set data structure (207) stores data that controls aspects of dynamic media layout for a zone. The block set data structure (207) may be identical or similar to the block set map data structure (107) of FIG. 1b. In one embodiment, the block set data structure (207), which may be table-like, may have multiple entries. In the block set data structure (207), each block set entry identifies the number / count (271) of the integrated circuit dies (e.g., Die A and Die B) where the data of the zone is stored. For each integrated circuit die used in the zone, the block set entry of the block set data structure (207) has a die identifier (273), a block identifier (275), a page map entry identifier (277), a page map offset value, etc.

[0053] The die identifier (273) identifies a specific IC die (e.g., die A or die B) in the media of the memory subsystem (110), on which subsequent IC die data of a region may be stored. The block identifier (275) identifies a specific block of memory (e.g., NAND flash memory or other media) within the IC die identified using the die identifier (273), on which subsequent data of a region may be stored. The page map entry identifier (237) identifies a page map entry in the page map data structure (205), which identifies a page that may be used to store subsequent data of a region.

[0054] For example, the memory subsystem (110) receives multiple streams of write commands. In one embodiment, each individual stream of the multiple streams is configured to write data sequentially to a logical address space in one embodiment; and in another embodiment, the streams of the multiple streams are configured to write data pseudo-sequentially, or in one embodiment, randomly to a logical address space. Each write stream includes a set of commands tagged to write, trim, and overwrite a set of data together as a group. In a group, data may be written sequentially, randomly, or pseudo-sequentially to a logical space. Preferably, in a group, data is written to an erase block set, in which memory cells store data for the stream but not data from other streams. The erase block set may be erased to remove data of a stream without erasing data from other streams.

[0055] For example, each write stream is allowed to be written sequentially to LBAs in a section of the namespace allocated to the media of the memory device(s) (130, 140) of the memory subsystem (110), but writing data out of order in the LBA (or logical address) space is prohibited. The conversion processor (123) of the memory subsystem (110) identifies multiple media units in the memory subsystem (110) that are available for writing data simultaneously.

[0056] The conversion processor (123) can select a first command from multiple streams for simultaneous execution in multiple media units available for recording data. The conversion processor (123) can dynamically respond to the first commands selected for simultaneous execution in multiple media units to generate and store a portion of a media layout that maps from logical addresses identified by the first commands in a logical address space to physical addresses of memory units of multiple memory units.

[0057] The command execution processor (124) can execute the first commands simultaneously by storing data in memory units according to physical addresses. For example, when scheduling the first commands for execution, the execution of the second commands may be in progress in a subset of memory units of the media of the memory subsystem (110). Thus, the subset of memory units used for the execution of the second commands is not available for the first commands. After the first commands are scheduled and part of the media layout for the logical addresses used for the first commands is determined, the first commands may be executed in multiple media units simultaneously and / or concurrently with the execution of the second commands in the remaining media units of the memory subsystem (110).

[0058] For example, after identifying multiple memory units (e.g., IC dies) available for the execution of the next commands, the conversion processor (123) can identify physical addresses from the block set data structure (207) that can be used to store data for the next commands. The physical addresses can be used to update the corresponding entries of the logical-to-physical block map data structure (203) for the LBA addresses used for the next commands.

[0059] For example, if the IC die is capable of writing data, the conversion processor (123) can determine the command for a region that can be written / programmed to memory cells on the IC die. From the block set data structure (207), the conversion processor (123) finds an entry for the region, finds a block identifier (275) and a page map entry identifier (277) associated with the identifier (273) of the integrated circuit die, and uses the die identifier (273), block identifier (275), and page map entry identifier (277) to update the corresponding fields of the entry in the logic-to-physical block map data structure (203) for the LBA used in the command for the region.

[0060] FIG. 3 is a block diagram of the interrelationships of the command generation processor (122), the conversion processor (123), and the command execution processor (124) of the subsystem memory controller (115) of FIG. 1a and 1b according to one embodiment. In various embodiments, the controller (115) includes a shared volatile memory (140B) and a command buffer (140C) in the shared volatile memory (140B). In one embodiment, the shared volatile memory (140B) is part of the local memory (119) or volatile memory device (140A) discussed with reference to FIG. 1b. In various embodiments, the command generation processor (122) may receive a first read request from a host system (120) (or other request agent). The first read request may include a first LBA corresponding to a first physical address of the memory device (130 or 140) to which the read operation is directed. When servicing a first read request, the command generation processor (122) may generate a first logical transmission unit (LTU) including a first LBA, and the first LTU is mapped to a first physical address of a memory device.

[0061] In some embodiments, the conversion processor (123) may be configured to automatically store (or buffer) LTU to physical address (PA) mappings (301) in shared volatile memory (140B) when their data is programmed into memory device(s) (130, 140). For example, the LTU to PA mapping (301) may be part of a logical to physical block map data structure (203) and a page map data structure (205), and individual physical addresses are written when programmed into the memory device (130 or 140). This may provide a fast-accessible data structure that provides only the LTU to PA mapping at the command tag level. In some embodiments, the LTU to PA mapping (301) in shared volatile memory (140B) may be processed as a cache to maintain this data structure in a size-limited manner.

[0062] Referring further to FIG. 3, the conversion processor (123) may more optionally set a flag (303) (e.g., a bit flag, etc.) in the shared volatile memory (140B). Thus, each entry of the LTU to PA mapping (301) may include an LTU number and a physical address mapped to a flag. In an alternative embodiment, a bit value of the bit map stored in the registers (112) (Fig. 1b) may be set. One of the bit values ​​of the bit map may correspond to a specific LTU and thus function as a flag (303) in the shared volatile memory (140B). The bit map may correspond to a physical address space known to be written sequentially by ZNS operation, for example. The flag (303) (or a bit value within the bit map) may indicate whether the LTU to PA mapping entry is associated with a region of the LBA address space, where the region is mapped to data written sequentially to the memory device (130 or 140). The conversion processor (123) may optionally further set a die availability flag (305) to indicate that the die where the physical address is located is available for service commands.

[0063] In various embodiments, when the flag (303) is set and the die availability flag (305) is set, the command generation processor (122) performs the read preview optimization disclosed herein. The read optimization may include, for example, auto-incrementing a first physical address retrieved from the LTU to PA mapping (301) for a first read request to determine subsequent physical addresses within the offset value of the first physical address. In one embodiment, the auto-increment is performed to increase the first physical address by a page number until the end of the read window size is reached from the first physical address.

[0064] The command generation processor (122) may then generate (or update) a set of command tags used to direct the command execution processor (124) within the command buffer (140C) to retrieve data from the memory device (130 or 140) and store the data in the set of buffers discussed with reference to FIG. 1b. The command generation processor (122) may then transmit a group of commands, each containing one of the sets of command tags individually, to the command execution processor (124) of the processing device. The set of commands may be buffered within the command buffer (140C) as Cmd[0], Cmd[1], Cmd[2],... Cmd[n]. In one embodiment, the command generation processor (122) may interlink a set of command tags into a command chain (e.g., a chain of individual commands) and transmit the command chain in a single command message to the command execution processor (124).

[0065] After the command execution processor (124) stores data in individual buffers allocated for the read preview of the first (or original) read command, the command generation processor (122) may return the data stored at the first physical address to the host system (120) or other request agent. However, the command generation processor (122) may also service subsequent read commands directed directly from the buffers to subsequent physical addresses. For example, in response to a second read request, the command generation processor (122) may determine that the second LBA of the second read request corresponds to the second physical address among the subsequent physical addresses. Then, the command generation processor (122) may retrieve a second subset of data from the second buffer of the set of command tags of the set of buffers having the buffer address associated with the second command tag, and may transmit the second subset of data to the host system (120) in response to the first subsequent read commands.

[0066] As an example of the above sequential read optimization including a read preview operation, assume that each zone is 100MB and that the host system (120) attempts read access to sequential read locations. The host system (120) may issue multiple read requests within exemplary LBAs mapped to the zones exemplified in Table 2.

[0067] Within the LBA value: Zone ID (ZID) 300-399 3 200-299 2 100-199 1 0-99 0

[0068] Assuming there are 200 pages in each block set (e.g., block stripe), these zone IDs can be converted into next block set identifiers through the zone map data structure (201) and pointers can be written as exemplified in Table 3. Each block set identifier identifies the block set (or block stripe) where data is written, and the write pointer tracks the location in the specified zone where new write data should be written next. Data up to the write pointer is readable from the starting location described in Table 2 for each zone.

[0069] Zone ID (ZID) Block set identifier; record pointer 3 0xA, 99 2 0xF, 200 1 0x7, 178 0 0x2, 0

[0070] Accordingly, assuming that a first read request is sent from LBA (200), the command generation processor (122) determines that the zone ID is 2. In response, the command generation processor (122) may perform the read preview operation disclosed herein with multiple commands instructing the command execution processor (124) to store data associated with LBA values ​​(200 to 208), for example, a value obtained by adding an offset of 8 to the base LBA value, in a set of allocated buffers. The offset value may be determined by a predetermined number of pages determined by a predetermined amount of data written sequentially at one time or the amount of data that the buffers can cache. It is assumed that the host system (120) may issue a second read request to an LBA value (201), which is the next sequential LBA after LBA (200). A second subset of data for the LBA value (201) is now stored in buffers, and the command generation processor (122) can return the second subset of data to the host system (120) in response to a second read request.

[0071] FIG. 4 is a flowchart of a method (400) for sequential read optimization according to one embodiment. The method (400) may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (e.g., instructions that operate or are executed on the processing device), or a combination thereof. In some embodiments, the method (400) is performed by the controller (115) of FIG. 1a and 1b (e.g., a command generation processor (122)). Although illustrated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in all embodiments. Other process flows are possible.

[0072] Referring to FIG. 4, in operation (410), the processing logic receives a read request containing a first logical block address (LBA) of the LBA address space for the memory device. In operation (415), the processing logic creates a first logical transfer unit (LTU) containing the first LBA, and the first LTU is mapped to a first physical address of the memory device. As long as the conversion processor (123) has already created an LTU-to-PA entry in the LTU-to-PA mappings (301) of the shared volatile memory (140B) (Fig. 3), the first LTU does not need to be sent to the conversion processor (123). The processing logic can then access the first physical address indexed for the first LTU within the shared memory (140B) (Fig. 3).

[0073] Referring continuing to FIG. 4, in operation (420), the processing logic determines whether a quick lookup flag is set. This quick lookup flag may be a flag (303) associated with a first physical address set in the shared volatile memory (140B); or the quick lookup flag may be a bit value of one of the registers (112) that stores a bit map associated with the ZNS-related physical address space of the memory device (130 or 140). In either case, the quick lookup flag may indicate that the first LTU is associated with a region of multiple sequential LBAs that are sequentially mapped to multiple sequential physical addresses. In operation (440), the processing logic determines whether a die availability flag (305), discussed with reference to FIG. 3, is set.

[0074] In operation (430), if the fast lookup flag or die availability flag is not set, the processing logic submits a read request through a normal read path, which includes sending the first LTU to the conversion processor (123) so that the conversion processor (123) performs a lookup within the ZNS data structures and maps the first LTU to the first physical address.

[0075] In operation (450), assuming that a fast lookup flag and a die availability flag are set for the first LTU, the processing logic retrieves a first physical address stored (or buffered) therein by the conversion processor (123) from the volatile memory (e.g., the shared volatile memory (140B) of FIG. 3). The first physical address may be indexed within an entry of the LTU to PA mappings (301) of the shared volatile memory (140B).

[0076] In operation (460), the processing logic allocates a set of buffers in volatile memory, wherein the capacity of the set of buffers corresponds to the amount of data stored in the first physical address and the subsequent physical addresses sequentially numbered within the read window size starting from the first physical address. The volatile memory storing the buffers may be local memory (119), a volatile memory device (140A), and / or shared volatile memory (140B). In various embodiments, the processing logic determines each subsequent physical address by increasing the first physical address by a page number until the end of the read window size (e.g., an offset value) is reached.

[0077] In operation (470), the processing logic generates a set of command tags that instructs the command execution processor (124) of the processing device to retrieve data from the memory device and store the data in a set of buffers. The set of command tags may include a first command tag associated with a first physical address and additional command tags associated with subsequent physical addresses.

[0078] In operation (480), the processing logic transmits a group of commands, each containing a set of command tags individually, to a command execution processor (124). In one embodiment, a command generation processor (122) may interlink a set of command tags into a command chain (e.g., a chain of individual commands) and transmit the command chain to the command execution processor (124) in a single command message.

[0079] FIG. 5 is a flowchart of a method (500) for sequential read optimization according to a related embodiment. The method (500) may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuit, etc.), software (e.g., instructions that operate or are executed on the processing device), or a combination thereof. In some embodiments, the method (500) is performed by the controller (115) of FIG. 1a and 1b (e.g., a command generation processor (122)). Although illustrated in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in all embodiments. Other process flows are possible.

[0080] Referring to FIG. 5, in operation (510), the processing logic receives a read request containing a first logical block address (LBA) of the LBA address space for the memory device. In operation (520), the processing logic generates a first logical transfer unit (LTU) containing the first LBA and mapped to a first physical address of the memory device.

[0081] In operation (530), the processing logic reads a flag to determine that the first LTU is associated with a region of the LBA address space, wherein the region includes multiple sequential LBAs that are sequentially mapped to multiple sequential physical addresses. As discussed, the flag may be a flag (303) stored in the shared volatile memory (140B) or a bit value of a bit map stored in the registers (112). In either case, the flag or bit value may indicate that the LTU is associated with a region that is mapped to data that is sequentially written to the memory device.

[0082] In operation (540), the processing logic allocates a set of buffers in volatile memory, wherein the capacity of the set of buffers corresponds to the amount of data stored in subsequent physical addresses sequentially numbered within a read window size starting from a first physical address and a physical address. The volatile memory storing the buffers may be local memory (119), a volatile memory device (140A), or other shared volatile memory (140B). In various embodiments, the processing logic determines each subsequent physical address by increasing the first physical address by a page number until the end of the read window size is reached.

[0083] In operation (550), the processing logic generates a set of command tags that instructs the command execution processor of the processing device to retrieve data from the memory device and store the data in a set of buffers. In this embodiment, the set of command tags includes at least a first command tag associated with a first physical address and a second command tag associated with a second physical address, which are subsequent physical addresses that sequentially follow the first physical address.

[0084] FIG. 7 illustrates an exemplary machine of a computer system (700) on which a set of instructions for enabling the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system (700) may correspond to a host system (e.g., the host system (120) of FIG. 1a) that includes, is connected to, or utilizes a memory subsystem (e.g., the memory subsystem (110) of FIG. 1a). In alternative embodiments, the machine may be connected (e.g., network) to another machine on a LAN, intranet, extranet, and / or the Internet. In a client-server network environment, the machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0085] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing a series of commands (sequentially or not) that specify the action to be taken by the machine. Additionally, although a single machine is exemplified, the term “machine” should be considered to include any set of machines that execute a set (or multiple sets) of instructions individually or jointly to perform any one or more of the methodologies discussed herein.

[0086] An exemplary computer system (700) includes a processing device (702), a main memory (704) (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory (706) (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system (718), which communicate with each other via a bus (730).

[0087] The processing device (702) represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processing device (702) may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device (702) is configured to execute instructions (726) for performing the operations and steps discussed herein. The computer system (700) may further include a network interface device (708) for communicating through a network (720).

[0088] The data storage system (718) may include a machine-readable storage medium (724) (also referred to as a computer-readable medium) in which one or more sets of software or instructions (726) that implement any one or more of the methodologies or functions described herein are stored. The instructions (726) may also reside in the main memory (704) and / or processing device (702) in whole or at least partially during execution by the computer system (700), and the main memory (704) and processing device (702) also constitute the machine-readable storage medium. The machine-readable storage medium (724), the data storage system (718), and / or the main memory (704) may correspond to the memory subsystem (110) of FIGS. 1a and 1b.

[0089] In one embodiment, the instruction (726) includes instructions for implementing a function corresponding to the buffer manager (113) of FIG. 1b. Although the machine-readable storage medium (724) is illustrated as an exemplary embodiment of a single medium, the term “non-transient machine-readable storage medium” should be considered to include a single medium or multiple media storing one or more sets of instructions. The term “machine-readable storage medium” should also be considered to include any medium capable of storing or encoding a set of instructions executed by a machine and enabling the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0090] Parts of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. Such algorithmic descriptions and representations are methods used by technicians in the field of data processing technology to most effectively convey the content of their work to others in the relevant field. An algorithm is generally regarded in this specification as a sequence of self-consistent operations leading to a desired result. Operations are operations that require the physical manipulation of physical quantities. Generally, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and manipulated. For general use, it has sometimes proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0091] However, it should be kept in mind that all such terms and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to such quantities. The present disclosure may refer to the operations and processes of similar electronic computing devices that manipulate and convert data represented as physical (electronic) quantities within a computer system or within the registers and memory of a computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0092] The present disclosure also relates to an apparatus for performing the operation of the present specification. The apparatus may include a general-purpose computer that is specifically configured for an intended purpose or is optionally activated or reconfigured by a computer program stored in the computer. Such computer programs may be stored on any type of disk, including but not limited to floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions coupled to a computer system bus.

[0093] The algorithms and displays presented in this specification are not inherently associated with any specific computer or other device. Various general-purpose systems may be used with programs according to the teachings of this specification, or it may prove convenient to configure more specialized devices to perform the methods. The structures of such various systems appear as described below. Furthermore, this disclosure is not described by reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described in this specification.

[0094] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium in which instructions are stored, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer-readable) storage medium, e.g., read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage medium, optical storage medium, flash memory component, etc.

[0095] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the present specification and drawings should be conceived in an illustrative sense rather than a restrictive one.

Claims

Claim 1 A system comprises: a memory device; a volatile memory including buffers; and a processing device coupled to the memory device and the volatile memory, wherein a command generation processor of the processing device: receives a read request from a host system including a first logical block address (LBA) of an LBA address space for the memory device; generates a first logical transfer unit (LTU) to include the first LBA—wherein the first LTU is mapped to a first physical address of the memory device—; reads a flag from the volatile memory to determine that the first LTU is associated with a region of the LBA address space—wherein the region includes a plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses; A system comprising a command execution processor of the processing device and generating a set of command tags that instructs the processing device to retrieve data from the memory device and store the data in a set of buffers, wherein the set of command tags includes a first command tag associated with a first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. Claim 2 A system according to claim 1, wherein each command tag of the set of command tags comprises: an LTU number identifying an LTU mapped to a physical address in the physical address space of the memory device; and a buffer address of a location within the set of buffers. Claim 3 A system according to claim 1, wherein the set of command tags further includes additional command tags associated with subsequent physical addresses sequentially numbered after the second physical address, and each subsequent physical address is increased by a page number from the first physical address until the end of the read window size is reached. Claim 4 In claim 1, the command generation processor of the processing device also: retrieves the first physical address from the volatile memory; and returns to the host system a first subset of the data retrieved from the first physical address and stored in the first buffer of the set of buffers. Claim 5 In paragraph 4, in response to a second read request, the command generation processor determines that the second LBA of the second read request corresponds to the second physical address; retrieves a second subset of the data from a second buffer of the set of buffers—wherein the second buffer has a buffer address associated with the second command tag—; and transmits the second subset of the data to the host system. Claim 6 In claim 1, the translation processor of the processing device sets the flag in the volatile memory based on the data sequentially written to the memory device. Claim 7 A system according to claim 1, wherein the command generation processor also transmits a group of commands, each comprising one of the sets of command tags individually, to the command execution processor of the processing device, and in response to the reception of the set of command tags, the command execution processor retrieves the data from the memory device and stores the data in the set of buffers according to the individual buffer addresses of the set of command tags. Claim 8 In claim 1, the command generation processor also: interlinks the set of command tags to a command chain; and transmits the command chain to the command execution processor in a single command message, a system. Claim 9 In claim 1, the command generation processor also: a 2-3 tree algorithm in which the buffers are classified by LTU numbers; or a system that tracks and allocates the buffers within the volatile memory using one of an N-way cache using a hash algorithm. Claim 10 In a method, the command generation processor of a processing device receives a read request including a first logical block address (LBA) of an LBA address space for a memory device; the command generation processor generates a first logical transfer unit (LTU) to include the first LBA—wherein the first LTU is mapped to a first physical address of the memory device—; the command generation processor reads a bit value of a bit map from a volatile memory to determine that the first LTU is associated with a region of the LBA address space—wherein the region includes a plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses—; the command generation processor allocates a set of buffers to the volatile memory—wherein the capacity of the set of buffers corresponds to the amount of data stored at the first physical address and subsequent physical addresses sequentially numbered within a read window size starting from the first physical address—; A method comprising the step of generating a set of command tags by the command generation processor, which instructs the command execution processor of the processing device to retrieve the data from the memory device and store the data in the set of buffers, wherein the set of command tags includes at least a first command tag associated with the first physical address and a second command tag associated with the second physical address among the subsequent physical addresses sequentially following the first physical address. Claim 11 A method according to claim 10, further comprising: by the command generating processor: the step of retrieving the first physical address from the volatile memory; the step of determining that a die availability flag associated with the first physical address is set; and the step of returning to a requesting agent the first subset of the data retrieved from the first physical address and cached in the first buffer of the set of buffers. Claim 12 A method according to claim 11, further comprising: receiving a second read request; determining that a second LBA of the second read request corresponds to the second physical address within the read window size from the first physical address; retrieving a second subset of the data from a second buffer of the set of buffers—wherein the second buffer has a buffer address associated with the second command tag—; and transmitting the second subset of the data to the request agent. Claim 13 A method according to claim 10, comprising the step of tracking the use of a set of buffers through the use of one of a flag or a counter for each buffer, wherein the tracking enables the use of the set of buffers by multiple host applications corresponding to multiple zones. Claim 14 In claim 10, the set of command tags further includes additional command tags associated with the subsequent physical addresses to include the second command tag, and the method further includes the step of determining the subsequent physical addresses by increasing the first physical address by a page number until the end of the read window size is reached from the first physical address. Claim 15 A method according to claim 10, wherein the step of generating the set of command tags further comprises: within the command buffer of the volatile memory: the first command tag with the first LTU number of the first LTU and the first buffer address of the set of buffers; and the second command tag with the second LTU number of the second LTU corresponding to the second LBA and the second buffer address of the set of buffers. Claim 16 A method according to claim 10, further comprising: a step of determining by a conversion processor of the processing device that the first LBA is associated with the area; and a step of setting the bit value associated with the first physical address in the volatile memory based on the data sequentially written to the memory device. Claim 17 In claim 10, the set of command tags further includes additional command tags associated with subsequent physical addresses to include the second command tag, and the method further comprises: transmitting a group of commands, each comprising the set of command tags, to a command execution processor by the command generation processor; retrieving the data from the first physical address and the subsequent physical addresses of the memory device by the command execution processor; and storing the data in a set of buffers according to the individual buffer addresses of the set of command tags. Claim 18 A method according to claim 10, further comprising the steps of: interlinking a set of command tags to a command chain; and transmitting the command chain to a command execution processor in a single command message. Claim 19 A method according to claim 10, further comprising the step of tracking the allocation of a set of buffers within the volatile memory through one of an N-way cache using a 2-3 tree algorithm in which the set of buffers is classified by an LTU; or a hash algorithm. Claim 20 As a non-transitory computer-readable medium for storing instructions, the instructions are executed by a command generation processor of a processing device of a subsystem memory controller, wherein the processing device comprises: receiving a read request including a first logical block address (LBA) of an LBA address space for a memory device; generating a first transfer unit (LTU) by the command generation processor to include the first LBA—wherein the first LTU is mapped to a first physical address of the memory device—; reading a flag from volatile memory to determine that the first LTU is associated with a region of the LBA address space—wherein the region includes a plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses—; allocating a set of buffers to the volatile memory—wherein the capacity of the set of buffers is sequentially numbered within the first physical address and subsequent physical addresses starting from the first physical address A non-transient computer-readable medium comprising: a quantity of data stored at an address that matches the amount of data stored at the address; and a step of generating a set of command tags that instructs a command execution processor of the processing device to retrieve the data from the memory device and store the data in a set of buffers, wherein the set of command tags comprises at least a first command tag associated with a first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address.

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