Packaging Substrate

Abstract

The packaging substrate of the embodiment comprises a glass core; an upper redistribution layer; and a lower redistribution layer. The glass core is a plate-shaped glass having vias, the upper redistribution layer is a redistribution layer disposed on top of the glass core, and the lower redistribution layer is a redistribution layer disposed on bottom of the glass core. The redistribution layer includes a wiring layer and an insulating layer. The wiring layer is a patterned copper layer having grains, and an upper surface is located on top of the upper redistribution layer, and an electronic device is mounted on the upper surface. C is the area ratio of grains in the wiring layer disposed on the upper redistribution layer, where the ratio of the long axis to the short axis is 3:1 or greater, and D is the area ratio of grains in the wiring layer disposed on the lower redistribution layer, where the ratio of the long axis to the short axis is 3:1 or greater. The value obtained by dividing C of the packaging substrate by D is 0.85 or greater and 0.99 or less. An embodiment can provide a packaging substrate that improves signal integrity and reduces the occurrence of problems such as electromagnetic interference even during high-frequency signal transmission by controlling the crystal structure of copper placed in the wiring layer.

Description

Technology Field

[0001] An embodiment relates to a packaging substrate with improved integrity and reliability of electrical signal transmission. Background Technology

[0003] In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process.

[0004] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself.

[0005] Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch.

[0006] Recently, research is underway on applying glass substrates as packaging substrates for high-end applications. By forming through-holes in the glass substrate and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0007] Related prior art includes Korean registered patent No. 10-2400616 and Korean published patent No. 10-2023-0154459. The problem to be solved

[0009] The objective of the embodiment is to provide a packaging substrate that reduces signal reflection and distortion caused by impedance mismatch between wiring layers and improves the quality of signal transmission.

[0010] The purpose of the embodiment is to provide a packaging substrate that improves signal integrity by controlling the crystal structure of copper placed in the wiring layer and reduces the occurrence of problems such as electromagnetic interference even during high-frequency signal transmission.

[0011] The purpose of the embodiment is to provide a packaging substrate with improved reliability by reducing heat generation during electrical signal transmission to improve the efficiency of power and signal transmission. means of solving the problem

[0013] A packaging substrate according to one embodiment for achieving the above objective is a packaging substrate comprising: a glass core; an upper redistribution layer; and a lower redistribution layer; wherein the glass core is a plate-shaped glass having vias disposed therein, the upper redistribution layer is disposed on the upper side of the glass core, the lower redistribution layer is disposed on the lower side of the glass core, and each of the upper redistribution layer and the lower redistribution layer includes a wiring layer and an insulating layer.

[0014] The above wiring layer is a patterned copper layer having grains, the above insulating layer is a layer comprising an insulating polymer resin or an insulating inorganic material, an upper surface is located on the upper part of the upper wiring layer and an electronic component is mounted on the upper surface, and a lower surface opposite to the upper surface is located on the lower part of the lower wiring layer.

[0015] C is the area ratio of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the upper wiring layer above.

[0016] D is the area ratio of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the lower wiring layer above.

[0017] The value of C of the above packaging substrate divided by D may be 0.85 or higher and 0.99 or lower.

[0018] The copper layer comprises (111) direction-oriented grains, (200) direction-oriented grains, (220) direction-oriented grains, (211) direction-oriented grains and (310) direction-oriented grains.

[0019] TC is the sum of the area ratio of the (220) direction-oriented grain, the area ratio of the (211) direction-oriented grain, and the area ratio of the (310) direction-oriented grain.

[0020] TD is the sum of the area ratio of the (111) direction-oriented grains and the area ratio of the (200) direction-oriented grains.

[0021] A is the ratio of TD based on TC in the wiring layer disposed in the upper redistribution layer.

[0022] B is the ratio of TD based on TC in the wiring layer disposed in the lower redistribution layer.

[0023] The value obtained by dividing the above A of the above packaging substrate by the above B may be 0.60 or more and 0.75 or less.

[0024] The average size of the grains in the wiring layer disposed in the upper wiring layer may be larger than the average size of the grains in the wiring layer disposed in the lower wiring layer.

[0025] A of the above packaging substrate may be 0.2 or higher.

[0026] The average size of the grains in the wiring layer disposed in the upper wiring layer above may be 0.45 μm or more and 0.48 μm or less.

[0027] The average size of the grains in the wiring layer disposed in the lower wiring layer above may be 0.50 μm or more and 0.53 μm or less.

[0028] The above packaging substrate may have an impedance of 49Ω or more and 52Ω or less.

[0029] The above packaging substrate has an electrical conductivity of 5.0 x 10 7 It may be more than S / m.

[0030] The above packaging substrate may have a reflection coefficient of 3.2% or less.

[0031] The above packaging substrate may have a signal delay of 80 pc or less. Effects of the invention

[0033] The packaging substrate of the embodiment can reduce signal reflection and distortion caused by impedance mismatch between wiring layers and improve the quality of signal transmission. In addition, by controlling the crystal structure of copper during electrical signal transmission, signal integrity can be improved, and the occurrence of problems such as electromagnetic interference can be reduced even during high-frequency signal transmission. Furthermore, by reducing heat generation during electrical signal transmission, the efficiency of power and signal transmission can be improved, thereby enhancing reliability. Brief explanation of the drawing

[0035] FIG. 1a is a drawing showing the EBSD Map of Example 1-1; FIG. 1b is a drawing showing the area ratio of grains in Example 1-1 where the long-short axis ratio is 3:1 or greater; FIG. 1c is a drawing showing the area ratio of each oriented grain of Example 1-1; FIG. 2a is a drawing showing the EBSD Map of Example 1-2; FIG. 2b is a drawing showing the area ratio of grains in Example 1-2 where the long-short axis ratio is 3:1 or greater; and FIG. 2c is a diagram showing the area ratio of each orientation grain in Examples 1-2. Specific details for implementing the invention

[0036] Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals.

[0037] Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components.

[0038] Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”.

[0040] In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A.

[0041] In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B.

[0042] In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified.

[0043] In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings.

[0044] In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other.

[0045] Unless otherwise specified in this specification, the physical property values ​​of each component within the packaging substrate are interpreted as being measured at room temperature. Room temperature is 20°C to 25°C.

[0047] The packaging substrate of the embodiment utilizes a glass core. This offers advantages that distinguish it from conventional silicon substrates and pre-flegs (polymer-impregnated glass fiber substrates). First, compared to pre-flegs, it enables the expression of fine wiring. Additionally, the glass substrate possesses insulating properties, and there is less concern regarding the occurrence of parasitic elements even when driven at high frequencies. This distinguishes it from silicon substrates, which exhibit semiconductor characteristics and consequently exhibit parasitic element phenomena during high-frequency operation.

[0048] In this regard, a packaging substrate incorporating a glass core is advantageous for packaging semiconductor devices that utilize high frequencies. However, regarding electrical signal transmission, signal reflection or distortion may occur. Recognizing the need to improve signal integrity and reliability in the packaging substrate, the following embodiments are presented.

[0049] The following describes an example of implementation in more detail.

[0050] To achieve the above objective, a packaging substrate according to one embodiment comprises: a glass core; an upper redistribution layer; and a lower redistribution layer.

[0051] The above glass core is a plate-shaped glass with vias arranged therein.

[0052] Glass cores utilize plate glass (glass substrates) for semiconductors, which are highly commercially viable due to their lower cost and relatively ease of large-area manufacturing compared to substrates such as sapphire. Additionally, they possess insulating properties compared to inorganic semiconductor substrates like silicon. This enables packaging substrates with glass cores to offer advantages such as superior power efficiency and greater stability at higher frequencies.

[0053] As for the above-mentioned plate glass, a semiconductor glass substrate may be applied, and borosilicate glass may be applied as an example, but is not limited thereto.

[0054] The above glass core is formed by vias in the glass plate. In addition to vias, other structures such as cavities may be formed.

[0055] The above glass core can be obtained by selectively etching the above glass plate or etching it at a different speed. The etching may include laser etching, chemical etching, etc. Additionally, a glass core can be manufactured by selectively etching only the parts requiring etching through masking, or by creating defects in the glass plate using a laser or the like and then creating a difference in the etching speed to form vias, etc.

[0056] An electrically conductive layer may be disposed on the surface of the glass core. For example, the electrically conductive layer may be a copper layer, but is not limited thereto.

[0057] The surface of the glass core includes the upper and / or lower surface of the plate glass. Also, the surface of the glass core includes the surface of the via.

[0058] The electrically conductive layer may be disposed on the upper and / or lower surface of the plate glass, and may also be disposed on the surface of the via or in a form that fills the via.

[0059] A packaging substrate can transmit electrical signals to a device or another substrate placed on its upper and / or lower surface using a glass core as a support.

[0060] The upper redistribution layer is a redistribution layer placed on top of the glass core.

[0061] An upper surface is located on the upper side of the upper redistribution layer, and an electronic component is mounted on the upper surface.

[0062] The lower redistribution layer is a redistribution layer placed below the glass core.

[0063] A lower surface facing the upper surface is located at the bottom of the lower redistribution layer.

[0064] The redistribution layer includes a wiring layer and an insulation layer.

[0065] The wiring layer is a patterned copper layer.

[0066] The copper layer contains metallic copper having grains.

[0067] The copper layer can be an electroplated layer.

[0068] The insulating layer is a layer containing an insulating polymer resin or an insulating inorganic material.

[0069] The above insulating polymer resin may be, for example, an epoxy resin, a polyimide resin, etc. The above insulating inorganic material may be, for example, silica.

[0070] For example, the insulating layer may be ABF (Ajinomoto Build-up Film) or EMC (Epoxy Molding Compound).

[0071] In the wiring layer, copper layers can be arranged in a predetermined pattern.

[0072] The circuit layer is a copper layer arranged in a flat, predetermined pattern.

[0073] The through-electrode is a pattern in which copper layers are connected vertically.

[0074] The wiring layer may include both the circuit layer and the through electrode.

[0075] A single layer of wiring is collectively referred to as a single layer of through-electrode and a single layer of circuit connected thereto.

[0076] The upper redistribution layer may include one or more layers, two or more layers, or three or more layers of the wiring layer. Additionally, the upper redistribution layer may include 25 or fewer layers, 20 or fewer layers, or 15 or fewer layers of the wiring layer.

[0077] The lower redistribution layer may include one or more layers, two or more layers, or three or more layers of the wiring layer. Additionally, the lower redistribution layer may include 20 or fewer layers, 15 or fewer layers, or 10 or fewer layers of the wiring layer.

[0078] The above packaging substrate may further include a cover layer on the upper redistribution layer. The cover layer may be a polyimide layer, but is not limited thereto.

[0079] The above packaging substrate may further include a solder resist layer under the lower redistribution layer. The solder resist layer may be a solder resist applied to a semiconductor or a composition for a solder mask.

[0081] Wiring layers play a crucial role in the electrical signal transmission of packaging substrates. For example, if an impedance mismatch occurs between the upper and lower wiring layers of a packaging substrate, signal reflection and distortion can occur frequently. In particular, such impedance mismatches present in the high-speed signal transmission paths of semiconductor substrates degrade signal quality and reduce the reliability of data transmission. Consequently, if an impedance mismatch occurs between the upper and lower wiring layers of a packaging substrate, there are limitations in maintaining signal integrity in modern electronic devices that require high-speed communication.

[0082] Furthermore, the balance of crystal structures between wiring layers is also related to signal integrity. Specifically, differences in grain structure can occur between the upper and lower wiring layers of a packaging substrate, which can lead to non-uniform electron transport paths. This is one of the causes of problems such as electromagnetic interference (EMI) during high-frequency signal transmission. Additionally, such imbalances in crystal structures can induce distortion during signal transmission, leading to system performance degradation. Moreover, significant differences in electrical conductivity between the upper and lower wiring layers can reduce power transfer and signal transmission efficiency.

[0083] Accordingly, the inventors present an embodiment by confirming that mitigating the conductivity difference between the upper and lower wiring layers of a packaging substrate, improving impedance matching, mitigating signal loss in the transmission path, and mitigating heat generation can ultimately have a positive effect on the overall reliability and lifespan of the packaging substrate and the semiconductor package to which it is applied.

[0085] (111), (200), (220), (211), and (310) each represent the crystal orientation of the copper grains. The copper layer comprises (111) oriented grains, (200) oriented grains, (220) oriented grains, (211) oriented grains, and (310) oriented grains.

[0086] The orientation distribution and ratio of copper grains in the wiring layer can be confirmed through EBSD (Electron Backscatter Diffraction) measurements. Specific measurement methods and conditions are the same as those described in the laboratory examples.

[0087] (111) The plane is the plane with the densest atomic arrangement in the face-centered cubic (FCC) structure. This plane has high electrical conductivity and excellent mechanical strength.

[0088] The (200) plane is identical to the (100) plane and is the plane with the second densest atomic arrangement. This plane also exhibits relatively good electrical conductivity.

[0089] (220) plane is identical to (110) plane and is a plane with an intermediate atomic density.

[0090] (211) and (310) planes are planes with a relatively less dense atomic arrangement.

[0091] TC is the sum of the area ratio of the (220) direction-oriented grain, the area ratio of the (211) direction-oriented grain, and the area ratio of the (310) direction-oriented grain.

[0092] TD is the sum of the area ratio of the (111) direction-oriented grains and the area ratio of the (200) direction-oriented grains.

[0093] The ratio of the above TC and the above TD is related to the distribution ratio of grains with high atomic density and grains with low atomic density.

[0094] A is the ratio of TD based on TC in the wiring layer disposed in the upper wiring layer, and B is the ratio of TD based on TC in the wiring layer disposed in the lower wiring layer.

[0095] The packaging substrate of the embodiment may have a value of A divided by B of 0.60 or higher and 0.75 or lower. The value of A divided by B may be 0.62 or higher, 0.64 or higher, 0.66 or higher, or 0.68 or higher. A packaging substrate in which the value of A divided by B is within the above range may have high electrical conductivity, which can serve to reduce resistance in the electron transport path. This allows the packaging substrate to substantially suppress signal reflection and distortion caused by impedance mismatch, and enables excellent electrical signal transmission.

[0096] A of the above packaging substrate may be 0.2 or higher. A may be 0.21 or higher, 0.22 or higher, or 0.23 or higher. A may be 0.5 or lower, 0.4 or lower, or 0.3 or lower.

[0097] B of the above packaging substrate may be 0.5 or less. B may be 0.45 or less, 0.4 or less, or 0.35 or less. B may be 0.1 or more, 0.15 or more, 0.2 or more, 0.25 or more, or 0.3 or more.

[0098] C is the area ratio (%) of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the upper wiring layer.

[0099] D is the area ratio (%) of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the lower wiring layer above.

[0100] The value obtained by dividing C of the above packaging substrate by D may be 0.85 or higher and 0.99 or lower. The value obtained by dividing C by D may be 0.87 or higher, 0.9 or higher, or 0.92 or higher. The value obtained by dividing C by D may be 0.98 or lower, 0.97 or lower, or 0.96 or lower. A packaging substrate having these characteristics may have a wiring layer having a grain structure suitable for an electron transport path. This contributes to maintaining or increasing the electrical conductivity of the wiring layer and is thought to play an important role in reducing electromagnetic interference (EMI) and crosstalk phenomena, particularly during high-frequency signal transmission. A packaging substrate having the above characteristics may have reduced resistance in the electron transport path, reduced signal distortion, and consequently improved electrical conductivity.

[0101] The average size of the grains in the wiring layer disposed in the upper redistribution layer may be larger than the average size of the grains in the wiring layer disposed in the lower redistribution layer. In this case, the mechanical strength and electrical performance of the packaging substrate can be improved simultaneously.

[0102] The average size of the grains in the wiring layer disposed in the upper wiring layer may be 0.45 μm or more and 0.48 μm or less. The size may be 0.46 μm or more, or 0.465 μm or more. The size may be 0.48 μm or less, 0.475 μm or less, or 0.47 μm or less.

[0103] When the average grain size is as described above, an excellent wiring layer suitable for the upper redistribution layer can be obtained, with mechanical strength and electrical performance of the wiring layer.

[0104] The average size of the grains in the wiring layer disposed in the lower wiring layer may be 0.50 μm or more and 0.53 μm or less. The size may be 0.505 μm or more, or 0.51 μm or more. The size may be 0.525 μm or less, or 0.52 μm or less.

[0105] When the average grain size is as described above, an excellent wiring layer suitable for the lower rewiring layer can be obtained, with mechanical strength and electrical performance of the wiring layer.

[0106] The impedance of the above packaging substrate may be 49Ω or more and 52Ω or less. The impedance may be 49.3Ω or more, 49.6Ω or more, or 49.8Ω or more. The impedance may be 51.5Ω or less, 51Ω or less, or 50.5Ω or less. In this case, the packaging substrate enables signal transmission with higher transmission efficiency.

[0107] The above packaging substrate has an electrical conductivity of 5.2 x 10 7 It may be greater than S / m. The above electrical conductivity is 5.4 x 10 7 S / m or more, 5.6 x 10 7S / m or more, or 5.7 x 10 7 It may be greater than S / m. Also, the above electrical conductivity is 10 x 10 7 S / m or less, 9.9 x 10 7 S / m or less, or 9.8 x 10 7 It may be less than S / m.

[0108] The above impedance and electrical conductivity values ​​are based on measurements taken by the method presented in the laboratory examples described below.

[0109] The above packaging substrate may have a reflection coefficient of 3.2% or less. The reflection coefficient may be 3.1% or less, 3% or less, 2.9% or less, or 2.8% or less. The reflection coefficient may be 2% or more, 2.3% or more, or 2.5% or more.

[0110] The above packaging substrate may have a signal delay of 80 pc or less. The signal delay may be 78 ps or less, 76 ps or less, or 75 ps or less. The signal delay may be 50 ps or more, 65 ps or more, or 70 ps or more.

[0111] The packaging substrate of the embodiment has excellent crystal structure and electrical characteristics of the wiring layer, so stable and reliable performance can be expected in electronic devices requiring high-speed signal transmission.

[0112] The packaging substrate of the embodiment can reduce transmission loss and is highly useful in 5G communication, high-speed computing, data transmission systems, etc., where high-speed signal transmission is required.

[0114] The following provides a more detailed explanation through specific embodiments. The following embodiments are merely examples to aid in understanding the present invention and do not limit the scope of the invention.

[0116] Preparation Example

[0117] After cutting a glass substrate to a size of 10 cm x 10 cm, the substrate surface was etched in a mixture of 1.8 M hydrofluoric acid (HF) and 1.0 M nitric acid (HNO₃) for 5 minutes to clean it. Immediately after etching, the substrate was rinsed with deionized water for 1 minute and 30 seconds, followed by neutralization treatment using a 4.5% neutralization solution (sodium bicarbonate) for 30 seconds. The neutralized substrate was rinsed again with deionized water and completely dried with nitrogen gas. This substrate was used as a glass core to form a redistribution layer as shown below.

[0119] Example 1

[0120] Example 1-1: Upper redistribution layer

[0121] A titanium (Ti) seed layer was deposited to a thickness of 50 nm on the upper surface of a glass core via sputtering, followed by the deposition of copper (Cu) to a thickness of 120 nm to form a seed layer. The electroplating solution consisted of 75 g / L copper(II) sulfate, 200 g / L sulfuric acid, and 50 mg / L hydrochloric acid (HCl), with 4.0 ppm polyethylene glycol (PEG), 3.0 ppm sodium sulfide (SPS), and 0.8 ppm Janus Green B (JGB) added as additives. Electroplating was performed at a temperature of 24°C with a current density of 1.8 A / dm² for 33 minutes. During this process, a copper wiring layer with a thickness of 9 μm was formed. After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 220°C for 45 minutes in a nitrogen atmosphere to grow grains and optimize electrical conductivity.

[0122] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulator layers. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 20 μm.

[0124] Example 1-2: Lower redistribution layer

[0125] Sputtering and plating were performed in the same manner as in Example 1-1. However, for electroplating, the current density was set to 1.8 A / dm² at a temperature of 25°C, and the plating was carried out for 28 minutes. During this process, a copper wiring layer was formed with a thickness of 8.5 μm.

[0126] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 210°C for 25 minutes in a vacuum atmosphere to grow grains and optimize electrical conductivity.

[0127] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three layers at the bottom were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 18 μm.

[0129] Example 2

[0130] Example 2-1: Upper redistribution layer

[0131] Sputtering and plating were performed in the same manner as in Example 1-1. However, for electroplating, the current density was set to 1.95 A / dm² at a temperature of 24°C, and the plating was carried out for 28 minutes. During this process, a copper wiring layer was formed with a thickness of 9.2 μm.

[0132] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 227°C for 38 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0133] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 18 μm.

[0135] Example 2-2: Lower redistribution layer

[0136] Sputtering and plating were performed in the same manner as in Example 1-1. However, for electroplating, the current density was set to 1.95 A / dm² at a temperature of 25°C, and the plating was performed for 29 minutes. During this process, a copper wiring layer was formed with a thickness of 9.0 μm.

[0137] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 223°C for 32 minutes in a vacuum atmosphere to grow grains and optimize electrical conductivity.

[0138] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three layers at the bottom were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 17 μm.

[0140] Example 3

[0141] Example 3-1: Upper redistribution layer

[0142] Sputtering and plating were performed in the same manner as in Example 1-1. However, for electroplating, the current density was set to 1.85 A / dm² at a temperature of 23°C, and the plating was carried out for 33 minutes. During this process, a copper wiring layer was formed with a thickness of 9.3 μm.

[0143] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 232°C for 40 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0144] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 19 μm.

[0146] Example 3-2: Lower redistribution layer

[0147] Sputtering and plating were performed in the same manner as in Example 1-1. However, for electroplating, the current density was set to 2.05 A / dm² at a temperature of 26°C, and the plating was performed for 27 minutes. During this process, a copper wiring layer was formed with a thickness of 9.1 μm.

[0148] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 222°C for 30 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0149] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three bottom layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 18 μm.

[0151] Comparative Example 1

[0152] Comparative Example 1-1: Upper cultivation layer

[0153] A titanium (Ti) seed layer was deposited to a thickness of 50 nm on the upper surface of a glass core by sputtering, followed by the deposition of copper (Cu) to a thickness of 120 nm to form a seed layer. The electroplating solution consisted of 75 g / L copper(II) sulfate, 200 g / L sulfuric acid, and 50 mg / L hydrochloric acid (HCl), with 4.0 ppm polyethylene glycol (PEG), 3.0 ppm sodium sulfide (SPS), and 0.8 ppm Janus Green B (JGB) added as additives. Electroplating was performed at a temperature of 24°C with a current density of 1.8 A / dm² for 33 minutes. During this process, a copper wiring layer was formed to a thickness of 9 μm.

[0154] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 235°C for 38 minutes in a nitrogen atmosphere to grow grains and optimize electrical conductivity.

[0155] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 17 μm.

[0157] Comparative Example 1-2: Lower distribution layer

[0158] Sputtering and plating were performed in the same manner as in Comparative Example 1-1. However, for electroplating, the current density was set to 2.1 A / dm² at a temperature of 24°C, and the plating was performed for 29 minutes. During this process, a copper wiring layer was formed with a thickness of 8.2 μm.

[0159] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 240°C for 30 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0160] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three bottom layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 17 μm.

[0162] Comparative Example 2

[0163] Comparative Example 2-1: Upper cultivation layer

[0164] Sputtering and plating were performed in the same manner as in Comparative Example 1-1. However, for electroplating, the current density was set to 2.0 A / dm² at a temperature of 22°C, and the plating was carried out for 34 minutes. During this process, a copper wiring layer was formed with a thickness of 7.3 μm. After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 225°C for 38 minutes in a vacuum atmosphere to grow crystal grains and optimize electrical conductivity.

[0165] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 16 μm.

[0167] Comparative Example 2-2: Lower distribution layer

[0168] Sputtering and plating were performed in the same manner as in Comparative Example 1-1. However, for electroplating, the current density was set to 2.4 A / dm² at a temperature of 23°C, and the plating was performed for 30 minutes. During this process, a copper wiring layer was formed with a thickness of 8.1 μm.

[0169] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 240°C for 32 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0170] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three bottom layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 17 μm.

[0172] Comparative Example 3

[0173] Comparative Example 3-1: Upper cultivation layer

[0174] Sputtering and plating were performed in the same manner as in Comparative Example 1-1. However, for electroplating, the current density was set to 1.8 A / dm² at a temperature of 24°C, and the plating was carried out for 31 minutes. During this process, a copper wiring layer was formed with a thickness of 8.2 μm. After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 228°C for 40 minutes in a vacuum atmosphere to grow crystal grains and optimize electrical conductivity.

[0175] Subsequently, a total of six copper wiring layers were laminated to form the upper redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All six upper layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the upper redistribution layer was fully laminated, polyimide was laminated to a thickness of 18 μm.

[0177] Comparative Example 2-2: Lower distribution layer

[0178] Sputtering and plating were performed in the same manner as in Comparative Example 1-1. However, for electroplating, the current density was set to 1.9 A / dm² at a temperature of 25°C, and the plating was performed for 29 minutes. During this process, a copper wiring layer was formed with a thickness of 8.4 μm.

[0179] After the electroplating was completed, the substrate was washed with deionized water and dried with nitrogen gas. The formed copper wiring layer was heat-treated at 232°C for 30 minutes in a vacuum atmosphere to grow the grains and optimize electrical conductivity.

[0180] Subsequently, a total of three copper wiring layers were laminated to form the lower redistribution layer. Each wiring layer was formed by repeating electroplating and heat treatment processes, and an epoxy film insulator (ABF, manufactured by Ajinomoto) was laminated between each layer to prevent electrical interference and maintain insulation. All three bottom layers were formed through the repeated lamination process of copper wiring layers and epoxy film insulators. After the lower redistribution layer was fully laminated, a solder resist was laminated to a thickness of 18 μm.

[0181] The manufacturing method conditions of the samples of the examples and comparative examples are summarized in Table 1 below.

[0182] division Electroplating temperature (°C) Current density (A / dm²) Plating time (minutes) Copper wiring layer thickness (μm) Heat treatment temperature (°C) Heat treatment time (min) Protective layer thickness (μm) Example 1-1 24 1.8 33 9 220 45 20 Examples 1-2 25 1.8 28 8.5 210 25 18 Example 2-1 24 1.95 28 9.2 227 38 18 Example 2-2 25 1.95 29 9 223 32 17 Example 3-1 23 1.85 33 9.3 232 40 19 Example 3-2 26 2.05 27 9.1 222 30 18 Comparative Example 1-1 23 2 34 7.8 235 38 17 Comparative Example 1-2 24 2.1 29 8.2 240 30 17 Comparative Example 2-1 22 2 34 7.3 225 38 16 Comparative Example 2-2 23 2.4 30 8.1 240 32 17

[0183] Measurement of electrical conductivity

[0184] Electrical conductivity measurements were performed in accordance with the ASTM B193-19 standard. The electrical conductivity was calculated by measuring the resistance of copper thin film samples using the 4-point probe method with a Keithley 2450 SourceMeter. The thickness of the samples was precisely measured using a scanning electron microscope (SEM) or a profilometer, and measurements were conducted at a temperature of 23 ± 1°C. The current range was set to 0.1 mA to 100 mA and the voltage range to 1 mV to 100 mV. Measurements were repeated three times at five locations for each sample, and the mean and standard deviation were calculated from a total of 15 data points. Additionally, reliability was ensured by calibrating the equipment with standard copper samples and evaluating uncertainty, and measures to prevent contamination during sample handling were taken into consideration.

[0186] Measurement of impedance

[0187] Impedance was measured using a Keithley 2450 SourceMeter. A 4-point probe method was applied for impedance measurement, and this was utilized as a standard method to precisely measure the resistance and impedance of the sample. The equipment used was the Model 2450 manufactured by Keithley Instruments, Inc., and the impedance of the wiring layer of the upper and lower redistribution layers was measured, respectively. Measurements were performed at a room temperature of 23°C, and to obtain accurate data, the sample was measured three times and the average value was used.

[0188] Prior to measurement, the sample was washed with ethanol and completely dried with nitrogen gas. Subsequently, the impedance of the sample was measured using a Keithley 2450 SourceMeter while supplying a current of 1 mA. Data was collected using precision resistance measurement mode by connecting 4-point probes to the electrodes of the wiring layer of the upper and lower redistribution layers. Impedance values ​​were measured in the frequency band from 1 Hz to 10 MHz, and the measured data was automatically collected via the Keithley Test Script Processor (TSP) program. Each measurement was repeated three times to calculate the average, and the standard deviation was also recorded to ensure the reliability of the results.

[0189] To reduce noise that may occur during impedance measurement, all wiring used shielded cables to minimize external interference.

[0190] The measurement results are shown in Table 2 below.

[0192] Measurement of EBSD (Electron Backscatter Diffraction)

[0193] Sample pretreatment was performed as follows. Packaging substrate specimens were cut at random locations using a knife. The cut samples were hot-mounted using carbon paste (15 minutes). The mounted samples were polished to expose the wiring layer (copper layer) of the upper redistribution layer and the wiring layer (copper layer) of the lower redistribution layer, respectively.

[0194] Polishing was performed as follows. It was polished with water at a speed of 120 RPM for 2 hours using SiC sandpaper (#600, #2000, and #4000, respectively). Afterwards, it was polished with ethanol at a speed of 120 RPM for 20 minutes using diamond suspension (DP-suspension, 3 µm and 1 µm, respectively). Afterwards, it was polished with lubricant blue at a speed of 120 RPM for 1 hour using colloidal silica suspension (OP-suspension, 0.04 µm).

[0195] The polished samples were washed with ethanol using an ultrasonic cleaner and then dried with a hair dryer for 10 minutes. The dried samples were measured using SEM EBSD with an applied acceleration voltage of 15 kV. The analysis area was positioned randomly, and measurements were taken for 30 minutes per sample using a width of 40 µm and a step size of 0.06 µm.

[0196] The SEM instrument used was JEOL’s JSM-7100F, and the EBSD instrument used was EDAX.

[0197] The EBSD analysis program used OIM data collection, and the data processing program used TSL OIM Analysis.

[0198] The measurement results are shown in Table 2 below. In addition, the measurement results of Example 1-1 and Example 1-2 are presented in FIGS. 1a to 1c and FIGS. 2a to 2c, respectively.

[0199] A* B* C** (%) D** (%) A / B Example 1 0.229 0.342 27.4 29.3 0.669 Example 2 0.25 0.35 27.2 29.4 0.714 Example 3 0.26 0.34 28.3 29.5 0.765 Comparative Example 1 0.45 0.55 25.7 32.2 0.818 Comparative Example 2 0.18 0.55 22.8 33.1 0.327 Comparative Example 3 0.3 0.62 35.1 34.7 0.692 　 Average upper grain size (μm) Average size of lower grains (μm) CD Electrical conductivity (S / m) Impedance (Ω) Example 1 0.465 0.509 0.935 5.75 x 10 7 50.5 Example 2 0.461 0.512 0.925 5.72 x 10 7 50.7 Example 3 0.469 0.518 0.959 5.68 x 10 7 50.9 Comparative Example 1 0.445 0.539 0.797 4.80 x 10 7 57.5 Comparative Example 2 0.432 0.548 0.688 4.65 x 10 7 61.2 Comparative Example 3 0.491 0.534 1.012 4.55 x 10 7 60.7

[0200] * A is the ratio of TD based on TC in the wiring layer placed in the upper wiring layer, and B is the ratio of TD based on TC in the wiring layer placed in the lower wiring layer, TC is the sum of the area ratio of (220) oriented grains, the area ratio of (211) oriented grains, and the area ratio of (310) oriented grains measured by EBSD, and TD is the sum of the area ratio of (111) oriented grains and the area ratio of (200) oriented grains measured by EBSD.

[0201] ** C is the area ratio (%) of grains in which the ratio of the long axis to the short axis, measured by EBSD, is 3:1 or greater in the wiring layer placed in the upper wiring layer, and D is the area ratio (%) of grains in which the ratio of the long axis to the short axis, measured by EBSD, is 3:1 or greater in the wiring layer placed in the lower wiring layer.

[0202] FIG. 1a is a diagram showing the EBSD map of Example 1-1, FIG. 1b is a diagram showing the area ratio of grains with an axis-to-axis ratio of 3:1 or greater in Example 1-1, and FIG. 1c is a diagram showing the area ratio of each oriented grain in Example 1-1. FIG. 2a is a diagram showing the EBSD map of Example 1-2, FIG. 2b is a diagram showing the area ratio of grains with an axis-to-axis ratio of 3:1 or greater in Example 1-2, and FIG. 2c is a diagram showing the area ratio of each oriented grain in Example 1-2.

[0203] Referring to Table 1, Figures 1a to 1c, and Figures 2a to 2c, the A / B ratio in the examples ranged from 0.669 to 0.765. This indicates that (111 crystal area ratio + 200 crystal area ratio) was appropriately maintained relative to (220 crystal area ratio + 211 crystal area ratio + 310 crystal area ratio), demonstrating excellent electrical characteristics between the wiring layers. In this regard, the impedance of the examples was measured to range from 50.5Ω to 50.9Ω, showing low signal loss and high transmission efficiency. Additionally, the electrical conductivity was 5.68 x 10⁻⁶ 7 5.75 x 10 at S / m 7 It was confirmed that the electrical transmission characteristics were excellent by maintaining a high level of S / m.

[0204] The C / D ratio also ranged from 0.925 to 0.959, which is interpreted as indicating that grains with a long axis / short axis ratio of 3:1 or higher were formed in a balanced manner, contributing to the minimization of electrical interference during high-frequency transmission. The average grain size was also stably maintained at 0.461μm to 0.469μm in the wiring layer of the upper redistribution layer and 0.509μm to 0.518μm in the wiring layer of the lower redistribution layer, indicating that excellent electrical characteristics and structural stability are maintained.

[0205] On the other hand, in the comparative example, the A / B ratio ranged from 0.327 to 0.818, and the impedance increased from 57.5Ω to 61.2Ω. This is thought to be due to electrical imbalance between the wiring layers. In particular, the impedance value in Comparative Example 2 was very high at 61.2Ω, suggesting that signal reflection and loss increased and signal transmission efficiency was significantly reduced.

[0206] Furthermore, in the comparative examples, the C / D ratio ranged from 0.688 to 1.012, indicating that the wiring layer of the upper redistribution layer had a higher proportion of grains with a long-axis to short-axis ratio compared to the wiring layer of the lower redistribution layer. This can lead to interlayer imbalance, resulting in a lack of harmony in the electrical characteristics between the wiring layers. The average grain size was also unevenly formed between the upper and lower redistribution layers in the comparative examples, which is highly likely to cause structural instability along with a degradation of electrical performance between the wiring layers. The electrical conductivity in the comparative examples was also 4.55 x 10⁻⁶ 7 4.80 x 10 at S / m 7 It was found to be S / m, which was lower compared to the examples. This indicates that the low conductivity means the electron transport path was not optimized, and consequently, electrical loss occurred.

[0208] Time Domain Reflectometry (TDR)

[0209] Time Domain Reflectometry was performed.

[0210] TDR analysis followed the IPC-TM-650 2.5.5.10 method, which is more suitable for electronic device measurements, while referencing the ASTM D5272 standard. Reflection coefficients and signal delay times were measured using a Tektronix DSA8300 Digital Sampling Oscilloscope and an 80E10 TDR module, utilizing a GGB Industries Model 40A-GSG-150-P probe. Samples were prepared with dimensions of 1 cm x 1 cm, and the thickness of the copper wiring layers ranged from 8–12 μm for the top layer to 7–10 μm for the bottom layer. The signal transmission characteristics of the top and bottom wiring layers were analyzed by applying a pulse signal with an amplitude of 200 mV and a rise time of 30 ps in the 20 GHz bandwidth. Measurements were performed in a temperature-controlled environment of 23 ± 1°C, and the mean and standard deviation were calculated based on a total of 15 measurements obtained by repeating the measurements three times at five different locations on each sample. For data analysis, Tektronix IConnect® software was used to generate impedance profiles and precisely calculate reflection coefficients and signal delay times. To ensure measurement accuracy, the system was calibrated with a standard 50Ω load, and measurement uncertainty was also evaluated.

[0211] Reflection Coefficient (%) Signal Delay (ps) Example 1 2.7 76 Example 2 2.8 74 Example 3 2.9 73 Comparative Example 1 4.8 88 Comparative Example 2 5.2 89 Comparative Example 3 5 86

[0212] Referring to Table 3 above, the reflection coefficients in Examples 1, 2, and 3 showed very low values ​​in the range of 2.7% to 2.9%, while the reflection coefficients in Comparative Examples 1, 2, and 3 showed a range of 4.8% to 5.2%, indicating relatively high signal loss. The signal delay time was also short in the range of 73 ps to 76 ps for Examples 1, 2, and 3, whereas relatively long signal delays occurred in Comparative Examples 1, 2, and 3, ranging from 86 ps to 89 ps, confirming that there is a difference in transmission performance between the examples and the comparative examples. These results suggest that the examples can provide stable performance during high-speed signal transmission.

[0214] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

Claim 1 Glass core; upper redistribution layer; A packaging substrate comprising: a glass core and a lower redistribution layer; wherein the glass core is a plate-shaped glass having vias disposed therein, the upper redistribution layer is disposed on the upper side of the glass core, the lower redistribution layer is disposed on the lower side of the glass core, each of the upper redistribution layer and the lower redistribution layer includes a wiring layer and an insulating layer, the wiring layer is a patterned copper layer having grains, the insulating layer is a layer comprising an insulating polymer resin or an insulating inorganic material, an upper surface is located on the upper side of the upper redistribution layer and an electronic device is mounted on the upper surface, and a lower surface facing the upper surface is located on the lower side of the lower redistribution layer, C is the area ratio of grains in the wiring layer disposed on the upper redistribution layer such that the ratio of the long axis to the short axis is 3:1 or greater, D is the area ratio of grains in the wiring layer disposed on the lower redistribution layer such that the ratio of the long axis to the short axis is 3:1 or greater, and the value obtained by dividing C of the packaging substrate by D is 0.85 or greater and 0.99 A packaging substrate, wherein the copper layer comprises (111) direction oriented grains, (200) direction oriented grains, (220) direction oriented grains, (211) direction oriented grains, and (310) direction oriented grains, TC is the sum of the area ratio of (220) direction oriented grains, the area ratio of (211) direction oriented grains, and the area ratio of (310) direction oriented grains, TD is the sum of the area ratio of (111) direction oriented grains and the area ratio of (200) direction oriented grains, A is the ratio of TD based on TC in the wiring layer disposed on the upper redistribution layer, B is the ratio of TD based on TC in the wiring layer disposed on the lower redistribution layer, and the value obtained by dividing A by B is 0.60 or more and 0.75 or less. Claim 2 delete Claim 3 delete Claim 4 A packaging substrate according to claim 1, wherein A of the packaging substrate is 0.2 or greater. Claim 5 A packaging substrate according to claim 1, wherein the average size of the grains in the wiring layer disposed on the upper redistribution layer is 0.45 μm or more and 0.48 μm or less. Claim 6 A packaging substrate according to claim 1, wherein the average size of the grains in the wiring layer disposed on the lower redistribution layer is 0.50 μm or more and 0.53 μm or less. Claim 7 In claim 1, the packaging substrate is a packaging substrate having an impedance of 49Ω or more and 52Ω or less. Claim 8 In claim 1, the packaging substrate has an electrical conductivity of 5.0 x 10 7 Packaging substrate with S / m or greater. Claim 9 In claim 1, the packaging substrate is a packaging substrate having a reflection coefficient of 3.2% or less. Claim 10 In claim 1, the packaging substrate is a packaging substrate having a signal delay of 80 pc or less.

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