Method of setting initial erase voltage

Abstract

A method for setting an initial erase voltage includes performing a preprogramming operation on a first target memory cell, setting an erase voltage, performing an erase operation on the first target memory cell using the erase voltage, performing an erase verification operation on the first target memory cell using a plurality of verification voltages, and determining whether to set the erase voltage as an initial erase voltage based on the erase verification result.

Description

Technology Field

[0001] The present invention relates to a voltage setting method, and in particular to a method for setting an initial erase voltage. Background Technology

[0002] The erase time of flash memory is a critical factor related to test costs and product applications. In the case of NOR-type flash memory products with a tunnel oxide structure, the erase time during cycle operations is prolonged because charge traps form in the tunnel oxide.

[0003] In conventional technology, to reduce the erase time, an erase pulse is first generated during an erase operation, followed by an erase verification to determine whether the target memory cell passes the verification. If the target memory cell does not pass the erase verification, an erase pulse is continuously generated. This process is repeated, and after several erase pulses, the erase voltage is increased to accelerate the erase speed.

[0004] In the above erase operation, it is necessary to set a single initial erase voltage. Generally, the initial erase voltage for a single wafer or a batch of samples is set identically. However, due to differences between dies in the wafer process, the erase time increases with the cycle operation. Therefore, it cannot be said that the same initial erase voltage is suitable for all wafers or samples. Prior art literature

[65535] Published Patent Application No. 10-2016-0112450 (20160928) Published Patent Application No. 10-2023-0138142 (20231005) The problem to be solved

[0005] The present invention provides a method for setting an initial erase voltage to shorten the erase time by setting a different initial erase voltage to a memory die. means of solving the problem

[0006] One embodiment of the present invention provides a method for setting an initial erase voltage. The setting method comprises: performing a preprogramming operation on a first target memory cell; setting an erase voltage and performing an erase operation on the first target memory cell using the erase voltage; performing an erase verification operation on the first target memory cell using a plurality of verification voltages; and determining whether to set the erase voltage as an initial erase voltage based on the erase verification result. Effects of the invention

[0007] The present invention provides a method for setting an initial erasure voltage that can shorten the erasure time. Brief explanation of the drawing

[0008] [Fig. 1] This is a block diagram showing a memory storage device according to an embodiment of the present invention. [Fig. 2] This is a schematic diagram showing the distribution of threshold voltage of a memory cell according to one embodiment of the present invention. [Fig. 3] This is a step flowchart showing a method for setting an initial erasure voltage according to an embodiment of the present invention. [Fig. 4] This is a step flowchart showing a method for setting an initial erasure voltage according to another embodiment of the present invention. [Fig. 5] This is a block diagram showing a memory storage device according to another embodiment of the present invention. [Fig. 6] This is a step flowchart showing a method for setting an initial erasure voltage according to another embodiment of the present invention. [Fig. 7] This is a step flowchart showing a method for setting an initial erasure voltage according to another embodiment of the present invention. Specific details for implementing the invention

[0009] Referring to FIG. 1, the memory storage device (100) includes a memory array (110), a sense amplifier circuit (120), a voltage generation circuit (130), a counter circuit (140), and a control circuit (150). The memory array (110) includes a plurality of memory cells. The memory storage device (100) is, for example, a NOR-type flash memory, but the type of memory storage device (100) is not limited in the present invention.

[0010] The control circuit (150) is used to perform a pre-program operation, an erase operation, or an erase verification operation on the memory array (110). For example, the control circuit (150) can be used to set an initial erase voltage for the erase operation and to set a verification voltage for the erase verification operation. The control circuit (150) is used to perform a block or sector erase operation on the memory array (110) according to an erase command. Before performing the erase operation, the control circuit (150) first performs a pre-program operation on the selected block or sector, sets an initial erase voltage for the erase operation, and then performs the erase operation on the selected block or sector.

[0011] In one embodiment, the control circuit (150) may be a digital logic circuit, and may be a hardware circuit designed according to, for example, a Hardware Description Language (HDL) or any other digital circuit design method known to those skilled in the art, and realized by a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or an Application-specific Integrated Circuit (ASIC). Alternatively, the control circuit (150) may be a processor or controller equipped with computational functions.

[0012] In addition, the hardware structure of the memory array (110), sense amplifier circuit (120), voltage generation circuit (130), and counter circuit (140) can be sufficiently taught, suggested, and described in practice from general knowledge of the relevant technical field.

[0013] Hereinafter, with reference to FIGS. 1 to FIG. 3, it will be explained how the control circuit (150) sets the initial erase voltage of the erase operation. In FIG. 2, the horizontal axis represents the threshold voltage of the memory cell, the vertical axis represents the number of memory cells, PPV is the verification voltage used for preprogramming verification, and EV, EV1, and EV2 are the verification voltages used for erase verification. Among these, the verification voltage EV2 (second verification voltage) is greater than the verification voltage EV1 (first verification voltage), and the verification voltage EV1 is greater than the verification voltage EV.

[0014] In this embodiment, the control circuit (150) can set the initial erase voltage of each sector, for example, by using the method flow of FIG. 3. The setting of the initial erase voltage of each sector may be the same or different. Generally, in a block erase command, the initial erase voltage of all sectors is the same. The algorithm of the embodiment of the present invention finds the adjusted erase voltage and applies it simultaneously to all sectors of the block to be erased. When the erase command is a sector erase command, the algorithm of the embodiment of the present invention finds the adjusted erase voltage and applies it to this sector. In FIG. 2, the distribution curve (200) is the threshold voltage distribution of the entire memory cell of the target sector after performing a preprogramming operation on the selected sector (hereinafter referred to as the target sector).

[0015] In step S100, the control circuit (150) selects a first target memory cell from the target sector and performs a preprogramming operation. In one embodiment, the number of the first target memory cells is, for example, 32, 64, 128, or another suitable number, and the present invention does not limit the number of the first target memory cells. In step S100, the control circuit (150) may perform a preprogramming operation for the entire target sector.

[0016] In the sense amplifier circuit (120), a corresponding number of sense amplifiers (122) perform a sensing operation on the first target memory cell and complete an erase verification operation. The voltage generation circuit (130) can provide verification voltages EV, EV1, and EV2 to the sense amplifiers (122) through the same signal line L1.

[0017] In step S110, the control circuit (150) sets a first erase voltage and performs an erase operation on the first target memory cell using the set first erase voltage. In step S120, the control circuit (150) performs an erase verification operation on the first target memory cell using a verification voltage EV1. Next, in step S130, the control circuit (150) performs an erase verification operation on the first target memory cell using a verification voltage EV2. That is, in this embodiment, the control circuit (150) performs an erase verification operation on the first target memory cell in sequence using verification voltages EV1 and EV2.

[0018] In step S140, the control circuit (150) determines whether the number of first target memory cells that did not pass the verification of verification voltage EV1 but passed the verification of verification voltage EV2 is greater than the reference amount.

[0019] If the number of first target memory cells that have not passed verification of verification voltage EV1 but have passed verification of verification voltage EV2 is greater than the reference amount, it means that the first erase voltage set by the control circuit (150) in step S110 is appropriate as the initial erase voltage. Accordingly, in step S150, the control circuit (150) sets the first erase voltage as the initial erase voltage of the target sector. In this embodiment, the reference amount may be set in advance, and the reference amount may be a reference ratio.

[0020] Meanwhile, if the number of first target memory cells that passed the verification of verification voltage EV1 is greater than the reference amount (distribution curve (210) of FIG. 2), it means that the first erase voltage is too high, and the control circuit (150) returns to step S100 and performs a preprogramming operation again on the first target memory cells. In step S110, the control circuit (150) lowers the first erase voltage to the second erase voltage and performs an erase operation on the target memory cells using the second erase voltage. Next, in steps S120 and S130, the control circuit (150) performs an erase verification operation on the first target memory cells in sequence using verification voltages EV1 and EV2. In step S140, if the number of first target memory cells that do not pass the verification of verification voltage EV1 but pass the verification of verification voltage EV2 can be made larger than the reference amount, in step S150, the control circuit (150) sets the second erase voltage as the initial erase voltage of the target sector.

[0021] Alternatively, if the number of first target memory cells that do not pass verification of verification voltage EV2 is greater than a reference amount (e.g., distribution curve (220) of FIG. 2), it means that the first erase voltage is too low, and the control circuit (150) returns to step S100 and performs a preprogramming operation again on the first target memory cells. In step S110, the control circuit (150) raises the first erase voltage to the third erase voltage and performs an erase operation on the target memory cells using the third erase voltage. Next, in steps S120 and S130, the control circuit (150) performs an erase verification operation on the first target memory cells in sequence using verification voltages EV1 and EV2. In step S140, if the number of first target memory cells that do not pass the verification of verification voltage EV1 but pass the verification of verification voltage EV2 can be made larger than the reference amount, in step S150, the control circuit (150) sets the third erase voltage as the initial erase voltage of the target sector.

[0022] In the embodiment of FIG. 1, the counter circuit (140) includes a first counter (142) and a second counter (144). The first counter (142) is used to count the number of first target memory cells that have passed verification of the verification voltage EV1 and to provide the count result to the control circuit (150). The second counter (144) is used to count the number of first target memory cells that have not passed verification of the verification voltage EV2 and to provide the count result to the control circuit (150).

[0023] In the embodiment of FIG. 3, the control circuit (150) executes S140 from step S100 repeatedly until the judgment in step S140 is "YES", and then executes step S150, but the present invention is not limited thereto. In another embodiment, the control circuit (150) may execute step S150 after executing a predetermined number of erase operations (e.g., 2 times) for the first target memory cell, and the adjusted erase voltage may be set as the initial erase voltage of the target sector.

[0024] Specifically, referring to FIG. 4, in the embodiment of FIG. 4, the control circuit (150) repeats steps S240 from step S200 and performs a predetermined number of erase operations on the first target memory cell, and then performs step S250. That is, in step S260, the control circuit (150) determines whether the number of erase operations performed on the first target memory cell has exceeded a predetermined number. If the number of erase operations exceeds a predetermined number, the control circuit (150) adjusts the erase voltage in step S270 and then performs step S250, so that the adjusted erase voltage can be set as the initial erase voltage of the target sector. In this embodiment, the predetermined number is set to, for example, two times, but the present invention is not limited thereto.

[0025] Accordingly, by using the method of FIG. 3 or FIG. 4, an initial erase voltage required for the erase operation of each sector can be set. Also, by the method of FIG. 3 or FIG. 4, the same or different initial erase voltage can be set for each block.

[0026] Referring to FIGS. 1 and FIGS. 5, in the embodiment of FIG. 1, the control circuit (150) performs an erase verification operation on the first target memory cell using verification voltages EV1 and EV2 in sequence. Furthermore, the voltage generation circuit (130) provides the verification voltages EV, EV1, and EV2 to the sense amplifier (124) through the same signal line L1. However, the present invention is not limited thereto.

[0027] In the embodiment of FIG. 5, the control circuit (150) can execute an erase verification operation on a first target memory cell using a verification voltage EV1 and simultaneously execute an erase verification operation on a second target memory cell using a verification voltage EV2, thereby shortening the erase verification time. Among these, the first target memory cell and the second target memory cell are target memory cells of different groups within the same block or sector. The number of second target memory cells is the same as that of the first target memory cell. Accordingly, in this embodiment, the control circuit (150) executes an erase verification operation on the first target memory cell and the second target memory cell, respectively, using verification voltages EV1 and EV2, and sets an initial erase voltage based on the verification results of both.

[0028] The voltage generation circuit (130) provides a verification voltage EV, EV1 to a sense amplifier (122) corresponding to a first target memory cell via signal line L1. The voltage generation circuit (130) provides a verification voltage EV2 to a sense amplifier (124) corresponding to a second target memory cell via signal line L2.

[0029] Referring to FIG. 6, in this embodiment, at step S320, the control circuit (150) performs an erase verification operation on a first target memory cell using a verification voltage EV1, and simultaneously performs an erase verification operation on a second target memory cell using a verification voltage EV2. Next, at step S330, the control circuit (150) determines whether the number of first target memory cells that did not pass the verification of verification voltage EV1 and the number of second target memory cells that passed the verification of verification voltage EV2 are greater than a reference amount. Accordingly, at step S340, the control circuit (150) can set the set or adjusted erase voltage as the initial erase voltage of the target sector.

[0030] Accordingly, in the embodiment of FIG. 6, an erase verification operation is performed on the first target memory cell and the second target memory cell, respectively, using verification voltages EV1 and EV2, and an initial erase voltage is set based on the two verification results.

[0031] In the embodiment of FIG. 6, the control circuit (150) may execute S330 repeatedly from step S300 and, after executing a predetermined number of erase operations for the first target memory cell and the second target memory cell, execute step S340. That is, if the number of erase operations exceeds a predetermined number, the control circuit (150) may execute step S340 after adjusting the erase voltage and set the adjusted erase voltage as the initial erase voltage of the target sector.

[0032] Referring to FIGS. 1 and FIGS. 7, the method for setting an initial erase voltage according to the present embodiment is applicable to the memory storage device (100) of FIG. 1, but the present invention is not limited thereto. Taking the memory storage device (100) of FIG. 1 as an example, in step S400, the control circuit (150) performs a preprogramming operation on the first target memory cell. In step S410, the control circuit (150) sets an erase voltage and performs an erase operation on the first target memory cell using the erase voltage. In step S420, the control circuit (150) performs an erase verification operation on the first target memory cell using a plurality of verification voltages EV1 and EV2. In step S430, the control circuit (150) determines whether to set the erase voltage as an initial erase voltage based on the result of the erase verification.

[0033] In addition, since the method for setting the initial erasure voltage of the present embodiment can be sufficiently taught, suggested, and described from the description of the embodiments of FIGS. 1 to 6, a detailed description is omitted.

[0034] To summarize the above, in an embodiment of the present invention, an appropriate initial erase voltage for a block or sector can be determined by using a plurality of verifications to perform a plurality of erase verification operations on one or more target memory cells of the same block or sector. Accordingly, by the method of setting an initial erase voltage of an embodiment of the present invention, a different initial erase voltage can be set for a memory die, and the erase time can be shortened. In addition, before each cycle operation is initiated, the control circuit may reset the initial erase voltage for that cycle's erase operation.

[0035] Although the present invention is disclosed through embodiments as described above, it is not intended to limit the invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the invention. Accordingly, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

[0036] [Industrial Applicability]

[0037] The method for setting the initial erase voltage of the present invention can also be applied to a memory storage device. Explanation of the symbols

[0038] 100: Memory storage device 110: Memory array 120: Sense Amplifier Circuit 122, 124: Sense Amp 130: Voltage generation circuit 140: Counter circuit 142, 144: Counter 150: Control circuit EV, EV1, EV2, PPV: Verification voltage L1, L2: Signal lines S100, S110, S120, S130, S140, S150, S200, S210, S220, S230, S240, S250, S260, S270, S300, S310, S320, S330, S340, S400, S410, S420, S430: Method Step

Claims

Claim 1 A method for setting an initial erase voltage comprises: executing a preprogramming operation on a first target memory cell and adjusting an initial state for setting an erase voltage of the first target memory cell by means of the preprogramming operation; setting an erase voltage and executing an erase operation on the first target memory cell using the erase voltage; executing an erase verification operation on the first target memory cell using a plurality of verification voltages including a first verification voltage and a second verification voltage greater than the first verification voltage; and determining whether to set the erase voltage as the initial erase voltage based on the number of the first target memory cells distributed between the first verification voltage and the second verification voltage. A step of determining whether to set the erase voltage as the initial erase voltage based on the erase verification result includes setting the erase voltage as the initial erase voltage when the number of first target memory cells that have not passed the verification of the first verification voltage but have passed the verification of the second verification voltage is greater than a reference amount. A method for setting an initial erase voltage, comprising adjusting the erase voltage when the number of the first target memory cells that passed the verification is greater than or equal to a reference amount, or when the number of the first target memory cells that did not pass the verification of the second verification voltage is greater than or equal to a reference amount. Claim 2 A method for setting an initial erase voltage according to claim 1, wherein the step of executing the preprogramming operation for the first target memory cell includes executing the preprogramming operation for the block or sector where the first target memory cell is located. Claim 3 A method for setting an initial erase voltage according to claim 1, wherein the step of executing the erase verification operation for the first target memory cell using the plurality of verification voltages includes executing the erase verification operation for the first target memory cell using the first verification voltage and the second verification voltage in sequence. Claim 4 A method for setting an initial erase voltage according to claim 1, further comprising executing the erase operation on the first target memory cell using the adjusted erase voltage, and a step of determining whether to set the erase voltage as the initial erase voltage based on the erase verification result, wherein the step comprises setting the adjusted erase voltage as the initial erase voltage based on the erase verification result. Claim 5 A method for setting an initial erase voltage according to claim 1, wherein the step of determining whether to set the erase voltage as the initial erase voltage based on the erase verification result includes lowering the erase voltage when the number of the first target memory cells that passed the verification of the first verification voltage is greater than or equal to a reference amount, and setting the erase voltage after lowering as the initial erase voltage. Claim 6 A method for setting an initial erase voltage according to claim 1, wherein the step of determining whether to set the erase voltage as the initial erase voltage based on the erase verification result includes raising the erase voltage when the number of the first target memory cells that did not pass the verification of the second verification voltage is greater than or equal to a reference amount, and setting the erase voltage after raising as the initial erase voltage. Claim 7 A method for setting an initial erase voltage according to claim 1, comprising: performing a preprogramming operation on a second target memory cell; performing an erase operation on the second target memory cell using the erase voltage; and performing an erase verification operation on the second target memory cell using a plurality of verification voltages, wherein the first target memory cell and the second target memory cell are target memory cells of different groups within the same block or sector. Claim 8 A method for setting an initial erase voltage in claim 7, wherein the erase verification operation of the first target memory cell and the second target memory cell is executed simultaneously. Claim 9 A method for setting an initial erase voltage according to claim 7, wherein the plurality of verification voltages includes a first verification voltage and a second verification voltage, and the second verification voltage is greater than the first verification voltage, and a step of executing the erase verification operation for the first target memory cell using the plurality of verification voltages includes executing the erase verification operation for the first target memory cell using the first verification voltage, and a step of executing the erase verification operation for the second target memory cell using the plurality of verification voltages includes executing the erase verification operation for the second target memory cell using the second verification voltage. Claim 10 A method for setting an initial erase voltage according to claim 7, wherein the number of erase operations performed on the first target memory cell or the second target memory cell is less than or equal to a predetermined number. Claim 11 delete Claim 12 delete

Images