Conformal thermal CVD with controlled film properties and high deposition rates

Abstract

Methods and apparatus for depositing dielectric films on features on semiconductor substrates are described herein. The method comprises the step of depositing a dielectric film using controlled thermal chemical vapor deposition with periodic passivation and densification to modulate film properties.

Description

Background Technology

[0001] Semiconductor equipment manufacturing involves the deposition of materials over large areas, such as in gap-filling applications, for the manufacture of memory devices, including 3D NAND. As devices are miniaturized, structures are used to manufacture efficient and multiple memory cells to maximize the density of memory cells in memory devices. 3D NAND technology solves the challenges associated with 2D NAND technology by vertically stacking memory cells.

[0002] The description of the background art provided in this specification is intended to provide the context of the present disclosure in general. To the extent described in this background art section, the work of the inventor named in this specification, as well as aspects of the present technology that would not otherwise qualify as prior art at the time of filing, are not explicitly or implicitly acknowledged as prior art to the present disclosure.

[0003] Citation as a reference

[0004] The PCT (101) application is filed concurrently with this specification as part of this application. Each application claiming priority or benefit, as identified in the PCT application form filed concurrently with this application, is incorporated herein by reference in its entirety for all purposes.

[0005] One embodiment comprises a method for processing substrates within a chamber, the method comprising: providing a semiconductor substrate having features; and depositing a dielectric material within features on a semiconductor substrate; wherein the semiconductor substrate is exposed to a plasma-free environment comprising the deposition precursor and the reaction material, and the deposition precursor and reaction material are introduced into the chamber housing the semiconductor substrate to form the dielectric material, and the dielectric material is deposited on features of the semiconductor substrate by introducing a passivation gas into the chamber and igniting a passivation plasma in a gas atmosphere (ambient).

[0006] In various embodiments, the method also includes the step of exposing a dielectric material to a densification plasma in a chamber generated in an inert gas atmosphere. In some embodiments, the step of depositing the dielectric material further includes the step of introducing a deposition precursor and the reaction material, the step of introducing a passivation gas, and the step of exposing the dielectric material to a densification plasma in a chamber generated in an inert gas atmosphere, repeating these steps alternately in time.

[0007] In various embodiments, the step of depositing a dielectric material further includes the step of alternately repeating the steps of introducing a deposition precursor and a reaction material into a plasma-free environment and introducing them into a passivation gas in time.

[0008] In some embodiments, the feature has a feature opening of about 70 nm to about 5 µm. In some embodiments, the feature is at least about 6 µm deep.

[0009] In some embodiments, the method also includes the step of changing the chamber pressure to control the thickness profile of the dielectric material.

[0010] In some embodiments, the densification plasma is generated using high-frequency and low-frequency plasmas selected to form a concave dielectric material. In some embodiments, the densification plasma is generated in situ.

[0011] In some embodiments, the passivation plasma preferentially etches the dielectric material at or near the feature opening. In some embodiments, the passivation gas is a halogen-containing gas. In some embodiments, the passivation gas is nitrogen trifluoride. In some embodiments, the passivation plasma is generated in situ.

[0012] In some embodiments, the introduction of the deposition precursor and the reaction material, and the introduction of the passivation gas, are performed without destroying the vacuum.

[0013] In some embodiments, introducing a deposition precursor and a reaction material and exposing the dielectric material to a densifying plasma is performed without destroying the vacuum.

[0014] In some embodiments, the dielectric material is deposited at a temperature of about 400°C to about 800°C.

[0015] In some embodiments, the dielectric material comprises silicon oxide. In some embodiments, the deposition precursor is aminosilane. In some embodiments, the reactant comprises an oxygen-containing gas.

[0016] In some embodiments, the feature is a re-entrant feature. In some embodiments, the feature is formed in a multilayer stack. In some embodiments, the feature has an aspect ratio of about 0.8:1 to about 10:1.

[0017] Another aspect comprises methods for processing substrates within a chamber, said method comprising: providing a semiconductor substrate having features in the chamber; and introducing a deposition precursor and a reaction material into a chamber housing the semiconductor substrate to expose the semiconductor substrate to a plasma-free environment containing the deposition precursor and the reaction material to form a dielectric material, and depositing a dielectric material on features on the semiconductor substrate by exposing the dielectric material to a densifying plasma within the chamber generated in a passivation gas atmosphere.

[0018] In some embodiments, the method also includes the step of introducing a passivation gas into a chamber and igniting the passivation gas.

[0019] In various embodiments, the step of depositing a dielectric material also includes the step of introducing a deposition precursor and a reactive material in a plasma-free environment and the step of exposing the dielectric material to a densifying plasma generated in an inert gas atmosphere, which are repeated in a time-alternating manner.

[0020] In some embodiments, the feature has a feature opening of about 70 nm to about 5 µm. In some embodiments, the feature is at least about 6 µm deep.

[0021] In some embodiments, the method also includes the step of changing the chamber pressure to control the thickness profile of the dielectric material.

[0022] In some embodiments, the densification plasma is generated using high-frequency and low-frequency plasmas selected to form a concave dielectric material. In some embodiments, the densification plasma is generated in-situ.

[0023] In some embodiments, the passivation plasma preferentially etches the dielectric material at or near the feature opening. In some embodiments, the passivation gas is a halogen-containing gas. In some embodiments, the passivation gas is nitrogen trifluoride. In some embodiments, the passivation plasma is generated in situ.

[0024] In some embodiments, the introduction of the deposition precursor and the reaction material and the introduction of the passivation gas are performed without destroying the vacuum.

[0025] In some embodiments, introducing a deposition precursor and a reaction material and exposing the dielectric material to a densifying plasma is performed without destroying the vacuum.

[0026] In some embodiments, the dielectric material is deposited at a temperature of about 400°C to about 800°C.

[0027] In some embodiments, the dielectric material comprises silicon oxide. In some embodiments, the deposition precursor is aminosilane. In some embodiments, the reactant comprises an oxygen-containing gas.

[0028] In some embodiments, the feature is a re-entrant feature. In some embodiments, the feature is formed in a multilayer stack. In some embodiments, the feature has an aspect ratio of about 0.8:1 to about 10:1.

[0029] Another embodiment comprises an apparatus for processing a semiconductor substrate comprising a semiconductor material, the apparatus comprising one or more process chambers, wherein at least one process chamber comprises a showerhead, a heated pedestal for heating the semiconductor substrate to a temperature of at least about 650°C; a plasma generator capable of generating plasma within at least one process chamber; one or more gas sources; one or more gas inlets for delivering gas from the one or more gas sources to the one or more process chambers through the showerhead; and a controller having at least one processor and a memory, wherein the at least one processor and the memory are connected so as to be able to communicate with each other, and the at least one processor is operably connected to at least flow control hardware, and the memory is at least an operation for setting the temperature of the heated pedestal to less than about 650°C; and the following operations in time-separated pulses: an operation for inducing the introduction of a deposition precursor and a reaction material into the one or more process chambers through the showerhead; and stores computer-executable instructions for controlling the flow control hardware by an operation that causes the introduction of an operation that causes plasma generation when an inert gas is introduced into the one or more process chambers after causing the interruption of the introduction of the deposition precursor and the reaction material.

[0030] In various embodiments, controller instructions for inducing temporally separated pulses include instructions for inducing the generation of a second plasma when a passivation gas is introduced into one or more process chambers.

[0031] In various embodiments, time-separated pulses are performed without destroying the vacuum.

[0032] In various embodiments, time-separated pulses are performed in the same process chamber.

[0033] In various embodiments, at least one of inducing the introduction of the deposition precursor and the reaction material and inducing the generation of plasma is performed by high-speed switching.

[0034] These features and other features will be described later with reference to the associated drawings. Brief explanation of the drawing

[0035] Figure 1 is a process flowchart illustrating the operations of the method. Figures 2, 3, and 4a are schematic examples of substrates of a patterning scheme. Figure 4b is a semiconductor of the substrate shown in Figure 4a. Figures 5a, 6a, 7a, 8, and 9 are schematic examples of substrates of a patterning scheme. FIGS. 5b, FIGS. 6b, and FIGS. 7b are side views of schematic examples of the substrates shown in FIGS. 5a, FIGS. 6a, and FIGS. 7a, respectively. FIGS. 10a, FIGS. 10b, FIGS. 10c, FIGS. 10d, FIGS. 10e, FIGS. 10f, FIGS. 10ga, FIGS. 10ha, and FIGS. 10ia are cross-sectional views of substrates having various feature opening types and sidewall features. FIG. 10 gb, FIG. 10 gca, FIG. 10 gcb, FIG. 10 gd, FIG. 10 gge, FIG. 10 hb, FIG. 10 hcb, FIG. 10 hdd, FIG. 10 he, FIG. 10 ib, FIG. 10 ica, FIG. 10 icb, FIG. 10 id, and FIG. 10 ie are cross-sectional views of substrates filled using specific disclosed embodiments. FIG. 11 is a process flowchart illustrating operations for a method performed according to specific disclosed embodiments. FIG. 12 is a timing sequence diagram showing examples of cycles in a method according to specific disclosed embodiments. FIG. 13 is a schematic diagram of an exemplary process chamber for carrying out the disclosed embodiments. FIG. 14 is a schematic diagram of an exemplary process tool for carrying out the disclosed embodiments. FIGS. 15 to 17 are charts of experiments performed using a process according to a specific disclosed embodiment. Specific details for implementing the invention

[0036] In the following description, numerous specific details are provided to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced with or without some or all of these specific details. In other examples, well-known process operations have not been described in detail to avoid unnecessarily obscuring the disclosed embodiments. While the disclosed embodiments will be described together with specific examples, it should be understood that this is not intended to limit the disclosed embodiments.

[0037] The semiconductor manufacturing process involves the deposition of a dielectric material. The dielectric material may include a silicon oxide material in various embodiments. The dielectric material may be deposited on various topologies on a partially manufactured semiconductor device, such as features, gaps, and other regions. As used herein, the term “feature” refers to negative features having feature openings. Exemplary features include large areas, gaps, tenches, and other holes in the partially manufactured semiconductor device. The dielectric material may be deposited to form pillars, fill high aspect ratio features, cover large areas of the substrate, or fill other regions of the partially manufactured semiconductor device.

[0038] High aspect ratio features may include features with an aspect ratio of at least 3:1, at least 1:5, at least 1:7, at least 1:10, at least 1:20, at least 1:50, or at least 1:200. Features deposited over a large area may be referred to as “large area gap fill (LAG)” applications. The large area may be defined by wide feature openings and a low aspect ratio, such as having aspect ratios of about 0.8:1 and about 10:1. Some large features may have feature openings of about 70 nm to about 5 µm, or about 70 nm to about 5 µm, or about 2 µm, or at least about 2 µm. In some embodiments, the large area may have a depth of at least 6 µm or at least about 10 µm.

[0039] Some LAG applications involve deposition on stepped structures, such as structures used to form 3D-NAND structures that may exist on partially manufactured semiconductor devices. Some embodiments described herein may be applied to 3D-NAND structures having at least about 96 pairs or at least about 128 pairs. An exemplary technique for forming 3D-NAND structures is described below with respect to FIGS. 1 through 9.

[0040] FIG. 1 is a process flowchart of operations performed according to a method for forming a 3D NAND structure. In operation (182), a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. An exemplary substrate (100) is provided as a schematic example in FIG. 2. Referring again to FIG. 1, in operation (184), a film stack of oxide and nitride films is deposited alternately on the substrate. This can be referred to as an "ONON" stack (O is oxide, N is nitride). Although oxide and nitride are illustrated, it will be understood that other combinations of films may be used for specific embodiments. In some embodiments, the deposited oxide layer is a silicon oxide layer. In some embodiments, the deposited nitride layer is a silicon nitride layer. Each of the oxide layer and the nitride layer may be deposited with approximately the same thickness, such as about 10 nm to about 100 nm, or in some embodiments, about 350 Å. The oxide layers may also be deposited at a deposition temperature of about room temperature to about 800 °C. The oxide layer and nitride layer for forming an alternating oxide film and nitride film stack may be deposited using any suitable technique such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD. The film stack may comprise at least about 48 pairs, or at least about 512 pairs, or at least about 600 pairs of alternating oxide and nitride layers, each of which constitutes one pair.

[0041] FIG. 3 is an exemplary schematic example of a substrate (100) having alternating oxide films (101) and nitride films (102) deposited on the substrate (100). The structure shown in FIG. 3 shows the oxide (101) deposited first, followed by the nitride (102), oxide (101), nitride (102), etc., but the nitride (102) may be deposited first, followed by the oxide (101), nitride (102), oxide (101), etc. After depositing the ONON stack, a channel (not shown in FIG. 3) can be etched into the ONON stack. Referring again to FIG. 1, in operation (186), a stepped pattern is formed on the substrate. The “stepped pattern” referred to herein includes two or more steps, each including an oxide layer and a nitride layer. It will be understood that the top layer of each set of oxide layers and nitride layers may be an oxide or nitride for forming steps of a stepped pattern. The stepped pattern may be formed using various patterning techniques. For example, one technique may include the step of depositing a sacrificial layer on a substrate to etch each set of oxide layers and nitride layers to form steps, and covering areas of the substrate.

[0042] FIG. 4a provides an example of a substrate (100) comprising a stepped pattern of oxide layers (111) and nitride layers (112) and a hard mask (110) on the top nitride layer (112). FIG. 4a illustrates four steps of the stepped pattern, but the stepped pattern may include multiple decks, each having multiple steps. The number of steps in each deck and in the entire stepped pattern varies depending on the application. In some embodiments, the stepped pattern has about 24 to about 256 steps. In some embodiments, the stepped pattern has more than 256 steps. The number of steps of the steps affects the depth of the ONON stack, and the greater the number of steps, the deeper the depth of the ONON stack. Each step comprises a nitride layer (112) and an oxide layer (111), and the distance d shown in FIG. 4a may be about 150 nm to about 1000 nm, e.g. 500 nm, in some embodiments. This region of each step extending from the edge of the step above may be referred to as a "pad" with a surface distance d.

[0043] For the purposes of discussion, the following discussion and subsequent schematic examples of substrates will include a semiconductor (199) as shown in FIG. 4b.

[0044] In operation (188) of FIG. 1, an oxide is deposited on a substrate. This oxide may be deposited over a large area, so that it is effectively deposited within a large “feature.” In various embodiments, the oxide may have the same composition as the oxide deposited on a layer of the ONON stack. In various embodiments, the oxide deposited on the substrate is deposited at a deposition temperature different from the deposition temperature used to deposit the oxide layer in the ONON stack. The oxide deposition temperature for large features may be 400°C to 800°C, or 500°C to 650°C, or at least 550°C, or 600°C to 650°C. The vertical slits may subsequently be etched into the ONON stack, and in some embodiments, the steps are filled after the oxide is deposited.

[0045] FIG. 5a illustrates an exemplary substrate (100) comprising an ONON step, a hard mask (110), and an oxide (122) deposited on a substrate. FIG. 5b illustrates a side view of the substrate (100) after a vertical slit (130) has been etched.

[0046] In operation (190), the nitride is selectively etched against the oxide on the substrate. FIG. 6a illustrates an exemplary schematic example of a substrate (100) having horizontal gaps (132) formed by etching the nitride. FIG. 6b illustrates a side view of a cross-section of the substrate in which gaps (132) are formed by selectively etching the nitride.

[0047] In operation (192), tungsten is deposited in the gaps of the substrate to form tungsten word lines. Although tungsten is illustrated in this example, it will be understood that other metals may be used. Tungsten can be deposited by any suitable technique such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or a tungsten nucleation layer is deposited before depositing bulk tungsten. FIG. 7a shows an example of a substrate (100) containing deposited tungsten word lines (140). FIG. 7b shows a schematic example of a cross-sectional view of the substrate seen in a side view having tungsten (140) deposited on an edge where a conventional nitride was present.

[0048] Referring again to FIG. 1, in operation (194), the oxide is vertically etched to form vias. The oxide may also be etched by dry etching by exposure to one or more of the following gases: O2, Ar, hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), SF6, trifluoromethane (CHF3), and CF4. FIG. 8 illustrates an exemplary substrate (100) comprising a stepped pattern ONON stack in which vias (137) are etched into the oxide (122).

[0049] In FIG. 1, in operation (196), tungsten is deposited within vias and interconnected with tungsten wordlines. An example illustrating tungsten (142) deposited in vias is provided in FIG. 9. The vias have variable depths and may have a depth of at least about 1 μm or from about 1 μm to about 50 μm. The depth varies and expands according to the number of steps. Shallow vias may be defined as having a depth of less than 3.0 μm, such as between about 1.5 μm and 3.0 μm. Deep vias may have a depth of more than 3.0 μm. The critical dimension of the vias formed in the oxide may be from about 50 nm to about 500 nm. The vias may be etched using a dry etching process that may involve a masking operation to pattern the oxide. As noted above, during the operation (188) in which oxide is deposited on the substrate, this process can be considered a LAG application.

[0050] Current gap-filling depositions for large areas may include sub-atmosphere chemical vapor deposition processes, PECVD tetraethylorthosilicate (TEOS) deposition processes, or atomic layer deposition (ALD) processes. However, SACVD tends to crack and produces tensile films that cannot fill reentrant features. It may be difficult to use SACVD to fill features with aspect ratios greater than about 6:1. Low-density films tend to shrink upon heat treatment and may possess greater tensile stress. Generally, tensile stress is used for crack propagation, and shrinkage is believed to provide the driving force for cracking. PECVD TEOS can fill features with aspect ratios up to about 0.8:1. Although PECVD TEOS does not crack when deposited with sufficient compressive stress, its applications are limited. Some processes involve the fabrication of 3D-NAND structures with features having aspect ratios of approximately 5:1 or greater, but SACVD and PECVD TEOS may not necessarily be suitable for deposition on such large features. Additionally, while ALD can be used to deposit highly conformal films with excellent step coverage, it makes the deposition process more expensive because it can take a long time to deposit on very large features. Generally, in the fabrication of semiconductor devices, there is a challenge of depositing materials not only on gaps but also on large-area gaps. High-density plasma chemical vapor deposition (HDP CVD) can be used, but utilizing this process for low aspect ratio gaps can be costly due to the bottom-up filling characteristics of the deposition process, resulting in overburden deposition as high as the depth of the gap, which can be very large.This overburden will be polished, which increases costs. This increase in costs can be a significant challenge to overcome, especially when the feature size is large. Flowable techniques can be used, but they cannot necessarily be used for wider features because they involve adding multiple steps to the process scheme and tend to have high shrinkage and integration issues. Atomic layer etching can be used for high aspect ratio filling, but the process can be more expensive because it fills features with larger critical dimensions.

[0051] A method for depositing a dielectric material by thermal CVD combined with densification and passivation operations is provided herein. Specific disclosed embodiments include performing thermal CVD having a densification operation, thermal CVD having a passivation operation, or thermal CVD having both a post-deposition operation and a passivation operation. The passivation and / or densification operations may be performed periodically. Specific disclosed embodiments include cycling between thermal CVD, densification, and passivation using plasma. Specific disclosed embodiments may be used to fill an entire structure, to partially fill a structure, to deposit a material after liner deposition, or to any other part of a semiconductor substrate processing scheme. Periodic passivation combined with thermal CVD can also be described as "dep-etch-dep," where passivation constitutes "etch" and thermal CVD constitutes "dep," but passivation does not necessarily involve etching. In some embodiments, passivation reduces the nucleation rate at the surface or reduces the deposition rate of the material without etching the surface.

[0052] In some embodiments, the dielectric material deposited using specific disclosed embodiments has an improved wet etching rate. Some films deposited using specific disclosed embodiments may be conformal and / or have high step coverage. The conformality of the film may be measured by step coverage. As used herein, "step coverage" is calculated by dividing the average thickness of the film deposited on the sidewall by the average thickness of the film deposited on top of the feature and multiplying by 100 to obtain a percentage. The disclosed embodiments may deposit films having at least about 50%, or at least about 95%, or about 100%, or 100% step coverage. In some embodiments, the feature is completely filled using specific disclosed embodiments alone or in combination with thermal CVD without passivation and / or densification.

[0053] Specific disclosed embodiments may be used to deposit dielectric materials over large areas, re-entries, feature widths, and the like. In various embodiments, the dielectric material is silicon oxide. While silicon oxide is described herein as an example, it will be understood that many other materials may be deposited using specific disclosed embodiments, which have the advantage of controlling deposition and depositing materials within features of various shapes, re-entries, widths, and depths. Other materials include, but are not limited to, metal oxides, semiconductor oxides, nitrides, carbides, and doped variations thereof, including doped oxides.

[0054] Specific disclosed embodiments can be applied to depositing materials on a wide variety of features. FIGS. 10a through 10e, FIGS. 10ga, FIGS. 10ha, and FIGS. 10ia show examples of feature shapes and re-entrant features. FIGS. 10f, FIGS. 10gb through 10gd, FIGS. 10hb through 10hd, and FIGS. 10ib through 10id show examples of dielectric materials partially deposited on various feature shapes. FIGS. 10ge, FIGS. 10he, and FIGS. 10ie show examples of dielectric materials deposited on various feature shapes.

[0055] FIG. 10a illustrates an exemplary feature (1002a) having a multilayer stack comprising a first composition (1004a) and a second composition (1014a) arranged in alternating horizontal layers, wherein the feature (1002a) is defined by etching holes in the multilayer stack and lining the holes with a liner (1006a). The feature (1002a) has a vertical sidewall substantially perpendicular to the top field area of ​​the substrate of the feature portion (1002a) such that at or near the feature opening, the feature opening is nearly equal to the width of the feature (1002a) at the bottom of the feature (1002a) with little or no stubs on the sidewalls of the feature (1002a). Note that while the liner (1006a) is illustrated in the various examples described herein, in some embodiments the liner is not present. Although the first composition (1004a) and the second composition (1014a) are illustrated, it will be understood that variations in the layers of the composition and more or fewer compositions may vary. Additional layers and materials may also be present on the substrate. Where the liner (1006a) is present, the liner (1006a) may be a nitride material, such as silicon nitride, but is not limited thereto, and in some embodiments, the liner (1006a) may be a polysilicon material.

[0056] FIG. 10b shows an exemplary feature (1002b) defined by etching a hole in the material (1004b) and lining it with a liner (1006b). The feature (100b) has straight vertical sidewalls with few or no stubs on the sidewalls. Note that while the liner (1006b) is illustrated in various examples described herein, in some embodiments the liner is absent. Additional layers and materials may also be present on the substrate. Where the liner (1006b) is present, the liner (1006b) may be a nitride material, such as silicon nitride, but is not limited thereto, and in some embodiments, the liner (1006b) may be a polysilicon material.

[0057] FIG. 10c illustrates a defined exemplary feature (1002c) by etching a hole in a material (1004c) and lining it with a liner (1006c) so that the feature (1002c) has a positive inclined sidewall such that the width of the feature opening (1020c) located at the top of the feature (1002c) is greater than the width between the sidewalls of the bottom (1012c). Note that while the liner (1006c) is illustrated in various examples described herein, in some embodiments the liner is absent. Additional layers and materials may also be present on the substrate. Where the liner (1006c) is present, the liner (1006c) may be a nitride material such as silicon nitride, and in some embodiments, the liner (1006c) may be a polysilicon material.

[0058] FIG. 10d is an example of a defined feature (1002d) in which a hole is etched in the material (1004d) and lined with a liner (1006d) so that the feature (1002d) has negatively inclined sidewalls, such that the feature opening (1020d) at the top of the feature (1002d) is narrower than the width between the sidewalls of the bottom (1012d). In some cases, the horizontal thickness of the liner (1006d) may be at least as thick as the maximum sidewall thickness. Note that while the liner (1006d) is illustrated in various examples described herein, in some embodiments the liner is absent. Additional layers and materials may also be present on the substrate. If a liner (1006d) is present, the liner (1006d) may be a nitride material, but is not limited thereto, and in some embodiments, the liner (1006d) may be a polysilicon material.

[0059] FIG. 10e illustrates an exemplary feature (1002e) defined by etching a hole in a material (1004e) and lining it with a liner (1006e) so that the feature (1002e) has sidewall stubs (1016e). In some embodiments, the feature may have sidewall stubs due to the type of etching performed to form the feature or one or more materials on which the feature is formed. The gap fill of a feature of the shape shown in FIG. 10a through FIG. 10e depends on the type and profile of the feature.

[0060] FIG. 10f illustrates an exemplary substrate having two features defined by etching holes in a multilayer stack having alternating layers of a first composition (1004f) and a second composition (1014f) and lining them with a conformal liner (1006f). In some embodiments, the multilayer stack may have more layers than shown in FIG. 10f. In some embodiments, the multilayer stack may have an upper deck and a lower deck. In some embodiments, the multilayer stack may have a dual deck. In some embodiments, the multilayer stack may have multiple decks. A deck may refer to a set of two or more layers of the multilayer stack material. This example illustrates a partially deposited dielectric material (1099f). Sometimes, the deposition of the dielectric material (1099f) results in non-uniform deposition on the sidewalls of the feature, which may cause the formation of gaps or seams in the feature. Specific disclosed embodiments can address these concerns and adequately fill these features.

[0061] FIGS. 10ga to 10ie illustrate examples of substrates having features that can be deposited with a gapfill material using specific disclosed embodiments. FIG. 10ga illustrates a feature (1002g) defined by etching a hole in the material (1004g), thereby causing the feature (1002g) to have divots (1016g) on ​​the sidewalls of the feature (1002g). This is an example of a feature that may have critical dimension bowing. By utilizing specific disclosed thermal CVD operation and selectable densification, the feature can be filled and can produce a structure that causes a small gap with a dielectric material (1008g-a) deposited on the feature, as illustrated in the example of FIG. 10gb. After stopping the thermal CVD and performing the passivation operation, more dielectric material can be deposited by thermal CVD, and the formation of gaps can be reduced by optionally repeating the passivation and deposition cycles. Partial filling following the stopping of the thermal CVD may result in a partially filled substrate as shown in FIG. 10gca, whereby the feature (1002g) is partially filled with dielectric material (1018g-a). With the dielectric material (1028g-a) deposited thereon, cycles of deposition and passivation may be performed, as shown in the example of the partially filled substrate in FIG. 10gd. After several cycles of deposition and passivation, or after deposition without passivation when a certain amount of material is sufficiently deposited on the feature, the feature is filled gap-free and, in some embodiments, is filled seam-free with a dielectric material (1038g-a) deposited inside, as shown in FIG. 10ge.Note that in some embodiments, instead of first partially depositing by thermal CVD before cycling between passivation and deposition, performing passivation and deposition cycles on the substrate from the time the feature begins to be filled may produce a partially filled substrate in which a dielectric material (1018g-b) is deposited on the feature, as shown in FIG. 10gcb.

[0062] FIG. 10ha illustrates a feature (1002h) defined by etching holes in a material (1004h), thereby including a divot (1016h) on the sidewall of the feature (1002h). This is an example of a feature having a top reentrancy. By utilizing a specific disclosed thermal CVD operation and selectable densification, the feature may be filled and may produce a structure such as the example in FIG. 10hb, and a dielectric material (1008h-a) may be deposited on the feature, resulting in elongated gaps. After stopping the thermal CVD and performing a passivation operation, more dielectric material may be deposited by thermal CVD, and the formation of gaps may be reduced by selectively repeating the passivation and deposition cycles. Partial filling resulting from the interruption of thermal CVD may produce a partially filled substrate as shown in FIG. 10hca, whereby the feature (1002h) is partially filled with a dielectric material (1018h-a). A cycle of deposition and passivation may be performed, resulting in a partially filled substrate as shown in FIG. 10hd, having a dielectric material (1028h-a) deposited on top. After several cycles of deposition and passivation, or after deposition without passivation when a certain amount of material is sufficiently deposited on the feature, the feature is filled gap-free, and in some embodiments, seam-free, as shown in FIG. 10he, with a dielectric material (1038H-a) deposited inside. Note that in some embodiments, instead of first partially depositing by thermal CVD before cycling between passivation and deposition, performing passivation and deposition cycles on the substrate from the time the feature begins to be filled may result in a partially filled substrate as shown in FIG. 10hcb, where the dielectric material (1018h-b) is deposited on the feature.

[0063] FIG. 10ia shows features (1002i) defined by etching holes in material (1004i), said features (1002i) including widened bottom portions (1016i) in the features (1002i). This is an example of a feature having deep reentrancy. By utilizing a specific initiated thermal CVD operation and selective densification, said features can be filled and formed into a structure such as the example in FIG. 10ib, and dielectric material (1008i-a) is deposited on said features, resulting in the formation of a long gap. After stopping the thermal CVD and performing a passivation operation, more dielectric material is subsequently deposited by thermal CVD, and the formation of the gap can be reduced by selectively repeating passivation and deposition periodically in a cycle. Partial filling resulting from the interruption of thermal CVD can cause a partially filled substrate as illustrated in FIG. 10ica, whereby the feature (1002i) is partially filled with dielectric material (1018i-a). A cycle of deposition and passivation may be performed, resulting in an example of a partially filled substrate as illustrated in FIG. 10id, having dielectric material (1028i-a) deposited on top. After several cycles of deposition and passivation, or after deposition without passivation when a certain amount of material is sufficiently deposited on the feature, the feature is filled gap-free, and in some embodiments, seam-free, as shown in FIG. 1038ie, having dielectric material (1038i-a) deposited inside. Note that in some embodiments, instead of first partially depositing by thermal CVD before the cycle between passivation and deposition, performing the passivation and deposition cycles on the substrate from the time the feature begins to be filled may produce a substrate partially filled by the deposition of a dielectric material (1018i-b) on the feature as shown in FIG. 10icb.

[0064] FIG. 11 provides a process flow diagram illustrating operations that may be performed according to specific disclosed embodiments. The operations of FIG. 11 may be performed in any order, and some operations may be omitted. In some embodiments, the operations may be performed in cycles. Non-limiting examples of cycles include (1) operation (1106), followed by operation (1108), followed by operation (1112), (2) operation (1108), then operation (1106), then operation (1112), and (3) operation (1108), then operation (1112), then operation (1106). Additionally, operation (1108) may be performed for a longer period after passivation and / or densification without periodic passivation or densification.

[0065] Process conditions may affect the deposition rate of the dielectric material. For example, chamber pressure may be modulated to affect the deposition rate of the dielectric material deposited in a large gap. For example, as chamber pressure increases, the deposition rate of the dielectric material increases. Rapid deposition may include increasing the chamber pressure so that the chamber pressure becomes at least 10 Torr, or at least 15 Torr, or at least 20 Torr. The chamber pressure for operations (1102 to 1118) may be at least about 10 Torr, or at least about 15 Torr, or at least about 20 Torr. In some embodiments, the chamber pressure is about 0.1 Torr to about 30 Torr. The chamber pressure may change between operations and may be different or the same in any operation of FIG. 11, as in operation (1010). In some embodiments, the chamber pressure is maintained constant throughout operations (1102 to 1118). In some embodiments, the chamber pressure is the same during operation (1105) and operation (1106).

[0066] In operation (1102), the substrate is provided to the process chamber. The substrate may have a feature. The feature may be a large gap having an aspect ratio of at least about 5:1 and a depth of at least about 10 μm. The feature may have a feature opening of about 5000 nm, about 2500 nm, about 70 nm to about 5 μm, or about 70 nm to about 500 μm, or about 5 nm to about 500 nm, or about 25 nm to about 300 nm, or about 2 μm, or at least about 2 μm.

[0067] In some embodiments, the feature may have an aspect ratio of at least about 2:1, at least about 3:1, at least about 4:1, at least about 6:1, or at least about 10:1. Via, trench, or other recessed features may be referred to as unfilled features or features.

[0068] In some embodiments, the substrate includes a partially fabricated structure, such as a partially fabricated 3D-NAND structure having a stepped topography. In some embodiments, the substrate includes a single deep multilayer stack having one or more internally etched features. In some embodiments, the substrate includes a top deck stack having internally etched features. In some embodiments, the substrate includes a dual deck stack having internally etched features. In some embodiments, the substrate includes a bottom deck stack having internally etched features. In some embodiments, the substrate may have a structure as illustrated in FIG. 4a, FIG. 4b, FIG. 10a, FIG. 10b, FIG. 10c, FIG. 10d, FIG. 10e, FIG. 10f, FIG. 10ga, FIG. 10ha, and FIG. 10ia.

[0069] The substrate may be provided to a process chamber equipped to generate plasma. The substrate may be provided to a process chamber without a plasma generator. The process chamber may include a heated pedestal for holding a semiconductor substrate such that, during a process within the chamber, the process environment is between the substrate on the pedestal and the showerhead, and may include a showerhead for delivering one or more gases to the process environment within the process chamber. Further examples of features of the process chamber are described below with reference to FIGS. 13 and 14.

[0070] In a selectable operation (1104), an inert gas may be introduced to stabilize the temperature of the substrate prior to deposition. In various embodiments, the inert gas may be any one of helium, argon, nitrogen, oxygen, nitrous oxide, hydrogen, and combinations thereof. The inert gas may flow continuously during all, any, most, or at least one of operations (1106), (1108), (1110), (1112), and (1114). In some embodiments, the inert gas flows continuously throughout all operations of (1106), (1108), (1110), (1112), and (1114). In some embodiments including dep-etch-dep, the inert gas also flows during the etching operation. In some embodiments, the inert gas may also be used as a carrier gas to deliver gas to the process chamber. In some embodiments, the inert gas may also be used as a purge gas to remove excess byproducts or gases between specific operations. In some embodiments, the inert gas may comprise one or more gases used during operations (1106), (1108), (1110), (1112) and / or (1114). In some embodiments, one or more gases used for the inert gas may be used for operations (1106), (1112), (1114) and / or (1116). In some embodiments, the inert gas is the same as one or more gases used in operations (1106), (1108), (1110), (1112) and / or (1114). In some embodiments, the inert gas is different from one or more gases used in operations (1106), (1108), (1110), (1112) and / or (1114).

[0071] In various embodiments, an inert gas is delivered during operation (1104), and the pedestal temperature is set to a target temperature to heat the substrate. The inert gas may be selected to facilitate heating of the substrate. For example, the pedestal may be set to a temperature that heats the substrate to at least about 550°C or at least about 650°C. The substrate temperature affects the deposition rate of the dielectric material. The deposition rate may vary depending on the relative gas flow. In one non-limiting example, at a temperature of about 550°C, little or no deposition occurs, whereas at a deposition temperature of about 650°C, at least 2 / s or more, or 10 / s or more, or 20 A deposition rate of more than / s can be achieved.

[0072] The deposition temperature can also be selected based on the specific application and the selected specific gas, as well as the presence of other materials on the substrate, so as not to degrade or damage the material on the substrate. Depending on some logic applications, the substrate may withstand temperatures up to approximately 650°C. For some memory applications, the substrate may withstand temperatures of approximately 650°C.

[0073] In operation (1106), a passivation gas and / or plasma is introduced into the process chamber. In some embodiments, the liner may be deposited in-situ before the passivation gas is ignited. In various embodiments, a passivation gas is used. In various embodiments, the passivation gas is ignited using plasma and is introduced into the chamber from a remote plasma chamber or generated within the chamber. The composition of the passivation gas depends on the material to be deposited. In some embodiments, for the deposition of dielectric materials, the passivation gas is a halogen-containing gas. In some embodiments, the passivation gas is a fluorine-containing gas. Non-limiting examples of gases that may be used to suppress deposition include nitrogen trifluoride (NF3), nitrogen (N2), etc. Plasma etching and / or passivation plasma operations may include flowing NF3 and igniting the plasma. As used herein, “directional” or “preferential” may be defined as etching more material at the top or near the feature than at the rest of the feature, such as inside or interior of the feature. Operation (1106) may be used to preferentially passivate feature openings. Operation (1106) may be used to preferentially etch material at or near feature openings. In some embodiments, preferential etching may be performed by etching the material deposited at or near the feature openings and then depositing additional material, which results in a higher nucleation rate at the interior of the feature than at the feature openings.In some embodiments, preferential passivation may be performed by passivating the surface using plasma gas or plasma to reduce the deposition and / or nucleation rate of material to be deposited at or near the feature openings, and then depositing additional material, which results in a higher nucleation rate inside the feature than at the feature openings.

[0074] In operation (1106), both the gas flow and the duration of the passivation exposure can be adjusted to increase the tunability of the deposited film. A larger gas flow is more likely to cause the passivation gas to exhibit etching properties, which can open feature openings or reduce gaps in partially filled features to enable bottom-up deposition in some embodiments. The flow rate may also be adjusted to deposit material to achieve filling of various features. For example, the deposition of material on the bottom, top, or both of features of a multilayer stack or dual-deck substrate can be adjusted by varying the flow rate of the passivation gas during passivation. In some embodiments, for a 4-station chamber, the passivation gas may flow at a flow rate of about 6000 sccm or less, or about 5 sccm to about 6 slm, or about 200 sccm to about 5000 sccm, or about 400 sccm to about 1000 sccm. In some embodiments, the passivation gas is diluted. For example, about 10 sccm to about 30 sccm of passivation gas may be diluted from a total gas flow of about 120 slm to about 160 slm. The flow percentage of the passivation gas in the total flow of all gases may be about 0.001% to about 0.003%.

[0075] During operation (1106), one or more other added gases may flow. The added gases include inert gases such as hydrogen, nitrogen, argon, helium, oxygen, and combinations thereof. In some embodiments, nitrogen may flow at a flow rate for the 4-station chamber of about 1000 sccm to about 40 slm, or about 25 slm to about 45 slm. In some embodiments, hydrogen may flow at a flow rate for the 4-station chamber of about 0 slm to about 5 slm. In some embodiments, argon may flow at a flow rate for the 4-station chamber of about 25 slm to about 45 slm. In some embodiments, oxygen may flow at a flow rate for the 4-station chamber of about 0 slm to about 5 slm. In some embodiments, helium may flow at a flow rate for a 4-station chamber of about 0 slm to about 20 slm.

[0076] The pedestal temperature during the above operation (1106) may be about 400°C to about 800°C. The pressure may be between about 0 Torr and about 100 Torr.

[0077] In various embodiments, the plasma is ignited during operation (1106). The plasma is generated by igniting a passivation gas. The plasma can be generated remotely or in-situ. In some embodiments, a combination of low frequency (LF) plasma and high frequency (HF) plasma is used to generate a plasma capable of controlling the properties of the deposited film by affecting the passivation level of the substrate surface during operation (1106). The plasma can be generated with radio frequency plasma power of about 0 W to about 6000 W for the high frequency plasma and about 0 W to about 5000 W for the low frequency plasma. The plasma power can be about 250 W to about 10000 W, or about 5500 W. The operation (1106) can be performed for a duration of about 0.1 seconds to about 500 seconds or more. The duration depends on the film being deposited, the deposition conditions and passivation process conditions, and the characteristics of the features (e.g., feature width, feature depth, etc.). Generally, a longer exposure to the plasma can be used in combination with a longer deposition (e.g., a longer duration of operation (1108)).

[0078] When HF and LF plasmas are used, the HF power may be about 0W to about 10,000W or about 0W to about 6,000W at a frequency of 13.6 MHz, and the LF power may be about 0W to about 5,000W or about 0W to about 3,000W at a frequency of about 430 MHz. When a single frequency plasma is used, HF is used having a maximum HF power of about 6,000 W at a frequency of 13.6 MHz.

[0079] Other tunable characteristics of operation (1106) include, but are not limited to, chamber pressure, pedestal temperature, gas flow dilution amount, plasma power, and plasma frequency. Passivation in operation (1106) may be referred to as the “etch” operation in a deposition-etch-deposit (dep-etch-dep) process, where dep refers to operation (1108). Various deposition-etch-deposit (dep-etch-dep) operations may be used, such as performing alternating cycles of deposition and passivation; performing cycles including deposition, then passivation, then deposition, then passivation, then deposition without passivation; and performing multiple cycles of alternating deposition, then passivation and deposition. Variations of deposition-etch-deposit (dep-etch-dep) may be used to reduce overhang caused by deposition or by the underlying structure. Depth-etch-depth (dep-etch-dep) can be used to deposit material on re-entrant features. Depth-etch-depth (dep-etch-dep) can be used to deposit material on features that slope sidewalls to reduce re-entrant. In some embodiments, operation (1106) is omitted.

[0080] In some embodiments, a purge operation (not shown) is performed after operation (1106). In some embodiments, a purge operation is performed before operation (1008).

[0081] In operation (1108), to deposit a dielectric material on the surface of a substrate, the substrate is exposed to a deposition precursor and a reaction material. In operation (1108), the deposition precursor and the reaction material may flow simultaneously and continuously into a process chamber housing the substrate. The surface on the substrate exposed to the deposition precursor and the reaction material varies according to the specific use of the specific disclosed embodiments. In some embodiments, the surface comprises silicon, polysilicon, amorphous silicon, silicon dioxide, silicon nitride, silicon carbide, silicon nitride, other materials, and combinations thereof.

[0082] The deposition precursor may be any Group IV containing precursor, such as a silicon containing precursor. In some embodiments, the deposition precursor may be a germanium containing precursor. In some embodiments, hydrogen gas is co-flowed into the chamber in addition to the deposition precursor and the reaction material. In various embodiments, the deposition precursor is an aminosilane.

[0083] The above deposition precursor is selected based on the material to be deposited. For example, in the case of silicon oxide deposition, a silicon-containing precursor may be selected. Exemplary silicon-containing precursors include silicon-containing precursors having the following structures.

[0084]

[0085] Here, R1, R2, and R3 may be the same or different substituents and may include silanes, amines, halides, hydrogen, or organic groups, such as alkylamines, alkoxy, alkyl, alkenyl, alkynyl, and aromatic groups.

[0086] An exemplary silicon-containing precursor comprises polysilanes (H3Si(SiH2)nSiH3), wherein n>1, such as silane, disilane, trisilane, tetrasilane; and trisiliamin.

[0087]

[0088] In some embodiments, the silicon-containing precursor is an alkoxysilane. Alkoxysilanes that may be used include, but are not limited to, the following.

[0089] Hx-Si-(OR)y, where x = 1-3, x+y = 4 and R is a substituted or unsubstituted alkyl group and

[0090] Hx(RO)y-Si-Si-Si-(OR)yHx, where x = 1-2, x+y = 3 and R is a substituted or unsubstituted alkyl group.

[0091] Examples of silicon-containing precursors are: tetraethyl orthosilicate (TEOS), TMOS (tetramethoxysilane), octamethylcyclotetrasiloxane (OMCTS), methylsilane, trimethylsilane (3MS), ethylsilane, butasilan, pentasilane, octasilan, heptasilane, hexasilane, cyclobutasilan, cycloheptasilane, cyclohexasilane, cyclooctasilane, cyclopentasilan, 1,4-dioxa 2,3,5,6-tetrasilacyclohexane, diethoxymethylsilane (DEMS), diethoxysilane (DES), dimethoxymethylsilane, dimethoxysilane (DMOS), methyl-diethoxysilane (MDES), methyldimethoxysilane (MDMS), octamethoxydodecasiloxane (OMODDS), tert-butoxydisilane, Includes tetramethylcyclotetrasiloxane (TMCTS), tetraoxymethylcyclotetrasiloxane (TOMCTS), triethoxysilane (TES), triethoxysiloxane (TRIES), and trimethoxysilane (TMS or TriMOS).

[0092] As mentioned above, in some embodiments, the silicon-containing precursor may be an amino-silane having hydrogen atoms, such as bis-diethyl-amino-silane, di-iso-propylamino-silane, tert-butylaminosilane (BTBAS), or tris-(dimethyl-amino)-silane (3DMAS). Aminosilane precursors include, but are not limited to: Hx-Si-(NR)y, where x = 1-3, x + y = 4, R is an organic group or a hydride group.

[0093] In some embodiments, the halogen-containing silane may be used to include at least one hydrogen atom. Such silane may have the chemical formula SiXaHy, where y ≥ 1. For example, dichlorosilane (H2SiCl2) may be used in some embodiments.

[0094] The reaction material used to react with the deposition precursor is selected according to the material to be deposited in the large gap and the selected deposition precursor. For example, for the deposition of silicon oxide, one option is to use a silicon-containing precursor as the deposition precursor and an oxidant or oxidizing agent as the reaction material. Exemplary oxidants include, but are not limited to, oxygen, ozone, peroxide, nitric oxide, nitrous oxide, water, and combinations thereof. The reaction material gas flow to the 4-station chamber may be about 200 sccm to about 5000 sccm.

[0095] The deposition precursor and the reaction material may be delivered simultaneously to a process chamber to create a process environment within a chamber containing both the deposition precursor and the reaction material. In some embodiments, the deposition precursor and reaction material flows are turned on at different times, but there is at least some duration during which the flow of the deposition precursor and the flow of the reaction material are turned on simultaneously, thereby creating a process environment within the process chamber containing both the deposition precursor and the reaction material. In some embodiments, the step of delivering the precursor and the reaction material includes turning on the flow of the deposition precursor and turning on the flow of the reaction material simultaneously, approximately simultaneously, or at least for a duration of time, such that both flows are turned on. These gases may be delivered to a showerhead, and then said gases may be delivered to a process environment within a process chamber, where the gases can react to deposit a film on a semiconductor substrate. In some embodiments, the delivery of each process gas may be delivered to the showerhead using different lines to prevent them from reacting before reaching the process environment.

[0096] Operation (1108) may be performed for any appropriate duration. The duration of operation (1108) as described herein refers to the duration during which the substrate is exposed to a processing environment containing both the deposition precursor and the reaction material. That is, in some embodiments, the duration of maintaining the flow of the deposition precursor and the duration of maintaining the flow of the reaction material may be different. In some embodiments, the flow of the deposition precursor and the flow of the reaction material are on for the same duration.

[0097] In some embodiments, the duration of operation (1108) may be about 1 second, or at least about 1 second. The deposition rate of operation (1108) depends on the flow of the reaction gas as well as the specific precursor and the process conditions under which the selected reaction gas is delivered to the substrate. In some embodiments, the deposition rate is about 3 / s to about 60 / s, or at least about 50 It may be / s. The pressure of the process chamber may be about 9 Torr to about 40 Torr, or at least about 30 Torr. The gas flow rate depends on the gas used. In some embodiments, the deposition precursor flows in the range of about 1000 sccm to about 3000 sccm, and the oxidizing agent flows in the range of about 2000 sccm to about 5000 sccm. In some embodiments, H2 flows with the oxidizing agent at a flow rate of 0 sccm to about 5000 sccm. In the case of H2 that does not flow with the oxidizing agent, the flow rate of H2 is 0 sccm. As previously mentioned, the inert gas may flow continuously during operation (1006). In some embodiments, the inert gas flows at a flow rate of about 2000 sccm to about 12000 sccm.

[0098] In features that involve shrinkage or are susceptible to pinch-off, operation (1006) may be performed until the feature is pinch-off in at least some embodiments. Features of different sizes may be pinch-off at different times. In conformal deposition, deposition begins at each surface and proceeds with growth generally orthogonal to the surface. Growth of the dielectric in the feature begins at each sidewall and proceeds until growth pinch-off of the feature.

[0099] In various embodiments, the operation (1108) may be performed until the opening of the feature is closed. In some embodiments, a seam may be formed at or near the opening of the feature. For the purposes of this invention, “near the opening” is defined as an approximate location or area within the feature (i.e., along the sidewall of the feature) corresponding to about 0% to about 20% of the feature depth measured from the field area. In certain embodiments, the area near the opening corresponds to the area of ​​the opening. Additionally, “inside the feature” or “interior of the feature” is defined as an approximate location or area within the feature corresponding to about 20% to about 60% of the feature depth measured from the field area above the feature. Generally, when a specific parameter value (e.g., thickness) is designated as "near the opening" or "inside the feature," this value represents the measurement obtained within that location / area or the average of multiple measurements.

[0100] In operation (1110), the process chamber is optionally purged. Purging may be performed when the flow of the deposition precursor and reaction material(s) in operation (1110) is reduced and / or turned off. Purging may be performed according to the plasma process conditions used in subsequent operations. In some embodiments, the purging time is longer than the duration between the repetition of operations (1112) and (1108) described below. Generally, the precursor flow is turned off or diverted during purging, and only the purging gas flows. The step of purging the chamber may include the step of flowing the purging gas or sweep gas, which may be a carrier gas used in other operations or other gases. In some embodiments, purging may include exhausting the chamber. Examples of purging gases include argon, nitrogen, hydrogen, helium, and combinations thereof. In some embodiments, operation (1110) may include one or more exhaust sub-steps for exhausting the process chamber. Alternatively, it will be understood that in some embodiments, operation (1110) may be omitted. Operation (1110) may have any suitable duration, such as about 0 seconds to about 60 seconds, for example, about 0.01 seconds. In some embodiments, increasing the flow rate of one or more purge gases may reduce the duration of operation (1110). For example, the purge gas flow rate may be adjusted according to the thermodynamic and / or geometric properties of the various reactants of the process chamber and / or process chamber piping to modify the duration of operation (1110). In one non-limiting example, the duration of the purge step may be adjusted by adjusting the purge gas flow rate. This may reduce the deposition cycle time, which may improve substrate throughput.In some embodiments, the operation (1106 to 1110) is optionally repeated in multiple cycles.

[0101] In a selectable operation (1112), densification is performed. In some embodiments, densification is performed by introducing a plasma generated from an inert gas. In some embodiments, densification is performed by introducing a plasma generated from a non-inert gas. The plasma may be generated using a noble gas, an oxidizing gas, or other gas. Non-limiting examples of gases include argon, nitrogen, hydrogen, oxygen, nitrous oxide, helium, and combinations thereof. The plasma may be generated in-situ in a furnace or within a chamber in a processing environment on a substrate. In some embodiments, the plasma is generated in a processing environment between the substrate and the showerhead in a process chamber. The plasma is generated under selected process conditions to control the features of the film deposited in operation (1112). In some embodiments, a capacitively coupled plasma is used to generate the plasma. In some embodiments, an inductively coupled plasma is used to generate the plasma.

[0102] For example, in some embodiments, high-pressure radio frequency plasma is generated to form a uniform film within a wafer wet etch rate. The high pressure may be at least about 10 Torr, or about 10 Torr to about 50 Torr, or about 10 Torr to about 35 Torr, or about 10 Torr to about 25 Torr.

[0103] In some embodiments, a low-pressure radio frequency plasma is generated to control the deposited material to form a specific dome shape within the wafer wet etching rate. The dome-shaped layer may include a convex region at or near the center of the wafer. The low pressure may be less than about 10 Torr, or a pressure of about 2 Torr to about 10 Torr.

[0104] The thickness non-uniformity of the film within the wafer and the etching rate can be tuned by adjusting the pressure. In one non-limiting example, a dome-shaped film can be changed into a dish-shaped film by adjusting the pressure, such as using a pressure of about 6 Torr, a flat film at about 18 Torr, and a dish-shaped film at about 20 Torr.

[0105] In some embodiments, a combination of low frequency (LF) and high frequency (HF) plasma is used to generate a plasma capable of changing whether the resulting film has a dome or dish shape. The plasma may be generated with radio frequency plasma power of about 1000 W to about 10000 W, or about 5500 W. The duration of the operation (1112) depends on the application in which the specific disclosed embodiments are used. In some embodiments, the operation (1112) may be performed for about 0.1 seconds to about 500 seconds or about 1 second to about 3 seconds.

[0106] When HF and LF plasmas are used, the HF power at a frequency of 13.6 MHz may be approximately 0 W to approximately 10,000 W, and the LF power at a frequency of approximately 430 MHz may be approximately 0 W to approximately 3,000 W. When a single-frequency plasma is used, an HF having a maximum HF power of approximately 6,000 W at a frequency of 13.6 MHz is used.

[0107] The temperature during this operation may be the same in operation (1106) and / or operation (1108) or both. In some embodiments, the temperature during operation (1112) is about 550°C to about 650°C, or about 650°C.

[0108] In operation (1114), the chamber is optionally purged. The purging gases and purging conditions may be any one of those described above in relation to operation (1110).

[0109] In operation (1118), it is determined whether the film has been deposited as intended, deposited to an intended thickness, and deposited with desired film properties such as wet etch rate, concavity, uniformity, or conformality. If not, many variations of operations (1106 to 1114) may be performed. Although specific operations that are optionally repeated are illustrated in FIG. 11, it will be understood that any variation repeating one or more of operations (1106 to 1114) may be used. In some embodiments, operations (1108 to 1118) are repeated in cycles. In some embodiments, operations (1006 to 1114) are repeated in cycles. The operations may be repeated for at least about 2 cycles, or for about 2 cycles to about 2000 cycles, or for about 100 cycles to about 1500 cycles.

[0110] In one example of a repeating cycle, operation (1108) may be performed for about x seconds and operation (1112) may be performed for about y seconds, where x and y depend on specific characteristics required for the resulting film. In some embodiments, x is about 0.1 seconds to about 10 seconds. In some embodiments, y is about 0.1 seconds to about 3 seconds. In some embodiments, x is about 0.1 seconds to about 10 seconds and y is about 0.1 seconds to about 3 seconds. In some embodiments, x and y may each be at least about 1 second. In some embodiments, x may be about 1 second and y may be about 3 seconds. In some cases, continuous deposition may be used, where y=0. In continuous deposition, operations (1110) and operations (1114) are not performed. In some embodiments, operations (1110, 1114) are not performed in one or more repeated cycles. Film properties can be tuned by adjusting the ratio of the duration of operation (1106) to the duration of operation (1108) to the duration of operation (1112). That is, film properties can be tuned by adjusting the ratio of passivation time to deposition time to densification time. In some embodiments, if the deposition cycle includes an increased duration of operation (1108), the duration of operation (1112) may also be increased. In some embodiments, operations (1104 to 1118) are performed without breaking the vacuum. In some embodiments, operations (1104 to 1118) are performed in the same chamber.

[0111] In various embodiments, the transition between operation (1106), operation (1108), and operation (1112) may be performed by high-speed switching. High-speed switching may be performed using specific valves and / or plasma turn-on techniques and components. In some embodiments, high-speed switching valves can be operated to open and close rapidly without gas pressure surges or flow instability. The high-speed switching valves may be opened and closed within 100 milliseconds, or within 80 milliseconds, or within 60 milliseconds, or within 40 milliseconds, or within 30 milliseconds, or within 20 milliseconds, or longer. The high-speed switching valves may be operably connected to receive signals from a controller to open or close. In various embodiments, the switching is performed rapidly while minimizing pressure changes between operations. In some embodiments, two or more of operations (1104 to 1114) are performed in the same chamber or the same station. Switching may be performed using a multi-planum shower head, where one or more source gases are distributed separately to the shower head before being delivered to the process chamber or the station housing the substrate. In some embodiments, the volume of the gas composition in a confined area within the vacuum chamber, such as a plasma confinement zone, can be replaced (i.e., flushed out) by another gas composition introduced into the vacuum chamber within a short time. This gas replacement can be achieved in less than about 1 second, more preferably within about 200 ms, by providing a valve with a fast switching capability in the gas distribution system.In various embodiments, a gas switching section (not shown) comprises a high-speed switching valve arrangement configured to receive (iii) a signal to open a first group of high-speed switching valves and close a second group of high-speed switching valves to supply the first process gas to an inner zone and an outer zone as the second process gas is diverted to a bypass line through a first group of first gas flow paths, and (iv) a signal to close a first group of high-speed switching valves and open a second group of high-speed switching valves to switch the first process gas flow and the second process gas flow to supply the second process gas to an inner zone and an outer zone as the first process gas is diverted to a bypass line through a second group of first gas flow paths. In some embodiments, while diverting the second (and optionally third, fourth, or more) process gas to one or more bypass lines, two or more operations (1104 to 1114) are performed so that the first process gas is introduced into the process chamber. The first process gas is then ignited to generate a first plasma. In some cases, this first plasma may be a passivation plasma, such as an NF3 plasma. In some embodiments, the first process gas is introduced, and no plasma is generated in this operation (e.g., when the first process gas is a precursor or reactive material used for thermal deposition). The flow of the first and second process gases is diverted so that the second process gas is supplied into the process chamber while diverting the first process gas to the bypass line. For example, this second process gas may be a thermal deposition precursor gas. In some embodiments, the second process gas may be a densification gas.The first process gas may be replaced by the second process gas in the restricted area of ​​the process chamber within a period of less than about 1 second or less than about 200 ms. In some embodiments, the second process gas is ignited to generate a second plasma, such as for densification, passivation, or suppression. In some embodiments, the second process gas is not ignited and flows thermally for thermal deposition, etc. The flows of the first and second process gases may be switched to supply the second process gas into the plasma process chamber while diverting it to a bypass line, and the second process gas may be replaced by the first process gas in the restricted area of ​​the process chamber within a period of less than about 1 second or less than about 200 ms. In some embodiments, the flows of the second and third process gases may be switched. Any number of process gas flows may be switched in a manner similar to that described in the above examples. A gas supply system designed for high-speed gas switching is jointly owned U.S. Patent No. 7,459,100; Disclosed in Patent No. 7,708,859; and Patent No. 8,088,248; and U.S. Patent Publication No. 2007 / 0066038, the disclosures of which are incorporated herein by reference.

[0112] The temperature of the chamber components can be controlled to selectively deposit material onto a substrate without substantially depositing material onto the chamber components. For example, the temperature of the components within the process chamber other than the pedestal may be set to a temperature of about 300°C or less, and as described herein, deposition using CVD and densification achieves substantially faster deposition on the substrate on the pedestal than depositing material on the surface of the process chamber. When the temperature of said components is about 550°C or less, no film accumulation occurs on said components. This selectivity prevents delamination at higher accumulation levels when material accumulates on the surface of the process chamber from processing numerous wafers in the same chamber, which allows the process chamber to be used until the accumulation on the non-pedestal components of the chamber reaches an acceptable thickness. Generally, the process chamber can withstand more than three times the amount of accumulation caused by atomic layer deposition processes. Overall, this is highly advantageous for reducing ownership costs and decreasing the frequency of chamber cleaning.

[0113] In some embodiments, the pedestal is made of aluminum nitride. In some embodiments, the pedestal is ceramic. In some cases, the tool may be retrofitted by replacing the pedestal with a ceramic pedestal, and the heaters and cooling components may be modified to cool other components while maintaining the pedestal temperature at about 550°C or higher, or from about 550°C to about 650°C. In some embodiments, the showerhead is made of aluminum.

[0114] FIG. 12 illustrates a timing scheme diagram illustrating an example of a method performed according to specific disclosed embodiments. While a specific order of operations is indicated, it can be understood that the operations may be performed in any order. The process (1200) includes a first cycle (120aA) and a second cycle (1201b). The inert gas illustrated in FIG. 12 may refer to one or more of a carrier gas, an inert gas, a diluent gas, or other gases used during various operations, depending on the composition of the gas. The inert gas may be Ar or He. Other gases that may be used instead of the inert gas include H2, N2, O2, or combinations thereof. While the "on" phase shows a constant amount, it can be understood that different levels or amounts of the "on" phase may be used in each phase. Although not illustrated, in various embodiments, purging may be performed between the densification phase (1212A) and the passivation phase (1206A) and between the densification phase (1212B) and the passivation phase (1206B).

[0115] The first cycle (1201A) includes four phases: a deposition phase (1208A), a densification phase (1212A), a passivation phase (1206A), and a purge phase (1210A). The deposition phase (1208A) may correspond to the operation (1108) of FIG. 11. During the deposition phase (1208A), the passivation gas flow is turned off, the plasma is turned off, the inert gas flow is kept turned on, the deposition precursor flow is turned on, and the reaction material flow is turned on. In the present embodiments, the deposition precursor flow is turned on when the reaction material flow starts, but it will be understood that in some embodiments, the deposition precursor flow may be turned on immediately before the reaction material flow, or the reaction material flow may be turned on immediately before the deposition precursor flow.

[0116] The densification phase (1212A) may correspond to the operation (1112) of FIG. 11. During the densification phase (1212A), the plasma is turned on while the deposition precursor flow is turned off and the reaction material flow is turned off. In some cases, an inert gas such as Ar may flow during the densification phase (1212A), as shown as an exemplary inert gas. It should be noted that the inert gas in this specification may mean carrier gases and / or gases that flow during the plasma exposure phase.

[0117] The passivation phase (1206A) may correspond to the operation (1106) of FIG. 11. During the curing passivation phase (1206A), the deposition precursor flow is turned off, the reaction material flow is turned off, the passivation gas flow is turned on, and the plasma is turned on. The inert gas may continue to flow.

[0118] The purge phase (1210A) may correspond to the operation (1110) of FIG. 11, in which the deposition precursor gas flow is turned off, the reaction material gas flow is turned off, the passivation gas flow is turned off, and the inert gas flow may continue to be turned on while the plasma is turned off.

[0119] In this example, it is determined that the film is not sufficiently deposited in the operation (1118) of Fig. 11 and the cycle of operation is repeated.

[0120] The second cycle (1201B) includes four phases: a deposition phase (1208B), a densification phase (1212B), a passivation phase (1206B), and a purge phase (1210B). The deposition phase (1208B) may correspond to the repetitive operation (1108) of FIG. 11. During the deposition phase (1208B), the passivation gas flow is turned off, the plasma is turned off, the inert gas flow remains on, the deposition precursor flow is turned on, and the reaction material flow is turned on. In this example, the deposition precursor flow is turned on when the reaction material flow starts, but it will be understood that in some embodiments, the deposition precursor flow may be turned on immediately before the reaction material flow, or the reaction material flow may be turned on immediately before the deposition precursor flow.

[0121] The densification phase (1212B) may correspond to the repetitive operation (1112) of FIG. 11. In the densification phase (1212B), the deposition precursor flow is turned off and the plasma is turned on while the reaction material flow is turned off. In some cases, an inert gas such as Ar may also flow during the high densification phase (1212B), as shown as an exemplary inert gas. Note that the inert gas here may refer to a carrier gas and / or a gas flowing during the plasma exposure phase.

[0122] The passivation phase (1206B) may correspond to the operation (1106) of FIG. 11. During the curing passivation phase (1206B), the deposition precursor flow is turned off, the reaction material flow is turned off, the passivation gas flow is turned on, and the plasma is turned on. The inert gas may continue to flow.

[0123] The purge phase (1210B) may correspond to the operation (1110) of FIG. 11, in which the deposition precursor gas flow is turned off, the reaction gas flow is turned off, the passivation gas flow is turned off, and the plasma is turned off while the inert gas flow is continuously turned on.

[0124] device

[0125] FIG. 13 schematically illustrates an embodiment of a deposition process station (1300) having a process chamber body (1302) for maintaining a process environment. A plurality of deposition process stations (1300) may be included. For example, FIG. 14 illustrates an embodiment of a multi-station processing tool (1400). In some embodiments, the process station (1300) may be suitable for a variable pressure processing environment. In some embodiments, the multi-station processing tool (1400) includes stations set to variable parameters. In some embodiments, one or more hardware parameters of the deposition process station (1300), including those discussed in detail below, may be programmatically adjusted by one or more computer controllers (1350).

[0126] The deposition process station (1300) fluidly communicates with the reaction mass transfer system (1301a) to deliver process gas to the distribution shower head (1306). The reaction mass transfer system (1301a) includes a gas source comprising a process gas and a carrier gas source. The gas supply source may include a deposition precursor gas, or an oxidizing gas (e.g., ozone), or a source for N2, O2, Ar, or H2 gas to be supplied to the distribution shower head (1306). One or more inlet valves (1320) may also control the inflow of process gas into one or more direct gas lines toward the distribution shower head (1306). Plasma may also be delivered to the distribution shower head (1306) or generated in the deposition process station (1300). The deposition process station (1300) may have a limited volume to isolate energy within the deposition process station (1300). The deposition process station (1300) may be equipped with one or more high-speed switching valves that can be operably connected to open and close upon receiving a signal from a controller. In some embodiments, the deposition process station (1300) may be equipped with a switching unit (not shown) used for high-speed switching of the gas flow. In some embodiments, the deposition process station (1300) is equipped with high-speed RF turn-on components for rapidly turning on and off the plasma. In some embodiments, the plasma is generated remotely, plasma species are distributed, and the inflow of plasma species is controlled using high-speed switching valves. A reaction material supply system (1301a) operates to control the flow rate of different gases that can be supplied to the switching unit (not shown) and to selectably adjust the composition.The reaction mass transfer system (1301a) may provide different flow rates of process and carrier gases and / or chemicals to a switching section (not shown) through a gas passage as illustrated. In addition, the flow rates of process gases and / or carrier gases and / or chemicals supplied to the showerhead (1306) (other gases may be diverted to a bypass line (not shown), and this may fluidly communicate with a vacuum pumping system, such as between a turbopump and a roughing pump).

[0127] In some embodiments, the processing environment within the deposition process station (1300) may include one or more zones. The reaction mass transfer system (1301a) may provide the necessary gas flow and / or gas chemicals across the substrate (1312), thereby improving substrate processing uniformity.

[0128] The showerhead (1306) distributes process gas to the substrate (1312). In the embodiments illustrated in FIG. 13, the substrate (1312) is positioned beneath the showerhead (1306) and is shown resting on a pedestal (1308). The showerhead (1306) may have any suitable shape and may have any number and arrangement of ports for distributing process gas to the substrate (1312). In some embodiments, the showerhead (1306) may be a temperature-controlled aluminum showerhead. For example, in some embodiments, the showerhead (1306) is set to a setpoint temperature of about 300°C. In some embodiments, the showerhead (1306) may be equipped with multiple plenums that allow different gases to flow separately to the showerhead and / or deposition process station (1300), enabling rapid switching between gas flows.

[0129] The pedestal (1308) may be a ceramic material or another suitable material. In some embodiments, the pedestal (1308) may be a ceramic pedestal capable of operating at high temperatures, such as about 650°C or at least about 650°C.

[0130] In some embodiments, the pedestal (1308) may be a ceramic pedestal. In some embodiments where a ceramic pedestal is used, a focus ring (1313) may be on the pedestal (1308) so that the focus ring can be used to focus the plasma to control plasma non-uniformity at the wafer edge.

[0131] In some embodiments, the pedestal (1308) may be an aluminum nitride pedestal. In some embodiments where an aluminum nitride pedestal is used, the focus ring (1313) may be optional.

[0132] The pedestal (1308) may have a thin stem that acts as a thermal break for the chamber vacuum seal. In some embodiments, the pedestal (1308) may include a dual zone heater (i.e., an inner heater and an outer heater) to address thermal uniformity.

[0133] In some embodiments, the pedestal (1308) may be raised or lowered to expose the substrate (1313) to the volume between the substrate (1312) and the dispensing shower head (1306). In some embodiments, it will be understood that the pedestal height may be programmed by a suitable computer controller (1350).

[0134] In another scenario, adjusting the height of the pedestal (1308) may change the plasma density during the plasma activation cycle within the process in embodiments where the plasma is ignited. At the end of the process step, the pedestal (1308) may be lowered during another substrate transfer step so that the substrate (1312) can be removed from the pedestal (1308).

[0135] In some embodiments, the pedestal (1308) may be temperature-controlled via a heater (1310). In some embodiments, the pedestal (1308) may be heated to a temperature of at least about 650°C during the deposition of the silicon oxide film as described in the disclosed embodiments. In some embodiments, the pedestal is set to a temperature of about 500°C to about 900°C, or about 400°C to about 650°C, or about 400°C to about 800°C, or about 600°C to about 700°C.

[0136] Additionally, in some embodiments, pressure control for the process station (1300) may be provided by a butterfly valve (1318). As illustrated in the embodiment of FIG. 13, the butterfly valve (1318) throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the process station (1300) may be adjusted by changing the flow rate of one or more gases introduced into the process station (1300).

[0137] In some embodiments, the position of the dispensing showerhead (1306) may be adjusted proportionally to the pedestal (1308) to change the volume between the substrate (1312) and the dispensing showerhead (1306). Additionally, it will be understood that the vertical position of the pedestal (1308) and / or the showerhead (1306) may be changed by any suitable mechanism within the scope of the invention. In some embodiments, the pedestal (1308) may include a rotation axis for rotating the orientation of the substrate (1312). In some embodiments, it will be understood that one or more of these exemplary adjustments may be performed programmatically by one or more suitable computer controllers (1350).

[0138] In some embodiments where plasma may be used as discussed above, the distribution shower head (1306) and pedestal (1308) electrically communicate with a radio frequency (RF) power supply (1314) and a matching network (1316) to power the plasma. In some embodiments, plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply (1314) and the matching network (1316) may operate at any suitable power to form a plasma having a composition of desired radical species. Examples of suitable power are about 0 W to about 6000 W. Plasma may also be used during densification after performing chemical vapor deposition of dielectric material on a substrate surface. The RF power supply (1314) may provide RF power of any suitable frequency. In some embodiments, the RF power supply (1314) may be configured to control high-frequency and low-frequency RF power independently of each other. An exemplary low-frequency RF frequency may include a frequency of about 10 kHz to about 2 MHz or about 10 kHz to about 500 kHz, but is not limited thereto. An exemplary high-frequency RF frequency may include a frequency of about 1.8 MHz to about 100 MHz, or about 1.8 MHz to about 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 40 MHz, or greater than 60 MHz, but is not limited thereto. It will be understood that any suitable parameter may be adjusted discretely or continuously to provide plasma energy for surface reaction.

[0139] In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage and current sensors (e.g., VI probes). In another scenario, plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopic sensors (OES). In some embodiments, one or more plasma parameters may be programmed based on measurements from these in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop to provide programmed control of plasma power. It will be understood that in some embodiments, other monitors may be used to monitor plasma and other process characteristics. These monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0140] In some embodiments, instructions for the controller (1350) may be provided via input / power control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process phase may be included in the corresponding recipe phase of the process recipe. In some cases, the process recipe phases may be arranged sequentially so that all instructions for the process phase are executed simultaneously with the corresponding process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in the recipe phase. For example, the first recipe phase may include instructions for setting the flow rate of an inert gas, instructions for setting the flow rate of a carrier gas (e.g., Ar), instructions for igniting the plasma, and time delay instructions for the first recipe phase. The second recipe phase may include instructions for setting the flow rate of an inert gas and / or precursor gas, instructions for setting the flow rate of a carrier gas (such as Ar), and time delay instructions for the second recipe phase. The third recipe phase may include instructions for controlling the flow rate of an oxidizer gas such as ozone, instructions for controlling the flow rate of a carrier or purge gas, and time delay instructions for the fourth recipe phase. The fourth, subsequent recipe phase may include instructions for controlling or stopping the flow rate of an inert gas and / or reactant gas, instructions for controlling the flow rate of a carrier gas or purge gas, and time delay instructions for the fifth recipe phase. The fifth, subsequent recipe phase may include instructions for controlling or stopping the flow rate of a single gas, instructions for generating plasma, and time delay instructions for the fifth recipe phase.It will be understood that these recipe phases may be further subdivided and / or repeated in any appropriate manner within the scope of the disclosed embodiments. In some embodiments, the controller (1350) may include any features described below in relation to the system controller (1450) of FIG. 14.

[0141] As described above, one or more process stations may be included in a multi-station processing tool. FIG. 14 shows a schematic diagram of one embodiment of a multi-station processing tool (1400) including an inbound load lock (1402) and an outbound load lock (1404), and either or both of the inbound load lock (1402) and the outbound load lock (1404) may include a remote plasma source. At atmospheric pressure, a robot (1406) is configured to move a substrate or wafer from a cassette loaded via a pod (1408) to the inbound load lock (1402) via an atmospheric port (1410). The substrate is placed on the pedestal (1412) of the inbound load lock (1402) by the robot (1406), the atmospheric port (1410) is closed, and the load lock is pumped down. If the inbound load lock (1402) includes a remote plasma source, the substrate may be exposed to remote plasma treatment at the load lock before being introduced into the process chamber (1414). Additionally, the substrate may also be heated at the inbound load lock (1402), for example, to remove moisture and adsorbed gases. Next, a chamber transfer port (1416) leading to the processing chamber (1414) is opened, and another robot (not shown) places the substrate into the reactor on the pedestal of the first station shown within the reactor for processing. While the embodiment shown in FIG. 14 includes a load lock, it will be understood that in some embodiments, the substrate may enter the process station directly. In various embodiments, a soak gas is introduced into the station when the substrate is placed on the pedestal (1412) by the robot (1406).

[0142] The illustrated process chamber (1414) includes four process stations numbered 1 through 4 in the embodiments illustrated in FIG. 14. Each station has a heated pedestal (indicated as (1418) in the case of station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, the process station may be switchable between ALD and PEALD process modes. Additionally, or alternatively, in some embodiments, the process chamber (1414) may include one or more matched pairs of ALD and plasma-enhanced ALD process stations. Although the illustrated processing chamber (1414) includes four stations, it will be understood that the process chamber according to the present invention may have any number of stations. For example, in some embodiments, the processing chamber may have five or more stations, whereas in other embodiments, the processing chamber may have three or fewer stations.

[0143] FIG. 14 illustrates an embodiment of a wafer handling system (1490) for transporting substrates within a processing chamber (1414). In some embodiments, the wafer handling system (1490) may transport substrates between various process stations and / or between a process station and a load lock. It will be understood that any suitable wafer handling system may be used. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 14 also illustrates an embodiment of a system controller (1450) used to control process conditions and hardware status of a process tool (1400). The system controller (1450) may include one or more memory devices (1456), one or more mass storage devices (1454), and one or more processors (1452). The processor 1452 may include a CPU or computer, analog and / or digital input / power connections, a stepper motor controller board, etc. In some embodiments, the system controller (1450) includes machine-readable instructions for performing operations such as those described above in relation to FIGS. 2, FIGS. 3 and FIGS. 4.

[0144] In some embodiments, a system controller (1450) controls the activities of a process tool (1400). The system controller (1450) executes system control software (1458) that is stored in a mass storage device (1454), loaded into a memory device (1456), and executed on a processor (1452). Alternatively, control logic may be hardcoded in the controller (1450). ASICs (Applications Specific Integrated Circuits), PLDs (Programmable Logic Devices) (e.g., field programmable gate arrays or FPGAs), etc., may be used for this purpose. Wherever "software" or "code" is used in the following discussion, functionally similar hardcoded logic may be used instead. System control software (1458) may include instructions for controlling timing, gas mixture, amount of gas flow, chamber and / or station pressure, chamber and / or station temperature, substrate temperature, target power level, RF power level, substrate pedestal, chuck and / or susceptor position, and other parameters of a specific process performed by the process tool (1400). The system control software (1458) may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be created to control the operation of process tool components used to perform various process tool processes. The system control software (1458) may be coded in any suitable computer-readable programming language.

[0145] In some embodiments, the system control software (1458) may include input / power control (IOC) sequencing instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored in a mass storage device (1454) and / or memory device (1456) associated with the system controller (1450) may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0146] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal (1418) and to control the gap between the substrate and other parts of the process tool (1400).

[0147] The process gas control program may include code for controlling the gas composition (e.g., the first precursor gas, soaking gas, second reaction material gas, and purge gas described herein) and the flow rate, and may optionally include code for flowing gas to one or more process stations prior to deposition to stabilize pressure in the process station. The pressure control program may include code for controlling pressure within the process station by controlling, for example, a throttle valve in the exhaust system of the process station, the flow of gas to the process station, etc.

[0148] The heater control program may include code that controls the current to the heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (e.g., soaking gas) to the substrate.

[0149] A plasma control program may include code for setting RF power levels applied to process electrodes at one or more process stations according to embodiments of the present specification.

[0150] The pressure control program may include code for maintaining the pressure in the reaction chamber according to the embodiments of the present specification.

[0151] In some embodiments, there may be a user interface associated with a system controller (1450). The user interface may include a display screen, graphic software display and pointing devices of device and / or process conditions, and user input devices such as a keyboard, touch screen, microphone, etc.

[0152] In some embodiments, parameters adjusted by the system controller (1450) may be associated with process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface.

[0153] Signals for monitoring the process may be provided from various process tool sensors by analog and / or digital input connections of the system controller (1450). Signals for controlling the process may be output through analog and digital power connections of the process tool (1400). Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0154] The system controller (1450) may provide program instructions for implementing the deposition process described above, such as processes that employ soaking before initiating ALD on a substrate inserted into a reaction chamber, while soaking is performed under any of the soaking conditions described herein. The program instructions may control various process parameters such as direct current (DC) power levels, RF bias power levels, pressure, temperature, etc. The instructions may control parameters to operate in-situ deposition of film stacks according to various embodiments described herein.

[0155] The system controller may generally include one or more memory devices and one or more processors configured to execute instructions so that the devices perform the method according to the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations according to the disclosed embodiments may be coupled to the system controller.

[0156] In some embodiments, a system controller (1450) is part of the system, which may be part of the examples described above. Such a system may include semiconductor processing equipment comprising a processing tool or processing tools, a chamber or chambers, a platform or platforms for processing and / or specific processing components (wafer pedestal, gas flow system, etc.). Such systems may be integrated with electronic devices for controlling the operation of a semiconductor wafer or substrate before, during, and after processing. The electronic device may be referred to as a "controller," which may control various components or sub-parts of the system or systems. A system controller (1450) may be programmed to control any process disclosed herein, including, depending on processing conditions and / or the type of system, the supply of processing gas, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid transfer setting, position and motion setting, and wafer transfer into and out of a load lock connected to or interfaced with a tool and other transfer tools and / or a specific system.

[0157] Generally speaking, the system controller (1450) may be defined as an electronic device having various integrated circuits, logic, memory and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions delivered to the system controller (1450) or the system in the form of various individual settings (or program files) that define operation parameters for performing a specific process on or for a semiconductor wafer. In some embodiments, the operation parameters may be part of a recipe defined by process engineers to achieve one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0158] In some embodiments, the system controller (1450) may be part or combination of computers that are integrated into the system, coupled to the system, or otherwise networked to the system, or a combination thereof. For example, the system controller (1450) may be located in the 'cloud' or may be all or part of a fab host computer system capable of enabling remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance metrics from multiple manufacturing operations, change parameters of the current processing, and set processing steps to follow the current processing or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a local network or a network including the Internet. The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which is communicated from the remote computer to the system. In some examples, the system controller (1450) receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool configured to interface with or control the system controller (1450). Accordingly, as described above, the system controller (1450) may be distributed by including one or more individual controllers that are networked and operated together toward a common purpose, such as the processes and controls described herein, for example.Examples of distributed controllers for this purpose would be one or more integrated circuits in the chamber communicating with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control the process of the chamber.

[0159] Exemplary systems may include, without limitation, a plasma etching chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a PVD chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be used or associated with the manufacture and / or manufacture of semiconductor wafers.

[0160] As described above, depending on the process steps or steps to be performed by the tool, the system controller (1450) may communicate with other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or one or more of the tools used for material transport to bring containers of wafers from tool locations and / or load ports and from tool locations and / or load ports in the semiconductor manufacturing plant.

[0161] Suitable apparatus for carrying out the method disclosed herein is further discussed and described in U.S. Patent Application No. 13 / 084,399, filed April 11, 2011, titled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION”; and U.S. Patent Application No. 13 / 084,305, filed April 11, 2011, titled “SILICON NITRIDE FILMS AND METHODS”, each of which is incorporated herein by reference in its entirety.

[0162] The apparatus / process described herein may be used in conjunction with lithography patterning tools or processes for the manufacture or fabrication of, for example, semiconductor devices, displays, LEDs, solar panels, etc. Generally, but not necessarily, such tools / processes are used or performed together in a common manufacturing facility. Lithography patterning of a film generally comprises: (1) applying a photoresist to a workpiece using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate, furnace, or ultraviolet (UV) curing tool; (3) exposing the photoresist to visible light, UV, or X-ray light using a tool such as a wafer stepper; and (4) developing the resist to pattern the resist by selectively removing the resist using a tool such as a wet bench. (5) transferring a resist pattern to a lower film or workpiece using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper, some or all of which are included, and each of the operations is enabled using a plurality of possible tools.

[0163] experiment

[0164] Experiment 1

[0165] Experiments were performed on two different substrates. The first substrate underwent blanket deposition of a silicon oxide film using chemical vapor deposition (CVD) at a temperature of 550°C for 30 seconds in a chamber with a pressure of 12 Torr, with tris(dimethylamino)silane (3DMAS) as a silicon precursor and oxygen at 5000 sccm as a reactive agent. Argon flowed as a carrier / purge gas at 9200 sccm, and hydrogen flowed as a process gas at 5000 sccm. The resulting substrate had a deposition rate of 0.7 Å / s. The second substrate underwent blanket deposition of a silicon oxide film at a temperature of 650°C for 30 seconds in a chamber with a pressure of 12 Torr, using 3DMAS as a silicon precursor and oxygen at 5000 sccm as a reactive agent. Argon flows as a carrier / purge gas at 9200 sccm, and hydrogen flows with the process gas at 5000 sccm. The resulting substrate has a deposition rate of 3.81 Å / s. Comparative deposition rates (DR) are provided in the graph of Fig. 15. These results suggest a strong dependence of the deposited film on temperature.

[0166] Experiment 2

[0167] Experiments were performed on different substrates. Multiple substrates underwent blanket deposition of silicon oxide films in a chamber at a temperature of 650°C for 30 seconds using tris(dimethylamino)silane (3DMAS) as a silicon precursor and oxygen at 5000 sccm as a reactive substance. Argon flowed as a carrier / purge gas at 9200 sccm, and hydrogen flowed with the process gas at 5000 sccm. The films were deposited at chamber pressures of 9 Torr, 12 Torr, 15 Torr, 17.5 Torr, and 19.5 Torr. The resulting substrate deposition rates are graphed in Fig. 16. The results suggest a strong dependence of the deposition rate on chamber pressure, with elevated deposition rates observed at higher chamber pressures.

[0168] Experiment 3

[0169] Experiments were performed on four different substrates. The first substrate involved blanket deposition of a silicon oxide film by using tris(dimethylamino)silane (3DMAS) as a silicon precursor and 5000 sccm of oxygen as a reactant in a chamber at a temperature of 650°C for 30 seconds without subsequent densification.

[0170] The second substrate, the third substrate, and the fourth substrate involve blanket deposition of a silicon oxide film using multiple deposition cycles. Each deposition cycle involves (1) simultaneous exposure to 3DMAS as a silicon precursor and oxygen as a reactive material at a temperature of 650 °C; (2) purging; (3) radio frequency densification; and (4) purging. For the second substrate, a chamber pressure of 6 Torr is used, while during densification, a high-frequency plasma is generated using 3500 W and a low-frequency plasma is generated using 2000 W. For the third substrate, a chamber pressure of 6 Torr is used, and during densification, a single-frequency high-frequency plasma is generated using 5500 W plasma power. For the fourth substrate, a chamber pressure of 19.5 Torr is used, and during densification, a single-frequency high-frequency plasma is generated using 5500 W plasma power.

[0171] The normalized wet etching rate amounts of the resulting substrate are graphed in FIG. 17. The normalized wet etching rate amounts are normalized to standard high temperature furnace oxide. Series (1701) shows the normalized wet etching rate amounts of the first substrate, series (1702) shows the normalized wet etching rate amounts when the film is deposited using dual frequency plasma, series (1703) shows the normalized wet etching rate amounts when the film is deposited using 6 Torr pressure and single frequency plasma, and (1705) shows the normalized wet etching rate amounts when the film is deposited using 19.5 Torr pressure and single frequency plasma. Without densification, the WERR is about 8.5 (1701), but can be reduced to about 5 (1702, 1703, 1704) and can be used to adjust the film profile (1702, 1702). With densification, the wet etching rate ratio can be in the range of about 1.5 to about 6. In some embodiments, using densification, the wet etching rate can be 0.2 compared to the undensified film.

[0172] Experiment 4

[0173] To obtain FTIR (Fourier-transform IR spectroscopy) spectra for films deposited using chemical vapor deposition at 650 °C without densification and films deposited using chemical vapor deposition at 650 °C with radio frequency (RF) densification, experiments were performed with cycles such that each deposition cycle involved 1 second of CVD followed by 1 second of densification.

[0174] In the FTIR spectrum obtained from the cyclo-deposited film with densification, all peaks associated with -OH bonds were removed, which suggests that high-quality films were deposited.

[0175] Experiment 5

[0176] Experiments were performed to measure the wet etching rates of various films deposited on large features. The wet etching rates were evaluated by dipping in hydrofluoric acid diluted to 100:1 for 10 minutes. The first substrate contains features with an aspect ratio of approximately 1:10, and the features are filled with dielectric material deposited using CVD at a chamber pressure of 19.5 Torr without densification or deposition cycles. The wet etching rate ratios were evaluated at the top of the feature (6.51), the middle of the feature (6.43), and the bottom of the feature (6.57).

[0177] The second substrate includes a feature having an aspect ratio of about 1:10, and the feature is filled with a dielectric material deposited using deposition cycles, the cycles include 1 second of CVD at a chamber pressure of 19.6 torr and 6 seconds of radio frequency (RF) densification at 6 torr. Wet etching rate ratios were obtained at the top of the feature (3.77), the middle of the feature (4.12), and the bottom of the feature (4.17).

[0178] These results suggest that the CVD and densification cycles substantially reduce the wet etching rate.

[0179] Experiment 6

[0180] Experiments were performed with substrates having high aspect ratio features and polysilicon liners. The polysilicon liners showed reduced damage when exposed to cycles of thermal CVD and plasma densification using suppressed plasma with NH3 plasma, which may be due to increased deposition rate during deposition and reduced reactivated residual fluorine.

[0181] Deposition involved thermal CVD with a depth-dependent inhibition step time used for plasma densification and downward inhibition to a target location within high aspect ratio features. The use of thermal CVD during deposition results in an elevated deposition rate and less noticeable damage.

[0182] conclusion

[0183] The embodiments disclosed above describe the deposition of a material on a substrate, such as a wafer, a substrate, or other workpiece. The workpiece may be of various shapes, sizes, and materials. In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially manufactured integrated circuit" are used interchangeably.

[0184] Those skilled in the art will understand that the term “partially manufactured integrated circuit” may refer to a silicon wafer during any of the many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry generally have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise noted, the processing details cited herein (e.g., flow rate, power level, etc.) relate to processing substrates with a diameter of 300 mm or process chambers configured to process substrates with a diameter of 300 mm and may be scaled to suit substrates or chambers of other sizes. In addition to semiconductor wafers, other workpieces to which the embodiments disclosed herein may be used include various articles such as printed circuit boards. The processes and apparatus may be used in the manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc.

[0185] The ranges described in this specification include their endpoints.

[0186] In this specification, "silicon oxide" comprises a compound containing silicon and oxygen atoms, and Si comprising integer values ​​of x and y and non-integer values ​​of x and y. x O y It is referred to as including all stoichiometric possibilities for. For example, "silicon oxide" is defined by the chemical formula SiO₂. n It includes compounds having, where 1 ≤ n ≤ 2, n can be an integer or non-integer value. "Silicon oxide" is SiO 1.8 It may include sub-stoichiometric compounds such as. "Silicon oxide" may include silicon dioxide (SiO2) and silicon monoxide (SiO). Silicon oxide also includes both natural and synthetic variations and includes all crystalline and molecular structures, including tetrahedral coordination of oxygen atoms surrounding a central silicon atom. "Silicon oxide" also includes amorphous silicon oxide and silicates. In some embodiments, silicon oxide refers to a silicon-rich film. Impurities such as carbon, nitrogen, boron, phosphorus, and germanium may be additionally added to the silicon oxide.

[0187] "Silicon nitride" refers to Si, including integer values ​​of x and y such as x=3 and y=4, and non-integer values ​​of x and y. x N y It is referred to as including all stoichiometric possibilities for. For example, the chemical formula "silicon nitride" SiN n It includes compounds having , where 1 ≤ n ≤ 2, where n can be an integer or non-integer value and may be Si3N4. SiN 1.7It may include substoichiometric compounds where n is about 0.8 to about 1.7, as shown above. Silicon nitride may contain 0% to 25% hydrogen or 10% to 25% hydrogen. Silicon nitride also includes silicon nitride in which some hydrogen is bonded to silicon or nitrogen, silicon nitride in which some oxygen is bonded to silicon or nitrogen, or a combination thereof. Silicon nitride also includes both natural and synthetic variations and includes all lattice, crystal, and molecular structures, including triangular alpha silicon nitride, hexagonal beta silicon nitride, and cubic gamma silicon nitride. "Silicon nitride" also includes amorphous silicon nitride and may include silicon nitride with trace impurities.

[0188] As described in this specification, it will be understood that temperature may refer to a temperature at which a pedestal holding a substrate can be set. "Substrate temperature," "gas temperature," and "deposition temperature" may all refer to a temperature at which the pedestal is set.

[0189] Although the foregoing embodiments have been described in some detail for the sake of clarity of understanding, it will be apparent that specific changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative methods for implementing the processes, systems, and apparatuses of the embodiments. Accordingly, the embodiments are considered exemplary and are not limiting, nor are they limited to the details set forth herein.

Claims

Claim 1 A substrate processing method for processing substrates within a chamber, comprising: providing a semiconductor substrate having features to the chamber; and a step of depositing a dielectric material within the features on the semiconductor substrate, wherein the semiconductor substrate is exposed to a plasma-free environment comprising a deposition precursor and a reaction material, and the deposition precursor and the reaction material are introduced into the chamber housing the semiconductor substrate to form the dielectric material, and the step of introducing a passivation gas into the chamber and igniting a passivation plasma in a passivation gas atmosphere. Claim 2 A substrate processing method according to claim 1, further comprising the step of exposing the dielectric material to a densifying plasma in the chamber generated in an inert gas atmosphere. Claim 3 A substrate processing method according to claim 1, wherein the step of depositing the dielectric material further comprises the step of alternately repeating in time between the step of introducing the deposition precursor and the reaction material and the step of introducing the passivation gas in a plasma-free environment. Claim 4 A substrate processing method according to claim 2, wherein the step of depositing the dielectric material further comprises the step of introducing the deposition precursor and the reaction material in a plasma-free environment, the step of introducing the passivation gas, and the step of exposing the dielectric material to the densifying plasma in the chamber generated in the inert gas atmosphere, wherein the steps are repeated alternately in time. Claim 5 A method for processing substrates within a chamber, comprising: providing a semiconductor substrate having features to a chamber; introducing the deposition precursor and the reaction material into the chamber housing the semiconductor substrate to form a dielectric material by exposing the semiconductor substrate to a plasma-free environment comprising a deposition precursor and a reaction material; and depositing the dielectric material within the features on the semiconductor substrate by exposing the dielectric material to a densifying plasma within the chamber generated in an inert gas atmosphere. Claim 6 A substrate processing method according to claim 5, further comprising the step of introducing a passivation gas into the chamber and igniting a passivation plasma. Claim 7 A substrate processing method according to claim 5, wherein the step of depositing the dielectric material further comprises the step of alternately repeating in time between the step of introducing the deposition precursor and the reaction material in a plasma-free environment and the step of exposing the dielectric material to the densifying plasma generated in an inert gas atmosphere. Claim 8 An apparatus for processing a semiconductor substrate comprising a semiconductor material, comprising one or more process chambers, wherein at least one process chamber comprises: a showerhead; a heated pedestal for heating the semiconductor substrate to a temperature of at least 650°C; a plasma generator capable of generating plasma within the at least one process chamber; one or more gas sources; one or more gas inlets for delivering gas from the one or more gas sources to the one or more process chambers through the showerhead; and a controller having at least one processor and a memory, wherein the at least one processor and the memory are communicably connected to each other, the at least one processor is operably connected to at least flow control hardware, and the memory is at least: a step of setting the temperature of the heated pedestal to less than 650°C; and the following actions in time-separated pulses: an action of inducing the introduction of a deposition precursor and a reaction material into the one or more process chambers through the showerhead; A semiconductor substrate processing apparatus storing executable instructions for a computer to control at least one processor to control the flow control hardware by the step of causing the introduction of an operation that causes plasma generation when an inert gas is introduced into the one or more process chambers after causing the interruption of the introduction of the deposition precursor and the reaction material. Claim 9 A semiconductor substrate processing apparatus according to claim 8, wherein the controller instructions for inducing the temporally separated pulses include instructions for inducing the generation of a second plasma when a passivation gas is introduced into the one or more process chambers. Claim 10 A semiconductor substrate processing apparatus according to claim 8 or 9, wherein at least one of the operation inducing the introduction of the deposition precursor and the reaction material and the operation inducing the generation of the plasma is performed by high-speed switching.

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