Display device

Abstract

A display device comprises a substrate; a polycrystalline silicon film disposed on the substrate; and a first buffer film disposed between the substrate and the polycrystalline silicon film and including one surface in contact with the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first RMS roughness range, and the first RMS roughness range is 1.5 nm or less.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. Accordingly, display devices recently include Liquid Crystal Displays (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Displays (OLEDs), and Micro Light Emitting Diode Displays.

[0003] The display device includes a light-emitting diode and a plurality of thin-film transistors connected to the light-emitting diode. The thin-film transistors may include a channel region and a source / drain region of a polycrystalline silicon film.

[0004] When the thin-film transistor is turned on in the operating voltage range, current flows through the thin-film transistor, and when it is turned off again in the non-operating voltage range, the current flow is controlled by the thin-film transistor.

[0005] Meanwhile, the device characteristics of a thin-film transistor may vary depending on the crystal orientation, crystal size, and crystal defects of the polycrystalline silicon film providing the channel region and source / drain regions of the thin-film transistor. The problem to be solved

[0006] The problem that the present invention aims to solve is to provide a display device with improved device characteristics of a thin-film transistor.

[0007] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A display device according to one embodiment for solving the above problem comprises: a substrate; a polycrystalline silicon film disposed on the substrate; and a first buffer film disposed between the substrate and the polycrystalline silicon film and including one surface in contact with the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first RMS roughness range, and the first RMS roughness range is 1.5 nm or less.

[0009] The first buffer film may include a silicon oxide film.

[0010] A second buffer film is further included between the substrate and the first buffer film, and the second buffer film may include a material different from the first buffer film.

[0011] The second buffer membrane may include a silicon nitride film.

[0012] The polycrystalline silicon film comprises a surface in contact with one surface of the first buffer film and another surface opposite to the surface of the polycrystalline silicon film, and the surface of the polycrystalline silicon film has a second RMS roughness range, and the second RMS roughness range may be the same as the first RMS roughness range.

[0013] The other side of the polycrystalline silicon film has a third RMS roughness range, and the third RMS roughness range may be larger than the second RMS roughness range.

[0014] The polycrystalline silicon film comprises a surface in contact with one side of the first buffer film and another surface opposite to the surface of the polycrystalline silicon film, and the polycrystalline silicon film comprises hydrogen ions, and the sum of the concentrations of hydrogen ions near the surface of the polycrystalline silicon film may be greater than the sum of the concentrations of hydrogen ions near the center of the polycrystalline silicon film.

[0015] The vicinity of the one surface of the polycrystalline silicon film is 100 from the one surface of the polycrystalline silicon film It is defined as a first region extending to a depth, and the vicinity of the center of the polycrystalline silicon film extends 50 to one side and to the other side, respectively, from the center point of the polycrystalline silicon film. It can be defined as a second region, which is a depth interval.

[0016] The sum of the concentrations of hydrogen ions in the first region may be 100 times or more than the sum of the concentrations of hydrogen ions in the second region.

[0017] The hydrogen of the polycrystalline silicon film can be configured to be provided from the first buffer film.

[0018] The concentration of hydrogen ions on one side of the polycrystalline silicon film may be 200 times or more compared to the concentration of hydrogen ions at the center point of the polycrystalline silicon film.

[0019] The crystals of the above polycrystalline silicon film may have a ratio of 20% or more of a first crystal having a {100} crystal plane.

[0020] The first crystal of the polycrystalline silicon film may be at least 70% of the sum of the first crystal, the second crystal having a {101} crystal plane, and the third crystal having a {111} crystal plane.

[0021] The average crystal size of the above polycrystalline silicon film may be 350 nm or larger.

[0022] The defects in the above polycrystalline silicon film may be 1.E+17 (spins / cm3) or less.

[0023] The first RMS roughness is calculated by measuring 20 locations at intervals of 25 nm in a 500 nm length area, and the first RMS roughness measurement can be performed using TEM.

[0024] A display device according to another embodiment for solving the above problem comprises: a substrate; a polycrystalline silicon film disposed on the substrate; and a first buffer film disposed between the substrate and the polycrystalline silicon film and including one surface in contact with the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first RMS roughness range, the first RMS roughness range is 1.5 nm or less, and the crystal of the polycrystalline silicon film has a first crystal ratio having a {001} plane direction of 20% or more.

[0025] The first RMS roughness is calculated by measuring 20 locations at intervals of 25 nm in a 500 nm length area, and the first RMS roughness measurement can be performed using TEM.

[0026] The polycrystalline silicon film comprises a surface in contact with one surface of the first buffer film and another surface opposite to the surface of the polycrystalline silicon film, wherein the surface of the polycrystalline silicon film has a second RMS roughness range, the second RMS roughness range being the same as the first RMS roughness range, and the other surface of the polycrystalline silicon film includes a third RMS roughness range, the third RMS roughness range being greater than the second RMS roughness range.

[0027] The first crystal of the polycrystalline silicon film may be at least 70% of the sum of the first crystal, the second crystal having a {101} plane direction, and the third crystal having a {111} crystal direction.

[0028] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0029] The device characteristics of a thin-film transistor can be improved by a display device according to one embodiment.

[0030] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0031] FIG. 1 is a perspective view of a display device according to one embodiment. FIG. 2 is a plan view showing an example of a display panel according to one embodiment. Figure 3 is a circuit diagram showing an example of a subpixel of Figure 2. Figure 4 is a plan view showing an example of the first transistor of Figure 3. Figure 5 is a cross-sectional view taken along the line I-I' of Figure 4. Figure 6 is an enlarged view of area A of Figure 5. FIG. 7 is a photograph showing a second buffer film and an amorphous silicon film according to one embodiment. FIG. 8 is a photograph showing the measurement of the first roughness of the second buffer film according to one embodiment. Figures 9 to 11 are graphs showing the concentration distribution of hydrogen ions in a polycrystalline silicon film. Figure 12 is a table showing the hydrogen ion concentration area within the second buffer membrane and at the interface. Figure 13 is a table showing the hydrogen ion concentration within the second buffer membrane and at the interface. FIG. 14 is a drawing for comparing a polycrystalline silicon film according to one embodiment and a polycrystalline silicon film according to a comparative example. FIG. 15 is another drawing for comparing a polycrystalline silicon film according to one embodiment with a polycrystalline silicon film according to a comparative example. Figure 16 is a graph showing the correlation between the crystal orientation and defects of a polycrystalline silicon film. FIG. 17 is a graph illustrating that the hysteresis phenomenon of the first transistor according to one embodiment has been improved. Figure 18 is a magnified graph of a part of Figure 17. Figure 19 is a graph showing the correlation between the roughness of the second buffer film and the degree of hysteresis. Figure 20 is a photograph showing the second buffer film and the polycrystalline silicon film of the comparative example. FIG. 21 is a schematic diagram showing the manufacturing process steps of a second buffer membrane according to one embodiment. Figure 22 is a graph showing the correlation between the deposition rate of the second buffer film and the roughness of the second buffer film. Specific details for implementing the invention

[0032] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0033] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0034] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0035] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0036] Specific embodiments will be described below with reference to the attached drawings.

[0037] FIG. 1 is a perspective view of a display device according to one embodiment. FIG. 2 is a plan view showing an example of a display panel according to one embodiment.

[0038] In this specification, “top,” “top,” and “top surface” refer to the upward direction, i.e., the Z-axis direction, with respect to the display panel (100), and “bottom,” “bottom,” and “bottom surface” refer to the downward direction, i.e., the opposite direction of the Z-axis direction, with respect to the display panel (100). Additionally, “left,” “right,” “up,” and “down” refer to the direction when viewing the display panel (100) from a flat plane. For example, “left” refers to the opposite direction of the X-axis direction, “right” refers to the X-axis direction, “up” refers to the Y-axis direction, and “down” refers to the opposite direction of the Y-axis direction.

[0039] The display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). The display device (10) may be any one of an organic light-emitting display device, a liquid crystal display device, a plasma display device, a field emission display device, an electrophoretic display device, an electrowetting display device, a quantum dot light-emitting display device, and a micro LED display device. Although the following description focuses on the display device (10) being an organic light-emitting display device, the present invention is not limited thereto.

[0040] Referring to FIGS. 1 and FIGS. 2, a display device (10) according to one embodiment includes a display panel (100), a display driving unit (200), and a circuit board (300).

[0041] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) that intersects the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto, and may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0042] A display panel (100) may include a display area (DA) in which subpixels (PX) are formed to display an image, and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). If the display panel (100) includes a curved surface, the display area (DA) may be placed on the curved surface. In this case, the image of the display panel (100) may be visible even on the curved surface.

[0043] In the display area (DA), as well as subpixels (PX), scan lines (SL), light-emitting lines (EL), data lines (DL), and first driving voltage lines (VDDL) connected to the subpixels (PX) may be arranged. The scan lines (SL) and light-emitting lines (ECL) may be formed parallel in a first direction (X-axis direction), and the data lines (DL) may be formed parallel in a second direction (Y-axis direction) that intersects the first direction (X-axis direction). The first driving voltage lines (VDDL) may be formed parallel in the second direction (Y-axis direction) in the display area (DA). The first driving voltage lines (VDDL) formed parallel in the second direction (Y-axis direction) in the display area (DA) may be connected to each other in the non-display area (NDA).

[0044] Each subpixel (PX) may be connected to at least one of the scan lines (SL), any one of the data lines (DL), at least one of the light-emitting lines (EL), and any one of the first driving voltage lines (VDDL). In FIG. 2, for convenience of explanation, each subpixel (PX) is illustrated as being connected to two scan lines (SL), one data line (DL), one light-emitting line (EL), and the first driving voltage line (VDDL), but is not limited thereto. For example, each subpixel (PX) may be connected to three scan lines (SL) instead of two scan lines (SL).

[0045] Each of the subpixels (PX) may include a driving transistor, at least one switching transistor, a light-emitting element, and a capacitor. The driving transistor may emit light by supplying a driving current to the light-emitting element according to a data voltage applied to the gate electrode. The driving transistor and at least one transistor (T) may be thin film transistors. The light-emitting element may emit light according to the driving current of the driving transistor. The light-emitting element may be an organic light-emitting diode comprising a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may serve to maintain a constant data voltage applied to the gate electrode of the driving transistor.

[0046] The non-display area (NDA) can be defined as the area extending from the outside of the display area (DA) to the edge of the display panel (100). In the non-display area (NDA), a scan driver (410) for applying scan signals to scan lines (SL) and pads (DP) connected to data lines (DL) may be disposed. Since a circuit board (300) is attached to the pads (DP), the pads (DP) may be disposed on one side edge of the display panel (100), for example, on the lower side edge of the display panel (100).

[0047] The scan driver (410) can be connected to the display driver (200) through a plurality of first scan control wires (SCL1). The scan driver (410) can receive scan control signals from pads (DP) through a plurality of first scan control wires (SCL1). The scan driver (410) can generate scan signals according to the scan control signals and sequentially output the scan signals to the scan wires (SL). Subpixels (PX) to which data voltages are to be supplied are selected by the scan signals of the scan driver (410), and data voltages are supplied to the selected subpixels (PX).

[0048] The light emission control driver (420) can be connected to the display driving circuit (320) through a plurality of second scan control wires (SCL2). The light emission control driver (420) can receive light emission control signals from pads (DP) through a plurality of second scan control wires (SCL2). The light emission control driver (420) can generate light emission control signals according to the light emission control signals and sequentially output the light emission control signals to the light emission wires (EL).

[0049] In FIG. 2, the scan drive unit (410) is exemplified as being positioned outside one side of the display area (DA) and the light emission control drive unit (420) is exemplified as being positioned outside the other side of the display area (DA), but is not limited thereto. Both the scan drive unit (410) and the light emission control drive unit (420) may be positioned only outside one side of the display area (DA) or outside both sides of the display area (DA).

[0050] The display driver (200) receives digital video data and timing signals from the outside. The display driver (200) converts the digital video data into analog positive / negative data voltages and supplies them to the data wires (DL). The display driver (200) generates and supplies a scan control signal to control the operation timing of the scan driver (410) through the first scan control wires (SCL1). The display driver (200) generates and supplies a light emission control signal to control the operation timing of the light emission control driver (420) through the second scan control wires (SCL2). Additionally, the display driver (200) can supply a first driving voltage to the first driving voltage wire (VDDL).

[0051] The display driving unit (200) may be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF (chip on film) method. Alternatively, the display driving unit (200) may be directly attached to a display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method.

[0052] The circuit board (300) can be attached to the pads (DP) using an anisotropic conductive film. As a result, the lead wires of the circuit board (300) can be electrically connected to the pads (DP). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0053] Figure 3 is a circuit diagram showing an example of a subpixel of Figure 2.

[0054] Figure 3 illustrates a subpixel (PX) connected to the k-1 scan line (Sk-1), the k scan line (Sk), and the j data line (Dj).

[0055] Referring to FIG. 3, the subpixel (PX) can overlap with the k-1 scan line (Sk-1), the k scan line (Sk), and the j data line (Dj). Additionally, the subpixel (PX) can be connected to a first driving voltage line (VDDL) to which a first driving voltage is applied, an initialization voltage line (VIL) to which an initialization voltage is applied, and a second driving voltage line (VSSL) to which a second driving voltage lower than the first driving voltage is applied.

[0056] A subpixel (PX) includes a driving transistor, a light-emitting element (LE), switching elements, and a first capacitor (C1). For example, the subpixel (PX) may include a first transistor (T1) as the driving transistor and second to seventh transistors (T2, T3, T4, T5, T6, T7) as switching elements. However, the subpixel (PX) of this specification is not limited to that shown in FIG. 3.

[0057] The first transistor (T1) may include a first gate electrode, a first source electrode, and a first drain electrode. The first transistor (T1) controls the drain-source current (Ids, hereinafter referred to as "driving current") according to the data voltage applied to the first gate electrode. The driving current (Ids) flowing through the channel of the first transistor (T1) is proportional to the square of the difference between the voltage (Vgs) between the gate electrode and the first source electrode of the first transistor (T1) and the threshold voltage, as shown in Equation 1.

[0058]

[0059] In mathematical formula 1, k' represents a proportionality constant determined by the structure and physical characteristics of the first transistor (T1), Vgs represents the gate-source voltage of the first transistor (T1), and Vth represents the threshold voltage of the first transistor (T1).

[0060] The light-emitting element (EML) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (EML) may be proportional to the driving current (Ids). The light-emitting element (EML) may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. Alternatively, the light-emitting element (EML) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. Alternatively, the light-emitting element (EML) may be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. Alternatively, the light-emitting element (EML) may be a micro light-emitting diode.

[0061] The first electrode of the light-emitting element (EML) is connected to the second electrode of the fifth transistor (T5), and the second electrode can be connected to the second driving voltage wiring (VSSL). A parasitic capacitance (Cel) may be formed between the anode electrode and the cathode electrode of the light-emitting element (EML).

[0062] The second transistor (T2) is turned on by a scan signal of the k-th scan line (Sk) to connect the first source electrode of the first transistor (T1) to the j-th data line (Dj). The second transistor (T2) may include a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode may be connected to the k-th scan line (Sk), the second source electrode may be connected to the first source electrode of the first transistor (T1), and the second drain electrode may be connected to the data line (Dj).

[0063] The third transistor (T3) may be formed as a dual transistor comprising a third-1 transistor (T3-1) and a third-2 transistor (T3-2). The third-1 transistor (T3-1) and the third-2 transistor (T3-2) are turned on by a scan signal of the k-th scan wiring (Sk) to connect the first gate electrode and the first drain electrode of the first transistor (T1). That is, when the third-1 transistor (T3-1) and the third-2 transistor (T3-2) are turned on, the first gate electrode and the first drain electrode of the first transistor (T1) are connected, so the first transistor (T1) is driven as a diode. The third-1 transistor (T3-1) may include a third-1 gate electrode, a third-1 source electrode, and a third-1 drain electrode. The third-1 gate electrode is connected to the k-th scan wiring (Sk), the third-1 source electrode is connected to the first drain electrode of the first transistor (T1), and the third-1 drain electrode may be connected to the third-2 source electrode of the third-2 transistor (T3-2). The third-2 transistor (T3-2) may include a third-2 gate electrode, a third-2 source electrode, and a third-2 drain electrode. The third-2 gate electrode is connected to the k-th scan wiring (Sk), the third-2 source electrode is connected to the third-1 drain electrode of the third-1 transistor (T3-1), and the third-2 drain electrode may be connected to the first gate electrode of the first transistor (T1).

[0064] The fourth transistor (T4) may be formed as a dual transistor comprising a fourth-1 transistor (T4-1) and a fourth-2 transistor (T4-2). The fourth-1 transistor (T4-1) and the fourth-2 transistor (T4-2) are turned on by a scan signal of the k-1 scan line (Sk-1) to connect the first gate electrode of the first transistor (T1) with the initialization voltage line (VIL). Therefore, the first gate electrode of the first transistor (T1) can be discharged to the initialization voltage of the initialization voltage line (VIL). The fourth-1 transistor (T4-1) may include a fourth-1 gate electrode, a fourth-1 source electrode, and a fourth-1 drain electrode. The 4-1 gate electrode is connected to the k-1 scan wire (Sk-1), the 4-1 source electrode is connected to the first gate electrode of the first transistor (T1), and the 4-1 drain electrode may be connected to the 4-2 source electrode of the 4-2 transistor (T4-2). The 4-2 transistor (T4-2) may include a 4-2 gate electrode, a 4-2 source electrode, and a 4-2 drain electrode. The 4-2 gate electrode is connected to the k-1 scan wire (Sk-1), the 4-2 source electrode is connected to the 4-1 drain electrode of the 4-1 transistor (T4-1), and the 4-2 drain electrode may be connected to the initialization voltage wire (VIL).

[0065] The fifth transistor (T5) is connected between the first drain electrode of the first transistor (T1) and the anode electrode of the light-emitting element (EML). The fifth transistor (T5) is turned on by a light-emitting control signal of the k-th light-emitting wiring (Ek) to connect the first drain electrode of the first transistor (T1) and the anode electrode of the light-emitting element (EML). The fifth transistor (T5) may include a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the k-th light-emitting wiring (Ek), the fifth source electrode is connected to the first drain electrode of the first transistor (T1), and the fifth drain electrode is connected to the anode electrode of the light-emitting element (EML).

[0066] The sixth transistor (T6) is turned on by a light emission control signal of the k-th light emission wiring (Ek) to connect the first source electrode of the first transistor (T1) and the first driving voltage wiring (VDDL). The sixth transistor (T6) may include a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the k-th light emission wiring (Ek), the sixth source electrode is connected to the first driving voltage wiring (VDDL), and the sixth drain electrode is connected to the first source electrode of the first transistor (T1). When both the fifth transistor (T5) and the sixth transistor (T6) are turned on, a driving current (Ids) can be supplied to the light-emitting element (EML).

[0067] The seventh transistor (T7) is turned on by a scan signal of the k-th scan wiring (Sk) to connect the anode electrode of the light-emitting element (EML) and the initialization voltage wiring (VIL). The anode electrode of the light-emitting element (EML) can be discharged with an initialization voltage. The seventh transistor (T7) may include a seventh gate electrode, a seventh source electrode, and a seventh drain electrode. The seventh gate electrode is connected to the k-th scan wiring (Sk), the seventh source electrode is connected to the anode electrode of the light-emitting element (EML), and the seventh drain electrode is connected to the initialization voltage wiring (Vini).

[0068] A first capacitor (C1) is formed between the first drain electrode of the first transistor (T1) and the first driving voltage line (VDDL). One electrode of the first capacitor (C1) is connected to the first drain electrode of the first transistor (T1), and the other electrode can be connected to the first driving voltage line (VDDL).

[0069] The first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may each include a semiconductor layer. Some of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may include a semiconductor layer made of polycrystalline silicon, and some of the other first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may include a semiconductor layer made of oxide. For example, the semiconductor layers of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be made of polycrystalline silicon, or the semiconductor layers of the first transistor (T1), the fifth transistor (T5) to the seventh transistor (T7) among the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be made of polycrystalline silicon, and the semiconductor layers of the third transistor (T3) and the fourth transistor (T4) may be made of oxide.

[0070] FIG. 4 is a plan view showing an example of the first transistor of FIG. 3, FIG. 5 is a cross-sectional view taken along the line I-I' of FIG. 4, and FIG. 6 is an enlarged view of region A of FIG. 5.

[0071] Referring to FIGS. 4 to 6, the first transistor (T1) may include a gate electrode (111) of the first transistor (T1), a semiconductor layer of the first transistor (T1), and drain / source electrodes (141, 151) of the first transistor (T1). The semiconductor layer of the first transistor (T1) may be made of polycrystalline silicon. Hereinafter, the semiconductor layer of the first transistor (T1) will be referred to as a polycrystalline silicon film (131).

[0072] Although only the first transistor (T1) is illustrated in FIGS. 4 to 6, the description of the first transistor (T1) in FIGS. 4 to 6 can be applied as is to a transistor including a semiconductor layer made of polycrystalline silicon, within the scope where the technical concept is applied.

[0073] Referring to FIG. 4, a gate electrode (111) may be disposed on a polycrystalline silicon film (131). The gate electrode (111) may be disposed overlappingly with the polycrystalline silicon film (131) at the center of the polycrystalline silicon film (131).

[0074] A drain electrode (141) may be superimposed on the left side of the center of the polycrystalline silicon film (131). The drain electrode (141) may be electrically connected to the polycrystalline silicon film (131) through a first contact hole (CT1).

[0075] A source electrode (151) may be superimposed on the right side of the center of the polycrystalline silicon film (131). The source electrode (151) may be electrically connected to the polycrystalline silicon film (131) through a second contact hole (CT2).

[0076] The central portion of the polycrystalline silicon film (131) that overlaps with the gate electrode (111) is defined as a channel region, the region that overlaps with the drain electrode (141) of the polycrystalline silicon film (131) is defined as a drain region, and the region that overlaps with the source electrode (151) of the polycrystalline silicon film (131) can be defined as a source region. That is, the polycrystalline silicon film (131) may include a central channel region, a drain region on the left side of the channel region, and a source region on the right side of the channel region.

[0077] Referring to FIG. 5, the substrate (101) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. The substrate (101) may be made of an insulating material such as glass, quartz, or polymer resin.

[0078] A buffer film may be formed on the substrate (101). A buffer film according to one embodiment may be composed of a plurality of stacked films. For example, the buffer film may include a first buffer film (102) disposed on the substrate (101) and a second buffer film (103) on the first buffer film (102).

[0079] A first buffer layer (102) can be formed on the substrate (101) to protect the thin-film transistors and the light-emitting layer (192) from moisture and impurities (F, CH) penetrating through the substrate (101).

[0080] The first buffer film (102) may be formed from at least one inorganic film among a silicon oxide film, a silicon nitride film, a silicon oxynitride layer, a titanium oxide film, and an aluminum oxide film. For example, the first buffer film (102) may be formed by including a silicon nitride film. In some cases, the first buffer film (102) may serve to prevent heat from being released (heat sink) when manufacturing the polycrystalline silicon film (131). Meanwhile, the first buffer film (102) may serve to provide a large amount of hydrogen ions formed during manufacturing during the manufacturing of the polycrystalline silicon film (131) and / or after the manufacturing of the polycrystalline silicon film (131) is completed. A large amount of hydrogen ions provided during the manufacture of the polycrystalline silicon film (131) and / or after the manufacture of the polycrystalline silicon film (131) is completed can serve to recover internal defects of the amorphous silicon film during the manufacture of the polycrystalline silicon film (131) or to recover internal defects of the polycrystalline silicon film (131) when the manufacture of the polycrystalline silicon film (131) is completed.

[0081] The second buffer layer (103) on the first buffer layer (102) can serve to protect the thin-film transistors and the light-emitting layer (192) from moisture and impurities (F, CH) penetrating through the substrate (101), just like the first buffer layer (102).

[0082] The thickness of the second buffer film (103) may be greater than that of the first buffer film (102). For example, the thickness of the second buffer film (103) may be about 10 times or more the thickness of the first buffer film (102), but is not limited thereto.

[0083] The second buffer film (103) may be formed from at least one inorganic film among a silicon oxide film, a silicon nitride film, a silicon oxynitride layer, a titanium oxide film, and an aluminum oxide film. For example, the second buffer film (103) may be formed by including a silicon oxide film.

[0084] The second buffer film (103) can serve to prevent heat from being released (heat sink) when manufacturing the polycrystalline silicon film (131). Additionally, the second buffer film (103), like the first buffer film (102), can serve to provide a large amount of hydrogen ions formed during manufacturing during the manufacturing of the polycrystalline silicon film (131) and / or after the manufacturing of the polycrystalline silicon film (131) is completed. The large amount of hydrogen ions provided during the manufacturing of the polycrystalline silicon film (131) and / or after the manufacturing of the polycrystalline silicon film (131) is completed can serve to recover internal defects of the amorphous silicon film during the manufacturing of the polycrystalline silicon film (131) or to recover internal defects of the polycrystalline silicon film (131) upon the completion of the manufacturing of the polycrystalline silicon film (131). However, in an exemplary embodiment where the first buffer film (102) comprises a silicon nitride film and the second buffer film (103) comprises a silicon oxide film, the concentration of hydrogen ions contained within during manufacturing may be significantly higher in the first buffer film (102) than in the second buffer film (103). Accordingly, the source of the large amount of hydrogen ions provided during the manufacturing of the polycrystalline silicon film (131) and / or after the manufacturing of the polycrystalline silicon film (131) is completed may substantially be the first buffer film (102).

[0085] A polycrystalline silicon film (131) of the first transistor (T1) may be disposed on the second buffer film (103). As described above, the polycrystalline silicon film (131) may be divided into a drain region (131a), a source region (131b), and a channel region (131c).

[0086] A gate insulating film (120) may be disposed on a polycrystalline silicon film (131). The gate insulating film (120) may include an inorganic material. For example, the gate insulating film (120) may be formed from at least one inorganic film among a silicon oxide film, a silicon nitride film, a silicon oxynitride layer, a titanium oxide film, and an aluminum oxide film. In FIG. 5, the gate insulating film (120) is illustrated as being disposed across the entire front surface of the polycrystalline silicon film (131) to cover the gate insulating film (120), but is not limited thereto, and the gate insulating film (120) may be disposed only in the area where the polycrystalline silicon film (131) and the gate electrode (111) described later overlap.

[0087] The gate electrode (111) of the first transistor (T1) can be placed on the channel region (131c) of the polycrystalline silicon film (131).

[0088] The gate electrode (111) of the first transistor (T1) can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0089] A first insulating film (160) may be disposed on the gate electrode (111) of the first transistor (T1). The first insulating film (160) may be made of a glass insulating material or an inorganic insulating material.

[0090] A drain electrode (141) and a source electrode (151) may be disposed on the first insulating film (160). The drain electrode (141) may be electrically connected to the drain region (131a) of the polycrystalline silicon film (131) through the first contact hole (CT1), and the source electrode (151) may be electrically connected to the source region (131b) of the polycrystalline silicon film (131) through the second contact hole (CT2). The drain electrode (141) and the source electrode (151) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0091] A second insulating film (170) may be disposed on the source electrode (151) and the drain electrode (141). The second insulating film (170) may include a glass insulating material or an inorganic insulating material. The second insulating film (170) may be a protective film that protects the source electrode (151) and the drain electrode (141).

[0092] In FIG. 5, the first transistor (T1) is exemplified as being formed in a top gate configuration, but is not limited thereto. That is, the first transistor (T1) may be formed in a bottom gate configuration where the gate electrode (111) is located at the bottom of the polycrystalline silicon film (131), or in a double gate configuration where the gate electrode (111) is located at both the top and bottom of the polycrystalline silicon film (131).

[0093] A third insulating film (180) may be disposed on the second insulating film (170). The third insulating film (180) may include a glass insulating material or an inorganic insulating material. The third insulating film (180) may be a flattening film. The third insulating film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0094] A first electrode (191) of a light-emitting element (EML) and a pixel defining film (195) may be disposed on the third insulating film (180). The first electrode (191) may be a pixel electrode. The first electrode (191) may be electrically connected to a drain electrode (141) through a third contact hole (CT3). In a top emission structure that emits light in the direction of the second electrode (193) relative to the light-emitting layer (192), the first electrode (191) may be formed of a metallic material with high reflectivity. For example, the first electrode (191) may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). Alternatively, the first electrode (191) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al).

[0095] A pixel defining film (195) may be formed to partition the first electrode (191) on the third insulating film (180) to serve to define the light-emitting region of each sub-pixel (PX). To this end, the pixel defining film (195) may be formed to cover the edge of the first electrode (191). The light-emitting region of each sub-pixel (PX) represents a region in which the first electrode (191), the light-emitting layer (192), and the second electrode (193) are sequentially stacked so that holes from the first electrode (191) and electrons from the second electrode (193) combine with each other in the light-emitting layer (192) to emit light. The pixel defining film (195) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. In some embodiments, the pixel defining film (195) may include an inorganic material.

[0096] A light-emitting layer (192) is formed on the first electrode (191) and the pixel defining film (195). The light-emitting layer (192) may include an organic material and emit a predetermined color. For example, the light-emitting layer (192) may include a hole transporting layer, an organic material layer, and an electron transporting layer.

[0097] A second electrode (193) is formed on the light-emitting layer (192). The second electrode (193) may be formed to cover the light-emitting layer (192). The second electrode (193) may be a common layer formed in common on the subpixels (PX).

[0098] In the upper light-emitting structure, the second electrode (193) may include a transparent conductive material such as ITO or IZO, or a semi-transparent conductive material capable of transmitting light.

[0099] A sealing film (196) may be formed on the second electrode (193). The sealing film (196) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting layer (192). Additionally, the sealing film (196) may include at least one organic film to protect the light-emitting layer (192) from foreign substances such as dust. For example, the sealing film (196) may include a first inorganic sealing film (196a) on the second electrode (193), an organic sealing film (196b) on the first inorganic sealing film (196a), and a second inorganic sealing film (196c) on the organic sealing film (196b).

[0100] Alternatively, a sealing substrate may be disposed on the second electrode (193) instead of the sealing film (196), and the space between the second electrode (193) and the substrate may be empty in a vacuum state or a filling film may be disposed therein. The filling film may be an epoxy filling film or a silicone filling film.

[0101] Referring to FIG. 6, a polycrystalline silicon film (131) may be placed directly on a second buffer film (103). The second buffer film (103) may include a surface (103a) in contact with the polycrystalline silicon film (131) and a side (103b) opposite to the surface (103a), and the polycrystalline silicon film (131) may include a surface (131s1) in contact with the surface (103a) of the second buffer film (103) and a side (131s2) opposite to the surface (131s1).

[0102] As described above, the polycrystalline silicon film (131) can function as a current path, including the drain region (131a), source region (131b), and channel region (131c) of the first transistor (T1). Since current is inversely proportional to resistance, it is desirable for the polycrystalline silicon film (131) to have low internal resistance to function as a current path. If the function of the polycrystalline silicon film (131) as a current path is degraded, the transistor device characteristics described later may be reduced. Degradation of transistor device characteristics may cause a decrease in the mobility of the device and the occurrence of hysteresis in the transistor device.

[0103] The internal resistance of the polycrystalline silicon film (131) may be related to the type of main crystal inside the polycrystalline silicon film (131), the size of the crystal, and the presence of a healing medium that mitigates defects.

[0104] First, if the main crystal of the polycrystalline silicon film (131) is a first crystal having a {100} plane direction (

[0001] crystal direction), the amount of internal defects in the polycrystalline silicon film (131) is reduced, the internal resistance is lowered, and as a result, the device characteristics of the first transistor (T1) can be improved.

[0105] To explain more specifically, the main crystal of the polycrystalline silicon film (131) according to one embodiment is a first crystal having a {100} plane direction (

[0001] crystal direction), and the number of the first crystals may be about 20% or more of the total number of crystals. Furthermore, the number of the first crystals may be 70% or more of the sum of the number of the first crystals, the number of the second crystals having a {101} plane direction, and the number of the third crystals having a {111} plane direction.

[0106] Furthermore, in one embodiment, the average size of the crystals of the polycrystalline silicon film (131) may be 350 nm or larger. For example, the average size of the crystals of the polycrystalline silicon film (131) may be 396 nm or larger.

[0107] The type of main crystal and the average size of the crystal of the polycrystalline silicon film (131) according to one embodiment are related to the roughness of one surface (103a) of the second buffer film (103). That is, the smaller the roughness of one surface (103a) of the second buffer film (103), the more first crystals having a {100} plane direction with low defects become as main crystals, and the overall size of the crystals can be increased.

[0108] Hydrogen ions provided from the lower buffer membrane (102, 103) may be used as a healing medium to alleviate internal defects. Before heat treatment, the polycrystalline silicon membrane (131) contains a number of defects (broken bonds between silicon and silicon) in the amorphous silicon state, and the defects in the amorphous silicon state may remain unhealed and act as defects in the polycrystalline silicon membrane (131) even if the amorphous silicon melts after heat treatment.

[0109] Hydrogen ions provided from the lower buffer membrane (102, 103) are released from the lower buffer membrane (102, 103) when the amorphous silicon is heat-treated and enter the upper amorphous silicon to heal multiple defects (connecting broken silicon-silicon bonds). When the hydrogen ions enter the upper amorphous silicon during heat treatment and heal multiple defects, the overall size of the crystal formed thereafter is larger, and as a result, a polycrystalline silicon membrane (131) with low internal resistance can be formed.

[0110] In some cases, hydrogen ions that enter into the upper amorphous silicon can play a role in healing defects in the polycrystalline silicon (131) itself formed after heat treatment, even if they do not heal many defects during heat treatment.

[0111] That is, in terms of healing to alleviate internal defects in the amorphous silicon and / or crystalline silicon film (131) after heat treatment, it is desirable for a large amount of hydrogen ions mediating this to flow into the amorphous silicon during heat treatment. However, if the roughness of the second buffer film (103) is high, a pinhole may occur in the amorphous silicon deposited on the second buffer film (103). The pinhole can completely penetrate from one side (103a) of the second buffer film (103) of the deposited amorphous silicon to the other side opposite to said side. As a result, hydrogen ions that need to be reconnected to broken silicon-silicon bonds after flowing into the amorphous silicon during heat treatment may leak out through said pinhole.

[0112] In other words, the smaller the roughness of the second buffer film (103), the larger the crystal size of the polycrystalline silicon film (131) becomes, and the crystal direction may have the first crystal with small internal defects as the main crystal. Furthermore, the smaller the roughness of the second buffer film (103), the more the formation of pinholes inside the deposited amorphous silicon is suppressed, so that a more dense amorphous silicon is formed, and the concentration of hydrogen ions, which are defect healing mediators, increases inside the amorphous silicon and / or polycrystalline silicon during and / or after heat treatment of the amorphous silicon, thereby reducing internal defects and improving the characteristics of the first transistor (T1) device.

[0113] One side (103a) of the second buffer film (103) may have a first roughness range, one side (131s1) of the polycrystalline silicon film (131) may have a second roughness range, and the other side (131s2) of the polycrystalline silicon film (131) may have a third roughness range. The polycrystalline silicon film (131) may be placed directly on the second buffer film (103) and may conformally reflect the roughness of one side (103a) of the second buffer film (103). That is, the second roughness range of one side (131s1) of the polycrystalline silicon film (131) may be the same as the first roughness range. The third roughness range of the other side (131s2) of the polycrystalline silicon film (131) may be greater than the second roughness range of one side (131s1) of the polycrystalline silicon film (131). As illustrated in FIG. 6, the other side (131s2) of the polycrystalline silicon film (131) may include a plurality of attachments rising in an upward direction. The plurality of attachments of the other side (131s2) of the polycrystalline silicon (131) may be formed at the boundaries of the crystals of the polycrystalline silicon (131). A method for determining the first roughness range to the third roughness range will be described later.

[0114] FIG. 7 is a photograph showing a second buffer film and an amorphous silicon film according to one embodiment. FIG. 7 shows a cross-section of the second buffer film (103) and the deposited amorphous silicon film (131_1) through a transmission electron microscope (TEM).

[0115] Referring to FIG. 7, an amorphous silicon film (131_1) can be conformally deposited on one side (103a) of the second buffer film (103). It can be seen that after improving the roughness of the second buffer film (103), the amorphous silicon film (131_1) can be uniformly and well deposited on one side (103a) of the second buffer film (103). That is, by improving the roughness of the second buffer film (103), pinholes occurring inside the amorphous silicon film (131_1) can be significantly reduced.

[0116] FIG. 8 is a photograph showing the measurement of the first roughness of the second buffer film according to one embodiment. FIG. 8 only illustrates the method for determining the first roughness of the second buffer film (103), but since the method for determining the second and third roughness of the polycrystalline silicon film (131) may be the same as the method for determining the first roughness of the second buffer film (103) described below, a redundant description will be omitted.

[0117] Referring to FIG. 8, a horizontal reference line (CL) is applied in a 500 nm length (continuous section) of the second buffer film (103) using a transmission electron microscope (TEM) at an observation magnification of 30,000 or higher, and 20 points are measured at intervals of 25 nm. The standard deviation (RMS) of the measured values ​​can be determined as the first roughness of one surface (103a) of the second buffer film (103).

[0118] In one embodiment, the range of the first roughness of one surface (103a) of the second buffer film (103), determined by applying a horizontal reference line (CL) in a 500 nm region of the second buffer film (103) through a transmission electron microscope (TEM) at an observation magnification of 30,000 or higher and measuring 20 locations at 25 nm intervals, may be 1.5 nm or less.

[0119] One surface (103a) of the second buffer film (103) may have substantially the same roughness as the first roughness range over the entire area. In this specification, having substantially the same roughness should be understood as a concept that includes not only having the same roughness within the first roughness range over the entire area of ​​the one surface (103a) of the second buffer film (103), but also having a roughness level that is difficult to distinguish with the naked eye, such that the one surface (103a) of the second buffer film (103) has a variation of about 10% over the entire area.

[0120] As described above in FIG. 6, the second roughness range of one surface (131s1) of polycrystalline silicon (131) is the same as the first roughness range, so the second roughness range may be 1.5 nm or less.

[0121] One side (131s1) of the polycrystalline silicon (131) may have substantially the same roughness as the second roughness range over the entire area.

[0122] Additionally, the third roughness range of the other surface (131s2) of the polycrystalline silicon (131) may be greater than the second roughness range. Accordingly, the third roughness range of the other surface (131s2) of the polycrystalline silicon (131) may be greater than 1.5 nm, for example, 10 nm or more.

[0123] The other side (131s2) of the polycrystalline silicon (131) may have substantially the same roughness as the third roughness range over the entire area.

[0124] FIGS. 9 to 11 are graphs showing the concentration distribution of hydrogen ions within a polycrystalline silicon film, FIG. 12 is a table showing the hydrogen ion concentration area within the film and at the interface of the second buffer film, and FIG. 13 is a table showing the hydrogen ion concentration within the film and at the interface of the second buffer film. In FIGS. 9 to 11, the x-axis represents the sputtering time (SPT time(min)), the depth from the gate insulating film (120) to the second buffer film (103) in the thickness direction, and the y-axis represents the hydrogen ion concentration at that depth.

[0125] FIGS. 9 to 11 show the concentration of hydrogen ions according to depth over time, after the deposition of a polycrystalline silicon film (131) after roughness improvement (roughness of one surface (103a) of the second buffer film (103) is 1.5 nm or less) according to one embodiment and a polycrystalline silicon film before roughness improvement according to a comparative example (amorphous silicon film deposition, FIG. 9), after dehydrogenation (after hydrogen ions of the buffer film are released by the polycrystalline silicon film heat treatment process, FIG. 10), and after crystallization (Fig. 11).

[0126] In the hydrogen ion concentration graphs of FIGS. 9 to 11, a first region (R1) and a second region (R2) are defined, respectively. 50 in the direction from the center point (CP) of the amorphous silicon film or polycrystalline silicon film toward the gate insulating film (120). 50 in the direction toward the second buffer film (103) from the first point corresponding to the depth and the center point (CP) of the amorphous silicon film or polycrystalline silicon film. A second point corresponding to the depth is defined. The first region (R1) is defined as the interval from the first point to the second point.

[0127] The second region (R2) is defined as an interface region with the second buffer film of the amorphous silicon film or polycrystalline silicon film. The second region (R2) extends 100 in a direction toward the interior of the amorphous silicon film or polycrystalline silicon film from the boundary point with the second buffer film of the amorphous silicon film or polycrystalline silicon film. It is defined as the interval up to the depth point.

[0128] Referring to FIGS. 9 to 13, hydrogen ions can be distributed throughout the amorphous silicon film or polycrystalline silicon film during deposition, after dehydrogenation, and after crystallization of the polycrystalline silicon film.

[0129] According to one embodiment, the total hydrogen ion concentration in the second region (R2) of the polycrystalline silicon film (131) may be 100 times or more than the total hydrogen ion concentration in the first region (R1).

[0130] Furthermore, the concentration of hydrogen ions at the boundary point of the polycrystalline silicon film (131) according to one embodiment may be 200 times or more than the concentration of hydrogen ions at the center point (CP).

[0131] First, as shown in FIG. 9, when an amorphous silicon film is deposited on one side of the second buffer film, the total hydrogen ion concentration in the second region (R2) of the amorphous silicon according to the comparative example before buffer film roughness improvement was found to be 1.5 times greater than the total hydrogen ion concentration in the first region (R1).

[0132] According to one embodiment after improving the buffer film roughness, the total hydrogen ion concentration in the second region (R2) of the amorphous silicon was found to be twice as large as the total hydrogen ion concentration in the first region (R1).

[0133] Referring further to Fig. 13, it was confirmed that the concentration of hydrogen ions at the boundary point of the amorphous silicon film according to the comparative example before buffer film roughness improvement was 1.8 times greater than the concentration of hydrogen ions at the center point (CP).

[0134] According to one embodiment after improving the buffer film roughness, the concentration of hydrogen ions at the boundary point of the amorphous silicon film was found to be 3.9 times greater than the concentration of hydrogen ions at the center point (CP).

[0135] Through this, it can be seen that the total hydrogen ion concentration in the second region (R2) of the amorphous silicon film in one embodiment is significantly greater than the total hydrogen ion concentration in the second region (R2) of the amorphous silicon film in the comparative example. This difference can also be confirmed in the first region (R1). Furthermore, it can be seen that at specific points in each region (R1, R2), the hydrogen ion concentration of the amorphous silicon film according to one embodiment is greater than the hydrogen ion concentration of the amorphous silicon according to the comparative example (especially at the boundary point). As described above, the amorphous silicon film according to one embodiment is deposited on one side (103a) of a second buffer film (103) having a uniform first roughness of 1.5 nm or less, thereby forming a generally precise amorphous silicon, whereas the amorphous silicon film according to the comparative example is deposited on one side of the second buffer film before roughness improvement, thereby forming a number of pinholes, so the total hydrogen ion concentration in each region (R1, R2) and a specific point (center point (CP) or boundary point) can be smaller than that of the amorphous silicon film according to one embodiment.

[0136] Next, as shown in FIG. 10, when dehydrogenated during the heat treatment process of a polycrystalline silicon film, the total hydrogen ion concentration in the second region (R2) of the amorphous silicon film (or polycrystalline silicon film, or a mixture of amorphous silicon film and polycrystalline silicon film) according to the comparative example before buffer film roughness improvement was found to be 3.5 times greater than the total hydrogen ion concentration in the first region (R1).

[0137] According to one embodiment, after improving the buffer film roughness when dehydrogenated during the heat treatment process of a polycrystalline silicon film, the total hydrogen ion concentration in the second region (R2) of the amorphous silicon film (or polycrystalline silicon film, or a mixture of amorphous silicon film and polycrystalline silicon film) was found to be 11.3 times greater than the total hydrogen ion concentration in the first region (R1).

[0138] Referring further to Fig. 13, it was confirmed that the concentration of hydrogen ions at the boundary point of the amorphous silicon film (or polycrystalline silicon film, or a mixture of amorphous silicon film and polycrystalline silicon film) according to the comparative example before buffer film roughness improvement was 4.8 times greater than the concentration of hydrogen ions at the center point (CP).

[0139] According to one embodiment after improving the buffer film roughness, the concentration of hydrogen ions at the boundary point of the amorphous silicon film (or polycrystalline silicon film, or a mixture of amorphous silicon film and polycrystalline silicon film) was found to be 23.9 times greater than the concentration of hydrogen ions at the center point (CP).

[0140] Next, as shown in FIG. 11, the total hydrogen ion concentration in the second region (R2) of the polycrystalline silicon film according to the comparative example before buffer film roughness improvement after crystallization of the polycrystalline silicon film was found to be 76.5 times or more than the total hydrogen ion concentration in the first region (R1).

[0141] According to one embodiment, after crystallization of the polycrystalline silicon film and improvement of buffer film roughness, the total hydrogen ion concentration in the second region (R2) of the polycrystalline silicon film was found to be 495.6 times greater than the total hydrogen ion concentration in the first region (R1).

[0142] Referring further to Fig. 13, it was confirmed that the concentration of hydrogen ions at the boundary point of the polycrystalline silicon film according to the comparative example before buffer film roughness improvement was 180.8 times greater than the concentration of hydrogen ions at the center point (CP).

[0143] According to one embodiment after improving the buffer film roughness, the concentration of hydrogen ions at the boundary point of the polycrystalline silicon film was found to be 1238.0 times greater than the concentration of hydrogen ions at the center point (CP).

[0144] Through this, it can be confirmed that the polycrystalline silicon film according to the embodiment with improved buffer film roughness has a more precise crystal structure, so hydrogen ions are distributed in large numbers near the interface with the second buffer film, whereas the polycrystalline silicon film according to the comparative example before buffer film roughness improvement has a less precise crystal structure compared to the polycrystalline silicon film according to the embodiment, so hydrogen ions are distributed in large numbers near the center. It can be seen that the difference is more than 5 times.

[0145] Hydrogen ions distributed in large numbers near the interface with the second buffer film can perform a defect healing function at the lower part (back channel) of the polycrystalline silicon film, which is the interface with the second buffer film, thereby playing a role in making the lower part of the polycrystalline silicon film more precise.

[0146] In addition, the total hydrogen ion concentration across the entire region of the polycrystalline silicon film may be greater in the case of the polycrystalline silicon film according to one embodiment than in the case of the polycrystalline silicon film according to the comparative example. As illustrated in FIG. 11, the total hydrogen ion concentration of the polycrystalline silicon film according to the comparative example at the center (first region (R1)) and the hydrogen ion concentration at the center point (CP) are each greater than the total hydrogen ion concentration of the polycrystalline silicon film according to one embodiment and the hydrogen ion concentration at the center point (CP), respectively; however, the polycrystalline silicon film according to one embodiment has a significantly larger hydrogen ion concentration compared to the comparative example at the interface with the second buffer film, so the overall total hydrogen ion concentration may be greater than that of the comparative example. That is, since the total hydrogen ion concentration of the polycrystalline silicon film according to one embodiment is greater than that of the polycrystalline silicon film according to the comparative example, the defect healing function of hydrogen ions is performed better than that of the polycrystalline silicon film according to the comparative example, and the device characteristics of the first transistor can be improved.

[0147] FIG. 14 is a drawing for comparing a polycrystalline silicon film according to one embodiment with a polycrystalline silicon film according to a comparative example, FIG. 15 is another drawing for comparing a polycrystalline silicon film according to one embodiment with a polycrystalline silicon film according to a comparative example, and FIG. 16 is a graph showing the correlation between the crystal direction of a polycrystalline silicon film and the number of defects. The x-axis of FIG. 16 represents the ratio of the first crystal to the sum of the first crystal, the second crystal, and the third crystal, and the y-axis represents the number of defects of the polycrystalline silicon film (131) in the ratio of the first crystal.

[0148] Referring to FIGS. 14 to 16, the main crystal of the polycrystalline silicon film (131) according to one embodiment is a first crystal having a {100} plane direction (

[0001] crystal direction), and the number of the first crystals may be at least about 20% of the total number of crystals. Furthermore, the number of the first crystals may be at least 70% of the sum of the number of the first crystals, the number of the second crystals having a {101} crystal direction, and the number of the third crystals having a {111} crystal direction.

[0149] In addition, the average size of the crystals of the polycrystalline silicon film (131) according to one embodiment is about 350 nm or more, or about 370 nm or more, or about 396 nm, which is larger than the average size of the crystals of the polycrystalline silicon film according to the comparative example, and the size uniformity is also excellent.

[0150] As shown in FIG. 15, the ratio of the first crystal to the total of the polycrystalline silicon film according to the comparative example is 4.48%, the ratio of the second crystal is 16.06%, and the ratio of the third crystal is 1.43%. In contrast, it was confirmed that the ratio of the first crystal to the total of the polycrystalline silicon film (131) according to one embodiment is 21.20%, the ratio of the second crystal is 8.59%, and the ratio of the third crystal is 0.24%. That is, it can be seen that the polycrystalline silicon film (131) according to one embodiment has a larger ratio of the first crystal to the total compared to the polycrystalline silicon film according to the comparative example.

[0151] As illustrated in FIG. 16, it can be seen that as the proportion of the first crystal, second crystal, and third crystals in the polycrystalline silicon film (131) increases, the number of defects in the polycrystalline silicon film (131) decreases. In one embodiment, when the proportion of the first crystal in the group is 20%, the number of defects ranges from about 8.E+17 (spins / cm3) to about 1.E+18 (spins / cm3), whereas when the proportion of the first crystal in the group is 70%, the number of defects may range from about 2.E+17 (spins / cm3) or less. For example, when the proportion of the first crystal in the group is 70%, the number of defects may be about 1.E+17 (spins / cm3) or less.

[0152] FIG. 17 is a graph illustrating that the hysteresis of the first transistor according to one embodiment has been improved, and FIG. 18 is a graph showing an enlarged portion of FIG. 14.

[0153] FIGS. 17 and 18 compare the driving current (A) according to the driving voltage (Vg) of the first transistor (T1) of a display device (10) including a second buffer film (103) with improved roughness and a polycrystalline silicon film (131) according to one embodiment with the driving current (Id(A)) according to the driving voltage (Vg(V)) of the first transistor (T1) of a display device including a second buffer film and a polycrystalline silicon film before improvement of roughness according to a comparative example.

[0154] In this specification, the hysteresis phenomenon of the first transistor means that a difference in driving voltage (Vg(V)) occurs at the same driving current (Id(A)) between the forward behavior (behavior from turn-off to turn-on, Forward swing) of the first transistor (T1) and the reverse behavior (behavior from turn-on to turn-off, Reverse swing) of the first transistor (T1).

[0155] Referring to FIGS. 17 and 18, it can be seen that when the driving current (Id) is 1.00E-09, the driving voltage (Vg) in the positive behavior of the first transistor (T1) of the display device (10) according to one embodiment differs by 0.18V from the driving voltage (Vg) in the reverse behavior, whereas the driving voltage (Vg) in the positive behavior of the first transistor of the display device according to the comparative example differs by 0.22V from the driving voltage (Vg) in the reverse behavior. That is, it can be seen that the hysteresis phenomenon of the device is reduced in the first transistor (T1) according to one embodiment compared to the first transistor according to the comparative example.

[0156] FIG. 19 is a graph showing the correlation between the first roughness of the second buffer film and the degree of hysteresis, and FIG. 20 is a photograph showing the second buffer film of the comparative example and the polycrystalline silicon film. FIG. 20 shows the measurement of the roughness of one surface of the second buffer film using an atomic force microscope (AFM).

[0157] Referring to FIGS. 19 and 20, it can be seen that there is a correlation between the first roughness of one surface (103a) of the second buffer film (103) and the degree of hysteresis. That is, a correlation of 0.6863 (R- 2 It can be seen that the first roughness and the degree of hysteresis of one surface (103a) of the second buffer film (103) are proportional to (=0.6863).

[0158] FIG. 20 relates to a comparative example in which the first roughness of one surface of the second buffer film is about 3.7 nm (RMS) when measured by an atomic force microscope and the roughness is about 5.5 nm (RMS) when measured by a transmission electron microscope. As shown in FIG. 19, it can be seen that the degree of hysteresis of the first transistor according to the comparative example is about 0.22 V at a driving current (Id) of about 1.00E-09 A. On the other hand, in the case of the first transistor (T1) in which the first roughness of one surface (103a) of the second buffer film (103) according to one embodiment is 1.5 nm or less (transmission electron microscope measurement) and 1.9 nm or less (atomic force microscope measurement), the degree of hysteresis is about 0.18 V at a driving current (Id) of about 1.00E-09 A, which is about 0.04 V less than that of the first transistor according to the comparative example.

[0159] Hereinafter, a method for manufacturing a second buffer film (103) to form the roughness of one surface (103a) of the second buffer film (103) according to one embodiment at the level of 1.5 nm or less (transmission electron microscope measurement) and 1.9 nm or less (atomic force microscope measurement) as described above will be explained.

[0160] FIG. 21 is a schematic diagram showing the manufacturing process steps of a second buffer film according to one embodiment. FIG. 22 is a graph showing the correlation between the deposition rate of the second buffer film and the roughness of the second buffer film.

[0161] Referring to FIGS. 21 and FIGS. 22, a second buffer film (103) according to one embodiment is formed through plasma enhanced chemical vapor deposition (PECVD).

[0162] According to one embodiment, a first roughness of the second buffer film (103) at a level of 1.5 nm or less (measured by transmission electron microscopy) or 1.9 nm or less (measured by atomic force microscopy) can be formed by increasing the dissociation power of the first reaction gas and the second reaction gas that serve as the material of the second buffer film (103). For example, the first reaction gas is silane (SiH4) and the second reaction gas is nitrogen oxide (NxO), but is not limited to those exemplified. The first reaction gas and the second reaction gas react with each other to produce a product (103a).

[0163] In order to increase the dissociation power of the first reaction gas and the second reflection gas, it may be considered to lower the deposition rate of the product (103a) (or the second buffer film material, e.g., SiO2) formed by the mutual reaction of the first reaction gas and the second reaction gas. That is, lowering the deposition rate of the product reduces the proportion of incompletely dissociated structures of the first reaction gas and the second reflection gas, and allows for the formation of a large amount of dissociated structures of Si from the first reaction gas and dissociated structures of O from the second reaction gas.

[0164] As illustrated in FIG. 22, in a second buffer film forming process having a first roughness of 1.5 nm or more according to one embodiment, the product deposition rate may be 60 A / s or less, more preferably 55 A / s or less.

[0165] The deposition rate can be controlled by the flow rates of the reaction gases, the power of the plasma, and chamber pressure conditions. To form a second buffer film according to one embodiment in which the product deposition rate is 60 A / s or less, more preferably 55 A / s or less, the flow rates of the reaction gases may be reduced, the power of the plasma may be increased, or the chamber pressure may be reduced. To form a second buffer film according to one embodiment, all three conditions of controlling the reaction gas flow rate, increasing the plasma power, and reducing the chamber pressure may be considered, but at least one factor may be considered.

[0166] To explain more specifically, in some embodiments, the flow rate ratio of the first reaction gas and the second reaction gas can be set to 1:20 or higher.

[0167] In addition, in some embodiments, the plasma power can be increased to 6K or higher.

[0168] In addition, in some embodiments, the chamber pressure can be reduced to 1200 Torr or less.

[0169] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0170] 10: Display device 101: Board 102: First buffer layer 103: Second buffer layer 131: Polycrystalline silicon

Claims

Claim 1 A substrate; a polycrystalline silicon film disposed on the substrate; a gate insulating film located on the polycrystalline silicon film; A display device comprising a first buffer film disposed between the substrate and the polycrystalline silicon film and including one surface in contact with the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first RMS roughness range and the first RMS roughness range is 1.5 nm or less, the polycrystalline silicon film includes one surface in contact with the one surface of the first buffer film and another surface opposite to the one surface of the polycrystalline silicon film, the other surface of the polycrystalline silicon film is in contact with the gate insulating film, the polycrystalline silicon film contains hydrogen ions, the sum of the concentrations of the hydrogen ions near the one surface of the polycrystalline silicon film is greater than the sum of the concentrations of the hydrogen ions near the center of the polycrystalline silicon film, and the concentration of the hydrogen ions near the other surface of the polycrystalline silicon film is greater than the concentration of the hydrogen ions near the center of the polycrystalline silicon film. Claim 2 In claim 1, the first buffer film is a display device comprising a silicon oxide film. Claim 3 A display device according to claim 2, further comprising a second buffer film between the substrate and the first buffer film, wherein the second buffer film comprises a material different from the first buffer film. Claim 4 In claim 3, the second buffer film is a display device comprising a silicon nitride film. Claim 5 In claim 1, the one surface of the polycrystalline silicon film has a second RMS roughness range, and the second RMS roughness range is the same as the first RMS roughness range. Claim 6 In claim 5, the other surface of the polycrystalline silicon film has a third RMS roughness range, and the third RMS roughness range is greater than the second RMS roughness range, in a display device. Claim 7 delete Claim 8 In claim 1, the vicinity of the one surface of the polycrystalline silicon film is 100 from the one surface of the polycrystalline silicon film It is defined as a first region extending to a depth, and the vicinity of the center of the polycrystalline silicon film extends 50 to one side and to the other side, respectively, from the center point of the polycrystalline silicon film. A display device defined as a second region, which is a depth range. Claim 9 A display device according to claim 8, wherein the sum of the concentrations of hydrogen ions in the first region is 100 times or more than the sum of the concentrations of hydrogen ions in the second region. Claim 10 In claim 9, a display device configured such that the hydrogen ions of the polycrystalline silicon film are provided from the first buffer film. Claim 11 A display device according to claim 1, wherein the concentration of hydrogen ions on one surface of the polycrystalline silicon film is 200 times or more compared to the concentration of hydrogen ions at the center point of the polycrystalline silicon film. Claim 12 A display device according to claim 1, wherein the crystal of the polycrystalline silicon film has a ratio of 20% or more of a first crystal having a {100} crystal plane. Claim 13 A display device according to claim 12, wherein the first crystal of the polycrystalline silicon film is at least 70% of the sum of the first crystal, the second crystal having a {101} crystal plane, and the third crystal having a {111} crystal plane. Claim 14 A display device according to claim 13, wherein the average crystal size of the polycrystalline silicon film is 350 nm or more. Claim 15 In claim 14, a display device in which the defect of the polycrystalline silicon film is 1.E+17 (spins / cm3) or less. Claim 16 In claim 1, the first RMS roughness is calculated by measuring 20 locations at intervals of 25 nm in a length 500 nm area, and the first RMS roughness is measured using a TEM. Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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