Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device comprises: a first film having a first surface and a second surface opposite to each other; a second film having a third surface in contact with the second surface of the first film and a fourth surface opposite to the third surface; a trench having a first sub-trench extending from the fourth surface of the second film toward the first film and having a first width, and a second sub-trench disposed below the first sub-trench and having a second width smaller than the first width; a plug conductive film extending from the first surface of the first film to penetrate the bottom surface of the trench and having an upper surface disposed within the trench; a via including an insulating liner disposed between the plug conductive film and the first film; and wiring within the trench, wherein at least a portion of the upper surface of the plug conductive film and the side wall of the plug conductive film disposed within the trench are in contact with the wiring, and the upper surface of the insulating liner is exposed by the bottom surface of the second sub-trench.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] Due to the development of electronic technology, the down-scaling of semiconductor devices has recently progressed rapidly, leading to a demand for high integration and low power consumption of semiconductor chips. As the spacing between circuit components, such as wiring, is gradually decreasing, a problem is arising where the resistance between wiring and vias increases. Research is being conducted to solve the problem of increased resistance between wiring and vias in order to improve the reliability of semiconductor devices. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a semiconductor device in which a plug conductive film included in a via comes into direct contact with the wiring, thereby reducing the resistance between the via and the wiring.

[0004] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a first film having a first surface and a second surface opposite to each other; a second film having a third surface in contact with the second surface of the first film and a fourth surface opposite to the third surface; a trench having a first sub-trench extending from the fourth surface of the second film toward the first film and having a first width, and a second sub-trench disposed below the first sub-trench and having a second width smaller than the first width; a plug conductive film extending from the first surface of the first film to penetrate the bottom surface of the trench and having an uppermost surface disposed within the trench; a via including an insulating liner disposed between the plug conductive film and the first film; and wiring within the trench, wherein at least a portion of the uppermost surface of the plug conductive film and the sidewall of the plug conductive film disposed within the trench are in contact with the wiring, and the upper surface of the insulating liner is exposed by the bottom surface of the second sub-trench.

[0006] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a first film having a first surface and a second surface opposite to each other; a second film having a third surface in contact with the second surface of the first film and a fourth surface opposite to the third surface; a wiring extending from the fourth surface of the second film toward the first film and having a first portion having a first width and a second portion disposed below the first portion having a second width smaller than the first width; and a plug conductive film extending from the first surface of the first film to penetrate the bottom surface of the wiring, wherein a top surface and a portion of a side wall are in contact with the wiring, and an insulating liner disposed between the plug conductive film and the first film.

[0007] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises a substrate having a first surface and a second surface opposite to each other, an active pattern on the first surface of the substrate, a source / drain region in contact with the active pattern, a front wiring structure extending in a first direction on the first surface of the substrate and electrically connected to a source / drain region, a through-contact via electrically connected to a source / drain region on the side of the source / drain region, a buried wiring within the substrate electrically connected to the through-contact via, and a rear wiring structure electrically connected to the buried wiring on the second surface of the substrate, wherein the buried wiring includes a first portion extending from the second surface of the substrate toward the first surface and having a first width, and a second portion disposed below the first portion and having a second width smaller than the first width, and the through-contact via includes a plug conductive film penetrating the upper surface of the second portion, wherein the bottom surface and a portion of the sidewall are in contact with the buried wiring, and an insulating liner extending along the sidewall of the plug conductive film.

[0008] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0009] FIG. 1 is a drawing for illustrating a semiconductor device according to some embodiments. Figures 2 and 3 are enlarged views of part A of Figure 1. FIG. 4 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 5 is a drawing for explaining a semiconductor device according to some embodiments. Figures 6 to 10 are enlarged views of part B of Figure 5. FIG. 11 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 12 to 15 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 16 to 18 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 19 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 20 and FIGS. 23 are schematic cross-sectional views cut along AA of FIG. 19. FIG. 21 is a schematic cross-sectional view taken along BB of FIG. 19. FIG. 22 is a schematic cross-sectional view taken along CC of FIG. 19. FIGS. 24 and 25 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 26 and 27 are drawings for illustrating a semiconductor device according to some embodiments. FIG. 28 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 29 and FIGS. 30 are schematic cross-sectional views cut along DD of FIG. 28. Specific details for implementing the invention

[0010] FIG. 1 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 2 and FIG. 3 are enlarged views of part A of FIG. 1.

[0011] Referring to FIGS. 1 to 3, a semiconductor device according to some embodiments may include a first film (10), a second film (20), a via (30), and a wiring (40).

[0012] The first film (10) may include a first surface (10a) and a second surface (10b) that are opposite to each other. In some embodiments, the first film (10) may be a semiconductor substrate. For example, the first film (10) may be bulk silicon or a silicon-on-insulator (SOI). The first film (10) may be a silicon substrate or may include other materials, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. In some embodiments, the first film (10) may include an insulating material. For example, the first film (10) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0013] A second film (20) may be disposed on a second surface (10b) of a first film (10). The second film (20) may include a third surface (20a) and a fourth surface (20b) that are opposite to each other. The fourth surface (20b) of the second film (20) may be in contact with the second surface (10b) of the first film (10). The second film (20) may include an insulating material. For example, the second film (20) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0014] In the following description, the upper surface, uppermost surface, upper side, lower surface, lowermost surface, and lower part are based on the direction from the first film (10) toward the second film (20) or the direction from the via (30) toward the wiring (40), for example, the third direction (DR3). The first direction (DR1) and the second direction (DR2) may intersect each other in a direction parallel to the first surface (10a) of the first film (10). The third direction (DR3) may intersect the first and second directions (DR1, DR2).

[0015] A trench (t1) may be positioned within the second membrane (20) and the first membrane (10). The trench (t1) may extend from the fourth surface (20b) of the second membrane (20) toward the first membrane (10). The trench (t1) may penetrate the second membrane (20), and the bottom surface of the trench (t1) may be positioned within the second membrane (20). The bottom surface of the trench (t1) may be positioned below the third surface (20a) of the second membrane (20). The bottom surface of the trench (t1) may have a step.

[0016] The width of the trench (t1) in the first direction (DR1) can be reduced as it faces the first membrane (10).

[0017] In some embodiments, the trench (t1) may include a first sub-trench (t11), a second sub-trench (t12), and a third sub-trench (t13).

[0018] The first sub-trench (t11) may have a first width (W1). The second sub-trench (t12) may be positioned below the first sub-trench (t11). The second sub-trench (t12) may be formed on the bottom surface (t11bs) of the first sub-trench (t11). The second sub-trench (t12) may have a second width (W2) that is smaller than the first width (W1). The third sub-trench (t13) may be positioned below the second sub-trench (t12). The third sub-trench (t13) may be formed on the bottom surface (t12bs) of the second sub-trench (t12). The third sub-trench (t13) may have a third width (W3) that is smaller than the second width (W2). The bottom surface (t11bs) of the first sub-trench (t11) may be positioned below the third surface (20a) of the second membrane (20), the bottom surface (t12bs) of the second sub-trench (t12) may be positioned below the bottom surface (t11bs) of the first sub-trench (t11), and the bottom surface (t13bs) of the third sub-trench (t13) may be positioned below the bottom surface (t12bs) of the second sub-trench (t12). The first to third widths (W1, W2, W3) may each refer to the width in the first direction (DR1) of the bottom surfaces (t11bs, t12bs, t13bs) of the first to third sub-trenches (t11, t12, t13).

[0019] A via (30) may be placed within the first film (10). The via (30) may extend from the first surface (10a) of the first film (10) toward the second film (20). The upper surface of the via (30) may have a step.

[0020] In some embodiments, the via (30) may include an insulating liner (32), a first barrier conductive film (34), and a first plug conductive film (36).

[0021] The first plug conductive film (36) may extend from the first surface (10a) of the first film (10) to penetrate the bottom surface of the trench (t1). The first plug conductive film (36) may penetrate the bottom surface (t13bs) of the third sub-trench (t13). The upper surface (36us) of the first plug conductive film (36) may be positioned above the bottom surface (t13bs) of the third sub-trench (t13) and the bottom surface (t12bs) of the second sub-trench (t12). The upper surface (36us) of the first plug conductive film (36) and a portion of the side wall (36sw) of the first plug conductive film (36) may be positioned within the trench (t1). A portion of the upper surface (36us) of the first plug conductive film (36) and the side wall (36sw) of the first plug conductive film (36) may be exposed by a trench (t1). The upper surface (36us) of the first plug conductive film (36) may be the uppermost surface of the first plug conductive film (36).

[0022] The width of the first plug conductive film (36) in the first direction (DR1) can be reduced as it faces the second film (20).

[0023] In some embodiments, the first plug conductive film (36) may include a seam (36s) inside. The seam (36s) may extend in a third direction (DR3).

[0024] The first plug conductive film (36) may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0025] The first barrier conductive film (34) may be positioned between the first plug conductive film (36) and the insulating liner (32). The first barrier conductive film (34) may extend along at least a portion of the sidewall (36sw) of the first plug conductive film (36) from the first surface (10a) of the first film (10). The upper surface (34us) of the first barrier conductive film (34) may be positioned below the upper surface (36us) of the first plug conductive film (36) and the upper surface (32us) of the insulating liner (32). The upper surface (34us) of the first barrier conductive film (34) may be exposed by the bottom surface (t13bs) of the third sub-trench (t13).

[0026] The first barrier conductive film (34) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0027] An insulating liner (32) may be disposed between the first plug conductive film (36) and the first film (10). The insulating liner (32) may be disposed on at least a portion of the sidewall (36sw) of the first plug conductive film (36). The insulating liner (32) extends from the first surface (10a) of the first film (10), and the upper surface (32us) of the insulating liner (32) may be disposed below the upper surface (36us) of the first plug conductive film (36). The upper surface (32us) of the insulating liner (32) may be exposed by the bottom surface (t12bs) of the second sub-trench (t12).

[0028] The insulating liner (32) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof, but is not limited thereto.

[0029] The wiring (40) extends from the fourth side (20b) of the second membrane (20) toward the first membrane (10) so that the bottom surface may be placed within the first membrane (10). The wiring (40) may be placed within the trench (t1). The wiring (40) may fill at least a portion of the trench (t1). The width of the wiring (40) in the first direction (DR1) may decrease as it faces the first membrane (10).

[0030] In some embodiments, the wiring (40) may have a single conductive film structure. The wiring (40) may include a second plug conductive film (46). The second plug conductive film (46) may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0031] In some embodiments, the wiring (40) may not include an insulating liner. In some embodiments, the wiring (40) may further include an insulating liner. The insulating liner may extend along the sidewall of the second plug conductive film (46). The insulating liner may include an insulating material for electrically separating the second plug conductive film (46) from the first and second films (10, 20).

[0032] Referring to FIG. 2, in some embodiments, the wiring (40) may fill a trench (t1). Accordingly, the wiring (40) may include a first part (41), a second part (42) having a width smaller than that of the first part (41) below the first part (41), and a third part (43) having a width smaller than that of the second part (42) below the second part (42). For example, the first part (41) may have a third width (W3), the second part (42) may have a second width (W2), and the third part (43) may have a first width (W1). The lower surface of the wiring (40) may have a step.

[0033] The wiring (40) can come into contact with at least a portion of the upper surface (36us) of the first plug conductive film (36) and the side wall (36sw) of the first plug conductive film (36). The wiring (40) can come into contact with the upper surface (36us) and the side wall (36sw) of the first plug conductive film (36) exposed by the trench (t1). That is, the first plug conductive film (36) can penetrate the bottom surface of the third portion (43) of the wiring (40), and the upper portion of the first plug conductive film (36) can be placed within the wiring (40) and come into contact with the wiring (40). Accordingly, the via (30) can be electrically connected to the wiring (40).

[0034] The wiring (40) can fill the trench (t1) and come into contact with the upper surface (32us) of the insulating liner (32) and the upper surface (34us) of the first barrier conductive film (34).

[0035] Referring to FIG. 3, in some embodiments, the wiring (40) may fill a portion of the trench (t1). A void (20v) may be formed between the wiring (40) and the first barrier conductive film (34). The void (20v) may be formed when the wiring (40) does not completely fill the trench (t1) during the process of forming the wiring (40). The shape and arrangement of the void (20v) are not limited to those shown in FIG. 4 and may vary.

[0036] For example, the wiring (40) may include a first part (41) and a second part (42) having a width smaller than that of the first part (41) at the bottom of the first part (41). A void (20v) may be formed between the second part (42) of the wiring (40) and the first barrier conductive film (34).

[0037] In a semiconductor device according to some embodiments, the wiring (40) is in direct contact with the first plug conductive film (36) of the via (30), so the interface resistance can be reduced compared to the case where the wiring (40) is placed between the wiring (40) and the first plug conductive film (36) and the wiring (40) is in contact with the first barrier conductive film (34). Additionally, since the wiring (40) is in contact with the upper surface (36us) and part of the side wall (36sw) of the first plug conductive film (36), the contact area between the wiring (40) and the first plug conductive film (36) is increased, so the interface resistance can be reduced.

[0038] FIG. 4 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 3.

[0039] Referring to FIG. 4, in a semiconductor device according to some embodiments, the wiring (40) may have a multi-conducting film structure. The wiring (40) may include a second barrier conductive film (44) and a second plug conductive film (46).

[0040] The second barrier conductive film (44) may extend along the sidewall and bottom surface of the trench (t1). The second barrier conductive film (44) may extend along the bottom surface (t11bs, t12bs, t13bs) of each of the first to third sub-trenches (t11, t12, t13). The second barrier conductive film (44) may come into contact with the upper surface (32us) of the insulating liner (32) and the upper surface (34us) of the first barrier conductive film (34). For example, the second barrier conductive film (44) may fill the second sub-trench (t12) and the third sub-trench (t13) and may come into contact with the upper surface (36us) of the first plug conductive film (36). Alternatively, the upper surface (36us) of the first plug conductive film (36) may be disposed within the second plug conductive film (46), and the upper surface (36us) of the first plug conductive film (36) may be in contact with the second plug conductive film (46).

[0041] The second barrier conductive film (44) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0042] The second plug conductive film (46) can be placed on the second barrier conductive film (44). The second plug conductive film (46) can fill the trench (t1) on the second barrier conductive film (44).

[0043] FIG. 5 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 6 to 10 are enlarged views of part B of FIG. 5.

[0044] Referring to FIGS. 5 to 10, in some embodiments, the via (30) may include an insulating liner (32) and a first plug conductive film (36).

[0045] The first plug conductive film (36) may include a first part (361) and a second part (362) disposed below the first part (361). The upper surface (361us) of the first part (361) may be the uppermost surface (36us) of the first plug conductive film (36). The first part (361) may have a fourth width (W4). The fourth width (W4) may be smaller than the second width (W2). The second part (362) may have a fifth width (W5) that is smaller than the fourth width (W4). The fourth width (W4) may be the width in the first direction (DR1) of the lower surface of the first part (361), and the fifth width (W5) may be the width in the first direction (DR1) of the upper surface of the second part (362). The fourth and fifth widths (W4, W5) may each be the width in the first direction (DR1) of the first and second parts (361, 362) at the boundary between the first part (361) and the second part (362). That is, the first part (361) and the second part (362) may have a step difference at the boundary.

[0046] In some embodiments, the size of the grain in the first part (361) may differ from the size of the grain in the second part (362). The size of the grain in the first part (361) may be smaller than the size of the grain in the second part (362). This may be due to the manufacturing process of the first plug conductive film (36).

[0047] In some embodiments, the first part (361) may contain the same material as the second part (362). In some embodiments, the first part (361) may contain a different material from the second part (362).

[0048] The insulating liner (32) may extend along at least a portion of the sidewalls (361sw, 362sw) of the first plug conductive film (36). The insulating liner (32) may come into contact with the first plug conductive film (36). The insulating liner (32) may extend along at least a portion of the sidewalls (362sw) of the second portion (362).

[0049] In a semiconductor device according to some embodiments, the trench (t1) may include a first sub-trench (t11) and a second sub-trench (t12). The first portion (361) may penetrate the bottom surface (t12bs) of the second sub-trench (t12). The top surface (361us) of the first portion (361) and the side wall (361sw) of the first portion (361) may be exposed by the trench (t1). The top surface (32us) of the insulating liner (32) may be exposed by the second sub-trench (t12).

[0050] Referring to FIG. 6, in some embodiments, the wiring (40) may include a first portion (41) that fills the trench (t1) and a second portion (42) having a width smaller than that of the first portion (41) at the bottom of the first portion (41). The first plug conductive film (36) may penetrate the second portion (42).

[0051] The wiring (40) may come into contact with the upper surface (361us) of the first portion (361) of the first plug conductive film (36) and the side wall (361sw) of the first portion (361) of the first plug conductive film (36). The wiring (40) may come into contact with the upper surface (362us) of the second portion (362) of the first plug conductive film (36). The wiring (40) may come into contact with the upper surface (32us) of the insulating liner (32).

[0052] Referring to FIG. 7, in some embodiments, the wiring (40) may come into contact with the upper surface (361us) of the first part (361) and a portion of the side wall (361sw) of the first part (361). A void (40v) may be formed between the wiring (40) and the insulating liner (32). The shape and arrangement of the void (40v) are not limited to those shown in FIG. 7 and may vary.

[0053] Referring to FIGS. 8 and 9, unlike FIG. 6, in some embodiments, the bottom surface (t12bs) of the second sub-trench (t12) may be positioned below the boundary surface between the first part (361) and the second part (362). That is, a portion of the side wall (362sw) of the second part (362) may be further exposed by the trench (t1).

[0054] The wiring (40) may come into contact with the upper surface (361us) of the first part (361), the side wall (361sw) of the first part (361), the upper surface (362us) of the second part (362), and a portion of the side wall (362sw) of the second part (362). The wiring (40) may come into contact with the upper surface (32us) of the insulating liner (32).

[0055] Referring to FIG. 9, in some embodiments, a void (40v) may be formed between the wiring (40) and the insulating liner (32). The shape and arrangement of the void (40v) are not limited to those shown in FIG. 9 and may vary.

[0056] Referring to FIGS. 6 through 9, in some embodiments, the first plug conductive film (36) may not include a core inside. Referring to FIG. 10, in some embodiments, the first part (361) includes a core (361s) inside, but the second part (362) may not include a core inside.

[0057] FIG. 11 is a drawing for illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to FIG. 10.

[0058] Referring to FIG. 11, in a semiconductor device according to some embodiments, wiring (40) may have a multi-conducting film structure. Wiring (40) may include a second barrier conductive film (44) and a second plug conductive film (46). The second barrier conductive film (44) may extend along the bottom surfaces (t11bs, t12bs) of the first and second sub-trenches (t11, t12), respectively. The second barrier conductive film (44) may come into contact with the upper surface (32us) of the insulating liner (32) and the upper surface (34us) of the first barrier conductive film (34). For example, the second barrier conductive film (44) may fill the second sub-trench (t12) and come into contact with the upper surface (36us) of the first plug conductive film (36). Alternatively, the upper surface (36us) of the first plug conductive film (36) may be disposed within the second plug conductive film (46), and the upper surface (36us) of the first plug conductive film (36) may be in contact with the second plug conductive film (46).

[0059] FIGS. 12 to 15 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments.

[0060] Referring to FIG. 12, a second film (20) including a third surface (20a) and a fourth surface (20b) may be provided. A first film (10) including a first surface (10a) and a second surface (10b) may be provided on the third surface (20a) of the second film (20). The first film (10) may be placed on the third surface (20a) of the second film (20).

[0061] A trench (10t) may be formed within the first membrane (10). The trench (10t) may extend from the first surface (10a) of the first membrane (10) toward the second surface (10b) and penetrate the first membrane (10). For example, the bottom surface of the trench (10t) may be positioned within the second membrane (20).

[0062] An insulating liner (32) may be formed extending along the side wall and bottom surface of the trench (10t). On the insulating liner (32), a first barrier conductive film (34) may be formed extending along the insulating liner (32). The insulating liner (32) and the first barrier conductive film (34) may be formed conformally. A first plug conductive film (36) may be formed on the first barrier conductive film (34). The first plug conductive film (36) may fill the remaining trench (10t) after the insulating liner (32) and the first barrier conductive film (34) are formed. The first plug conductive film (36) may include a core (36s) inside.

[0063] Referring to FIG. 13, a first sub-trench (t11) may be formed within the second film (20). The first sub-trench (t11) may extend from the fourth surface (20b) of the second film (20) toward the third surface (20a). The first sub-trench (t11) may expose at least a portion of the via (30). That is, the via (30) may be shaped to penetrate the bottom surface of the first sub-trench (t11). An insulating liner (32) of the via (30) may be exposed by the first sub-trench (t11).

[0064] Alternatively, if the second film (20) is a substrate, the substrate may be removed and an insulating material applied. Accordingly, a second film (20) containing an insulating material may be formed. Subsequently, the first sub-trench (t11) described above may be formed.

[0065] Referring to FIG. 14, the insulating liner (32) exposed by the first sub-trench (t11) can be removed. The insulating liner (32) can be removed by a dry etching process or a wet etching process.

[0066] The upper surface of the insulating liner (32) may be positioned below the bottom surface of the first sub-trench (t11). Accordingly, a second sub-trench (t12) may be formed below the first sub-trench (t11). That is, the via (30) may be shaped to penetrate the bottom surface of the second sub-trench (t12). The first barrier conductive film (34) and the insulating liner (32) of the via (30) may be exposed by the first and second sub-trench (t11, t12).

[0067] Referring to FIG. 15, the first barrier conductive film (34) exposed by the first and second sub-trenches (t11, t12) can be removed. The first barrier conductive film (34) can be removed by a dry etching process or a wet etching process.

[0068] The upper surface of the first barrier conductive film (34) may be positioned below the bottom surface of the second sub-trench (t12). Accordingly, a third sub-trench (t13) may be formed below the second sub-trench (t12), and a trench (t1) including the first to third sub-trenches (t11, t12, 13) may be formed. That is, the via (30) may be shaped to penetrate the bottom surface of the third sub-trench (t13). The upper surface of the via (30) may be exposed by the trench (t1).

[0069] Next, referring to FIG. 1, wiring (40) filling the trench (t1) can be formed. The wiring (40) can be formed by a selective bottom-up metal fill method based on the first plug conductive film (36) exposed by the trench (t1). Alternatively, referring to FIG. 4, after forming the second barrier conductive film (44), the second plug conductive film (46) can be formed on the second barrier conductive film (44).

[0070] Alternatively, an insulating liner extending along the side wall and bottom surface of the trench (t1) may be formed, and then the lower surface of the insulating liner may be removed to expose the upper surface of the via (30). Subsequently, a second plug conductive film (46) or a second barrier conductive film (44) and a second plug conductive film (46) may be formed to fill the trench (t1) remaining after the insulating liner has been formed. Accordingly, wiring (40) including the insulating liner may be formed.

[0071] FIGS. 16 to 18 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. FIG. 16 is an intermediate step drawing for explaining a step after FIG. 12.

[0072] Referring to FIGS. 12 and 16, a portion of the first barrier conductive film (34) and a portion of the first plug conductive film (36) may be removed. This may be done by an etch-back process. A first portion (361) of the first plug conductive film (36) may remain.

[0073] At this time, the core (36s) inside the first plug conductive film (36) may be completely removed. Alternatively, the core (36s) inside the first part (361) may remain.

[0074] Referring to FIG. 17, a second portion (362) of the first plug conductive film (36) may be formed on a first portion (361) of the first plug conductive film (36). The second portion (362) may be formed by an optional bottom-up metal fill method based on the first portion (361). The second portion (362) may be formed without a barrier conductive film, and the grain size of the second portion (362) may be larger than the grain size of the first portion (361). Accordingly, a first plug conductive film (36) of low resistance with a larger volume, a relatively larger grain size, and no internal core may be formed compared to when a barrier conductive film is present.

[0075] Referring to FIG. 18, a first sub-trench (t11) may be formed within the second film (20). The first sub-trench (t11) may extend from the fourth surface (20b) of the second film (20) toward the third surface (20a) to expose the insulating liner (32) of the via (30).

[0076] Next, the insulating liner (32) exposed by the first sub-trench (t11) can be removed. The insulating liner (32) can be removed by a dry etching process or a wet etching process. Accordingly, a second sub-trench (t12) can be formed below the first sub-trench (t11). The upper surface of the via (30) can be exposed by the trench (t1).

[0077] Next, referring to FIG. 5, wiring (40) filling the trench (t1) can be formed. The wiring (40) can be formed by an optional bottom-up metal fill method based on the first plug conductive film (36) exposed by the trench (t1). Alternatively, referring to FIG. 11, after forming the second barrier conductive film (44), the second plug conductive film (46) can be formed on the second barrier conductive film (44).

[0078] Alternatively, an insulating liner extending along the side wall and bottom surface of the trench (t1) may be formed, and then the lower surface of the insulating liner may be removed to expose the upper surface of the via (30). Subsequently, a second plug conductive film (46) or a second barrier conductive film (44) and a second plug conductive film (46) may be formed to fill the trench (t1) remaining after the insulating liner has been formed. Accordingly, wiring (40) including the insulating liner may be formed.

[0079] FIG. 19 is a layout diagram illustrating a semiconductor device according to some embodiments. FIG. 20 and FIG. 23 are schematic cross-sectional views cut along AA of FIG. 19. FIG. 21 is a schematic cross-sectional view cut along BB of FIG. 19. FIG. 22 is a schematic cross-sectional view cut along CC of FIG. 19.

[0080] Referring to FIGS. 19 through 23, a semiconductor device according to some embodiments includes a first substrate (100), an active pattern (AP), a field insulating film (105), a gate structure (GS), a gate spacer (140), a gate capping pattern (150), a source / drain region (160), an interlayer insulating film (170), a front wiring structure (FS), a through-contact via (180), a buried wiring (190), and a back wiring structure (BS).

[0081] The first substrate (100) may be a semiconductor substrate. For example, the first substrate (100) may be bulk silicon or SOI (silicon-on-insulator).

[0082] A first substrate (100) may include a first surface (100a) and a second surface (100b) that are opposite to each other. An active pattern (AP) may be disposed on the first surface (100a) of the first substrate (100). In this specification, the first surface (100a) of the first substrate (100) on which the active pattern (AP) is disposed may also be referred to as the front side. Additionally, the second surface (100b) of the first substrate (100), which is opposite to the first surface (100a), may also be referred to as the back side.

[0083] An active pattern (AP) can be formed on a first surface (100a) of a first substrate (100). The active pattern (AP) can be extended in a second direction (DR2) parallel to the first surface (100a). Additionally, a plurality of active patterns (AP) can be extended side by side in the second direction (DR2).

[0084] In some embodiments, the active pattern (AP) may include first to third bridge patterns (111 to 113) that are stacked sequentially on the first substrate (100), spaced apart from each other, and each extend in a second direction (DR2). This active pattern (AP) may include an MBCFET comprising a multi-bridge channel. ® It can be used as a channel area. The number of bridge patterns included in the active pattern (AP) is merely exemplary and is not limited to what is illustrated.

[0085] In some embodiments, the active pattern (AP) may further include a pin pattern (110). The pin pattern (110) may protrude from a first surface (100a) of the first substrate (100) and extend in a second direction (DR2). First to third bridge patterns (111 to 113) may be stacked sequentially on the upper surface of the pin pattern (110).

[0086] A field insulating film (105) may be formed on a first surface (100a) of a first substrate (100). The field insulating film (105) may surround at least a portion of the side of an active pattern (AP). In some embodiments, the field insulating film (105) may include a concave upper surface. For example, with respect to the first surface (100a) of the first substrate (100), the height of the upper surface of the field insulating film (105) may decrease as it moves away from the pin pattern (110) and then become constant. Only the upper surface of the pin pattern (110) protruding above the top surface of the field insulating film (105) is illustrated, but this is merely illustrative. In another example, the upper surface of the pin pattern (110) may be placed in a co-plane with the top surface of the field insulating film (105).

[0087] The field insulating film (105) may include, for example, at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or a combination thereof, but is not limited thereto.

[0088] A gate structure (GS) can be formed on an active pattern (AP) and a field insulating film (105). The gate structure (GS) may intersect with the active pattern (AP). For example, the gate structure (GS) may be extended in a second direction (DR1) that is parallel to the first surface (100a) and intersects the second direction (DR2).

[0089] In some embodiments, at least a portion of the active pattern (AP) may extend in a second direction (DR2) and penetrate the gate structure (GS). For example, the first to third bridge patterns (111 to 113) may each extend in the second direction (DR2) and penetrate the gate structure (GS). The gate structure (GS) may surround the perimeter of each of the first to third bridge patterns (111 to 113).

[0090] The gate structure (GS) may include a gate dielectric film (120) and a gate electrode (130). The gate dielectric film (120) and the gate electrode (130) may be stacked sequentially on an active pattern (AP).

[0091] The gate dielectric film (120) may be laminated on the active pattern (AP). For example, the gate dielectric film (120) may extend along the top and side surfaces of the active pattern (AP) and the top surface of the field insulating film (105). Additionally, the gate dielectric film (120) may surround at least a portion of the perimeter of the active pattern (AP). For example, the gate dielectric film (120) may extend along the perimeter of each of the first to third bridge patterns (111 to 113).

[0092] The gate dielectric film (120) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0093] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate dielectric film (120) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0094] The gate electrode (130) can be laminated on the gate dielectric film (120). That is, the gate dielectric film (120) can be interposed between the active pattern (AP) and the gate electrode (130). The gate dielectric film (120) can also be interposed between the field insulating film (105) and the gate electrode (130).

[0095] Although the gate electrode (130) is illustrated as being a single film, this is merely exemplary, and it is understood that the gate electrode (130) may be formed by stacking multiple conductive layers. For example, the gate electrode (130) may include a work function control film that controls the work function and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0096] A gate spacer (140) may be formed on the first substrate (100) and the field insulating film (105). Additionally, the gate spacer (140) may extend along the side of the gate electrode (130). In some embodiments, a portion of the gate dielectric film (120) may be interposed between the gate electrode (130) and the gate spacer (140). For example, the gate dielectric film (120) may extend further along the inner side of the gate spacer (140).

[0097] The gate spacer (140) may include at least one insulating material, for example, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0098] A gate capping pattern (150) may be formed on a gate structure (GS). The gate capping pattern (150) may extend along the upper surface of the gate structure (GS). Only the upper surface of the gate capping pattern (150) is shown to be placed in a co-plane with the upper surface of the gate spacer (140), but this is merely illustrative. As another example, the gate capping pattern (150) may cover the upper surface of the gate spacer (140).

[0099] The gate capping pattern (150) may include at least one insulating material, for example, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0100] A source / drain region (160) may be formed on at least one side (e.g., both sides) of a gate structure (GS). Additionally, the source / drain region (160) may be connected to an active pattern (AP). For example, the upper surface of a pin pattern (110) may be connected to the source / drain region (160). Additionally, first to third bridge patterns (111 to 113) may each be connected to the source / drain region (160) by penetrating the gate structure (GS) and the gate spacer (140). The source / drain region (160) may be electrically isolated from the gate electrode (130) by the gate dielectric film (120) and / or the gate spacer (140). Such a source / drain region (160) may be provided as the source or drain of a field-effect transistor comprising the active pattern (AP) and the gate structure (GS).

[0101] In some embodiments, the source / drain region (160) may include an epitaxial layer. For example, the source / drain region (160) may be an epitaxial pattern formed by an epitaxial growth process.

[0102] The interlayer insulating film (170) may be formed to fill the space on the outer surface of the gate spacer (140). For example, the interlayer insulating film (170) may cover the field insulating film (105) and the source / drain region (160). The interlayer insulating film (170) may cover the upper surface of the gate spacer (140) and the upper surface of the gate capping pattern (150).

[0103] Each of the interlayer insulating films (170) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide.

[0104] A front wiring structure (FS) may be disposed on a first surface (100a) of a first substrate (100). For example, the front wiring structure (FS) may be formed on the upper surface of an interlayer insulating film (170). The front wiring structure (FS) may include a front interlayer insulating film (310), a plurality of front wiring patterns (FM1 to FM4), and a plurality of front via patterns (FV1 to FV4). The front wiring patterns (FM1 to FM4) may be stacked sequentially on the interlayer insulating film (170). The front via patterns (FV1 to FV4) may be stacked sequentially on the interlayer insulating film (170). The front via patterns (FV1 to FV4) may interconnect the front wiring patterns (FM1 to FM4). Front wiring patterns (FM1–FM4) and front via patterns (FV1–FV4) may be formed within the front wiring inter-insulating film (310). The front wiring patterns (FM1–FM4) and front via patterns (FV1–FV4) may each be mutually insulated by the front wiring inter-insulating film (310). The number of layers, number, and arrangement of the front wiring inter-insulating film (310), front wiring patterns (FM1–FM4), and front via patterns (FV1–FV4) are merely exemplary and are not limited to those depicted.

[0105] In some embodiments, the width of each front via pattern (FV1 to FV4) may decrease as it faces the first surface (100a) of the first substrate (100).

[0106] A front wiring structure (FS) can provide signal lines and / or power lines for various electronic devices (e.g., field-effect transistors including an active pattern (AP) and a gate structure (GS)) formed on a first surface (100a) of a first substrate (100). For example, a source / drain contact (CA) may be formed on a source / drain region (160). The source / drain contact (CA) may be connected to the source / drain region (160) by penetrating an interlayer insulating film (170). A first front via pattern (FV1) of the front wiring structure (FS) may be connected to the source / drain contact (CA). Through this, the front wiring structure (FS) may be electrically connected to the source / drain region (160). A silicide film (165) may be placed between the source / drain region (160) and the source / drain contact (CA).

[0107] The front wiring patterns (FM1~FM4) and front via patterns (FV1~FV4) may each include a barrier conductive film and a filling conductive film.

[0108] In some embodiments, the width of each source / drain contact (CA) may decrease as it faces the first surface (100a) of the first substrate (100).

[0109] A rear wiring structure (BS) may be disposed on a second surface (100b) of a first substrate (100). The rear wiring structure (BS) may include a rear wiring inter-insulating film (320), a plurality of rear wiring patterns (BM1 to BM3), and a plurality of rear via patterns (BV1 to BV3). The rear wiring patterns (BM1 to BM3) may be stacked sequentially on the second surface (100b) of the first substrate (100). The rear via patterns (BV1 to BV3) may be stacked sequentially on the second surface (100b) of the first substrate (100). The rear via patterns (BV1 to BV3) may interconnect the rear wiring patterns (BM1 to BM3). The rear wiring patterns (BM1 to BM3) and the rear via patterns (BV1 to BV3) may be formed within the rear wiring inter-insulating film (320). The rear wiring patterns (BM1 to BM3) and rear via patterns (BV1 to BV3) can each be mutually insulated by a rear wiring inter-insulating film (320). The number of layers, number, and arrangement of the rear wiring inter-insulating film (320), rear wiring patterns (BM1 to BM3), and rear via patterns (BV1 to BV3) are merely exemplary and are not limited to those depicted.

[0110] In some embodiments, the width of each back via pattern (BV1 to BV3) may decrease as it approaches the second surface (100b) of the first substrate (100).

[0111] In some embodiments, the back wiring structure (BS) may provide a Power Delivery Network (PDN) for various electronic devices (e.g., field-effect transistors including an active pattern (AP) and a gate structure (GS)) formed on the first surface (100a) of the first substrate (100). For example, the back wiring structure (BS) may be electrically connected to the buried wiring (190). A power voltage supplied from an external source (e.g., a source voltage (V SS ) or drain voltage (V DD)) can be delivered to the top wiring of the rear wiring structure (BS) (e.g., third rear wiring pattern (BM3)) and can be provided to the source / drain area (160) through the buried wiring (190), through contact vias (180) and source / drain contacts (CA).

[0112] In some embodiments, the buried wiring (190) may extend in a second direction (DR2) in a planar view. This buried wiring (190) may be provided as a power rail for various electronic devices (e.g., a field-effect transistor including an active pattern (AP) and a gate structure (GS)) formed on a first surface (100a) of the first substrate (100).

[0113] Although not specifically illustrated, the rear wiring patterns (BM1 to BM3) and rear via patterns (BV1 to BV3) may each include a barrier conductive film and a filling conductive film.

[0114] The through-contact via (180) can extend in a third direction (DR3) and penetrate the interlayer insulating film (170) and the field insulating film (105). The through-contact via (180) can be electrically connected to various electronic devices (e.g., a field-effect transistor including an active pattern (AP) and a gate structure (GS)) formed on the first surface (100a) of the first substrate (100).

[0115] In some embodiments, the through-contact via (180) may be electrically connected to the source / drain contact (CA). For example, the through-contact via (180) may contact the source / drain contact (CA). The through-contact via (180) may contact, for example, the upper surface of the source / drain contact (CA) in the third direction (DR3).

[0116] In some embodiments, the width of the through-contact via (180) may gradually decrease in a third direction (DR3) toward the front wiring structure (FS) toward the rear wiring structure (BS).

[0117] The buried wiring (190) may be formed within the first substrate (100). The buried wiring (190) may be connected to a through-contact via (180). For example, the upper surface of the buried wiring (190) may be connected to the lower surface of a through-contact via (180) that penetrates the first surface (100a) of the first substrate (100). Through this, the buried wiring (190) may be electrically connected to various electronic components (e.g., a field-effect transistor including an active pattern (AP) and a gate structure (GS)) formed on the first surface (100a) of the first substrate (100). For example, the buried wiring (190) may be electrically connected to a source / drain region (160).

[0118] In some embodiments, the width of the buried wiring (190) may gradually increase in a third direction (DR3) toward the second side (100b) of the first substrate (100) from the first side (100a) of the first substrate (100).

[0119] Referring to FIG. 20, the through-contact via (180) may include an insulating liner (182), a first barrier conductive film (184), and a first plug conductive film (186). The first plug conductive film (186) may include a core (186s) inside. The through-contact via (180), buried wiring (190), and the first substrate (100) may correspond to any one of the via (30), wiring (40), and second film (20) described using FIGS. 1 to 4. The insulating liner (182), the first barrier conductive film (184), and the first plug conductive film (186) may correspond to any one of the insulating liner (32), the first barrier conductive film (34), and the first plug conductive film (36) described using FIGS. 1 to 4. The via (30) and wiring (40) of FIG. 1 are shown as through-contact vias (180) and buried wiring (190) in FIG. 20, but are not limited thereto.

[0120] Referring to FIG. 23, the through-contact via (180) may include an insulating liner (182) and a first plug conductive film (186). The through-contact via (180), buried wiring (190), and first substrate (100) may correspond to any one of the via (30), wiring (40), and second film (20) described using FIGS. 5 through 11. The insulating liner (182) and the first plug conductive film (186) may correspond to any one of the insulating liner (32) and the first plug conductive film (36) described using FIGS. 1 through 4. Although the via (30) and wiring (40) of FIG. 5 are depicted as the through-contact via (180) and buried wiring (190) in FIG. 23, they are not limited thereto.

[0121] FIGS. 24 and 25 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 24 and 25 are schematic cross-sectional views cut along BB of FIG. 19.

[0122] Referring to FIG. 24, in a semiconductor device according to some embodiments, an internal spacer (145) may be further disposed on the side of the gate electrode (130). The internal spacer (145) may be formed on the side of the gate electrode (130) between the first to third bridge patterns (111 to 113). Additionally, the internal spacer (145) may be formed on the side of the gate electrode (130) between the pin pattern (110) and the first bridge pattern (111). The gate electrode (130) may be electrically isolated from the source / drain region (160) by the gate dielectric film (120), the gate spacer (140), and / or the internal spacer (145).

[0123] The internal spacer (145) may contain the same material as the gate spacer (140) or may contain a different material from the gate spacer (140).

[0124] Referring to FIG. 25, in a semiconductor device according to some embodiments, the outer wall of the source / drain region (160) may have a wave-like shape.

[0125] FIGS. 26 and 27 are drawings for illustrating a semiconductor device according to some embodiments. FIG. 26 is a schematic cross-sectional view taken along BB of FIG. 19. FIG. 27 is a schematic cross-sectional view taken along CC of FIG. 19. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 23.

[0126] Referring to FIGS. 26 and 27, in a semiconductor device according to some embodiments, the active pattern (AP) does not include a bridge pattern. The active pattern (AP) may be a pin-shaped pattern protruding above the upper surface of the field insulating film (105).

[0127] FIG. 28 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 29 and FIG. 30 are schematic cross-sectional views cut along DD of FIG. 28.

[0128] Referring to FIGS. 28 to 30, in a semiconductor device according to some embodiments, a through-contact via (180) may be electrically connected to a front wiring structure (FS). For example, the through-contact via (180) may be in contact with a front wiring pattern (FM1).

[0129] Referring to FIG. 29, the through-contact via (180) may include an insulating liner (182), a first barrier conductive film (184), and a first plug conductive film (186). The first plug conductive film (186) may include a core (186s) inside. The through-contact via (180), buried wiring (190), and the first substrate (100) may correspond to any one of the via (30), wiring (40), and second film (20) described using FIGS. 1 to 4. The insulating liner (182), the first barrier conductive film (184), and the first plug conductive film (186) may correspond to any one of the insulating liner (32), the first barrier conductive film (34), and the first plug conductive film (36) described using FIGS. 1 to 4. The via (30) and wiring (40) of FIG. 1 are shown as through-contact vias (180) and buried wiring (190) in FIG. 29, but are not limited thereto.

[0130] Referring to FIG. 30, the through-contact via (180) may include an insulating liner (182) and a first plug conductive film (186). The through-contact via (180), buried wiring (190), and first substrate (100) may correspond to any one of the via (30), wiring (40), and second film (20) described using FIGS. 5 through 11. The insulating liner (182) and the first plug conductive film (186) may correspond to any one of the insulating liner (32) and the first plug conductive film (36) described using FIGS. 1 through 4. Although the via (30) and wiring (40) of FIG. 5 are depicted as the through-contact via (180) and buried wiring (190) in FIG. 30, they are not limited thereto.

[0131] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0132] 10, 20: Acts 1 and 2 30: Via 40: Wiring 32: Insulation Liner 34, 44: 1st and 2nd barrier conductive films 36, 46: 1st and 2nd plug conductive films

Claims

Claim 1 A semiconductor device comprising: a first film including a first surface and a second surface opposite to each other; a second film including a third surface in contact with the second surface of the first film and a fourth surface opposite to the third surface; a trench including a first sub-trench having a first width extending from the fourth surface of the second film toward the first film and having a second sub-trench disposed below the first sub-trench and having a second width smaller than the first width; a via including a plug conductive film extending from the first surface of the first film to penetrate the bottom surface of the trench, with its uppermost surface disposed within the trench and an insulating liner disposed between the plug conductive film and the first film; and wiring within the trench, wherein the uppermost surface of the plug conductive film and at least a portion of the sidewall of the plug conductive film disposed within the trench are in contact with the wiring, and the upper surface of the insulating liner is exposed by the bottom surface of the second sub-trench. Claim 2 A semiconductor device according to claim 1, wherein the trench further comprises a third sub-trench disposed below the second sub-trench and having a third width smaller than the second width, the plug conductive film penetrates the bottom surface of the third sub-trench, the via further comprises a barrier conductive film between the plug conductive film and the insulating liner, and the upper surface of the barrier conductive film is exposed by the bottom surface of the third sub-trench. Claim 3 In Clause 2, the upper surface of the barrier conductive film is a semiconductor device in contact with the wiring. Claim 4 A semiconductor device according to claim 2, further comprising a void between the barrier conductive film and the wiring. Claim 5 A semiconductor device according to claim 1, wherein the plug conductive film comprises a first portion and a second portion disposed below the first portion, and at the boundary between the first portion and the second portion, the width of the first portion is smaller than the width of the second portion, and the boundary between the first portion and the second portion is disposed below the bottom surface of the first sub-trench. Claim 6 In claim 5, a semiconductor device in which the size of the grain of the first part is different from the size of the grain of the second part. Claim 7 In claim 5, the semiconductor device comprising the first part and the second part having different materials. Claim 8 In claim 5, the semiconductor device comprising the first part and the second part having the same material. Claim 9 A semiconductor device comprising: a first film including a first surface and a second surface opposite to each other; a second film including a third surface in contact with the second surface of the first film and a fourth surface opposite to the third surface; wiring extending from the fourth surface of the second film toward the first film and including a first portion having a first width and a second portion disposed below the first portion and having a second width smaller than the first width; and a via including a plug conductive film extending from the first surface of the first film to penetrate the bottom surface of the wiring, wherein the top surface and a portion of the sidewall are in contact with the wiring, and an insulating liner disposed between the plug conductive film and the first film. Claim 10 A substrate comprising a first surface and a second surface opposite to each other; an active pattern on the first surface of the substrate; a source / drain region in contact with the active pattern; a front wiring structure extending in a first direction on the first surface of the substrate and electrically connected to the source / drain region; a through-contact via electrically connected to the source / drain region on the side of the source / drain region; and a buried wiring within the substrate electrically connected to the through-contact via. A semiconductor device comprising a rear wiring structure electrically connected to the embedded wiring on the second surface of the substrate, wherein the embedded wiring includes a first portion having a first width extending from the second surface of the substrate toward the first surface and a second portion having a second width smaller than the first width disposed below the first portion and the through contact via includes a plug conductive film penetrating the upper surface of the second portion, wherein the bottom surface and a portion of the sidewall are in contact with the embedded wiring and an insulating liner extending along the sidewall of the plug conductive film.

Images