Semiconductor device and method of manufacturing the same

Abstract

A method for manufacturing a semiconductor device according to the present disclosure comprises: (A) a step of placing a first chip on a substrate; (B) a step of placing a plurality of height-bearing pieces on a substrate and around the first chip or around an area where the first chip is to be placed; (C) a step of preparing an adhesive-bearing chip having a second chip and an adhesive piece provided on one side of the second chip; and (D) a step of applying a pressure to the adhesive-bearing chip in the direction of the substrate such that at least a portion of the first chip and the height-bearing piece is embedded in the adhesive piece.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the increasing multifunctionality of electronic devices, stacked Multi-Chip Packages (MCPs) with high capacity achieved by stacking semiconductor devices in multiple layers are becoming widespread. Examples of stacked MCPs include wire-embedded and chip-embedded semiconductor packages. The adhesive film used in the manufacture of wire-embedded semiconductor packages is referred to as FOW (Film Over Wire). The adhesive film used in the manufacture of chip-embedded semiconductor packages is referred to as FOD (Film Over Die). As an example of a chip-embedded semiconductor package, an embodiment is known in which a controller chip is placed at the bottom and embedded with a film-like adhesive (see Patent Document 1). Prior art literature

[0003] Patent Document 1: Japanese Published Patent Application No. 2014-175459 The problem to be solved

[0004] However, as chip-embedded semiconductor devices become further miniaturized and thinned, and multifunctional and high-speed, there is a tendency for the area of ​​the controller chip to increase while the area of ​​the chips stacked on top of it decreases. In other words, there is a tendency for the area occupied by the controller chip relative to the stacked chips to increase. In addition, there is a tendency for the stacked chips to become further thinned. Due to these trends, the following challenges have become more pronounced.

[0005] · Remaining voids around the controller chip after compression (occurrence of voids).

[0006] · Leakage of adhesive used for embedding controller chips on the circuit board (occurrence of bleed).

[0007] · The chip placed thereon bends in the crescent direction due to insufficient removal of resin on the controller chip (occurrence of bowing). Additionally, bending in the crescent direction means that the chip bends upward convexly (see Fig. 12 (d)).

[0008] While a certain amount of voids can be eliminated by the pressure curing process after compression, there are cases where excessively large voids cannot be eliminated. Voids can cause delamination between the chip and the substrate or cracking of the package during reflow. Bleeds can contaminate surrounding wire bonding pads or the chip, leading to a decrease in wire bonding performance. Bowing can make multi-layer stacking of chips difficult or cause semiconductor devices to delaminate due to residual stress.

[0009] To address these challenges, various improvements are being made to the composition to control the fluidity of film adhesives. However, increasing the film's fluidity to reduce voids and bowing after compression tends to increase bleed. Conversely, reducing the film's fluidity to reduce bleed leads to an increase in voids and bowing. As such, voids, bowing, and bleed are in a trade-off relationship, making it difficult to resolve these issues solely through material improvements. Furthermore, regarding changes in process conditions such as compression temperature or compression load, for example, high temperature and high load compression tend to reduce voids while increasing bleed, making it difficult to simultaneously resolve the aforementioned challenges.

[0010] The present disclosure is made in consideration of the above circumstances and provides a method for manufacturing a semiconductor device using an adhesive film (FOD) for chip embedding, which can sufficiently suppress the occurrence of voids, bleeds, and bowing. Furthermore, the present disclosure provides a semiconductor device with excellent reliability in which the occurrence of voids, bleeds, and bowing during the manufacturing process is sufficiently suppressed. means of solving the problem

[0011] A method for manufacturing a semiconductor device according to one aspect of the present disclosure comprises the following process.

[0012] (A) A process of placing a first chip on a substrate.

[0013] (B) A process of placing a plurality of height plates around the first chip on a substrate or around an area where the first chip is to be placed.

[0014] (C) A process for preparing an adhesive piece attachment chip having a second chip and an adhesive piece provided on one side of the second chip.

[0015] (D) A process of applying pressure to the adhesive-attached chip in the direction of the substrate so that at least a portion of the first chip and the height-up piece is embedded in the adhesive piece.

[0016] In addition, (A), (B), and (C) may be carried out in any combination order.

[0017] The inventors examined methods to suppress the occurrence of voids, bleeds, and bowing in the manufacturing process of a semiconductor device and found that voids and bleeds occur due to bowing in the process of pressing a second chip against a first chip. FIGS. 12(a) to FIGS. 12(f) are cross-sectional views schematically illustrating a conventional process of pressing a chip against a controller chip. FIGS. 12(a) shows a state in which a substrate (10) is placed on a hot plate (H) and a controller chip (Tc) (first chip) is fixed to the substrate (10) by an adhesive piece (Ac). Then, an adhesive piece attached chip (31) (a laminate of an adhesive piece (A1) and a chip (T1) (second chip)) is placed above the controller chip (Tc), and the state is prepared for pressing. FIG. 12(b) shows a state in which the lower surface of the adhesive piece (A1) is in contact with the upper surface of the controller chip (Tc). FIG. 12(c) shows a state in which the adhesive piece (A1) has started to melt on the upper surface of the controller chip (Tc). FIG. 12(d) shows a state in which bowing has occurred on the chip (T1). FIG. 12(e) shows a state in which the edge portion of the adhesive piece (A1) is in contact with the surface of the substrate (10). FIG. 12(f) shows a state in which the thermal compression of the chip (T1) has ended. As shown in FIG. 12(f), bowing (bending in the crry direction) has occurred on the chip (T1), and voids (V) and bleeds (B) have occurred in the adhesive piece (A1). In this regard, the inventors have obtained a new discovery that, as shown in FIG. 13 (a) to FIG. 13 (c), if no bowing occurs in the chip (T1), voids and bleeds can also be suppressed.

[0018] (B) In the process, the raised piece placed on the substrate is intended to suppress the bowing of the second chip. (D) In ​​the process, the bowing of the second chip can be suppressed by applying pressure to the adhesive piece attached chip in the direction of the substrate so that the first chip and at least a portion of the raised piece are embedded in the adhesive piece (see FIG. 9). By doing so, the occurrence of voids and bleeds can also be suppressed.

[0019] (B) For the purpose of efficiently carrying out the process, a transfer film having a substrate film and a plurality of raised portions provided on the surface of the substrate film may be used. That is, the process (B) may include transferring the plurality of raised portions provided on the surface of the substrate film onto the surface of a substrate.

[0020] As described above, a certain amount of voids can be eliminated by a pressure curing process after compression. That is, if the adhesive piece is made of a thermosetting resin composition, a process of curing the adhesive piece by heating under a pressure atmosphere may be performed after process (D). By performing this process, voids can be further reduced.

[0021] According to the inventors' investigation, when the shape of the second chip in planar view is rectangular and the ratio of the length of the long side B to the length of the short side A of the rectangle B / A is 2 or more, open voids and bleeds are likely to occur due to bowing of the second chip in conventional compression methods. Since open voids do not disappear even after undergoing the pressure curing process as described above, they must be avoided. In contrast, according to the manufacturing method of the present disclosure, even if the shape of the second chip is rectangular in planar view and the ratio of the length of the long side B to the length of the short side A of the rectangle B / A is 2 or more, the bowing of the second chip is suppressed because the lower bending of the short side side of the second chip in process (D) is suppressed, and accordingly, open voids and bleeds are suppressed.

[0022] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a first chip disposed on the substrate, a plurality of height-proportioned pieces disposed around the first chip on the substrate, an adhesive piece that embeds at least a portion of the first chip and the height-proportioned pieces, and a second chip disposed to cover the first chip while adhering to the adhesive piece.

[0023] The above semiconductor device is manufactured, for example, by the above manufacturing method. Since the occurrence of voids, bleeds, and bowing during the manufacturing process is sufficiently suppressed, this semiconductor device has excellent reliability.

[0024] In the above semiconductor device, the second chip may be spaced apart from a plurality of height plates, and an adhesive (the adhesive plate) may be filled between the second chip and the plurality of height plates. Additionally, the second chip may be spaced apart from the first chip, and an adhesive (the adhesive plate) may be filled between the second chip and the first chip.

[0025] The height plate may have a multilayer structure including, for example, a dummy chip and an adhesive plate. The height plate may have a multilayer structure including a pair of surface layers made of a cured product of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers. The height plate may have a two-layer structure of a first layer and a second layer. The second layer may be, for example, an adhesive plate and may be composed of a cured product of a thermosetting resin composition. In addition, the first layer may be equivalent to the intermediate layer.

[0026] The first chip may be wire-connected to the substrate or flip-chip connected. Effects of the invention

[0027] According to the present disclosure, a method for manufacturing a semiconductor device using an adhesive film (FOD) for chip embedding is provided, wherein the occurrence of voids, bleeds, and bowing is sufficiently suppressed. Furthermore, according to the present disclosure, a semiconductor device with excellent reliability in which the occurrence of voids, bleeds, and bowing is sufficiently suppressed during the manufacturing process is provided. Brief explanation of the drawing

[0028] FIG. 1 is a cross-sectional view schematically illustrating one embodiment of a semiconductor device according to the present disclosure. FIGS. 2(a) and FIGS. 2(b) are plan views schematically illustrating examples of positional relationships between a chip and a plurality of height-reducing pieces. FIG. 3(a) is a schematic plan view showing an example of a laminated film for making a height-reducing plate, and FIG. 3(b) is a cross-sectional view along line bb of FIG. 3(a). FIG. 4 is a cross-sectional view schematically illustrating the process of laminating an adhesive layer and a laminated film shown in FIG. 3 (b). Figures 5(a) to 5(d) are cross-sectional views schematically illustrating the manufacturing process of the heightening piece. FIG. 6(a) and FIG. 6(b) are cross-sectional views schematically illustrating examples of adhesive chip attachments, respectively. Figure 7 is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor device shown in Figure 1. FIG. 8 is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor device shown in FIG. 1. FIG. 10 is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor device shown in FIG. 1. FIG. 11 is a cross-sectional view schematically showing an example of a transfer film used for arranging a raised piece on the surface of a substrate. Figures 12 (a) to 12 (f) are cross-sectional views schematically illustrating a conventional hot pressing process. FIGS. 13(a) to FIGS. 13(c) are cross-sectional views schematically showing that voids and bleeds are suppressed assuming that no bowing occurs in the chip being compressed. Specific details for implementing the invention

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In the following embodiments, the components (including steps, etc.) are not mandatory unless specifically stated otherwise. In the following description, the same or substantial parts are given the same reference numerals, and redundant descriptions are omitted. Also, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless specifically stated otherwise. The sizes of the components in each drawing are conceptual, and the dimensional ratios in the drawings are not limited to the ratios shown.

[0030] The numerical values ​​and ranges in this specification do not limit the present disclosure. In this specification, numerical ranges indicated by "~" represent a range that includes the numerical values ​​described before and after "~" as minimum and maximum values, respectively. In numerical ranges described stepwise in this specification, an upper or lower limit value described in one numerical range may be substituted with an upper or lower limit value of another numerical range described stepwise.

[0031] <First Embodiment>

[0032] [Semiconductor Device]

[0033] FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device according to the present embodiment. The semiconductor device (100) shown in this figure is, for example, a three-dimensional NAND type memory. A semiconductor device (100) comprises a substrate (10), a controller chip (Tc) (first chip) disposed on the surface of the substrate (10), a plurality of height plates (R) disposed around the controller chip (Tc) on the substrate (10), an adhesive plate (A1) that embeds the entire controller chip (Tc) and at least a portion of the height plates (R), a chip (T1) (second chip) disposed to cover the controller chip (Tc) while adhering to the adhesive plate (A1), five chips (T2, T3, T4, T5, T6) stacked on the surface of the chip (T1), wires (Wa, Wb) that electrically connect electrodes (10a, 10b) on the surface of the substrate (10) to the chips, and a sealing layer (50) that seals them. An adhesive plate (A2) is disposed between the chip (T1) and the chip (T2). An adhesive piece (A3) is placed between chips (T2) and chips (T3). An adhesive piece (A4) is placed between chips (T3) and chips (T4). An adhesive piece (A5) is placed between chips (T4) and chips (T5). An adhesive piece (A6) is placed between chips (T5) and chips (T6).

[0034] The substrate (10) may be an organic substrate or a metal substrate such as a lead frame. In order to suppress bending of the semiconductor device (100), the thickness of the substrate (10) may be, for example, 90 to 300 μm, or 90 to 210 μm.

[0035] The controller chip (Tc) is bonded to the substrate (10) by an adhesive piece (Ac) and is also electrically connected to the electrode (10a) by a wire (Wa). The shape of the controller chip (Tc) in a planar state is, for example, a square (square or rectangle). The length of one side of the controller chip (Tc) is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the controller chip (Tc) is, for example, 20 to 150 μm, and may be 30 to 100 μm. The thickness of the adhesive piece (Ac) is, for example, 5 to 40 μm, and may be 10 to 25 μm. The sum of the thickness of the controller chip (Tc) and the thickness of the adhesive piece (Ac) (distance from the upper surface of the substrate (10) to the upper surface of the controller chip (Tc)) is, for example, 25 to 190 μm, and may be 40 to 125 μm.

[0036] The height-up plate (R) is disposed around the controller chip (Tc) on the substrate (10). The height-up plate (R) serves to suppress bowing of the chip (T1) during compression of the chip (T1) (see FIG. 9). In this embodiment, the height-up plate (R) has a three-layer structure comprising a pair of surface layers (R1, R1) and an intermediate layer (R2) disposed between them. The length of one side of the height-up plate (R) in the planar state is, for example, 12 mm or less, and may be 2 to 10 mm or 3 to 8 mm.

[0037] The total thickness of the height plate (R) may be equal to the sum of the thickness of the controller chip (Tc) and the thickness of the adhesive plate (Ac), for example, 25 to 190 μm, or 40 to 125 μm or 40 to 115 μm. The ratio of the total thickness of the height plate (R) to the sum of the thickness of the controller chip (Tc) and the thickness of the adhesive plate (Ac) may be, for example, 0.8 to 1.2, or 0.9 to 1.1, or, for example, 0.5 to 1.2, or 0.8 to 1.1. By having this ratio within these ranges, a sufficiently uniform pressure can be applied to the chip (T1) during the compression process of the chip (T1) (see FIG. 9). Because of this, bowing of the chip (T1) can be suppressed, and as a result, the occurrence of voids and bleeds can also be suppressed. This ratio may be less than 1.0, 0.95 or less, or 0.90 or less. Since the height plate (R) is relatively thin, bleeding of the adhesive plate (A1) onto the surface of the height plate (R) can be suppressed. The adhesive plate (A1) protruding onto the surface of the height plate (R) may contaminate the wire bonding pad (not shown) of the chip (T1) during a subsequent process, which may cause a decrease in the reliability of the wire bonding.

[0038] The thickness of the surface layer (R1) may be, for example, 5 to 40 μm or 5 to 50 μm, or 5 to 25 μm or 5 to 20 μm. The thicknesses of the two surface layers (R1, R1) may be the same or different. The surface layer (R1) is made of a thermosetting resin composition. The thermosetting resin composition can go through a semi-cured (B-stage) state and then become a fully cured (C-stage) state through a subsequent curing treatment. The thermosetting resin composition includes an epoxy resin, a curing agent, and an elastomer (e.g., acrylic resin), and, if necessary, further includes an inorganic filler and a curing accelerator. The compositions of the two surface layers (R1, R1) may be the same or different.

[0039] The thickness of the intermediate layer (R2) is, for example, 5 to 75 μm or 5 to 90 μm, and may be 10 to 75 μm or 10 to 50 μm. It is preferable that the intermediate layer (R2) be made of a material having sufficiently high mechanical strength. Specific examples of the material include resins such as polyimide and polyethylene terephthalate (PET), and metals such as copper and aluminum. The tensile modulus of the material constituting the intermediate layer (R2) is, for example, 8.0 MPa or higher, and may be 9.0 MPa or higher or 10.0 MPa or higher. In addition, when the intermediate layer (R2) is made of a resin material, the intermediate layer (R2) is made of a material different from the resin material constituting the surface layer (R1). By having multiple layers made of different materials, the function can be distributed among each layer, thereby enabling the high functionality of the intermediate layer compared to a structure made of multiple layers of the same material.

[0040] As shown in FIG. 2(a), in the plan view, two height plates (R) (shape: rectangular) may be placed at positions corresponding to the short side of the chip (T1), and as shown in FIG. 2(b), in the plan view, one height plate (R) (shape: square, a total of four) may be placed at positions corresponding to the corners of the chip (T1). From the perspective of bleed suppression, it is preferable that the entirety of the multiple height plates (R) is not covered by the chip (T1); that is, in the plan view, it is preferable that a part of each height plate (R) is positioned to protrude outward from the chip (T1). It is preferable that the four corners of the chip (T1) cover at least a part of each height plate (R) in good balance. With this configuration, both bowing and bleed can be further sufficiently suppressed.

[0041] (Method for producing honorifics)

[0042] An example of a method for manufacturing a height-reducing plate (R) is described. Additionally, the surface layer (R1) shown in FIG. 1 is after the thermosetting resin composition constituting it has cured. Meanwhile, the surface layer (S1) and the surface layer (P1) obtained by fragmenting it are in a state before the thermosetting resin composition contained therein has completely cured (see FIG. 3(b) and FIG. 5(b)).

[0043] First, a laminated film (20) as shown in FIGS. 3(a) and FIGS. 3(b) is prepared. The laminated film (20) comprises a base film (1), an adhesive layer (2), and a three-layer film (15F). The base film (1) is, for example, a polyethylene terephthalate film (PET film). The adhesive layer (2) is formed into a circular shape by punching, etc. (see FIGS. 3(a)). The adhesive layer (2) is, for example, made of an ultraviolet-curing adhesive. This adhesive layer (2) has the property that its adhesiveness decreases when irradiated with ultraviolet light. The three-layer film (15F) is formed into a circular shape by punching, etc. and has a diameter smaller than that of the adhesive layer (2) (see FIGS. 3(a)).

[0044] The three-layer film (15F) is composed of a pair of surface layers (S1, S1) made of a thermosetting resin layer and an intermediate layer (M) sandwiched between them. The thickness of the surface layer (S1) is substantially the same as the surface layer (R1) described above, and may be, for example, 5 to 40 μm, 5 to 25 μm, or 5 to 20 μm. The thickness of the intermediate layer (M) is the same as the intermediate layer (R2) described above, and may be, for example, 5 to 75 μm, 10 to 75 μm, or 10 to 50 μm. The tensile modulus of the intermediate layer (M) is, for example, 8.0 MPa or more, and may be 9.0 MPa or more or 10.0 MPa or more. Since the tensile modulus of the intermediate layer (M) is 8.0 MPa or higher, in the process of picking up the height plate (R) (see Fig. 5 (d)), the intermediate layer (R2) acts like a spring plate, thereby achieving excellent pickup performance. In addition, the upper limit of the tensile modulus of the intermediate layer (M) is approximately 15 MPa in terms of material availability. Examples of materials constituting the intermediate layer (M) include polyimide and polyethylene terephthalate (PET). The intermediate layer (M) may also be a layer made of a thermosetting resin composition or a photocurable resin composition that has undergone curing treatment to achieve a tensile modulus within the above range.

[0045] A laminated film (20) can be manufactured, for example, by laminating a first laminated film having a base film (1) and an adhesive layer (2) on its surface, and a second laminated film having a cover film (3) and a three-layer film (15F) on its surface (see FIG. 4). The first laminated film is obtained by a process of forming an adhesive layer on the surface of the base film (1) by coating, and a process of processing the adhesive layer into a predetermined shape (e.g., a circle) by punching, etc. The second laminated film is obtained by a process of forming a surface layer (S1) on the surface of the cover film (3) (e.g., a PET film or a polyethylene film) by coating, a process of forming an intermediate layer (M) on the surface of the surface layer (S1), a process of forming a surface layer (S1) on the surface of the intermediate layer (M) by coating, and a process of processing the adhesive film formed through these processes into a predetermined shape (e.g., a circle) by punching, etc. When using the laminated film (20), the cover film (3) is peeled off at an appropriate timing.

[0046] As shown in FIG. 5(a), a dicing ring (DR) is attached to a laminated film (20). That is, the dicing ring (DR) is attached to the adhesive layer (2) of the laminated film (20), and a three-layer film (15F) is placed inside the dicing ring (DR). The three-layer film (15F) is reorganized by dicing (see FIG. 5(b)). In this way, a plurality of raised pieces (R) are obtained from the three-layer film (15F). Afterward, for example, the adhesive layer (2) is irradiated with ultraviolet light to reduce the adhesive force between the adhesive layer (2) and the raised pieces (R). After irradiation with ultraviolet light, as shown in FIG. 5(c), tension is applied to the base film (1) by pushing up the inner region of the dicing ring (DR) in the base film (1) with a ring (Ra), thereby separating the raised pieces (R) from each other.

[0047] Next, as shown in FIG. 5 (d), the height piece (R) is peeled off from the adhesive layer (2) by pushing it up with a pushing jig (42), and the height piece (R) is picked up by suctioning with a suction collet (44). Additionally, the curing reaction of the thermosetting resin may be carried out by heating the three-layer film (15F) before dicing or the height piece (R) before pickup. Excellent pickup performance can be achieved by ensuring that the height piece (R) is properly cured at the time of pickup. It is preferable that the cut for the re-cut be formed up to the outer edge of the height piece (R). The diameter of the three-layer film (15F) may be, for example, 300 to 310 mm or 300 to 305 mm. The shape of the three-layer film (15F) in the planar view is not limited to the circular shape shown in Fig. 3 (a), but may be square (square or rectangle).

[0048] In addition, although a three-layer structure of the height plate (R) is exemplified here, the height plate may be a two-layer structure in which one of the two surface layers (R1, R1) is missing. For example, the height plate may be a two-layer structure comprising a first layer in contact with the surface of the substrate (10) and a second layer provided on the surface of the first layer. The first layer corresponds to the surface layer (R1) described above, and its material and physical properties may be the same as those of the surface layer (R1). The second layer corresponds to the intermediate layer (R2) described above, and its material and physical properties may be the same as those of the intermediate layer (R2). The thickness of the two-layer structure of the height plate is, for example, 25 to 190 μm, and may be 40 to 125 μm or 40 to 115 μm. In addition, the height plate (R) may be a laminate of a dummy chip (first layer) and an adhesive plate (second layer) provided on one side of the dummy chip. The height plate of this configuration can be manufactured through a dicing process and a pickup process.

[0049] The chip (T1) is, for example, a memory chip. In a planar view, the chip (T1) has a larger area than the controller chip (Tc). The chip (T1) is placed on the substrate (10) via an adhesive piece (A1) so as to cover the entire controller chip (Tc). In a planar view, the shape of the chip (T1) is, for example, a square (square or rectangle). The length of one side of the chip (T1) is, for example, 12 mm or less, and may be 6 to 10 mm or 2 to 4 mm. When the shape of the chip is rectangular, the ratio B / A of the length of the long side B to the length of the short side A is, for example, 1.5 to 4, and may be 1.8 to 3.5 or 2.1 to 3.2. The thickness of the chip (T1) is, for example, 10 to 170 μm, and may be 10 to 30 μm. These chips have a complex circuit layer (upper side in FIG. 1) and a relatively thin semiconductor layer (lower side in FIG. 1). As the ratio of the thickness of the semiconductor layer to the total thickness of the chip decreases, the chip becomes prone to bending in the smile direction. For example, if this ratio is 80% or less, bending in the smile direction is prone to occur. Bending in the smile direction means that the chip bends so that it becomes convex downward.

[0050] The size of the chip (T1) and the adhesive piece (A1) in a planar view is substantially the same (see FIG. 6(a)). The adhesive piece attached chip (31) shown in FIG. 6(a) is a laminate of the adhesive piece (A1) (before curing) and the chip (T1). The adhesive piece attached chip (31) can be obtained by reorganizing the laminate of the adhesive film (FOD) for chip embedding and the semiconductor wafer.

[0051] As shown in FIG. 1, the chip (T1) is separated from a plurality of height plates (R) in the thickness direction of the semiconductor device (100). In addition, the chip (T1) is also separated from the controller chip (Tc) in the thickness direction of the semiconductor device (100). With this configuration, the occurrence of bowing of the chip (T1) can be suppressed, and the distance from the upper surface of the controller chip (Tc) to the lower surface of the chip (T1) can be sufficiently secured. Furthermore, an adhesive plate (A1) is filled between the chip (T1) and the plurality of height plates (R). An adhesive plate (A1) is also filled between the chip (T1) and the controller chip (Tc).

[0052] The chips (T2, T3, T4, T5, T6) are, for example, memory chips, just like the chip (T1). The shape, size, and thickness of the chips (T2, T3, T4, T5, T6) in planar form may be the same as those of the chip (T1). The size of the chip (T2) and the adhesive piece (A2) in planar form is substantially the same (see FIG. 6(b)). The adhesive piece attached chip (32) shown in FIG. 6(b) is a laminate of the adhesive piece (A2) (before curing) and the chip (T2). The adhesive piece attached chip (32) can be obtained by reorganizing the laminate of the die bonding film and the semiconductor wafer. This die bonding film may be thinner than the adhesive film (FOD) for chip embedding described above. By dicing, in addition to the adhesive piece attached chip (32), adhesive piece attached chips (33, 34, 35, 36) each containing chips (T3, T4, T5, T6) are also obtained.

[0053] Method for manufacturing a semiconductor device

[0054] The semiconductor device (100) is manufactured through the following process.

[0055] (A) A process of placing a controller chip (Tc) on a substrate (10) (see FIG. 7).

[0056] (B) A process of arranging a plurality of height plates (R) around a controller chip (Tc) on a substrate (10) (see FIG. 8).

[0057] In addition, process (A) may be performed first, followed by process (B), or process (B) may be performed first, followed by process (A). When process (A) is performed after process (B) has been performed first, in process (B), a plurality of height plates (R) may be placed around the area on the substrate (10) where the controller chip (Tc) is to be placed.

[0058] (C) A process for preparing an adhesive chip (31) (see (a) in FIG. 6). Process (C) may be performed at any timing prior to process (D).

[0059] (D) A process of applying pressure to the adhesive piece attachment chip (31) in the direction of the substrate (10) so that the entire controller chip (Tc) and a part of each height piece (R) are embedded in the adhesive piece (A1) (see FIG. 9).

[0060] (D) The process may be carried out, for example, on a hot plate. The temperature conditions for hot pressing are, for example, 80 to 150°C, and may be 90 to 130°C. The pressing pressure for hot pressing is, for example, 0.05 to 0.5 MPa, and may be 0.1 to 0.3 MPa.

[0061] (E) A process of sequentially stacking a plurality of adhesive-attached chips (32~36) on the surface of a chip (T1) (see FIG. 10).

[0062] (F) A process of sealing chips and wires, etc. on the surface of a substrate (10) with a sealant.

[0063] (D) In ​​the process, when applying pressure to the adhesive-attached chip (31) in the direction of the substrate (10), a plurality of raised pieces (R) are present around the controller chip, thereby maintaining the flat shape of the chip (T1) and suppressing the occurrence of bowing. That is, by compressing the chip (T1) so that the entire controller chip (Tc) and parts of each raised piece (R) placed at positions corresponding to the periphery of the chip (T1) are embedded in the adhesive piece (A1), a sufficiently uniform pressure is applied to the chip (T1) (see FIG. 9). Because of this, bowing of the chip (T1) can be suppressed, and as a result, the occurrence of voids and bleeds can also be suppressed.

[0064] Although embodiments of the present disclosure have been described above, the present invention is not limited to the above embodiments. For example, in the above embodiments, an embodiment in which a controller chip (Tc) is connected to a substrate (10) by a wire (Wa) has been illustrated, but the controller chip (Tc) may be flip-chip connected to the substrate (10). Also, in the above embodiments, a three-dimensional NAND type memory in which a controller chip is embedded has been illustrated, but the above embodiments may be applied to semiconductor devices in other forms in which other chips are embedded.

[0065] In the above embodiment, although the case in which a raised piece (R) is manufactured through a dicing process and a pickup process has been exemplified, a raised piece may also be placed on a substrate (10) using a transfer film. FIG. 11 is a cross-sectional view schematically showing an example of a transfer film. The transfer film (60) shown in FIG. 11 comprises a base film (61) and a plurality of raised pieces (R) provided on the surface of the base film (61). T Provides ). Raising piece (R T ) is, for example, composed of a thermosetting resin composition. By preparing such a transfer film (60) in advance, for example, a plurality of raised pieces (R) are collectively placed on the surface of a substrate (10) by means of a heat press. T It is possible to place ).

[0066] Industrial applicability

[0067] According to the present disclosure, a method for manufacturing a semiconductor device using an adhesive film (FOD) for chip embedding is provided, wherein the occurrence of voids, bleeds, and bowing is sufficiently suppressed. Furthermore, according to the present disclosure, a semiconductor device with excellent reliability in which the occurrence of voids, bleeds, and bowing is sufficiently suppressed during the manufacturing process is provided. Explanation of the symbols

[0068] 1… Recording film 2… adhesive layer 3… Cover film 10… circuit board 10a… electrode 10b… electrode 15F… 3-layer film 20… laminated film 31, 32, 33, 34, 35, 36… adhesive piece attachment chip 50… sealing layer 60… Transfer film 61… recording film 100… semiconductor device A1, A2, A3, A4, A5, A6, Ac… adhesive pieces DR… Dicing Ring P1, R1, S1… surface layer R, R T… Honorifics M, R2… middle layer T1… chip (second chip) T2, T3, T4, T5, T6… chips Tc… controller chip (1st chip) Wa, Wb… wire

Claims

Claim 1 (A) a process of placing a first chip on a substrate; (B) a process of placing a plurality of height-bearing pieces on the substrate and around the first chip or around an area where the first chip is to be placed; (C) a process of preparing an adhesive-bearing chip having a second chip and an adhesive piece provided on one side of the second chip; and (D) a process of applying pressure to the adhesive-bearing chip in the direction of the substrate so that at least a portion of the first chip and the height-bearing piece is embedded in the adhesive piece. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein (B) the process comprises transferring the plurality of raised pieces provided on the surface of a substrate film onto the surface of the substrate. Claim 3 A method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the adhesive piece is made of a thermosetting resin composition, and further comprising a process of curing the adhesive piece by heating under a pressurized atmosphere after process D. Claim 4 A method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein, in a planar view, the shape of the second chip is rectangular and the ratio of the length of the long side B to the length of the short side A, B / A, is 2 or more. Claim 5 A semiconductor device comprising a substrate, a first chip disposed on the substrate, a plurality of height plates disposed on the substrate and around the first chip, an adhesive plate that embeds at least a portion of the first chip and the height plates, and a second chip disposed to cover the first chip while adhering to the adhesive plate, wherein the height plates have a multilayer structure comprising a pair of surface layers made of a cured material of a thermosetting resin composition and an intermediate layer disposed between the pair of surface layers. Claim 6 A semiconductor device according to claim 5, wherein the second chip is spaced apart from the plurality of height plates, and the adhesive plate is filled between the second chip and the plurality of height plates. Claim 7 A semiconductor device according to claim 5 or claim 6, wherein the second chip is separated from the first chip, and the adhesive piece is filled between the second chip and the first chip. Claim 8 A semiconductor device according to claim 5 or claim 6, wherein the height portion has a multilayer structure comprising a dummy chip and an adhesive portion. Claim 9 delete Claim 10 A semiconductor device according to claim 5 or claim 6, wherein the first chip is flip-chip connected to the substrate.

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