Display device

Abstract

The embodiments relate to a display device comprising: a display panel on which pixels are arranged; a gate driving circuit composed of a stage circuit that outputs a gate signal to the pixels according to the voltages of a Q node and a QB node; a monitoring transistor connected to at least one of the Q node and the QB node of the stage circuit; a power control unit that generates a compensation value according to a monitoring voltage output from the monitoring transistor and provides a compensated driving voltage according to the compensation value to the gate driving circuit; and a timing controller that detects an abnormal state of the monitoring transistor and controls the output of the compensation value.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The display device includes a data driving circuit that supplies data signals to data lines of a pixel array, a gate driving circuit (or scan driving circuit) that sequentially supplies gate pulses (or scan pulses) synchronized with the data signals to the gate lines (or scan lines) of the pixel array, and a timing controller that controls the data driving circuit and the gate driving circuit. Each pixel may include a thin film transistor (TFT) that supplies voltage of a data line to a pixel electrode in response to a gate pulse.

[0003] The gate driving circuit includes a plurality of dependently connected stages. Each stage includes a Q node that charges the gate line, a QB node that discharges the gate line, and a control circuit that controls the voltages of the Q node and the QB node. The control circuit includes transistors. The device characteristics of these transistors can be degraded by DC gate bias stress, which can be a factor in the degradation of the gate driving circuit.

[0004] To detect degradation of the gate driving circuit, a method of detecting and compensating the voltage of the QB node using a dummy stage may be utilized. However, the dummy stage also contains thin-film transistors, which may degrade or experience defects such as short circuits. In this case, the degree of degradation of the gate driving circuit may be detected more significantly by the dummy stage, and a driving voltage higher than required for the gate driving circuit may be applied. This is problematic because it can further accelerate the degradation of the gate driving circuit and increase unnecessary power consumption. The problem to be solved

[0005] The embodiments provide a display device capable of detecting deterioration of a gate driving circuit.

[0006] The embodiments provide a display device that determines whether there is abnormal deterioration of the circuit element itself, which detects deterioration of the gate driving circuit. means of solving the problem

[0007] A display device according to one embodiment may include a display panel on which a pixel is arranged, a gate driving circuit composed of a stage circuit that outputs a gate signal to the pixel according to the voltage of a Q node and a QB node, a monitoring transistor connected to at least one of the Q node and the QB node of the stage circuit, a power control unit that generates a compensation value according to a monitoring voltage output from the monitoring transistor and provides a driving voltage compensated according to the compensation value to the gate driving circuit, and a timing controller that detects an abnormal state of the monitoring transistor and controls the output of the compensation value.

[0008] A monitoring unit that outputs an enable signal to the timing controller when the above compensation value increases above a predetermined level may be further included.

[0009] The above power control unit may include a first power conversion unit that converts an external voltage to output a driving voltage and a power compensation unit that outputs a compensation value based on the monitoring voltage.

[0010] The monitoring unit may include a switching transistor, one end of which is connected to a preset reference voltage and the other end of which is connected to the timing controller, and the gate electrode of which is connected to the output terminal of the power compensation unit.

[0011] The switching transistor above can be turned on as the gate-on voltage of the compensation value output from the power compensation unit increases, and output the predetermined voltage as the enable signal to the timing controller.

[0012] The power control unit further includes a second power converter that outputs a driving voltage of a preset level indicated by the timing controller, and the timing controller can block the output of the compensation value in response to the enable signal and control the second power control unit to output the driving voltage of the preset level.

[0013] The above preset level of driving voltage can be determined based on the total amount of data voltage applied to the display panel.

[0014] The above preset driving voltage level can be preset to different values ​​corresponding to one or more intervals for the total amount of the data voltage.

[0015] The timing controller can output digital data indicating the preset level of the driving voltage to the second power converter based on a look-up table that defines the preset level of the driving voltage corresponding to the total amount of the data voltage.

[0016] The power compensation unit may include an operational amplifier connected to one electrode of the monitoring transistor to receive the monitoring voltage and output the compensation value based on the difference between the monitoring voltage and the reference voltage.

[0017] The timing controller further includes a first switch connected to the output terminal of the operational amplifier and a second switch selectively connected to either the output terminal of the first power converter or the output terminal of the second power converter, wherein when the preset level of driving voltage is output, the first switch is turned off and the second switch is connected to the output terminal of the second power converter.

[0018] The monitoring transistor is placed on a display panel, and its gate electrode can be connected to at least one of the Q node and the QB node.

[0019] The above stage circuit may include a buffer circuit that outputs the gate signal, including a pull-up transistor connected to the Q node and a pull-down transistor connected to the QB node, and a control circuit that controls the voltages of the Q node and the QB node based on a driving voltage compensated according to the compensation value.

[0020] The monitoring transistor is a transistor with the same characteristics as the pull-up transistor or the pull-down transistor, and can degrade in the same way as the pull-up transistor or the pull-down transistor.

[0021] A display device according to one embodiment may include a gate driving circuit that outputs a gate signal, a monitoring transistor that detects degradation of the gate driving circuit, a power control unit that generates a compensation value in response to degradation detected by the monitoring transistor and provides a compensated driving voltage to the gate driving circuit according to the compensation value, a monitoring unit that detects an abnormal state of the monitoring transistor based on the compensation value, and a timing controller that blocks the output of the compensation value and provides a driving voltage of a preset level to the gate driving circuit when the monitoring transistor is determined to be in an abnormal state by the monitoring unit.

[0022] The above preset level of driving voltage can be determined based on the total amount of data voltage applied to the display panel.

[0023] The above preset driving voltage level can be preset to different values ​​corresponding to one or more intervals for the total amount of the data voltage. Effects of the invention

[0024] The display device according to the embodiments determines whether there is abnormal deterioration of the circuit element itself that detects the deterioration of the gate driving circuit, thereby allowing an appropriate driving voltage to be applied to the gate driving circuit.

[0025] In addition, the display device according to the embodiments can prevent unnecessary degradation and power consumption of the gate driving circuit, thereby enabling the implementation of a low-power display device. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment. FIG. 2 is an example diagram illustrating the implementation of a display device according to one embodiment. FIG. 3 is a schematic diagram showing the configuration of a gate driving circuit according to one embodiment. Figure 4 is a schematic diagram showing the stage circuit of Figure 3. FIG. 5 is a diagram showing the configuration of a power control unit according to one embodiment. Figures 6 and 7 are diagrams illustrating the connection relationship between the monitoring transistor and the power compensation unit. FIG. 8 is a diagram showing the connection relationships of some components of a display device equipped with a monitoring unit. FIG. 9 is a diagram showing the configuration of a power conversion unit according to one embodiment. Specific details for implementing the invention

[0027] Hereinafter, embodiments are described with reference to the drawings. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "joined" to another component, it means that it may be directly connected / joined to the other component or that a third component may be placed between them.

[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all of one or more combinations that the associated components may define.

[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present embodiments, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0031] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0033] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment.

[0034] Referring to FIG. 1, the display device (100) may include a display panel (110) and a display panel driving circuit.

[0035] The display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) around the display area (DA) where an image is not displayed. The display area (DA) includes data lines (DL), gate lines (GL) intersecting the data lines (DL), and an array (pixel array) of pixels (P) defined by the data lines (DL) and the gate lines (GL). At least some of the driving circuits may be mounted in the non-display area (NDA).

[0036] Pixels (P) may include red (R), green (G), and blue (B) subpixels for color implementation. In addition to the RGB subpixels, pixels (P) may further include white (W) subpixels. The present embodiment is not limited thereto, and pixels (P) may also include cyan (C), magenta (M), and yellow (Y) subpixels.

[0037] Each pixel (P) may include transistors formed at the intersections of corresponding data lines (DL) and gate lines (GL), storage capacitors, and light-emitting elements connected thereto. The pixel (P) may emit light in response to the amount of current flowing through the light-emitting element according to the control of the transistors.

[0038] The display panel driving circuit may include a data driving circuit (120), a gate driving circuit (130), a timing controller (140), and a power control unit (150).

[0039] The timing controller (140) receives a timing signal transmitted from an external system (not shown) and generates a data control signal (DCS) and a gate control signal (GCS). The timing signal may include a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The data control signal (DCS) is output to a data driving circuit (120), and the gate control signal (GCS) is output to a gate driving circuit (130). The timing controller (140) generates digital image data from the image signal transmitted from the external system and outputs it to the data driving circuit (120).

[0040] The data driving circuit (120) converts digital image data into an analog data voltage according to a data control signal (DCS). The data driving circuit (120) can apply the analog data voltage to corresponding pixels (P) through a data line (DL). In one embodiment, a multiplexer (not shown) may be placed between the data driving circuit (120) and the data lines (DL). The multiplexer can distribute the data voltage input from the data driving circuit (120) to the data lines (DL) under the control of a timing controller (140).

[0041] The gate driving circuit (130) can output a gate voltage sequentially through the gate line (GL) for one horizontal period in response to the gate control signal (GCS). Accordingly, the pixel row connected to each gate line (GL) is turned on for one horizontal period. The gate driving circuit (130) may be composed of stage circuits connected to each of the multiple gate lines (GL), and may be configured in the form of a GIP (Gate In Panel) mounted on the non-display area (NDA) of the display panel (110) as illustrated.

[0042] The power control unit (150) converts the external voltage (VCC) input from the outside into a high potential voltage (VDD) and a low potential voltage (VSS), which are standard power sources used inside the display device (100), and outputs them to the gate driving circuit (130). The power control unit (150) includes a voltage amplifier and can convert the external voltage (VCC) into a high potential voltage (VDD) and a low potential voltage (VSS).

[0044] FIG. 2 is an example diagram illustrating the implementation of a display device according to one embodiment.

[0045] Referring to FIG. 2, the display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed.

[0046] The data driving circuit (120) may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter, an output buffer, etc. Each source driver integrated circuit (SDIC) may, in some cases, further include an analog to digital converter.

[0047] Each source driver integrated circuit (SDIC) may be connected to the display panel (110) by Tape Automated Bonding (TAB), connected to a bonding pad of the display panel (110) by Chip On Glass (COG) or Chip On Panel (COP), or connected to the display panel (110) by Chip On Film (COF). At this time, each source driver integrated circuit (SDIC) may be mounted on a circuit film (SF) connected to a non-display area (NDA) of the display panel (110).

[0048] The data driving circuit (120) may be connected to one side (e.g., the upper side or the lower side) of the display panel (110). Depending on the driving method, panel design method, etc., the data driving circuit (120) may be connected to both sides (e.g., the upper side and the lower side) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0049] The gate driving circuit (130) can be implemented as a GIP type. In this case, the gate driving circuit (130) can be placed in the non-display area (NDA) of the display panel (110). In another embodiment, the gate driving circuit (130) may be implemented as a COF (Chip On Film) type.

[0050] The gate driving circuit (130) may be connected to one side of the display panel (110) or to both sides (left or right) as illustrated. Depending on the driving method, panel design method, etc., the gate driving circuit (130) may be connected to both sides (e.g., left and right) of the display panel (110), or to two or more of the four sides of the display panel (110).

[0051] In other embodiments, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed in the display area (DA). For example, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed so as not to overlap with the pixels (P), or may be placed so as to partially or entirely overlap with the pixels (P).

[0052] The display device (100) may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electrical devices for electrical connection between one or more source driver integrated circuits (SDIC) and other devices.

[0053] A circuit film (SF) on which a source driver integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted can be electrically connected to a display panel (110) and the other side can be electrically connected to a source printed circuit board (SPCB).

[0054] A timing controller (140) and a power control unit (150), etc., may be mounted on a control printed circuit board (CPCB). The timing controller (140) can perform overall control functions related to the driving of the display panel (110) and can control the operation of the data driving circuit (120) and the gate driving circuit (130). The power control unit (150) can supply various voltages or currents to the data driving circuit (120) and the gate driving circuit (130), etc., or control various voltages or currents to be supplied. The timing controller (140) may be implemented as various circuits or electronic components such as an IC (Integrate Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0055] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be electrically connected through at least one connecting cable (CBL). Here, the connecting cable (CBL) may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0056] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be implemented by integrating them into a single printed circuit board.

[0057] In one embodiment, the display device (100) may include one or more monitoring transistors (Tm) formed on the display panel (110) as shown in FIG. 2. The monitoring transistors (Tm) may be distributed on the display panel (110) as shown and arranged adjacent to four corners, but are not limited thereto. The monitoring transistors (Tm) may be connected to at least one node of the gate driving circuit (130), for example, the Q node and / or QB node to be described later.

[0058] The monitoring transistor (Tm) can transmit a monitoring voltage reflecting the degree of degradation of the circuit element constituting the gate driving circuit (130) to the timing controller (140) or power control unit (150).

[0060] FIG. 3 is a schematic diagram showing the configuration of a gate driving circuit according to one embodiment.

[0061] Referring to FIG. 3, the gate driving circuit (130) may include a plurality of stage circuits (ST). The stage circuits (ST) sequentially output gate voltages (Vg1~Vgn) to gate lines (GL1~GLn) in response to a gate shift clock (CLK) and a gate start signal (VST) provided by a timing controller (140, FIG. 1).

[0062] The gate voltage (Vg1~Vgn) can be a pulse signal swinging between the gate high voltage and the gate low voltage. The gate high voltage is a voltage higher than the threshold voltage of the transistors placed in the pixel array. The gate low voltage is a voltage lower than the gate high voltage and the threshold voltage of the transistors placed in the pixel array.

[0063] The transistors of the pixel array can be turned on in response to a gate high voltage to receive a data voltage.

[0065] Figure 4 is a schematic diagram showing the stage circuit of Figure 3.

[0066] Referring to FIG. 4, the stage circuit (ST) can output a gate voltage (Vg) using a gate shift clock (CLK). In the illustrated embodiment, an embodiment is shown in which one stage circuit (ST) receives one gate shift clock (CLK) and outputs one gate voltage (Vg), but the embodiment is not limited thereto. That is, one stage circuit (ST) can be configured to receive one or more gate shift clocks (CLK) and output a corresponding number of gate voltages (Vg).

[0067] The stage circuit (ST) may include a buffer circuit (BUF) connected to the Q node (Q) and QB node (QB) that receives a gate shift clock (CLK) as input and outputs a gate voltage (Vg), and a control circuit (CONT) that controls the buffer circuit (BUF).

[0068] The control circuit (CONT) receives a gate start signal (VST) and a reset signal (RST), and the operation of the buffer circuit (BUF) can be controlled by the input signals.

[0069] The buffer circuit (BUF) may include a pull-up transistor (Tu) and a pull-down transistor (Td). The pull-up transistor (Tu) and the pull-down transistor (Td) may be connected in series between nodes to which a low potential voltage (VSS) to which a gate shift clock (CLK) is applied is applied. A corresponding gate line (GL) is connected between the pull-up transistor (Tu) and the pull-down transistor (Td) to output a gate voltage (Vg).

[0070] To this end, a pull-up transistor (Tu) can be connected to a Q node (Q). The pull-up transistor (Tu) can be turned on according to the voltage of the Q node (Q) controlled by a control circuit (CONT) to output a gate shift clock (CLK) as a gate voltage (Vg).

[0071] A pull-down transistor (Td) can be connected to a QB node (QB). The pull-down transistor (Td) can be turned on according to the voltage of the QB node (QB), which is controlled by a control circuit (CONT), to output a low potential voltage (VSS) as a gate voltage (Vg).

[0073] FIG. 5 is a diagram showing the configuration of a power control unit according to one embodiment.

[0074] The power control unit (150) includes a first power conversion unit (151) and a second power conversion unit (153) that output a high potential voltage (VDD) and a low potential voltage (VSS), and a power compensation unit (152) that outputs a compensation value (VC) for the high potential voltage (VDD) and the low potential voltage (VSS).

[0075] The first power conversion unit (151) converts an external voltage (VCC) input from the outside into a high potential voltage (VDD) and a low potential voltage (VSS), which are standard power supplies used inside the display device (100), and outputs them. The first power conversion unit (151) includes a voltage amplifier and outputs the external voltage (VCC) as a high potential voltage (VDD) and a low potential voltage (VSS).

[0076] The second power conversion unit (153) converts an external voltage (VCC) input from the outside into a high potential voltage (VDDr) and a low potential voltage (VSSr) of a preset level and outputs them. For example, the second power conversion unit (151) can convert a preset voltage value indicated by n-bit binary data from a timing controller (140), etc., into a high potential voltage (VDDr) and a low potential voltage (VSSr) and output them. To this end, the second power conversion unit (153) may include a digital-to-analog converter (DAC).

[0077] The power compensation unit (152) outputs a compensation value (VC) of a driving voltage, for example, a high potential voltage (VDD), using a monitoring voltage (Vm) applied through a monitoring transistor (Tm). The compensation value (VC) can be added to the high potential voltage (VDD) and low potential voltage (VSS) output from the first power conversion unit (151) to generate a compensated high potential voltage (VDD') and a compensated low potential voltage (VSS'), and the compensated high potential voltage (VDD') and the compensated low potential voltage (VSS') can be output to the gate driving circuit (130). Here, the monitoring voltage (Vm) reflects the degree of degradation of the gate driving circuit (130) connected to the monitoring transistor (Tm), and can reflect the degradation and / or device characteristics of the monitoring transistor (Tm) itself. If a device defect occurs in the monitoring transistor (Tm), the compensation value (VC) based on the monitoring voltage (Vm) increases, and the compensated driving voltage (VDD') applied to the gate driving circuit (130) may rise unnecessarily.

[0078] To solve this problem, in one embodiment, the display device (100) may be configured to detect an abnormal state of the monitoring transistor (Tm). This configuration will be described in more detail below.

[0080] Figures 6 and 7 are diagrams illustrating the connection relationship between the monitoring transistor and the power compensation unit.

[0081] Referring to FIG. 6, the monitoring transistors (Tm) may be distributed on the display panel (110) as illustrated and positioned adjacent to the four corners, but are not limited thereto.

[0082] The monitoring transistor (Tm) is turned on according to the voltage of the Q node (Q) and / or QB node (QB) to supply a monitoring voltage (Vm) to the power compensation unit (152). Each monitoring transistor (Tm) can be connected to the power compensation unit (152) placed on the control printed circuit board (CPCB) via wiring through the circuit film (SF). For clarity, the source printed circuit board (SPCB) and the connecting cable (CBL) shown in FIG. 2 have been omitted, but wiring can be connected to the power compensation unit (152) via the circuit film (SF), the source printed circuit board (SPCB), and the connecting cable (CBL).

[0083] Referring to FIG. 7, the power compensation unit (152) can be mounted on a control printed circuit board (CPCB) as part of the power control unit (150). The power compensation unit (152) compares the monitoring voltage (Vm) from the monitoring transistor (Tm) with the reference voltage (Vr), amplifies the difference, and outputs a compensation value (VC). Accordingly, the compensation value (VC) is generated by the power compensation unit (152) as a voltage that varies in proportion to the difference between the monitoring voltage (Vm) and the reference voltage (Vr).

[0084] The compensation value (VC) is a voltage added to the high potential voltage (VDD) or low potential voltage (VSS) to compensate for the high potential voltage (VDD) or low potential voltage (VSS). Here, the high potential voltage (VDD) is the voltage for charging the Q node (Q) or the QB node (QB). The low potential voltage (VSS) is the voltage for discharging the Q node (Q) or the QB node (QB).

[0085] Referring further to FIG. 7, each of the monitoring transistors (Tm) may be connected to the Q node (Q) and / or QB node (QB) of the gate driving circuit (130). In the illustrated embodiment, the monitoring transistors (Tm) are shown connected to the QB node (QB), but the embodiment is not limited thereto.

[0086] In one embodiment, the monitoring transistor (Tm) is a transistor having substantially the same structure and characteristics as the pull-down transistor (Td), and its gate electrode may be connected to the QB node (QB) together with the gate electrode of the pull-down transistor (Td). In another embodiment, when the monitoring transistor (Tm) is connected to the Q node (Q), the monitoring transistor (Tm) is a transistor having substantially the same structure as the pull-up transistor (Tu), and its gate electrode may be connected to the Q node (Q) together with the gate electrode of the pull-up transistor (Tu).

[0087] If the pull-down transistor (Td) degrades due to gate bias stress, the monitoring transistor (Tm) sharing the QB node (QB) also degrades to the same level as the pull-down transistor (Td) because it receives the same stress. Therefore, the monitoring transistor (Tm) can be used to detect the degrade of the pull-down transistor (Td). Similarly, if the monitoring transistor (Tm) shares the Q node (Q) with the pull-up transistor (Tu), the monitoring transistor (Tm) can be used to detect the degrade of the pull-up transistor (Tu).

[0088] The power compensation unit (152) is connected to one electrode of the monitoring transistor (Tm) to receive the monitoring voltage (Vm). For example, the power compensation unit (152) is equipped with an operational amplifier (AMP) that amplifies the difference between two input signals.

[0089] A reference voltage (Vr) is applied to the inverting input terminal (-) of the operational amplifier (AMP). One electrode of the monitoring transistor (Tm) is connected to the non-inverting input terminal (+) of the operational amplifier (AMP). A monitoring voltage (Vm) from the monitoring transistor (Tm) is applied to the non-inverting input terminal (+) of the operational amplifier (AMP). At this time, the monitoring voltage (Vm) may be a predetermined voltage determined by distributing the voltage transmitted from the monitoring transistor (Tm) through the first resistor (R1) and the second resistor (R2). At this time, a predetermined high potential voltage may be applied to the first resistor (R1) and the second resistor (R2). Here, the high potential voltage may be 5V, but is not limited thereto.

[0090] At least one of a feedback capacitor (Cfb) and a feedback resistor (Rfb) may be connected between the inverting input terminal (-) and the output terminal of the operational amplifier (AMP). A predetermined reference voltage (Vr) determined by distributing a predetermined high potential voltage through a third resistor (R3) and a fourth resistor (R4) is applied to the inverting input terminal (-) of the operational amplifier (AMP). The high potential voltage may be, for example, 5V, but is not limited thereto.

[0091] The reference voltage (Vr) can be set to a voltage that does not strain the initial operation of the power compensation unit (152), allows the degradation of the monitoring transistor (Tm) to be detected from an initial low voltage, and can respond to the degradation of the gate driving circuit (130) in the operating environment. The reference voltage (Vr) may vary depending on the model or driving characteristics of the display device (100) and can be determined experimentally.

[0092] The operational amplifier (AMP) outputs a compensation value (VC) based on the difference between two input signals. As the difference between the monitoring voltage (Vm) and the reference voltage (Vr) increases, the voltage level of the compensation value (VC) output from the operational amplifier (AMP) rises. Therefore, if the threshold voltage of the monitoring transistor (Tm) shifts due to gate bias stress, causing the monitoring voltage (Vm) to decrease, the operational amplifier (AMP) can increase the compensation value (VC) until the monitoring voltage (Vm) and the reference voltage (Vr) become equal.

[0093] More specifically, the power compensation unit (152) senses the degree of degradation based on the decrease in current of the monitoring transistor (Tm) relative to the initial on current of the monitoring transistor (Tm). Then, the power compensation unit (152) increases the compensation value (VC) starting from the initial value. As the monitoring transistor (Tm) degrades due to gate bias stress, the on current decreases. This decrease in current is converted into a monitoring voltage (Vm) through resistors (R1, R2), input to an operational amplifier (AMP), and compared with a reference voltage (Vr).

[0094] The operational amplifier (AMP) increases the compensation value (VC) when the monitoring voltage (Vm) becomes equal to the reference voltage (Vr). This upwardly adjusted compensation value (VC) is added to the high potential voltage (VDD) generated in the first power conversion unit (151) to compensate the high potential voltage (VDD). The compensated high potential voltage (VDD') is the driving voltage of the gate driving circuit (130) and is applied to the gate driving circuit (130) to increase the voltage of the QB node (QB) (or Q node (Q)) to a sufficient voltage required and provide it to the gate driving circuit (130).

[0095] In this embodiment, due to a defect in the monitoring transistor (Tm) itself, the monitoring voltage (Vm) may not reflect the actual degree of degradation of the gate driving circuit (130). In this case, the monitoring voltage (Vm) measured by the monitoring transistor (Tm) may reflect a greater degree of degradation than the actual degree of degradation of the gate driving circuit (130). This increases the compensation value (VC) generated by the power compensation unit (152) and, consequently, increases the driving voltage applied to the gate driving circuit (130). Then, a high voltage is applied to the gate driving circuit (130), further accelerating degradation and causing unnecessary power consumption.

[0096] In one embodiment, the display device (100) further comprises a monitoring unit (160, FIG. 8) for determining a defect in the monitoring transistor (Tm) itself.

[0097] Below, an example of a display device (100) equipped with a monitoring unit (160) is described in more detail.

[0099] FIG. 8 is a diagram showing the connection relationships of some components of a display device having a monitoring unit. Specifically, FIG. 8 schematically illustrates the connection relationships of a display panel (110) in which a gate driving circuit (130) and a monitoring transistor (Tm) are arranged, a timing controller (140), a power control unit (150), and a monitoring unit (160).

[0100] Referring to FIG. 8, in one embodiment, the display device (100) may further include a monitoring unit (160). The monitoring unit (160) is provided to assist in detecting degradation of the gate driving circuit (130). For example, as described below, the display device (100) may include at least one monitoring transistor (Tm) for detecting degradation of the gate driving circuit (130), and the monitoring unit (160) may be configured to detect degradation of such monitoring transistor (Tm). Based on the degree of degradation of the monitoring transistor (Tm) determined by the monitoring unit (160) and the degree of degradation of the gate driving circuit (130) detected by the monitoring transistor (Tm), the magnitude of the driving voltage applied to the gate driving circuit (130), for example, high potential voltage (VDD', VDDr), may be controlled.

[0101] The monitoring unit (160) may include a switching transistor (T) that turns on or off in response to an input voltage. One end of the switching transistor (T) may be connected to a predetermined voltage, and the other end may be connected to a monitoring input pin (Monitor) of the timing controller (140). The gate electrode of the switching transistor (T) is connected to the output terminal of the operational amplifier (AMP) of the power compensation unit (152). In one embodiment, the gate electrode of the switching transistor (T) may be connected to the output terminal of the operational amplifier (AMP) through a fifth resistor (R5) and a sixth resistor (R6). The gate electrode of the switching transistor (T) may receive a predetermined voltage determined by distributing the compensation value (VC) output from the operational amplifier (AMP) through the resistors (R5, R6).

[0102] In this embodiment, a first switch (SW1), which is turned on / off by a timing controller (140), may be further connected to the output terminal of the operational amplifier (AMP). Additionally, a second switch (SW2), which is selectively connected to the first power converter (151) or the second power converter (153) by the timing controller (140), may be further connected to the output terminals of the first power converter (151) and the second power converter (153). The first and second switches (SW1, SW2) may receive a control signal according to the I2C communication standard from the timing controller (140).

[0103] Meanwhile, in the illustrated embodiment, the switching transistor (T) is connected to the output terminal of the operational amplifier (AMP) via the first switch (SW1), but the embodiment is not limited thereto. That is, in other embodiments, the switching transistor (T) may be directly connected to the output terminal of the operational amplifier (AMP).

[0104] In one embodiment, the compensation value (VC) output from the operational amplifier (AMP) can be gradually increased through the detection of degradation. In particular, if abnormal degradation, such as a short circuit, occurs in the monitoring transistor (Tm), the compensation value (VC) can be greatly increased. When the compensation value (VC) increases above a predetermined level and reaches the turn-on level of the switching transistor (T), the switching transistor (T) is turned on. Then, a current path is formed from the high potential voltage to the monitoring input pin (Monitor) of the timing controller (140), and a signal above a predetermined voltage level (e.g., an enable signal) is input to the monitoring input pin (Monitor). That is, when abnormal degradation occurs in the monitoring transistor (Tm) and the compensation value (VC) is set to be large, an enable signal can be input to the monitoring input pin (Monitor) of the timing controller (140).

[0105] The timing controller (140) can detect degradation and / or defects in the monitoring transistor (Tm) itself through an enable signal input to the monitoring input pin (Monitor). In other words, the monitoring unit (160) outputs an enable signal when the compensation value (VC) output from the voltage compensation unit (152) is above a predetermined level, and the timing controller (140) can determine the degradation of the monitoring transistor (Tm) based on the enable signal (in other words, based on the level of the compensation value (VC)). In this case, the timing controller (140) can control the application of an appropriate level of driving voltage to the gate driving circuit (130) directly through the power conversion unit (151) in place of the abnormally high compensation value (VC). The above process is described in detail as follows.

[0106] First, the timing controller (140) can turn on the first switch (SW1) to connect the output terminal of the operational amplifier (AMP) to the gate electrode of the switching transistor (T). Then, the compensation value (VC) output from the operational amplifier (AMP) can be applied to the gate electrode of the switching transistor (T). At this time, the second switch (SW2) is connected to the first power conversion unit (151) so that the high potential voltage (VDD) generated in the first conversion unit (151) is connected to the output terminal of the operational amplifier (AMP). Accordingly, the compensation value (VC) output from the operational amplifier (AMP) is added to the high potential voltage (VDD) output from the first power conversion unit (151), and the compensated high potential voltage (VDD') is applied to the gate driving circuit (130).

[0107] When an enable signal is not applied to the monitoring input pin (Monitor), the timing controller (140) connects the second switch (SW2) to the first power conversion unit (151), so that the first conversion conversion unit (151) is connected to the output terminal of the operational amplifier (AMP). Accordingly, the sum of the high potential voltage (VDD) generated from the first power conversion unit (151) and the compensation value (VC) output from the power compensation unit (152) is applied to the gate driving circuit (130) as a compensated high potential voltage (VDD').

[0108] When an enable signal is applied to the monitoring input pin (Monitor), the timing controller (140) can turn off the first switch (SW1) and connect the second switch (SW2) to the second power converter (153). Then, the timing controller (140) can control the second power converter (153) to output a high potential voltage (VDDr) of a preset level. Then, the compensation value (VC) generated by the power compensation unit (152) is not reflected in the high potential voltage (VDD), and the high potential voltage (VDDr) of a predetermined level output by the power converter (151) is applied to the gate driving circuit (130).

[0109] In one embodiment, when determining a voltage level (e.g., a DC voltage level), the timing controller (140) may use the accumulated data amount of the display panel (110). The accumulated data amount may be, for example, the total amount of data voltage applied to the display panel (110), and may be selected in various ways to reflect the stress index of the display panel (110). A larger accumulated data amount indicates greater degradation of the display panel (110) and consequently indicates that a higher driving voltage must be applied to the gate driving circuit (130). Accordingly, the timing controller (140) may determine the level of voltage to be output by the second power converter (153) based on the accumulated data amount.

[0110] In one embodiment, the voltage level may be preset in correspondence with one or more intervals of the accumulated data amount. For example, the voltage level may be preset to different values ​​corresponding to each of the eight intervals of the accumulated data amount. Here, the preset voltage levels are set so that the voltage level increases as the accumulated data amount increases.

[0111] The preset voltage levels can be represented as digital data, for example, n-bit binary data, and when eight voltage levels are set, the voltage levels can be represented as 3-bit binary data. Table 1 below shows an example (look-up table) for eight voltage levels represented as 3-bit binary data.

[0112] 000 : 0.48V (SPEC : 0.5V)001 : 3.03V (SPEC : 3.14V)010 : 6.12V (SPEC : 6.285V)011 : 9.22V (SPEC : 9.428V)100 : 12.3V (SPEC : 12.57V)101 : 15.38V (SPEC : 15.71V)110 : 18.47V (SPEC : 18.85V)111 : 21.55V (SPEC : 22V)

[0113] As described above, in the case where the display device (100) according to one embodiment detects the degradation of the monitoring transistor (Tm) placed on the display panel (110) and the compensation value (VC) increases unnecessarily, the timing controller (140) detects this and blocks the output of the inaccurate compensation value (VC), and applies a predetermined DC voltage corresponding to the accumulated stress of the display panel (110) to the gate driving circuit (130) through the second power conversion unit (153) to improve the reliability of the gate driving circuit (130).

[0114] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the technical configuration of the present invention described above may be implemented in other specific forms without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope of the present invention is defined by the claims set forth below rather than by the detailed description above. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0115] 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driving circuit 140: Timing Controller 150: Power control unit 160: Monitoring Department

Claims

Claim 1 A display device comprising: a display panel on which pixels are arranged; a gate driving circuit composed of a stage circuit that outputs a gate signal to the pixels according to the voltages of a Q node and a QB node; a monitoring transistor connected to at least one of the Q node and the QB node of the stage circuit; a power control unit that generates a compensation value according to a monitoring voltage output from the monitoring transistor and provides a driving voltage compensated according to the compensation value to the gate driving circuit; a monitoring unit that outputs an enable signal when the compensation value increases above a predetermined level; and a timing controller that controls the output of the compensation value to be blocked in response to the enable signal. Claim 2 delete Claim 3 A display device according to claim 1, wherein the power control unit comprises: a first power converter that converts an external voltage to output a driving voltage; and a power compensation unit that outputs a compensation value based on the monitoring voltage. Claim 4 In paragraph 3, the monitoring unit comprises a display device including a switching transistor, one end of which is connected to a predetermined voltage and the other end of which is connected to the timing controller, and the gate electrode of which is connected to the output terminal of the power compensation unit. Claim 5 A display device according to claim 4, wherein the switching transistor is turned on as the compensation value output from the power compensation unit increases to the gate-on voltage of the switching transistor, and outputs the predetermined voltage to the timing controller as the enable signal. Claim 6 A display device according to claim 5, wherein the power control unit further includes a second power converter that outputs a driving voltage of a preset level indicated by the timing controller, and the timing controller blocks the output of the compensation value in response to the enable signal and controls the second power converter to output the driving voltage of the preset level. Claim 7 In claim 6, the driving voltage of the preset level is determined based on the total amount of data voltage applied to the display panel, in a display device. Claim 8 A display device according to claim 7, wherein the driving voltage of the preset level is preset to different values ​​corresponding to one or more intervals for the total amount of the data voltage. Claim 9 In claim 7, the timing controller outputs digital data indicating the preset level of the driving voltage to the second power converter based on a look-up table that defines the preset level of the driving voltage corresponding to the total amount of the data voltage. Claim 10 In claim 6, the power compensation unit comprises an operational amplifier connected to one electrode of the monitoring transistor to receive the monitoring voltage and output the compensation value based on the difference between the monitoring voltage and the reference voltage, thereby forming a display device. Claim 11 A display device according to claim 10, further comprising: a first switch connected to the output terminal of the operational amplifier; and a second switch selectively connected to either the output terminal of the first power converter or the output terminal of the second power converter, wherein the timing controller turns off the first switch and connects the second switch to the output terminal of the second power converter when the preset level of driving voltage is output. Claim 12 In claim 1, the monitoring transistor is disposed on a display panel, and the gate electrode is connected to at least one of the Q node and the QB node, in a display device. Claim 13 A display device according to claim 12, wherein the stage circuit comprises: a buffer circuit that outputs the gate signal, including a pull-up transistor connected to the Q node and a pull-down transistor connected to the QB node; and a control circuit that controls the voltages of the Q node and the QB node based on a driving voltage compensated according to the compensation value. Claim 14 In paragraph 13, the monitoring transistor is a transistor having the same characteristics as the pull-up transistor or the pull-down transistor, and is a display device that degrades in the same way as the pull-up transistor or the pull-down transistor. Claim 15 A display device comprising: a gate driving circuit that outputs a gate signal; a monitoring transistor that detects degradation of the gate driving circuit; a power control unit that generates a compensation value in response to degradation detected by the monitoring transistor and provides a compensated driving voltage to the gate driving circuit according to the compensation value; a monitoring unit that outputs an enable signal when the compensation value increases above a predetermined level; and a timing controller that, when the enable signal is input, blocks the output of the compensation value and provides a driving voltage of a preset level to the gate driving circuit. Claim 16 In item 15, the above-mentioned preset level driving voltage is determined based on the total amount of data voltage applied to the display panel, a display device. Claim 17 A display device according to claim 16, wherein the driving voltage of the preset level is preset to different values ​​corresponding to one or more intervals for the total amount of the data voltage.

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