Memory device and operating method thereof

Abstract

The present technology includes a memory cell array comprising a plurality of memory cells connected to a plurality of word lines, a peripheral circuit that performs a program operation and a verification operation for selected memory cells among the plurality of memory cells, a compensation operation control unit that determines a compensation value for a plurality of verification voltages based on compensation information according to the progress of the program operation and a target program state during the verification operation, and a verification operation control unit that controls the peripheral circuit to perform the verification operation for selected memory cells among the plurality of memory cells based on the plurality of verification voltages and the compensation value.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device that performs program operation and verification operation and a method of operation thereof. Background Technology

[0003] A storage device is a device that stores data under the control of a host device, such as a computer or smartphone. A storage device may include a memory device where data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0004] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory.

[0005] Non-volatile memory devices perform electrical programming and erasing operations by changing the threshold voltage of memory cells while moving electrons. Due to the nature of programming operations utilizing electrons and verification operations verifying the programming process, problems may arise where current flows abnormally between the bit line and the source line caused by source line bouncing. In other words, source line bouncing can delay the completion of programming and verification operations and reduce the reliability of the operation results. To ensure the reliability of the operation results, a compensation operation exists that adjusts the verification voltage used for the verification operation according to the progress of the programming operation. The problem to be solved

[0007] An embodiment of the present invention provides a memory device that supports an enhanced compensation operation in a verification operation and a method of operating the same. means of solving the problem

[0009] A memory device according to an embodiment of the present invention may include a memory cell array comprising a plurality of memory cells connected to a plurality of word lines, a peripheral circuit that performs a program operation for selected memory cells among the plurality of memory cells and a verification operation for the program operation, a compensation operation control unit that determines a compensation value for a plurality of verification voltages based on compensation information and a target program state during the verification operation, and a verification operation control unit that controls the peripheral circuit to perform the verification operation for selected memory cells among the plurality of memory cells based on the plurality of verification voltages and the compensation value.

[0010] A method of operating a memory device according to an embodiment of the present invention includes a program step of programming selected memory cells among a plurality of memory cells using a program voltage, and a program verification step of verifying the threshold voltage of the selected memory cells using a plurality of verification voltages. The program verification step determines a plurality of compensation values ​​corresponding to each of the plurality of verification voltages based on compensation information, and can verify the threshold voltage of the selected memory cells based on the plurality of verification voltages and the plurality of compensation values.

[0011] A storage device according to an embodiment of the present invention includes a memory device comprising a plurality of memory cells connected to a plurality of word lines and a memory controller that controls the memory device, wherein the memory device may include a peripheral circuit that performs a program operation for selected memory cells among the plurality of memory cells and a verification operation for the program operation, and a control logic that, during the verification operation, determines a compensation value for a plurality of verification voltages according to the degree of progress of the program operation and a target program state based on compensation information, and controls the peripheral circuit to perform the verification operation based on the plurality of verification voltages and the compensation value. Effects of the invention

[0013] According to the present technology, a memory device that supports an enhanced compensation operation in a verification operation and a method of operating the same are provided. Brief explanation of the drawing

[0015] FIG. 1 is a drawing for explaining a storage device according to one embodiment of the present invention. FIG. 2 is a drawing for explaining a memory device according to an embodiment of the present invention. FIG. 3 is a drawing for explaining a memory block according to an embodiment of the present invention. FIG. 4 is a diagram illustrating program operation and verification operation according to an embodiment of the present invention. FIG. 5 is a diagram illustrating program operation and verification operation according to an embodiment of the present invention. FIG. 6 is a drawing for explaining a program loop according to one embodiment of the present invention. FIG. 7 is a drawing for explaining compensation information according to one embodiment of the present invention. FIG. 8 is a drawing for explaining a compensation operation according to an embodiment of the present invention. FIG. 9 is a drawing for explaining a compensation operation according to an embodiment of the present invention. FIG. 10 is a diagram illustrating control logic according to one embodiment of the present invention. FIG. 11 is a timing diagram for explaining a compensation operation according to one embodiment of the present invention. FIG. 12 is a drawing for explaining the operation method of a memory device according to one embodiment of the present invention. FIG. 13 is a drawing for explaining a Solid State Drive (SSD) system according to one embodiment of the present invention. Specific details for implementing the invention

[0016] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0018] FIG. 1 is a drawing for explaining a storage device according to one embodiment of the present invention.

[0019] Referring to FIG. 1, the storage device (1000) may include a memory device (100) and a memory controller (200).

[0020] The storage device (1000) may be a device that stores data under the control of a host (2000), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC, or in-vehicle infotainment system.

[0021] The storage device (1000) can be implemented as any one of various types of storage devices according to the host interface, which is the method of communication with the host (2000). For example, the storage device (1000) can be implemented as any one of various types of storage devices such as an SSD, a multi-media card in the form of an MMC, eMMC, RS-MMC, or micro-MMC, a secure digital card in the form of an SD, mini-SD, or micro-SD, a USB (Universal Serial Bus) storage device, a UFS (Universal Flash Storage) device, a PCMCIA (Personal Computer Memory Card International Association) card storage device, a PCI (Peripheral Component Interconnection) card storage device, a PCI-E (PCI Express) card storage device, a CF (Compact Flash) card, a Smart Media card, or a Memory Stick.

[0022] The storage device (1000) can be implemented in any one of various types of package forms. For example, the storage device (1000) can be implemented in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0023] The memory device (100) can store data or use stored data. Specifically, the memory device (100) can operate in response to the control of the memory controller (200). In addition, the memory device (100) may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array comprising a plurality of memory cells that store data.

[0024] Memory cells can be configured as a Single Level Cell (SLC) that stores one data bit, a Multi Level Cell (MLC) that stores two data bits, a Triple Level Cell (TLC) that stores three data bits, or a Quad Level Cell (QLC) that can store four data bits.

[0025] A memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and a single memory block may include a plurality of pages. Here, a page may be a unit for storing data in a memory device (100) or reading data stored in a memory device (100).

[0026] The memory device (100) may be implemented as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0027] A memory device (100) may receive commands and addresses from a memory controller (200). The memory device (100) may be configured to access an area selected by the received address among the memory cell arrays. Accessing the selected area may mean performing an operation corresponding to the received command for the selected area. For example, the memory device (100) may perform a write operation (program operation), a read operation, and an erase operation. Here, the program operation may be an operation in which the memory device (100) writes data to the area selected by the address. The read operation may mean an operation in which the memory device (100) reads data from the area selected by the address. The erase operation may mean an operation in which the memory device (100) erases data stored in the area selected by the address.

[0028] During a verification operation for a program operation, the potential of the source line increases, and a source line bouncing (SL bouncing) phenomenon may occur, which obstructs the flow of current between the source line and the bit line due to the increased potential of the source line. According to one embodiment of the present invention, the memory device (100) can ensure the reliability of the program operation and the verification operation by correcting the level of the verification voltage during the verification operation to prevent the source line bouncing phenomenon.

[0029] The memory controller (200) receives data and a logical address (LA) from the host (2000) and can convert the logical address into a physical address (PA) representing the address of the memory cells where the data included in the memory device (100) is to be stored. The logical address may be a logical block address (LBA), and the physical address may be a physical block address (PBA).

[0030] The memory controller (200) can control the memory device (100) to perform a program operation, a read operation, or an erase operation, etc., in accordance with a request from the host (2000). When performing a program operation, the memory controller (200) can provide a program command, a physical block address, and data to the memory device (100). When performing a read operation, the memory controller (200) can provide a read command and a physical block address to the memory device (100). When performing an erase operation, the memory controller (200) can provide an erase command and a physical block address to the memory device (100).

[0031] The memory controller (200) can control the memory device (100) to perform program operations, read operations, or erase operations independently of requests from the host (2000). For example, the memory controller (200) can control the memory device (100) to perform program operations, read operations, or erase operations used to perform background operations such as wear leveling, garbage collection, and read reclaim.

[0033] FIG. 2 is a drawing for explaining a memory device according to an embodiment of the present invention.

[0034] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0035] A memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) may be connected to a row decoder (121) via row lines (RL). Here, the row lines (RL) may include at least one source select line, a plurality of word lines, and at least one drain select line. The plurality of memory blocks (BLK1 to BLKz) may be connected to a page buffer group (123) via bit lines (BL1 to BLn). Each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. As an example, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a single page. Thus, a single memory block may include a plurality of pages.

[0036] The memory cells included in the memory cell array (110) can each be configured as a single level cell (SLC) that stores one data bit, a multi level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) that can store four data bits.

[0037] The peripheral circuit (120) may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array (110) under the control of the control logic (130). That is, the peripheral circuit (120) may drive the memory cell array (110) under the control of the control logic (130). For example, the peripheral circuit (120) may apply various operating voltages to row lines (RL) and bit lines (BL1~BLn) or discharge the applied voltages under the control of the control logic (130).

[0038] Specifically, the peripheral circuit (120) may include a row decoder (121), a voltage generator (122), a page buffer group (123), a column decoder (124), an input / output circuit (125), and a sensing circuit (126).

[0039] A row decoder (121) can be connected to a memory cell array (110) via row lines (RL). The row lines (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word lines may include normal word lines and dummy word lines. Additionally, the row lines (RL) may further include a pipe selection line.

[0040] The row decoder (121) may be configured to operate in response to the control of the control logic (130). The row decoder (121) may receive a row address (RADD) from the control logic (130). Specifically, the row decoder (121) may be configured to decode the row address (RADD). The row decoder (121) may select at least one memory block among the memory blocks (BLK1 to BLKz) according to the decoded row address (RADD). And, the row decoder (121) may select at least one word line of the selected memory block to apply voltages generated by the voltage generator (122) to at least one word line according to the decoded address.

[0041] For example, during a program operation, the row decoder (121) may apply a program voltage to the selected word lines and a program pass voltage at a level lower than the program voltage to the unselected word lines. During a program verification operation, the row decoder (121) may apply a verification voltage to the selected word lines and a verification pass voltage higher than the verification voltage to the unselected word lines. During a read operation, the row decoder (121) may apply a read voltage to the selected word lines and a read pass voltage higher than the read voltage to the unselected word lines.

[0042] In an embodiment, the erase operation of the memory cell array (110) can be performed in units of memory blocks. During the erase operation, the row decoder (121) can select one memory block according to the decoded address, and the row decoder (121) can apply a ground voltage to the word lines connected to the selected memory block.

[0043] The voltage generation unit (122) can operate in response to the control of the control logic (130). Specifically, the voltage generation unit (122) can be configured to generate multiple voltages using an external power supply voltage supplied to the memory device (100) in response to the control of the control logic (130). For example, the voltage generation unit (122) can generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage, etc., in response to the control of the control logic (130). That is, the voltage generation unit (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG).

[0044] As an example, the voltage generating unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (122) can be used as the operating voltage of the memory cell array (110).

[0045] As an example, the voltage generation unit (122) can generate multiple voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generation unit (122) includes multiple pumping capacitors that receive an internal power supply voltage, and can generate multiple voltages by selectively activating the multiple pumping capacitors in response to the control of the control logic (130). Then, the generated multiple voltages can be supplied to the memory cell array (110) by the row decoder (121).

[0046] The page buffer group (123) may include first to nth page buffers (PB1 to PBn). The first to nth page buffers (PB1 to PBn) may each be connected to the memory cell array (110) through first to nth bit lines (BL1 to BLn). Furthermore, the first to nth page buffers (PB1 to PBn) may operate in response to the control of the control logic (130). Specifically, the first to nth page buffers (PB1 to PBn) may operate in response to page buffer control signals (PBSIGNALS). For example, the first to nth page buffers (PB1 to PBn) may temporarily store data received through the first to nth bit lines (BL1 to BLn), or sense the voltage or current of the bit lines (BL1 to BLn) during a read or verification operation.

[0047] Specifically, during a program operation, the first to nth page buffers (PB1 to PBn) can transmit data (DATA) received through the input / output circuit (125) to selected memory cells through the first to nth bit lines (BL1 to BLn) when a program pulse is applied to a selected word line. The memory cells of the selected page can be programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied may have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied may maintain its threshold voltage.

[0048] During a program verification operation, the first to nth page buffers (PB1~PBn) can read page data from selected memory cells through the first to nth bit lines (BL1~BLn).

[0049] When a read operation is performed, the first to nth page buffers (PB1~PBn) can read data (DATA) from the memory cells of the selected page through the first to nth bit lines (BL1~BLn) and output the read data (DATA) to the input / output circuit (125) under the control of the column decoder (124).

[0050] When erasing, the first to nth page buffers (PB1~PBn) can float the first to nth bit lines (BL1~BLn).

[0051] The column decoder (124) can transfer data between the input / output circuit (125) and the page buffer group (123) in response to a column address (CADD). For example, the column decoder (124) can exchange data with the first to nth page buffers (PB1 to PBn) via data lines (DL) or exchange data with the input / output circuit (125) via column lines (CL).

[0052] The input / output circuit (125) can transmit a command (CMD) and an address (ADDR) received from the memory controller (200) to the control logic (130), or exchange data (DATA) with the column decoder (124).

[0053] The sensing circuit (126) can generate a reference current in response to an allow bit signal (VRYBIT) during a read operation or a verify operation, and output a pass signal (PASS) or fail signal (FAIL) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current.

[0054] The control logic (130) can control the peripheral circuit (120) by outputting an operation signal (OPSIG), a row address (RADD), page buffer control signals (PBSIGNALS) and an allow bit signal (VRYBIT) in response to a command (CMD) and an address (ADDR).

[0055] Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to a pass or fail signal. Furthermore, the control logic (130) can control the page buffer group (123) to temporarily store verification information, including the pass or fail signal, in the page buffer group (123). Specifically, the control logic (130) can determine the program state of the memory cell in response to a pass or fail signal. For example, if the memory cell operates as a Triple Level Cell (TLC), the control logic (130) can determine whether the program state of the memory cell is an erase state (E) or one of the first to seventh program states (P1 to P7).

[0057] FIG. 3 is a drawing for explaining a memory block according to an embodiment of the present invention.

[0058] Referring to FIG. 3, a memory block (BLKi) may have a plurality of word lines connected in parallel between a first select line and a second select line. Here, the first select line may be a source select line (SSL), and the second select line may be a drain select line (DSL). More specifically, the memory block (BLKi) may include a plurality of strings (ST) connected between bit lines (BL1~BLn) and a source line (SL). The bit lines (BL1~BLn) may each be connected to the strings (ST), and the source line (SL) may be connected to the strings (ST) in common. Since the strings (ST) may be configured identically, the string (ST) connected to the first bit line (BL1) will be described specifically as an example.

[0059] A string (ST) may include a source select transistor (SST), a plurality of memory cells (F1 to F16), and a drain select transistor (DST) connected in series between a source line (SL) and a first bit line (BL1). A single string (ST) may include at least one source select transistor (SST) and one drain select transistor (DST), and may also include more memory cells (F1 to F16) than the number shown in the drawing.

[0060] The source of the source select transistor (SST) can be connected to the source line (SL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (F1 to F16) can be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of the source select transistors (SST) included in different strings (ST) can be connected to the source select line (SSL), the gates of the drain select transistors (DST) can be connected to the drain select line (DSL), and the gates of the memory cells (F1 to F16) can be connected to multiple word lines (WL1 to WL16). Among the memory cells included in different strings (ST), a group of memory cells connected to the same word line can be called a physical page (PPG). Therefore, the memory block (BLKi) may contain as many physical pages (PPG) as there are word lines (WL1~WL16).

[0061] Memory cells can be configured as a Single Level Cell (SLC) that stores one data bit, a Multi Level Cell (MLC) that stores two data bits, a Triple Level Cell (TLC) that stores three data bits, or a Quad Level Cell (QLC) that can store four data bits.

[0062] A single-level cell (SLC) can store 1 bit of data. One physical page (PPG) of a single-level cell can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of cells contained in one physical page (PPG).

[0063] Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC) can store 2 bits or more of data. In this case, one physical page (PPG) can store 2 or more logical pages (LPG) of data.

[0065] FIG. 4 is a diagram illustrating program operation and verification operation according to an embodiment of the present invention.

[0066] Referring to FIG. 4, the memory cell can be programmed into an erase state (E) or first to seventh program states (P1 to P7) depending on the threshold voltage. Although the memory cell in FIG. 4 is illustrated as a Triple Level Cell (TLC) capable of being programmed into one erase state and seven program states, this is merely an example for convenience of explanation. In implementation, it may be implemented as a Multi Level Cell (MLC), Single Level Cell (SLC), Quad Level Cell (QLC), etc. Also, for convenience of explanation, the erase state and the program state are distinguished, but the erase state can be represented as the zeroth program state (P0). Therefore, the erase state (E) and the first to seventh program states (P1 to P7) illustrated in FIG. 4 may be represented as the zeroth to seventh program states.

[0067] Memory cells connected to a selected word line may have a threshold voltage included in any one of the erase state (E) or the first to seventh program states (P1 to P7). That is, memory cells may be programmed to have a threshold voltage included in any one of the erase state (E) or the first to seventh program states (P1 to P7). Before a program operation is performed, the memory cells may be in the erase state (E). During a program operation, memory cells in the erase state (E) may be programmed into any one of the seven program states as a program voltage is applied to the selected word line.

[0068] And, as a result of the program operation, for example, the erase state (E) or the first to seventh program states (P1 to P7) can be verified using a verification voltage. Specifically, the verification operation may include a sensing operation that applies a verification voltage to each memory cell and checks the current state or voltage flowing according to the applied verification voltage to identify whether the memory cell is an on cell or an off cell. During the sensing operation, the storage device (1000) sets the verification voltage based on the threshold voltage values ​​of the memory cells, and the storage device (1000) can distinguish whether the memory cells are on cells or off cells using the set verification voltage. Specifically, the erase state (E) and the first program state (P1) can be distinguished as an on cell and an off cell, respectively, by the first verification voltage (Vvf1). The first program state (P1) and the second program state (P2) can be distinguished into an on cell and an off cell, respectively, by the second verification voltage (Vvf2). The second program state (P2) and the third program state (P3) can be distinguished into an on cell and an off cell, respectively, by the third verification voltage (Vvf3). The third program state (P3) and the fourth program state (P4) can be distinguished into an on cell and an off cell, respectively, by the fourth verification voltage (Vvf4). The fourth program state (P4) and the fifth program state (P5) can be distinguished into an on cell and an off cell, respectively, by the fifth verification voltage (Vvf5). The fifth program state (P5) and the sixth program state (P6) can be distinguished into an on cell and an off cell, respectively, by the sixth verification voltage (Vvf6). The 6th program state (P6) and the 7th program state (P7) can be distinguished into an on cell and an off cell, respectively, by the 7th verification voltage (Vvf7).That is, during the sensing operation, the storage device (1000) can distinguish whether the memory cells are on cells or off cells by setting the level of the verification voltage higher than the maximum value of the on cell distribution to be distinguished and the level of the verification voltage lower than the minimum value of the off cell distribution.

[0069] Additionally, specifically, the storage device (1000) can identify the distribution of a specific memory cell by applying a first to seventh verification voltage (Vvf1 to Vvf7) to a specific memory cell. For example, if a specific memory cell is programmed to a fourth program state (P4), the specific memory cell may be sensed as an off cell when the first to fourth verification voltages are applied, and the specific memory cell may be sensed as an on cell when the fifth to seventh verification voltages are applied. Furthermore, the storage device (1000) can identify that a specific memory cell is programmed to a fourth program state (P4) by combining the sensed results. The storage device (1000) can identify the program state of a plurality of memory cells in the same way and can convert the identified program states into data by combining them.

[0071] FIG. 5 is a diagram illustrating program operation and verification operation according to an embodiment of the present invention.

[0072] Referring to FIG. 5, a program operation for forming a plurality of program states may include M program loops. Each program loop may include an operation of applying a program voltage to a selected word line and an operation of applying a verification voltage to a selected word line. In FIG. 5, “program operation” is a program operation in a broad sense that includes a verification operation for determining whether the program operation has been properly performed. Furthermore, the program operation may include a program period for applying a program voltage and a verify period for applying a verification voltage. The operation of applying a program voltage to a selected word line may be an operation of raising the threshold voltage of a memory cell, and the operation of applying a verification voltage may be an operation of determining the threshold voltage to check whether the corresponding memory cell has reached a target program state. For example, a first program loop may include an operation of applying a first program voltage (Vpgm1) and a plurality of verification voltages (Vvf1 to Vvf7) to a selected word line. For the convenience of explanation, it has been shown that 7 verification voltages are applied in all program loops, but the number of verification voltages is not limited to this, and only some of the 7 verification voltages may be applied.

[0073] As the program loop is executed sequentially, the program voltage can be increased by a step voltage (ΔVpgm). This is called the Incremental Step Pulse Program (ISPP) method. For example, the second program voltage (Vpgm2) applied to the word line selected in the second program loop can be greater than the first program voltage (Vpgm1) by a step voltage (ΔVpgm). For convenience of explanation, the step voltage is depicted as fixed, but the step voltage can be changed dynamically.

[0074] During the execution of M program loops, a memory cell that has reached a target program state may be placed in an inhibit state to prevent further programming. Even if a subsequent program loop proceeds, the threshold voltage of the memory cell in the inhibit state may be maintained. For example, a memory cell that has completed programming to the target program state (P2) in the second program loop may be placed in an inhibit state during the third program loop. In the embodiment, the bit line of the memory cell that has reached the target program state may be precharged with an inhibit voltage. When the bit line is precharged with an inhibit voltage, the channel of the memory cell is self-boosted by the program voltage, and the memory cell may not be programmed.

[0076] FIG. 6 is a drawing for explaining a program loop according to one embodiment of the present invention.

[0077] Referring to FIG. 6, the program operation may include a first program loop to a Nth program loop.

[0078] Among a plurality of memory cells, selected memory cells that are the subject of a program operation can be programmed into target program states through a program operation. The plurality of program states can be distinguished based on a threshold voltage. For example, if the selected memory cells operate as single-level cells (SLC), the target program states can be distinguished into erase states and program states. If the selected memory cells operate as multi-level cells (MLC), the target program states can be distinguished into one erase state and seven program states.

[0079] Each program loop may include a program period (61) and a program verify period (62). The program period (61) may be a period in which data is programmed into selected memory cells. The program period (61) may include a precharge period, a program voltage application period, and a discharge period. In the precharge period, a program allowance voltage may be precharged to a selected bit line, and a program prohibition voltage may be precharged to a non-selected bit line. In the program voltage application period, a program voltage may be applied to a selected word line, and a pass voltage may be applied to a non-selected word line. In the discharge period, the voltage precharged to the bit line and the voltage applied to the word line may be discharged. That is, the program period (61) may be a period for making the program state of the selected memory cells into a target program state.

[0080] The program verification section (62) may be a section for verifying the program state of the programmed memory cells. Alternatively, the program verification section (62) may be a section for verifying whether the program state or threshold voltage of the selected memory cells has reached the target program state after the program section (61).

[0081] Specifically, the program verification period (62) may include a sensing period and a check period. The sensing period may include a precharge period, an evaluation period, and a discharge period. In the precharge period, bit lines may be precharged. In the evaluation period, a verification voltage may be applied to a selected word line and a pass voltage may be applied to a non-selected word line. In the evaluation period, the precharged voltage on a bit line connected to a memory cell having a threshold voltage higher than the verification voltage may be maintained. In the evaluation period, the precharged voltage on a bit line connected to a memory cell having a threshold voltage lower than the verification voltage may be discharged in proportion to the length of the evaluation period. Voltage information regarding whether the precharged voltage was maintained or discharged may be stored in the page buffer group (123).

[0082] The check section may be a section for determining whether the program verification passes or fails using voltage information stored in the page buffer group (123). In the check section, the sensing circuit (126) may compare the number of memory cells having a threshold voltage lower than the verification voltage among the selected memory cells with a reference number. Then, the sensing circuit (126) may output a pass signal or a fail signal according to the comparison result. Here, determining whether the number of memory cells having a threshold voltage higher than the verification voltage among the selected memory cells is greater than the first reference number may be a pass bit check operation. Determining whether the number of memory cells having a threshold voltage lower than the verification voltage among the selected memory cells is less than the second reference number may be a fail bit check operation.

[0084] FIG. 7 is a drawing for explaining compensation information according to one embodiment of the present invention.

[0085] Referring to FIG. 7, a compensation information table (70) containing compensation information regarding a compensation operation is illustrated. The compensation information table (70) may include compensation information for verification operations that verify each of a plurality of program states. Specifically, the compensation information (71) for a verification operation (hereinafter, second verification operation) corresponding to a second program state (PV2) may be compensation information for a second verification voltage (Vvf2) for verifying the second program state (PV2). The compensation information may include a start loop indicating the application time of the compensation operation, an end loop indicating the end time of the compensation operation, a step loop indicating the number of loops for applying the correction value of the corresponding step, and an offset bias indicating the compensation value applied to the verification voltage.

[0086] For example, in the compensation information (71) for the second verification operation, the start loop may be 5, the end loop may be 30, the step loop may be 3, and the offset bias may be 50mV. According to the compensation information (71) for the second verification operation, the compensation operation may be applied from the 5th program loop, where the 5th program voltage is applied, to the 30th program loop, where the 30th program voltage is applied. Also, since the step loop of the compensation information (71) for the second verification operation is 3, the correction value may be changed for every 3 program loops, such as the 5th program loop, the 8th program loop, the 11th program loop, and the 14th program loop. Since the offset bias of the compensation information (71) for the second verification operation is 50mV, the level of the verification voltage may be increased by 50mV or decreased by 50mV for every 3 program loops. That is, when the program loop is the first to fourth program loop, the second verification voltage is applied at the initially set voltage level without correction, and when the program loop is the fifth to seventh program loop, the second verification voltage is applied at a voltage level increased or decreased by 50mV from the initially set voltage level. And, when the program loop is the eighth to tenth program loop, the second verification voltage is corrected to a voltage level increased or decreased by 100mV from the initially set voltage level. The compensation operation for the second verification voltage may be applied until the program loop reaches the termination loop. The same compensation operation may be applied to the remaining verification voltages excluding the second verification voltage.

[0088] FIG. 8 is a drawing for explaining a compensation operation according to an embodiment of the present invention.

[0089] Referring to FIG. 8, a program operation in which a compensation operation is applied to a first verification voltage (Vvf1) is illustrated. A memory device (100) can perform a compensation operation according to verification information (81) for the first verification voltage (Vvf1). According to the verification information (81) for the first verification voltage (Vvf1), the step loop may be 2, the start loop may be n-1, the end loop may be k, and the offset bias may be **mV. Specifically, the memory device (100) can apply a compensation operation to the first verification voltage (Vvf1) starting from the n-1st program loop according to the verification information (81) for the first verification voltage (Vvf1). That is, the memory device (100) can apply a first verification voltage (Vvf1) of an initially set voltage level before the n-1st program loop (e.g., the n-2nd program loop).

[0090] And, the memory device (100) can apply a first verification voltage (Vvf1) at a voltage level increased by an offset bias from the first verification voltage applied from the n+1 program loop to the n-1 program loop. And, the memory device (100) can perform a compensation operation for the first verification voltage (Vvf1) up to the k-th program loop according to the verification information (81) for the first verification voltage (Vvf1).

[0092] FIG. 9 is a drawing for explaining a compensation operation according to an embodiment of the present invention.

[0093] Referring to FIG. 9, a program operation in which a compensation operation is applied to a second verification voltage (Vvf2) and a third verification voltage (Vvf3) is illustrated. Referring to the verification information (91) for the second verification voltage (Vvf2) and the verification information (92) for the third verification voltage (Vvf3), the verification information (91) for the second verification voltage (Vvf2) and the verification information (92) for the third verification voltage (Vvf3) can be set independently. Specifically, the compensation operation for the second verification voltage (Vvf2) can be set to a step loop of 3, and the compensation operation for the third verification voltage (Vvf3) can be set to a step loop of 2. Additionally, the offset bias (SB2) for the second verification voltage (Vvf2) can be set to be smaller than the offset bias (SB3) for the third verification voltage (Vvf3).

[0094] And, the memory device (100) can perform a verification operation according to the verification information (91) for the second verification voltage (Vvf2) and the verification information (92) for the third verification voltage (Vvf3).

[0095] As illustrated in FIG. 8, when performing a verification operation or a compensation operation for the verification voltage, the memory device (100) may perform the verification operation by adding a correction value for the verification voltage equal to the offset bias as the program loop progresses, so that the level of the verification voltage increases. Alternatively, as illustrated in FIG. 9, the memory device (100) may perform the verification operation by subtracting a correction value for the verification voltage equal to the offset bias as the program loop progresses, so that the level of the verification voltage decreases.

[0097] FIG. 10 is a diagram illustrating control logic according to one embodiment of the present invention.

[0098] Referring to FIG. 10, the control logic (130) may include a compensation operation control unit (140) and a verification operation control unit (150).

[0099] The compensation operation control unit (140) may include a compensation information storage unit (141) and a program loop counter (142). The compensation information storage unit (141) may store compensation information including a start loop indicating the start time of the compensation operation, an end loop indicating the end time of the compensation operation, a step loop indicating the number of program loops applying the same compensation value, and an offset bias indicating the basic unit for changing the compensation value. Here, the compensation operation may mean an operation of determining a compensation value to correct each of a plurality of verification voltages used in the verification operation, and applying the determined compensation value to the corresponding plurality of verification voltages.

[0100] The compensation information storage unit (141) may include a compensation information table (70) illustrated in FIG. 7. Additionally, the compensation information storage unit (141) may include information regarding the verification voltage, such as information regarding the initial verification voltage or information regarding the optimal verification voltage. The compensation operation control unit (140) may obtain information regarding the verification voltage and compensation information from the compensation information storage unit (141), and the compensation operation control unit (140) may calculate a compensation value based on the obtained information regarding the verification voltage and compensation information. The compensation value may change according to the progress of the program operation, that is, the number of program loops. For example, the compensation operation control unit (140) may calculate a compensation value such that the compensation value for each of the multiple verification voltages increases as the number of program loops increases, based on compensation information corresponding to each of the multiple verification voltages. Alternatively, the compensation operation control unit (140) may calculate a compensation value such that the compensation value for each of the multiple verification voltages decreases as the number of program loops increases, based on compensation information corresponding to each of the multiple verification voltages. And, the compensation information storage unit (141) can store the number of program loops counted by the program loop counter (142) at regular intervals.

[0101] Additionally, the program loop counter (142) can count the number of program loops. The compensation operation control unit (140) can calculate a compensation value using the number of program loops counted by the program loop counter (142). According to one embodiment, the program loop counter (142) can count the number of program loops in addition to the number of program loops stored in the compensation information storage unit (141) before the program operation was stopped, when the program operation and verification operation are stopped in response to a stop command requesting the suspension of the program operation and then resumed by a resume command. At this time, if the program loop that was stopped at the time of the program operation is resumed, the program loop counter (142) does not count the corresponding program loop additionally. That is, the program loop of the resumed program operation is determined to be the same program loop as the program loop before the suspension, and the number of program loops is not counted additionally until the resumed program loop is terminated.

[0102] The program loop counter (142) can count the number of program loops by generating a constant signal whenever a program loop proceeds. The compensation operation control unit (140) may also count the number of program loops based on the signal received from the program loop counter (142). Specific details will be explained in detail with reference to the timing diagram of FIG. 11.

[0103] The verification operation control unit (150) can generate an operation voltage control signal so that an operation voltage, such as a verification voltage and a bitline precharge voltage for performing a program verification operation, is applied to a selected wordline or bitline. Additionally, the peripheral circuit (120) can generate an operation voltage including the verification voltage according to the operation voltage control signal of the verification operation control unit (150).

[0104] According to one embodiment, the verification operation control unit (150) can control the peripheral circuit (120) to perform a verification operation on selected memory cells among a plurality of memory cells based on a plurality of verification voltages and compensation values.

[0106] FIG. 11 is a timing diagram for explaining a compensation operation according to one embodiment of the present invention.

[0107] Referring to FIG. 11, a diagram illustrating a compensation operation over time is shown. Specifically, in response to a program command received from a memory controller (200), the memory device (100) can perform a program operation. Here, the program operation may refer to a program operation in a broad sense, including a program interval and a program verification interval.

[0108] And, when the program is running, the control logic (130) can generate a reset signal (RST). And, in response to the reset signal (RST), the compensation operation control unit (140) can load the compensation information stored in the compensation information storage unit (141) into the compensation operation control unit (140) to perform a compensation operation. When the compensation information is loaded into the compensation operation control unit (140), the compensation operation control unit (140) can start a compensation operation according to a start loop.

[0109] When a program voltage is applied to a selected word line or a selected memory cell, a pulse count signal may be generated by a program loop counter (142) that counts the number of program loops. The pulse count signal generated by the program loop counter (142) may be transmitted to a compensation operation control unit (140). Then, when the number of program loops counted by the program loop counter (142) reaches a start loop, the compensation operation control unit (140) may perform a compensation operation to correct the verification voltage used for the verification operation. For example, if the start loop of the compensation operation for the first verification voltage is 2, the compensation operation for the first verification voltage may start when the number of program loops becomes 2. The compensation operation may calculate the compensation value differently depending on the number of verification voltages or program loops, and the start loop of the compensation operation corresponding to the number of verification voltages may be set differently depending on each verification voltage.

[0110] The compensation operation control unit (140) can transmit a compensation control signal (CP ctrl) to the peripheral circuit (120) so that a program verification operation is performed based on a compensation value calculated according to the compensation operation and a previously set verification voltage. Subsequently, the compensation operation control unit (140) can perform a compensation operation according to compensation information including a step loop, an offset value, and an end loop. For example, if the step loop is 3, the compensation value can be increased or decreased according to the offset bias in the 5th program loop after the 2nd program loop in which the compensation operation started.

[0112] FIG. 12 is a drawing for explaining the operation method of a memory device according to one embodiment of the present invention.

[0113] In response to a program command received from a memory controller (200), the memory device (100) can perform a program operation. Here, the program operation may include a step of programming selected memory cells and a program verification step of verifying the programmed memory cells.

[0114] Specifically, the memory device (100) may include a plurality of memory cells and may program selected memory cells among the plurality of memory cells (S1210).

[0115] In the program verification step, the memory device (100) can verify the threshold voltage of selected memory cells using a plurality of verification voltages. According to one embodiment of the present invention, the memory device (100) can determine a plurality of compensation values ​​corresponding to each of the plurality of verification voltages based on compensation information (S1220). Then, the memory device (100) can verify the threshold voltage of selected memory cells based on the plurality of verification voltages and the plurality of compensation values ​​(S1230).

[0116] And, the program phase and the program verification phase constitute a program loop, and the program loop can be performed repeatedly until the program operation is completed. The memory device (100) can perform the program loop repeatedly until the program of the selected memory cells is completed (S1240).

[0117] According to one embodiment of the present invention, a plurality of reward values ​​may be set to increase or decrease as the program loop is repeatedly executed. Alternatively, the plurality of reward values ​​may be the same as the reward values ​​of the previous program loop.

[0119] FIG. 13 is a drawing for explaining a Solid State Drive (SSD) system according to an embodiment of the present invention.

[0120] Referring to FIG. 13, the SSD system (4000) may include a host (4100) and an SSD (4200). The SSD (4200) may exchange signals (SIG) with the host (4100) through a signal connector (4001) and receive power (PWR) through a power connector (4002). The SSD (4200) may include an SSD controller (4210), a plurality of flash memories (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0121] In an embodiment, the SSD controller (4210) can perform the function of the memory controller (200) described with reference to FIG. 1. The SSD controller (4210) can control a plurality of flash memories (4221 to 422n) in response to a signal (SIG) received from the host (4100). For example, the signal (SIG) may be signals based on the interface between the host (4100) and the SSD (4200). For example, the signal (SIG) may be a signal defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0122] The auxiliary power unit (4230) can be connected to the host (4100) via a power connector (4002). The auxiliary power unit (4230) can receive power (PWR) from the host (4100) and charge. The auxiliary power unit (4230) can provide power to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power unit (4230) may be located on the main board and provide auxiliary power to the SSD (4200).

[0123] The buffer memory (4240) can operate as a buffer memory of the SSD (4200). For example, the buffer memory (4240) can temporarily store data received from the host (4100) or data received from a plurality of flash memories (4221 to 422n), or temporarily store metadata (e.g., mapping tables) of the flash memories (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0125] 100: Memory device 200: Memory controller 1000: Storage device

Claims

Claim 1 A memory cell array comprising a plurality of memory cells connected to a plurality of word lines; a peripheral circuit that performs a program operation for selected memory cells among the plurality of memory cells and a verification operation for the program operation; a compensation operation control unit that determines a compensation value for a plurality of verification voltages according to the progress of the program operation and a target program state based on compensation information during the verification operation; and a verification operation control unit that controls the peripheral circuit to perform the verification operation for selected memory cells among the plurality of memory cells based on the plurality of verification voltages and the compensation value; wherein the compensation value is changed whenever a number of program loops corresponding to a step loop representing the number of program loops applying the same compensation value are executed. Claim 2 In claim 1, the compensation operation control unit is a memory device that determines, based on the compensation information corresponding to each of the plurality of verification voltages, that the compensation value for each of the plurality of verification voltages becomes equal or increases as the number of program loops increases. Claim 3 In claim 1, the compensation operation control unit is a memory device that determines, based on the compensation information corresponding to each of the plurality of verification voltages, that the compensation value for each of the plurality of verification voltages becomes equal or decreases as the number of program loops increases. Claim 4 A memory device according to claim 1, wherein the compensation information comprises a start loop indicating the start time of a compensation operation that corrects the compensation value to the plurality of verification voltages, a termination loop indicating the end time of the compensation operation, and an offset value indicating a basic unit that changes the compensation value. Claim 5 A memory device according to claim 1, wherein the compensation operation control unit comprises: a program loop counter that counts the number of program loops indicating the progress of the program operation; and a compensation information storage unit that stores the compensation information corresponding to each of the plurality of verification voltages and stores the number of program loops at regular intervals. Claim 6 In claim 5, the memory device wherein the compensation operation control unit suspends the program operation and the verification operation in response to a suspension command requesting the suspension of the program operation, and resumes the program operation and the verification operation in response to a resumption command requesting the resumption of the program operation, determines the compensation value for the plurality of verification voltages based on the number of program loops stored in the compensation information storage unit. Claim 7 A method of operation of a memory device comprising: a step of performing a program operation to program selected memory cells among a plurality of memory cells using a program voltage; and a step of performing a program verification operation to verify the threshold voltage of the selected memory cells using a plurality of verification voltages; wherein the step of performing the program verification operation determines a plurality of compensation values ​​corresponding to each of the plurality of verification voltages based on compensation information, verifies the threshold voltage of the selected memory cells based on the plurality of verification voltages and the plurality of compensation values, and the compensation value changes whenever a number of program loops corresponding to a step loop representing the number of program loops applying the same compensation value is performed. Claim 8 A method of operation of a memory device according to claim 7, further comprising the step of repeatedly performing a program loop including the program operation and the program verification operation until the program of the selected memory cells is completed. Claim 9 In claim 8, the above-mentioned plurality of compensation values ​​increase as the program loop is repeated, or a method of operation of a memory device that is identical to the compensation values ​​of the previous program loop. Claim 10 In claim 8, the above-mentioned plurality of compensation values ​​decrease as the program loop is repeated, or a method of operation of a memory device that is the same as the compensation values ​​of the previous program loop. Claim 11 A method of operation of a memory device according to claim 7, wherein the compensation information comprises a start loop indicating a start time of a compensation operation that corrects the compensation value to the plurality of verification voltages, a termination loop indicating a end time of the compensation operation, and an offset value indicating a basic unit that changes the compensation value. Claim 12 A method of operation of a memory device according to claim 7, further comprising: a step of counting a number of program loops indicating the number of times a program loop including the program operation and the program verification operation is performed; and a step of storing the number of program loops at regular intervals. Claim 13 A method of operation of a memory device according to claim 12, further comprising: a step of suspending the program operation and the verification operation in response to a suspension command requesting the suspension of the program operation; and a step of resuming the program operation and the verification operation in response to a resumption command requesting the resumption of the program operation, wherein the resumption step determines the compensation value for the plurality of verification voltages based on the number of stored program loops. Claim 14 A storage device comprising: a memory device including a plurality of memory cells connected to a plurality of word lines; and a memory controller for controlling the memory device; wherein the memory device comprises a peripheral circuit that performs a program operation for selected memory cells among the plurality of memory cells and a verification operation for the program operation, and a control logic that, during the verification operation, determines a compensation value for a plurality of verification voltages according to the progress of the program operation and a target program state based on compensation information, and controls the peripheral circuit to perform the verification operation based on the plurality of verification voltages and the compensation value, wherein the compensation value is changed whenever a number of program loops corresponding to a step loop representing the number of program loops applying the same compensation value are executed. Claim 15 In claim 14, the control logic is a storage device that determines, based on the compensation information corresponding to each of the plurality of verification voltages, that the compensation value for each of the plurality of verification voltages becomes equal or increases as the number of program loops increases. Claim 16 In claim 14, the control logic is a storage device that determines, based on the compensation information corresponding to each of the plurality of verification voltages, that the compensation value for each of the plurality of verification voltages becomes equal or decreases as the number of program loops increases. Claim 17 In claim 14, the compensation information comprises a storage device including a start loop indicating the start time of a compensation operation that corrects the compensation value to the plurality of verification voltages, a termination loop indicating the end time of the compensation operation, and an offset value indicating a basic unit that changes the compensation value. Claim 18 In claim 14, the control logic counts the number of program loops indicating the progress of the program operation, stores the compensation information corresponding to each of the plurality of verification voltages, and stores the number of program loops at regular intervals. Claim 19 A storage device according to claim 18, wherein the control logic suspends the program operation and the verification operation in response to a suspension command requesting the suspension of the program operation, and resumes the program operation and the verification operation in response to a resumption command requesting the resumption of the program operation, and determines the compensation value for the plurality of verification voltages based on the number of program loops stored in the control logic.

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