Non-volatile semiconductor memory device

Abstract

A non-volatile semiconductor memory device includes a memory cell array, a read and write circuit, and control logic. The memory cell array includes a plurality of non-volatile memory cells. The read and write circuit performs a program operation or a read operation on selected non-volatile memory cells among the plurality of non-volatile memory cells. The control logic controls the operation of the read and write circuit. The read and write circuit includes at least one capacitor for storing bit data.

Description

Technology Field

[0001] The present invention relates to a non-volatile semiconductor memory device, and more specifically, to a non-volatile semiconductor memory device in which the area occupied by read and write circuits is reduced. Background Technology

[0002] A semiconductor memory device may be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. A three-dimensional memory device is a memory device designed to overcome the integration density limitations of a two-dimensional memory device and may include a plurality of memory cells stacked vertically on a semiconductor substrate. A non-volatile semiconductor memory device is implemented such that a plurality of memory cells are non-volatile memory cells. Prior art literature

[65535] Republic of Korea Published Patent Application No. 10-2010-0013960 The problem to be solved

[0003] An embodiment of the present invention provides a non-volatile semiconductor memory device that reduces the area occupied by read and write circuits. means of solving the problem

[0004] A non-volatile semiconductor memory device according to an embodiment of the present invention includes a memory cell array, a read and write circuit, and control logic. The memory cell array includes a plurality of non-volatile memory cells. The read and write circuit performs a program operation or a read operation for selected non-volatile memory cells among the plurality of non-volatile memory cells. The control logic controls the operation of the read and write circuit. The read and write circuit includes at least one capacitor for storing bit data.

[0005] In one embodiment, the read and write circuit may include a plurality of page buffers, each connected to the memory cell array via a plurality of bit lines. Each of the plurality of page buffers may include an internal operation circuit and a temporary storage circuit. The internal operation circuit may be connected to a corresponding bit line among the plurality of bit lines. The temporary storage circuit may be connected to the internal operation circuit. The temporary storage circuit may include at least one control transistor and at least one capacitor. Effects of the invention

[0006] This technology can provide a non-volatile semiconductor memory device that reduces the area occupied by read and write circuits. Brief explanation of the drawing

[0007] FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention. Figure 2 is a diagram showing an example of a memory cell array of Figure 1. FIG. 3 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 2. FIG. 4 is a circuit diagram showing an example of one memory block (BLKb) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 1. FIG. 5 is a block diagram showing an exemplary embodiment of the page buffer (PB1) of FIG. 1. FIG. 6 is a circuit diagram showing an exemplary embodiment of the internal operation circuit (210) of FIG. 5. FIG. 7 is a circuit diagram showing an example (230a) of the temporary storage circuit of FIG. 5. FIG. 8 is a circuit diagram showing another example (230b) of the temporary storage circuit of FIG. 5. FIGS. 9a and FIGS. 9b are drawings for explaining the operation of storing bit data in the first storage unit (231) of FIG. 8. FIGS. 10a and FIGS. 10b are drawings for explaining the operation of reading bit data of “1” stored in the first storage unit (231) of FIG. 8. FIGS. 11a and FIGS. 11b are drawings for explaining the operation of reading “0” bit data stored in the first storage unit (231) of FIG. 8. FIG. 12 is a block diagram showing an application example (2000) of a storage device including a semiconductor memory device according to an embodiment of the present invention. FIG. 13 is a block diagram showing a computing system including a storage device described with reference to FIG. 12. Specific details for implementing the invention

[0008] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0010] FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention.

[0011] Referring to FIG. 1, the semiconductor memory device (100) includes a memory cell array (110), an address decoder (120), a read and write circuit (130), control logic (140), and a voltage generation unit (150).

[0012] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (120) via word lines (WL). The plurality of memory blocks (BLK1 to BLKz) are connected to a read and write circuit (130) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure. The memory cell array (110) may be composed of a memory cell array with a two-dimensional structure. According to an embodiment, the memory cell array (110) may be composed of a memory cell array with a three-dimensional structure.

[0013] Each of the plurality of memory cells included in the memory cell array can store at least 1 bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a single-level cell (SLC) that stores 1 bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a multi-level cell (MLC) that stores 2 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a memory cell that stores 3 bits or more of data.

[0014] In one embodiment, each of the plurality of memory cells included in the memory cell array may be a non-volatile memory cell. When the plurality of memory cells included in the memory cell array are composed of non-volatile memory cells, data stored in the memory cells can be maintained even if the power supply to the semiconductor memory device (100) is interrupted.

[0015] The address decoder (120), the read and write circuit (130), and the control logic (140) operate as peripheral circuits that drive the memory cell array (110). The address decoder (120) is connected to the memory cell array (110) via word lines (WL). The address decoder (120) is configured to operate in response to the control of the control logic (140). The address decoder (120) receives an address (ADDR). The address (ADDR) may include a block address, a column address, or a row address, etc.

[0016] The address decoder (120) is configured to decode a block address among the received addresses. The address decoder (120) selects at least one memory block according to the decoded block address. Additionally, during a read operation, when a read voltage is applied, the address decoder (120) applies a read voltage (Vread) generated by the voltage generator (150) to the selected word line among the selected memory blocks and applies a pass voltage (Vpass) to the remaining unselected word lines. Additionally, during a program verification operation, when a verification voltage generated by the voltage generator (150) is applied to the selected word line among the selected memory blocks and applies a pass voltage (Vpass) to the remaining unselected word lines.

[0017] The address decoder (120) is configured to decode the column address among the received addresses. The address decoder (120) transmits the decoded column address to the read and write circuit (130).

[0018] The read operation and program operation of the semiconductor memory device (100) are performed in page units. The address received upon request for the read operation and program operation includes a block address, a row address, and a column address. The address decoder (120) selects one memory block and one word line according to the block address and row address. The column address is decoded by the address decoder (120) and provided to the read and write circuit (130).

[0019] The address decoder (120) may include a block decoder, a row decoder, a column decoder, and an address buffer, etc.

[0020] The read and write circuit (130) includes a plurality of page buffers (PB1 to PBm). The read and write circuit (130) can operate as a “read circuit” during a read operation of the memory cell array (110) and as a “write circuit” during a write operation. The plurality of page buffers (PB1 to PBm) are connected to the memory cell array (110) through bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) continuously supply sensing current to the bit lines connected to the memory cells to sense the threshold voltage of the memory cells during a read operation and a program verification operation, and latches the sensing data by detecting through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell. The read and write circuit (130) operates in response to page buffer control signals output from the control logic (140).

[0021] The read and write circuit (130) senses data in a memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to an input / output buffer (not shown) of a semiconductor memory device (100). As an exemplary embodiment, the read and write circuit (130) may include a column selection circuit, etc., in addition to page buffers (or page registers).

[0022] The control logic (140) is connected to the address decoder (120), the read and write circuit (130), and the voltage generation unit (150). The control logic (140) receives a command (CMD) and a control signal (CTRL) through an input / output buffer (not shown) of the semiconductor memory device (100). The control logic (140) is configured to control the general operation of the semiconductor memory device (100) in response to the control signal (CTRL). Additionally, the control logic (140) outputs a control signal to adjust the sensing node precharge potential level of a plurality of page buffers (PB1~PBm). The control logic (140) can control the read and write circuit (130) to perform a read operation of the memory cell array (110).

[0024] Figure 2 is a diagram showing an example of a memory cell array of Figure 1.

[0025] Referring to FIG. 2, the memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described in more detail with reference to FIG. 3.

[0027] FIG. 3 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 2.

[0028] Referring to FIG. 3, a memory block (BLKa) includes multiple cell strings (CS11–CS1m, CS21–CS2m). Within the memory block (BLKa), m cell strings are arranged in the row direction (i.e., +X direction). In FIG. 3, two cell strings are shown arranged in the column direction (i.e., +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in the column direction.

[0029] Each of the plurality of cell strings (CS11~CS1m, CS21~CS2m) includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), and at least one drain select transistor (DST).

[0030] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0031] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCn).

[0032] As an example, source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 3, source select transistors of cell strings (CS11–CS1m) of the first row are connected to a first source select line (SSL1). Source select transistors of cell strings (CS21–CS2m) of the second row are connected to a second source select line (SSL2).

[0033] As another embodiment, the source selection transistors of the cell strings (CS11~CS1m, CS21~CS2m) can be commonly connected to a single source selection line.

[0034] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0035] The gates of the first to nth memory cells (MC1~MCn) of each cell string are each connected to the first to nth word lines (WL1~WLn).

[0036] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1 to MCn). The drain select transistors (DST) of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11 to CS1m) are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21 to CS2m) are connected to the second drain select line (DSL2).

[0037] Cell strings arranged in a column direction are connected to a bit line extending in a column direction. In FIG. 3, the cell strings of the first column (CS11, CS21) are connected to the first bit line (BL1). The cell strings of the m-th column (CS1m, CS2m) are connected to the m-th bit line (BLm).

[0038] Memory cells connected to the same word line within cell strings arranged in a row direction constitute one page. For example, among the cell strings (CS11–CS1m) of the first row, memory cells connected to the first word line (WL1) constitute one page. Among the cell strings (CS21–CS2m) of the second row, memory cells connected to the first word line (WL1) constitute another page. By selecting either of the drain selection lines (DSL1, DSL2), cell strings arranged in a row direction will be selected. By selecting any of the word lines (WL1–WLn), one page among the selected cell strings will be selected.

[0039] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the odd-numbered cell strings may be connected to the odd bit lines.

[0040] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCn). Or, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MC1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKa) is improved, while the size, i.e., the physical dimensions, of the memory block (BLKa) increases. As fewer dummy memory cells are provided, the size, i.e. the physical dimensions, of the memory block (BLKa) decrease, while the reliability of operation for the memory block (BLKa) may decrease.

[0041] Referring to FIG. 3, each of the plurality of cell strings (CS11–CS1m, CS21–CS2m) may be formed in an “I” shape between the bit lines (BL1–BLm) and the common source line (CSL). However, this is an example, and other shapes of memory blocks are also possible. For example, each of the plurality of cell strings included in the memory block may be formed in a ‘U’ shape. In this case, each cell string may include a pipe transistor. Additionally, among the memory cells included in each cell string, the memory cells of the first group may be serially connected between a source select transistor and a pipe transistor. That is, the memory cells of the first group and the memory cells of the second group may be connected through the pipe transistor. Meanwhile, among the memory cells included in each cell string, the memory cells of the first group may be serially connected between a pipe transistor and a drain select transistor. The gate of the pipe transistor of each cell string may be connected to a pipeline.

[0043] FIG. 4 is a circuit diagram showing an example of one memory block (BLKb) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 1.

[0044] Referring to FIG. 4, a memory block (BKLb) includes a plurality of cell strings (CS1 to CSm). The plurality of cell strings (CS1 to CSm) can each be connected to a plurality of bit lines (BL1 to BLm). Each of the plurality of cell strings (CS1 to CSm) includes at least one source select transistor (SST), first to nth memory cells (MC1 to MCn), and at least one drain select transistor (DST).

[0045] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0046] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCn).

[0047] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0048] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1~MCn).

[0049] Memory cells connected to the same word line constitute one page. Cell strings (CS1–CSm) will be selected by selecting the drain selection line (DSL). One page of the selected cell strings will be selected by selecting any one of the word lines (WL1–WLn).

[0050] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). Among the cell strings (CS1~CSm), the even-numbered cell strings may be connected to the even-bit lines, and the odd-numbered cell strings may be connected to the odd-bit lines.

[0052] FIG. 5 is a block diagram showing an exemplary embodiment of the page buffer (PB1) of FIG. 1.

[0053] The page buffer illustrated in FIG. 5 may be the first page buffer (PB1) among the page buffers (PB1 to PBm) included in the read and write circuit (130) of FIG. 1. Since the plurality of page buffers (PB1 to PBm) included in the read and write circuit (130) can be configured similarly to each other, one of the page buffers will be described as an example.

[0054] The page buffer (PB1) may include an internal operation circuit (210) connected to a bit line (BL1) and a temporary storage circuit (230) connected to the internal operation circuit (210) through a sensing node (SO) and a comparison node (COM). The internal operation circuit (210) can control the voltage of the bit line during operation on the memory cell array. Specifically, during a program operation, the internal operation circuit (210) controls the voltage of the bit line (BL1) to program the memory cell connected to the bit line (BL1). Additionally, during a read operation, the internal operation circuit (210) controls the voltage of the bit line (BL1) to read the data stored in the memory cell connected to the bit line (BL1). An exemplary embodiment of the internal operation circuit (210) will be described with reference to FIG. 6.

[0055] The temporary storage circuit (230) temporarily stores bit data. Specifically, when programming a memory cell connected to a bit line (BL1), the temporary storage circuit (230) can temporarily store bit data to be stored in the memory cell connected to the bit line (BL1). Additionally, the temporary storage circuit (230) can store the verification result for the memory cell connected to the bit line (BL1) as bit data.

[0056] Meanwhile, when a read operation is performed on a memory cell connected to the bit line (BL1), the temporary storage circuit (230) can store the threshold voltage sensing result using at least one read voltage as bit data. In other words, the temporary storage circuit can store bit data indicating whether the threshold voltage of the memory cell connected to the bit line (BL1) is greater than the read voltage.

[0057] To store bit data, the temporary storage circuit (230) may include at least one bit storage element. Exemplary embodiments of the temporary storage circuit (230) will be described with reference to FIGS. 7 and FIGS. 8.

[0059] FIG. 6 is a circuit diagram showing an exemplary embodiment of the internal operation circuit (210) of FIG. 5.

[0060] The internal operation circuit (210) can operate in response to a signal output from the control logic (140). The signals described below (PB_SENSE, SA_PRECH_N, SA_SENSE, SA_CSOC, SA_DISCH, PRECHSO_N) may be control signals output from the control logic (140). The internal operation circuit (210) is described in detail as follows.

[0061] Referring to FIG. 6, the internal operation circuit (210) is connected to a memory cell through a bit line (BL1) and can perform a bit line precharge operation by charging the bit line (BL1) with a charge supplied from the power supply voltage (VCORE) through the first to fifth NMOS transistors (N1 to N5) and the first to third PMOS transistors (P1 to P3). Additionally, the internal operation circuit (210) can discharge the charge charged to the bit line (BL1) to the ground voltage through the first NMOS transistor (N1), the fourth NMOS transistor (N4), and the fifth NMOS transistor (N5).

[0062] The first NMOS transistor (N1) is connected between the bit line (BL1) and the common node (CSO). The first PMOS transistor (P1) is connected between the power supply voltage (VCORE) and the sense amplifier node (SAN). The second NMOS transistor (N2) is connected between the common node (CSO) and the sense amplifier node (SAN). The second PMOS transistor (P2) is connected between the sense amplifier node (SAN) and the sensing node (SO). The third NMOS transistor (N3) is connected between the sensing node (SO) and the common node (CSO). The third PMOS transistor (P3) is connected between the power supply voltage (VCORE) and the sensing node (SO). The fourth and fifth transistors (N4, N5) are connected in series between the common node (CSO) and the ground voltage.

[0063] The first NMOS transistor (N1) is controlled by a page buffer sensing signal (PB_SENSE), the second NMOS transistor (N2) is controlled by a current sensing signal (SA_CSOC), and the third NMOS transistor (N3) is controlled by a sense amplifier sensing signal (SA_SENSE). Additionally, the fourth NMOS transistor (N4) is controlled by a sense amplifier discharge signal (SA_DISCH), and the fifth NMOS transistor (N5) and the first PMOS transistor (P1) are controlled by the node (QS) voltage of the sensing latch circuit (LS). The second PMOS transistor (P2) is controlled by a sense amplifier precharge signal (SA_PRECH_N), and the third PMOS transistor (P3) is controlled by a sensing node precharge signal (PRECHSO_N). That is, a page buffer sensing signal (PB_SENSE) is applied to the gate of the first NMOS transistor (N1), a current sensing signal (SA_CSOC) is applied to the gate of the second NMOS transistor (N2), and a sense amplifier sensing signal (SA_SENSE) is applied to the gate of the third NMOS transistor (N3). Additionally, a sense amplifier discharge signal (SA_DISCH) is applied to the gate of the fourth NMOS transistor (N4), and the node (QS) voltage of the sensing latch circuit (LS) is applied to the gates of the fifth NMOS transistor (N5) and the first PMOS transistor (P1). A sense amplifier precharge signal (SA_PRECH_N) is applied to the gate of the second PMOS transistor (P2), and a sensing node precharge signal (PRECHSO_N) is applied to the gate of the third PMOS transistor (P3).

[0064] The sensing latch circuit (LS) may include two inverters (not shown) connected to the node (QS), a sixth NMOS transistor (N6) acting as a reset transistor to control the voltage of the node (QS), and a seventh NMOS transistor (N7) acting as a set transistor. In one embodiment, the sensing latch circuit (LS) may be implemented as an SRAM structure including six transistors. The sixth NMOS transistor (N6) and the seventh NMOS transistor (N7) are each controlled by a reset control signal (RST_S) and a set control signal (SET_S), respectively. Meanwhile, the sixth NMOS transistor (N6) and the seventh NMOS transistor (N7) may be connected to the eighth NMOS transistor (N8) through a comparison node (COM). The eighth NMOS transistor (N8) is controlled by a page buffer reset control signal (PBRST) and may be connected to the ground voltage.

[0066] FIG. 7 is a circuit diagram showing an example (230a) of the temporary storage circuit of FIG. 5.

[0067] Referring to FIG. 7, the temporary storage circuit (230a) includes first to third latch circuits (L1, L2, L3) and a main latch circuit (LM). Bit data stored in the first latch circuit (L1) controls the operation of the 10th NMOS transistor (N10). The 10th NMOS transistor (N10) is connected to a sensing node (SO) through the 9th NMOS transistor (N9). The 9th NMOS transistor (N9) is controlled by a first transfer control signal (TRAN1).

[0068] Meanwhile, the first latch circuit (L1) includes a first NMOS transistor (N11) and a second NMOS transistor (N12). The first NMOS transistor (N11) and the second NMOS transistor (N12) are connected to a comparison node (COM). Additionally, a third NMOS transistor (N13) is connected between the comparison node (COM) and the ground voltage. The third NMOS transistor (N13) is controlled by the voltage of the sensing node (SO).

[0069] The bit data stored in the second latch circuit (L2) controls the operation of the 15th NMOS transistor (N15). The 15th NMOS transistor (N15) is connected to the sensing node (SO) through the 14th NMOS transistor (N14). The 14th NMOS transistor (N14) is controlled by the second transfer control signal (TRAN2).

[0070] Meanwhile, the second latch circuit (L2) includes a 16th NMOS transistor (N16) and a 17th NMOS transistor (N17). The 16th NMOS transistor (N16) and the 17th NMOS transistor (N17) are connected to a 22nd NMOS transistor (N22). The 22nd NMOS transistor (N22) is also connected to ground voltage and is controlled by the voltage of the sensing node (SO).

[0071] The bit data stored in the third latch circuit (L3) controls the operation of the 19th NMOS transistor (N19). The 19th NMOS transistor (N19) is connected to the sensing node (SO) through the 18th NMOS transistor (N18). The 18th NMOS transistor (N18) is controlled by the third transfer control signal (TRAN3).

[0072] Meanwhile, the third latch circuit (L3) includes a 20th NMOS transistor (N20) and a 21st NMOS transistor (N21). The 20th NMOS transistor (N20) and the 21st NMOS transistor (N21) are connected to a 22nd NMOS transistor (N22).

[0073] Bit data stored in the main latch circuit (LM) controls the operation of the 24th NMOS transistor (N24). The 24th NMOS transistor (N24) is connected to the sensing node (SO) through the 23rd NMOS transistor (N23). The 23rd NMOS transistor (N23) is controlled by the main transfer control signal (TRANM).

[0074] Meanwhile, the main latch circuit (LM) includes a 25th NMOS transistor (N25) and a 26th NMOS transistor (N26). The 25th NMOS transistor (N25) and the 26th NMOS transistor (N26) are connected to a 27th NMOS transistor (N27). The 27th NMOS transistor (N27) is also connected to ground voltage and is controlled by the voltage of the sensing node (SO).

[0075] The temporary storage circuit (230a) illustrated in FIG. 7 includes four latch circuits (L1, L2, L3, LM) and additional transistors for controlling them. Each of the four latch circuits (L1, L2, L3, LM) illustrated in FIG. 7 can be implemented as an SRAM structure containing six transistors. Therefore, implementing the temporary storage circuit (230a) illustrated in FIG. 7 requires a large number of transistors.

[0076] According to one embodiment of the present invention, a DRAM is used instead of an SRAM in the temporary storage circuit. A DRAM is a type of volatile memory device, and when the power supply to the DRAM is cut off, the data stored in the DRAM is lost. When a DRAM is used to store bit data, it can be implemented with one transistor and one capacitor. Therefore, the area required to implement the semiconductor memory device (100) can be reduced.

[0078] FIG. 8 is a circuit diagram showing another example (230b) of the temporary storage circuit of FIG. 5.

[0079] Referring to FIG. 8, the temporary storage circuit (230b) includes a sensing amplifier (235) and a plurality of storage units (231, 232). FIG. 8 illustrates an embodiment in which the temporary storage circuit (230b) includes two storage units (231, 232), but the present invention is not limited thereto. That is, a temporary storage circuit including various numbers of storage units may be implemented as needed.

[0080] The sensing amplifier (235) may include four NMOS transistors (N31, N32, N33, N34) and two PMOS transistors (P21, P22). The 34th NMOS transistor (N34) may be connected between the comparison node (COM) and ground. The 34th NMOS transistor (N34) may discharge the comparison node (COM) according to the voltage of the sensing node (SO).

[0081] Meanwhile, the sensing amplifier (235) is connected to the sensing node (SO) and the comparison node (COM). Additionally, the sensing amplifier (235) is connected to the first power supply (V1) and the second power supply (V2). An external voltage may be supplied through the first power supply (V1) and the second power supply (V2). Meanwhile, a control signal (EQ) may be transmitted to the sensing amplifier (235) from the control logic (140) of FIG. 1. The control signal (EQ) may be used to control the voltages of the sensing node (SO) and the comparison node (COM) to be equal.

[0082] Each of the plurality of storage units (231, 232) included in the temporary storage circuit (230b) includes an NMOS transistor (N35, N36) and a capacitor (C1, C2). That is, each of the plurality of storage units (231, 232) can be implemented as a DRAM structure.

[0083] As illustrated in FIG. 8, since each of the storage units (231, 232) used to store bit data includes only one transistor and one capacitor, the area required for implementing the page buffer circuit can be reduced.

[0085] FIGS. 9a and 9b are drawings illustrating the operation of storing bit data in the first storage unit (231) of FIG. 8. For convenience of discussion, components other than the sensing node (SO) and the first storage unit (231) are omitted from FIGS. 9a and 9b.

[0086] Referring to FIG. 9a, when the voltage of the sensing node (SO) is relatively high voltage (Va), if a turn-on voltage (VON) is applied to the gate of the 35th NMOS transistor (N35) included in the first storage unit (231), the first capacitor (C1) included in the first storage unit (231) is charged to high voltage (Va).

[0087] Meanwhile, referring to FIG. 9b, when the voltage of the sensing node (SO) is ground voltage, i.e., 0V, when a turn-on voltage (VON) is applied to the gate of the 35th NMOS transistor (N35) included in the first storage unit (231), the first capacitor (C1) included in the first storage unit (231) is discharged to 0V.

[0089] FIGS. 10a and FIGS. 10b are drawings for explaining the operation of reading bit data of “1” stored in the first storage unit (231) of FIG. 8.

[0090] Referring to FIG. 10a, the first capacitor (C1) of the first storage unit (231) is charged to a high voltage (Va). When the 35th NMOS transistor (N35) is turned on while the voltages of the sensing node (SO) and the comparison node (COM) are set to ½VCC, the voltage of the sensing node (SO) rises to ½VCC+ΔV. Accordingly, the 33rd NMOS transistor (N33) and the 21st PMOS transistor (P21) are turned on. Subsequently, the voltages of the node (No1) and the node (No2) are controlled to the power supply voltage (VCORE) and ground voltage (VSS), respectively.

[0091] Referring to FIG. 10b, when the first capacitor (C1) of the first storage unit (231) is charged to a high voltage (Va) and the 35th NMOS transistor (N35) is turned on, the voltage changes of the sensing node (SO), the comparison node (COM), and the first capacitor (C1) are illustrated. In FIG. 10b, the voltage of the first capacitor (C1) is shown as VC1. Initially, the voltage (VC1) of the first capacitor (C1) may be a high voltage (Va). As the voltage of the first selection signal (SEL1) is raised to the turn-on voltage (VON), the 35th NMOS transistor (N35) is turned on. Accordingly, the voltage (VC1) of the first capacitor (C1) decreases, and the voltage of the sensing node (SO) increases slightly. The voltage difference (ΔV) between the sensing node (SO) and the comparison node (COM) is amplified, causing the voltage of the sensing node (SO) to rise to the power supply voltage (VCORE) and the voltage of the comparison node (COM) to fall to the ground voltage (VSS). Additionally, the voltage (VC1) of the first capacitor (C1) can also rise to the power supply voltage (Vcore).

[0093] FIGS. 11a and FIGS. 11b are drawings for explaining the operation of reading “0” bit data stored in the first storage unit (231) of FIG. 8.

[0094] Referring to FIG. 11a, the first capacitor (C1) of the first storage unit (231) is discharged to 0V. When the 35th NMOS transistor (N35) is turned on while the voltages of the sensing node (SO) and the comparison node (COM) are set to ½VCC, the voltage of the sensing node (SO) drops to ½VCC-ΔV. Accordingly, the 32nd NMOS transistor (N32) and the 22nd PMOS transistor (P22) are turned on. Subsequently, the voltages of the node (No1) and the node (No2) are controlled to the power supply voltage (Vcore) and ground voltage (VSS), respectively.

[0095] Referring to FIG. 11b, when the first capacitor (C1) of the first storage unit (231) is discharged to 0V, the voltage changes of the sensing node (SO), the comparison node (COM), and the first capacitor (C1) are illustrated. As the voltage of the first selection signal (SEL1) is raised to the turn-on voltage (VON), the 35th NMOS transistor (N35) is turned on. Accordingly, the voltage (VC1) of the first capacitor (C1) rises, and the voltage of the sensing node (SO) drops slightly. As the voltage difference (ΔV) between the sensing node (SO) and the comparison node (COM) is amplified, the voltage of the sensing node (SO) drops to the ground voltage (VSS), and the voltage of the comparison node (COM) rises to the power supply voltage (VCORE). Additionally, the voltage (VC1) of the first capacitor (C1) also drops to the ground voltage (VSS).

[0096] As illustrated in FIGS. 10b and 11b, after a sensing operation in which the voltage difference (ΔV) between the sensing node (SO) and the comparison node (COM) is amplified based on the voltage (VC1) of the first capacitor (C1), the voltage (VC1) of the first capacitor (C1) recovers to the voltage prior to sensing. Therefore, the value of the bit data stored in the first storage unit (231) is maintained even after the sensing operation.

[0098] FIG. 12 is a block diagram showing an application example (2000) of a storage device including a semiconductor memory device according to an embodiment of the present invention.

[0099] Referring to FIG. 12, the storage device (2000) includes a semiconductor memory device (2100) and a controller (2200). The semiconductor memory device (2100) includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0100] In FIG. 12, a plurality of groups are each shown communicating with the controller (2200) through the first to k channels (CH1~CHk). Each semiconductor memory chip will be configured and operated in the same way as one of the semiconductor memory devices (100) described with reference to FIG. 1.

[0101] Each group is configured to communicate with the controller (2200) through a single common channel. The controller (2200) is configured to control multiple semiconductor memory chips of the semiconductor memory device (2100) through multiple channels (CH1~CHk).

[0102] In FIG. 12, it is described that multiple semiconductor memory chips are connected to a single channel. However, it will be understood that the storage device (2000) can be modified so that a single semiconductor memory chip is connected to a single channel.

[0104] FIG. 13 is a block diagram showing a computing system including a storage device described with reference to FIG. 12.

[0105] Referring to FIG. 13, the computing system (3000) includes a central processing unit (3100), RAM (3200, RAM, Random Access Memory), a user interface (3300), a power supply (3400), a system bus (3500), and a storage device (2000).

[0106] The storage device (2000) is electrically connected to the central processing unit (3100), RAM (3200), user interface (3300), and power supply (3400) via the system bus (3500). Data provided through the user interface (3300) or processed by the central processing unit (3100) is stored in the storage device (2000).

[0107] In FIG. 13, the semiconductor memory chip (2100) is shown as being connected to the system bus (3500) via the controller (2200). However, the semiconductor memory chip (2100) may be configured to be directly connected to the system bus (3500). In this case, the function of the controller (2200) will be performed by the central processing unit (3100) and the RAM (3200). Explanation of the symbols

[0108] 100: Semiconductor memory device 110: Memory cell array 120: Address decoder 130: Read and write circuit 140: Control logic 150: Voltage generation unit

Claims

Claim 1 A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of nonvolatile memory cells; a read and write circuit that performs a program operation or a read operation for selected nonvolatile memory cells among the plurality of nonvolatile memory cells; and a control logic that controls the operation of the read and write circuit, wherein the read and write circuit includes at least one capacitor for storing bit data, and the read and write circuit includes a plurality of page buffers each connected to the memory cell array through a plurality of bit lines, and each of the plurality of page buffers includes an internal operation circuit connected to a corresponding bit line among the plurality of bit lines; and a temporary storage circuit connected to the internal operation circuit, wherein the temporary storage circuit includes at least one control transistor and the at least one capacitor, and the internal operation circuit includes a first transistor connected between the bit line and a first node; a second transistor connected between the power supply voltage and a second node; a third transistor connected between the first node and the second node; a fourth transistor connected between the second node and the third node; and a fifth transistor connected between the first node and the third node. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 A non-volatile semiconductor memory device according to claim 1, wherein the first transistor, the third transistor, and the fifth transistor are NMOS transistors, and the second transistor and the fourth transistor are PMOS transistors. Claim 6 A non-volatile semiconductor memory device according to claim 5, further comprising: a sixth transistor connected to the first node; a seventh transistor connected in series between the sixth transistor and the ground voltage; an eighth transistor connected between the power supply voltage and the third node; and a latch circuit connected to the gate terminal of the second transistor and the gate terminal of the seventh transistor. Claim 7 A non-volatile semiconductor memory device according to claim 6, wherein the sixth transistor and the seventh transistor are NMOS transistors, and the eighth transistor is a PMOS transistor. Claim 8 In claim 6, the latch circuit comprises: a latch; a ninth transistor connected to the latch through a fourth node; and a tenth transistor connected to the latch through a fifth node, wherein the fourth node is connected to the gate terminal of the second transistor and the gate terminal of the seventh transistor, a non-volatile semiconductor memory device. Claim 9 A non-volatile semiconductor memory device according to claim 8, further comprising a 11th transistor connected to the 9th and 10th transistors through a 6th node. Claim 10 In claim 9, the temporary storage circuit is connected to the internal operation circuit through the third node and the sixth node, a non-volatile semiconductor memory device. Claim 11 A non-volatile semiconductor memory device according to claim 9, wherein at least one control transistor is connected to the third node and at least one capacitor is connected between the control transistor and the ground voltage. Claim 12 In claim 11, the temporary storage circuit further comprises a sensing amplifier connected to the third node and the sixth node, a non-volatile semiconductor memory device. Claim 13 A non-volatile semiconductor memory device according to claim 12, wherein, during a read operation for selected non-volatile memory cells, a voltage corresponding to the third node is charged to the capacitor. Claim 14 A non-volatile semiconductor memory device according to claim 12, wherein, during a program operation for selected non-volatile memory cells, the voltage charged in the capacitor is transferred to the third node. Claim 15 A non-volatile semiconductor memory device according to claim 12, wherein the sensing amplifier comprises: a 12th transistor connected between the 3rd node and the 6th node; 13th and 14th transistors connected in series between the 3rd node and the 6th node; 15th and 16th transistors connected in series between the 3rd node and the 6th node; and a 17th transistor connected between the 6th node and ground. Claim 16 A non-volatile semiconductor memory device according to claim 15, wherein the 12th transistor, the 13th transistor, the 14th transistor, and the 17th transistor are NMOS transistors, and the 15th transistor and the 16th transistor are PMOS transistors. Claim 17 A non-volatile semiconductor memory device according to claim 16, wherein a control signal received from the control logic is applied to the gate of the 12th transistor, the gates of the 13th transistor and the 15th transistor are connected to the 6th node, and the gates of the 14th transistor, the 16th transistor and the 17th transistor are connected to the 3rd node.

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