Stacked Light-Emitting Diode

Abstract

A stacked light-emitting diode device according to embodiments of the present invention comprises: a substrate; a first light-emitting layer disposed on the substrate; a tunnel junction layer disposed on the first light-emitting layer; a second light-emitting layer disposed on the tunnel junction layer; and a V-pit formed in a portion of the tunnel junction layer and the first light-emitting layer. By forming a V-pit in the tunnel junction layer, current can be uniformly distributed across a plurality of light-emitting layers and light-emitting efficiency can be improved, and the operating characteristics of the tunnel junction and the light-emitting efficiency of the entire device can be improved by optimizing the thickness ratio between the tunnel junction layer and an adjacent semiconductor layer.

Description

Technology Field

[0001] The present invention relates to a light-emitting diode device, and more specifically, to a stacked light-emitting diode device capable of improving the current dispersion efficiency of a first light-emitting layer and a second light-emitting layer by forming a V-pit in a tunnel junction layer. Background Technology

[0002] The present invention relates to a light-emitting diode (LED) device, and in particular, to a stacked light-emitting diode device capable of improving the luminous efficiency and current uniformity of an LED having a plurality of light-emitting layers by introducing a V-pit structure into a tunnel junction layer.

[0003] Light-emitting diodes (LEDs) are semiconductor devices that emit light when current flows through them. Due to characteristics such as low power consumption, long lifespan, and excellent luminous efficiency, they are widely used in various fields including lighting, displays, and communications. In particular, gallium nitride (GaN)-based LEDs exhibit superior luminescence characteristics in the short-wavelength visible light region, such as blue and green, making them a key component for high-efficiency white LEDs and micro LED displays.

[0004] As one method to further improve the luminous efficiency of LEDs, stacked LED structures are being researched to obtain higher light output from a single device by stacking multiple light-emitting layers. In such stacked structures, by providing multiple active layers that emit light in different wavelength bands, it is possible to realize light of various colors or achieve high output with a single device. For example, by stacking a blue light-emitting layer and a green light-emitting layer on a single device, a light source with a wide color reproduction range can be realized.

[0005] However, in a structure where multiple light-emitting layers are stacked, electrical connection between each light-emitting layer becomes an important challenge. In conventional stacked LEDs, a tunnel junction (TJ) structure is introduced to electrically connect the light-emitting layers. A tunnel junction is a structure in which a highly doped p-type semiconductor layer and an n-type semiconductor layer are joined, and it serves to electrically connect the two light-emitting layers in series by allowing current to flow through the tunneling phenomenon when an applied voltage is applied.

[0006] However, conventional stacked LEDs with tunnel junction structures suffer from a problem where current concentration occurs in specific paths, preventing the current from being uniformly distributed across the entire surface of the light-emitting layer. This current concentration causes localized heat generation and reduced efficiency, which in turn shortens the reliability and lifespan of the device. Furthermore, if the amount of current supplied to each light-emitting layer becomes uneven, it becomes difficult to stably maintain the target color tone and light output.

[0007] Meanwhile, V-pits are inverted pyramidal defect structures formed during the growth of nitride semiconductors using threading dislocations as nuclei, creating hexagonal pits on the surface of the semiconductor layer. Conventionally, V-pits have been recognized as defects that degrade crystal quality; however, recent research has reported that utilizing V-pits can improve the current dispersion characteristics and luminous efficiency of LEDs. Nevertheless, research on specific structures for forming V-pits in the tunnel junction layer and utilizing them to improve the current dispersion characteristics of stacked LEDs remains insufficient.

[0008] Furthermore, conventional stacked LEDs have limitations in tunnel junction operation characteristics and luminous efficiency because specific structural parameters, such as the thickness ratio of the tunnel junction layer to the adjacent semiconductor layer, are not optimized. Systematic research is required on the influence of the thickness ratio between the p-type and n-type junction layers within the tunnel junction layer, and the thickness ratio between the p-type and n-type semiconductor layers adjacent to the tunnel junction layer, on device characteristics.

[0009] Furthermore, for tunneling to occur in a stacked light-emitting diode structure with a tunnel junction, p-type and n-type dopants must be doped at very high concentrations, and the junction with such high doping concentrations must have a thin thickness sufficient for carriers to penetrate the junction and transition during band bending.

[0010] However, even when the p-GaN film in a GaN-based compound semiconductor light-emitting diode structure is doped to a high concentration using Mg dopants, the hole carrier concentration that substantially contributes to electrical conductivity remains at a limited level because a large amount of excess Mg dopants that do not contribute to electrical conductivity exist within the p-GaN film.

[0011] This excess Mg reacts with hydrogen decomposed from NH₃ gas during the growth of the p-GaN film to exist as Mg-H complexes with very high resistance. Therefore, Mg-doped p-GaN films must undergo an activation process after growth to operate normally as p / n junction light-emitting diodes; however, despite this activation process, there is a limitation in that it is difficult to increase the hole carrier concentration beyond a certain level.

[0012] In addition, excessive doping with p-type and n-type dopants leads to a problem where the crystal quality of the film forming the light-emitting diode structure deteriorates rapidly. Accordingly, there is a need for a new tunnel junction structure that can secure tunneling characteristics while maintaining high-quality film quality. Prior art literature

[0013] Korean Registered Patent Publication No. 10-2653842 Korean Registered Patent Publication No. 10-2505318 The problem to be solved

[0014] The present invention aims to solve the problem of providing a stacked light-emitting diode device having a high-quality tunnel junction structure, which improves the carrier tunneling effect without degrading film quality due to high-concentration doping by forming a tunnel junction having a V-pit structure.

[0015] In addition, the present invention aims to solve the problem of providing a stacked light-emitting diode device capable of uniformly distributing current across a plurality of light-emitting layers and improving light-emitting efficiency by forming a V-pit in the tunnel junction layer.

[0016] In addition, the present invention aims to solve the problem of providing a stacked light-emitting diode device in which a first light-emitting layer and a second light-emitting layer are electrically connected by a tunnel junction layer, and a V-pit is formed in the tunnel junction layer and the first p-type semiconductor layer to secure a current distribution path.

[0017] In addition, the present invention aims to solve the problem of providing a stacked light-emitting diode device in which a second n-type semiconductor layer is configured to fill the V-pit, thereby facilitating current flow within the V-pit and improving the electrical characteristics of the device.

[0018] In addition, the present invention aims to solve the problem of providing a stacked light-emitting diode device capable of maximizing the operating characteristics and luminous efficiency of a tunnel junction by optimizing the thickness ratio between the tunnel junction layer and an adjacent semiconductor layer.

[0019] In addition, the present invention aims to solve the problem of providing a stacked light-emitting diode device capable of independent current control by having a first terminal, a second terminal, and a third terminal. means of solving the problem

[0020] To solve the aforementioned problem, a stacked light-emitting diode device according to one embodiment of the present invention is characterized by improving current dispersion characteristics by forming a V-pit in a part of the tunnel junction layer and the first light-emitting layer.

[0021] Specifically, it may include a substrate; a first light-emitting layer disposed on the substrate; a tunnel junction layer disposed on the first light-emitting layer; a second light-emitting layer disposed on the tunnel junction layer; and a V-pit formed in a portion of the tunnel junction layer and the first light-emitting layer.

[0022] Additionally, the first light-emitting layer comprises a base layer disposed on the substrate; a first n-type semiconductor layer disposed on the base layer; a current diffusion layer disposed on the first n-type semiconductor layer; a first strain relief layer disposed on the current diffusion layer; a first active layer disposed on the first strain relief layer; a first blocking layer disposed on the first active layer; and a first p-type semiconductor layer disposed on the first blocking layer, and the V-pit may be formed in the tunnel junction layer and the first p-type semiconductor layer.

[0023] Additionally, the second light-emitting layer may include a second n-type semiconductor layer disposed on the tunnel junction layer; a second strain relief layer disposed on the second n-type semiconductor layer; a second active layer disposed on the second strain relief layer; a second blocking layer disposed on the second active layer; a second p-type semiconductor layer disposed on the second blocking layer; and a contact layer disposed on the second p-type semiconductor layer.

[0024] In addition, the second n-type semiconductor layer may be provided in a shape that fills the V-pit.

[0025] Additionally, it may include a first step in which a portion of the layers disposed on the upper side of the first n-type semiconductor layer is removed so that the upper side of the first n-type semiconductor layer is exposed; a second step in which a portion of the layers disposed on the upper side of the second n-type semiconductor layer is removed so that the upper side of the second n-type semiconductor layer is exposed; a first terminal disposed on the first n-type semiconductor layer exposed by the first step; a second terminal disposed on the second n-type semiconductor layer exposed by the second step; and a third terminal disposed on the contact layer.

[0026] In addition, the first p-type semiconductor layer and the tunnel junction layer are divided into a first region in which the V-pit is formed and a second region excluding the first region, and the thickness ratio of the tunnel junction layer and the first p-type semiconductor layer in the second region may be 1:4 to 1:5.

[0027] In addition, the thickness ratio of the tunnel junction layer and the second n-type semiconductor layer in the second region may be 1:25 to 1:30.

[0028] Additionally, the tunnel junction layer comprises a p-type junction layer disposed on the first p-type semiconductor layer; and an n-type junction layer disposed on the p-type junction layer, and the thickness ratio of the p-type junction layer to the n-type junction layer may be 1:2 to 1:4. Effects of the invention

[0029] The present invention has the effect of maximizing the carrier tunneling effect without degrading film quality due to high-concentration doping by forming a tunnel junction having a V-pit structure, and providing a stacked light-emitting diode device having a high-quality tunnel junction structure.

[0030] In addition, the present invention has the effect of providing a stacked light-emitting diode device capable of uniformly distributing current across a plurality of light-emitting layers and improving light-emitting efficiency by forming a V-pit in the tunnel junction layer.

[0031] In addition, the present invention has the effect of providing a stacked light-emitting diode device in which a first light-emitting layer and a second light-emitting layer are electrically connected by a tunnel junction layer, and a V-pit is formed in the tunnel junction layer and the first p-type semiconductor layer to secure a current distribution path.

[0032] In addition, the present invention has the effect of providing a stacked light-emitting diode device in which a second n-type semiconductor layer is configured to fill the V-pit, thereby facilitating current flow within the V-pit and improving the electrical characteristics of the device.

[0033] In addition, the present invention has the effect of providing a stacked light-emitting diode device capable of maximizing the operating characteristics and luminous efficiency of a tunnel junction by optimizing the thickness ratio between the tunnel junction layer and an adjacent semiconductor layer.

[0034] In addition, the present invention has the effect of providing a stacked light-emitting diode element capable of independent current control by having a first terminal, a second terminal, and a third terminal. Brief explanation of the drawing

[0035] FIG. 1 schematically illustrates a light-emitting diode element according to one embodiment of the present invention. FIG. 2 illustrates a cross-section of a light-emitting diode element according to one embodiment of the present invention. Figure 3 shows a cross-section of the V-pit of a light-emitting diode device according to one embodiment of the present invention. FIG. 4 specifically illustrates a cross-section of a light-emitting diode element according to one embodiment of the present invention. Specific details for implementing the invention

[0036] Hereinafter, embodiments are described in detail with reference to the attached drawings. However, various modifications may be made to the embodiments, and thus the scope of the patent application is not limited or restricted by these embodiments. It should be understood that all modifications, equivalents, and substitutions to the embodiments are included within the scope of the rights.

[0037] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, the embodiments are not limited to the specific disclosed forms, and the scope of this specification includes modifications, equivalents, or substitutions that fall within the technical concept.

[0038] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0039] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or coupled with that other component, or that there may be other components in between.

[0040] The terms used in the embodiments are for illustrative purposes only and should not be interpreted as intended to be limiting. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0041] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the embodiments pertain. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0042] In addition, when describing with reference to the attached drawings, identical components are assigned the same reference numeral regardless of drawing symbols, and redundant descriptions thereof are omitted. In describing the embodiments, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the embodiments, such detailed description is omitted.

[0043] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0044] In the embodiments of the present invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0045] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise.

[0046] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0047] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0048] When elements or layers are referred to as "on" another element or layer, this includes cases where another layer or element is placed directly on top of or in between. Throughout the specification, the same reference numerals refer to the same components.

[0049] The size and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

[0050] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and as will be fully understood by those skilled in the art, various technical interlocking and operation are possible, and each embodiment may be implemented independently of one another or together in an interlocking relationship.

[0051] FIG. 1 schematically illustrates a light-emitting diode element according to an embodiment of the present invention. FIG. 2 illustrates a cross-section of a light-emitting diode element according to an embodiment of the present invention. FIG. 3 illustrates a cross-section near the V-pit of a light-emitting diode element according to an embodiment of the present invention. FIG. 4 illustrates a cross-section of a light-emitting diode element according to an embodiment of the present invention in detail.

[0052] Referring to FIGS. 1 to 4, a stacked light-emitting diode element (1) according to one embodiment of the present invention will be described.

[0053] A stacked light-emitting diode device (1) according to one embodiment of the present invention may include a substrate (100), a first light-emitting layer (200), a tunnel junction layer (300), a second light-emitting layer (400), and a V-pit (500).

[0054] The substrate (100) functions as a base structure that supports the overall structure of the light-emitting diode element (1). The substrate (100) may be made of materials such as sapphire, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). In one embodiment of the present invention, the substrate (100) may be provided as a sapphire substrate.

[0055] The first light-emitting layer (200) may be disposed on the substrate (100). The first light-emitting layer (200) is a semiconductor stacked structure comprising an active layer that emits light of a predetermined wavelength band when current is applied. In one embodiment of the present invention, the first light-emitting layer (200) may be configured to emit light of a blue wavelength band.

[0056] The tunnel junction layer (300) can be placed on the first light-emitting layer (200). The tunnel junction layer (300) serves to electrically connect the first light-emitting layer (200) and the second light-emitting layer (400) in series. The tunnel junction layer (300) is a structure in which a highly doped p-type semiconductor layer and an n-type semiconductor layer are joined, and is provided so that current can flow through a tunneling phenomenon by an applied voltage.

[0057] The second light-emitting layer (400) may be disposed on the tunnel junction layer (300). The second light-emitting layer (400) may be configured to emit light in a different wavelength band or the same wavelength band as the first light-emitting layer (200). In one embodiment of the present invention, the second light-emitting layer (400) may be configured to emit light in a green wavelength band. In this way, by providing the first light-emitting layer (200) and the second light-emitting layer (400), which emit blue and green light respectively, in a single device, light of multiple wavelength bands can be realized in a single device.

[0058] The V-pit (500) may be formed in a part of the tunnel junction layer (300) and the first light-emitting layer (200). The V-pit (500) may be an inverted pyramidal structure formed using a penetration dislocation as a nucleus during the growth process of the nitride semiconductor, and may have a V-shaped cross-section that narrows as it goes downward from the surface of the semiconductor layer. The V-pit (500) may be artificially formed during the manufacturing process of the nitride semiconductor.

[0059] By forming a V-pit (500) in the tunnel junction layer (300), a current distribution path through the tunnel junction layer (300) is secured, allowing the current to be uniformly distributed across the front surface of the first light-emitting layer (200) and the second light-emitting layer (400). This prevents localized heat generation and efficiency degradation caused by current concentration and improves the light-emitting efficiency and reliability of the light-emitting diode device (1).

[0060] Meanwhile, the first light-emitting layer (200) may include a base layer (210), a first n-type semiconductor layer (220), a current diffusion layer (230), a first strain relaxation layer (240), a first active layer (250), a first blocking layer (260), and a first p-type semiconductor layer (270) that are sequentially stacked from the substrate (100).

[0061] A base layer (210) may be disposed on a substrate (100). The base layer (210) is provided to buffer the difference in lattice constants between the substrate (100) and the nitride semiconductor layer grown thereon and to improve crystal quality. The base layer (210) may be provided as an undoped GaN buffer layer.

[0062] The first n-type semiconductor layer (220) may be disposed on the base layer (210). The first n-type semiconductor layer (220) may be provided as a GaN-based semiconductor layer doped with n-type impurities. The first n-type semiconductor layer (220) serves to supply electrons in the first light-emitting layer (200) and may function as a common contact layer in one embodiment of the present invention.

[0063] The current diffusion layer (230) may be disposed on the first n-type semiconductor layer (220). The current diffusion layer (230) serves to uniformly diffuse the current supplied from the first n-type semiconductor layer (220) across the entire surface of the first active layer (250). The current diffusion layer (230) may be provided as an n-GaN-based semiconductor layer and may be referred to as a current spreading layer.

[0064] The first strain relief layer (240) may be disposed on the current diffusion layer (230). The first strain relief layer (240) is provided to relieve strain caused by lattice mismatch between the current diffusion layer (230) and the first active layer (250). The first strain relief layer (240) may be provided in the structure of an InGaN / InGaN strain relief layer.

[0065] The first active layer (250) may be disposed on the first strain relaxation layer (240). The first active layer (250) is a region where electrons and holes combine to emit light, and may be provided with a Multiple Quantum Well (MQW) structure. In one embodiment of the present invention, the first active layer (250) is provided with an InGaN / (In)GaN multiple quantum well structure and may emit light in the blue wavelength band.

[0066] The first blocking layer (260) may be disposed on the first active layer (250). The first blocking layer (260) serves to increase the electron-hole recombination efficiency within the first active layer (250) by blocking excessive electron flow from the first active layer (250). The first blocking layer (260) may be provided as an AlGaN-based electron blocking layer (EBL).

[0067] The first p-type semiconductor layer (270) may be disposed on the first blocking layer (260). The first p-type semiconductor layer (270) is provided as a GaN-based semiconductor layer doped with p-type impurities and serves to supply holes to the first active layer (250).

[0068] The V-pit (500) can be formed in the tunnel junction layer (300) and the first p-type semiconductor layer (270). That is, the lower portion of the V-pit (500) is located within the first p-type semiconductor layer (270), and the upper opening of the V-pit (500) can be formed to penetrate the tunnel junction layer (300). Through this, a current distribution path mediated by the V-pit (500) is formed between the first p-type semiconductor layer (270) and the tunnel junction layer (300), thereby improving current distribution characteristics.

[0069] Meanwhile, the second light-emitting layer (400) may include a second n-type semiconductor layer (410), a second strain-relaxing layer (420), a second active layer (430), a second blocking layer (440), a second p-type semiconductor layer (450), and a contact layer (460) that are sequentially stacked.

[0070] The second n-type semiconductor layer (410) may be disposed on the tunnel junction layer (300). The second n-type semiconductor layer (410) may be provided as a GaN-based semiconductor layer doped with n-type impurities. The second n-type semiconductor layer (410) serves to supply electrons in the second light-emitting layer (400).

[0071] The second strain relief layer (420) may be disposed on the second n-type semiconductor layer (410). The second strain relief layer (420) is provided to relieve strain caused by lattice mismatch between the second n-type semiconductor layer (410) and the second active layer (430). The second strain relief layer (420) may be provided as an InGaN / InGaN strain relief layer.

[0072] The second active layer (430) may be disposed on the second strain relaxation layer (420). The second active layer (430) is a region where electrons and holes combine to emit light, and may be provided with a multiple quantum well structure. In one embodiment of the present invention, the second active layer (430) may be provided with an InGaN / (In)GaN multiple quantum well structure to emit light in the green wavelength band.

[0073] The second blocking layer (440) may be disposed on the second active layer (430). The second blocking layer (440) may serve to increase the electron-hole recombination efficiency within the second active layer (430) by blocking excessive electron flow from the second active layer (430). The second blocking layer (440) may be provided as an AlGaN-based electron blocking layer.

[0074] The second p-type semiconductor layer (450) may be disposed on the second blocking layer (440). The second p-type semiconductor layer (450) may be provided as a GaN-based semiconductor layer doped with p-type impurities and may serve to supply holes to the second active layer (430).

[0075] The contact layer (460) may be disposed on the second p-type semiconductor layer (450). The contact layer (460) may be provided to form an ohmic contact with the third terminal (730) to be described later. The contact layer (460) may be provided as a GaN-based semiconductor layer doped with a high concentration of p-type impurities, i.e., a p++-GaN layer.

[0076] Meanwhile, the second n-type semiconductor layer (410) may be provided in a shape that fills the V-pit (500). That is, the internal space of the V-pit (500) formed in the tunnel junction layer (300) may have a structure in which it is filled by the growth of the second n-type semiconductor layer (410). By filling the interior of the V-pit (500) with the second n-type semiconductor layer (410), the junction area where the n-type semiconductor and the p-type junction layer of the tunnel junction layer (300) come into contact is increased even on the inner wall surface of the V-pit (500). Through this, a tunneling current path through the tunnel junction layer (300) is additionally formed around the V-pit (500), thereby further improving the current dispersion characteristics across the entire front surface of the device. In addition, by filling the interior of the V-pit (500) with a second n-type semiconductor layer (410), structural instability of the device caused by empty space inside the V-pit (500) can be prevented, and the growth quality of the subsequent semiconductor layer can be improved.

[0077] Meanwhile, the light-emitting diode element (1) may include a first step (610), a second step (620), a first terminal (710), a second terminal (720), and a third terminal (730). The first step (610) may be formed by removing a portion of the layers disposed on the upper side of the first n-type semiconductor layer (220) so that the upper side of the first n-type semiconductor layer (220) is exposed. That is, a first step (610) can be formed by removing a portion of the current diffusion layer (230), the first strain relief layer (240), the first active layer (250), the first blocking layer (260), the first p-type semiconductor layer (270), the tunnel junction layer (300), and the second light-emitting layer (400) disposed on the upper portion of the first n-type semiconductor layer (220) in the first light-emitting layer (200) through an etching process to expose a portion of the upper surface of the first n-type semiconductor layer (220).

[0078] The second step (620) can be formed by removing a portion of the layers disposed on the upper side of the second n-type semiconductor layer (410) so that the upper side of the second n-type semiconductor layer (410) is exposed. That is, the second step (620) can be formed by removing a portion of the second strain relief layer (420), the second active layer (430), the second blocking layer (440), the second p-type semiconductor layer (450), and the contact layer (460) disposed on the upper side of the second n-type semiconductor layer (410) in the second light-emitting layer (400) through an etching process to expose a portion of the upper surface of the second n-type semiconductor layer (410).

[0079] The first terminal (710) can be placed on the first n-type semiconductor layer (220) exposed by the first step (610). The first terminal (710) can function as an electrode to which current is applied for driving the first light-emitting layer (200).

[0080] The second terminal (720) can be placed on the second n-type semiconductor layer (410) exposed by the second step (620). The second terminal (720) can function as an electrode to which current is applied for driving the second light-emitting layer (400). Additionally, the second terminal (720) can be used as an intermediate terminal located between the first light-emitting layer (200) and the second light-emitting layer (400), and can also be used when driving the first light-emitting layer (200).

[0081] The third terminal (730) can be placed on the contact layer (460). The third terminal (730) can function as an electrode to which current is applied for driving the second light-emitting layer (400).

[0082] In this way, through a three-terminal structure having a first terminal (710), a second terminal (720), and a third terminal (730), it is possible to drive the first light-emitting layer (200) and the second light-emitting layer (400) independently or simultaneously in series, thereby allowing the light-emitting wavelength and light output of the device to be flexibly adjusted.

[0083] For example, the first light-emitting layer (200) can be driven by applying voltage between the first terminal (710) and the second terminal (720), the second light-emitting layer (400) can be driven by applying voltage between the second terminal (720) and the third terminal (730), and the first light-emitting layer (200) and the second light-emitting layer (400) can be driven simultaneously in series by applying voltage between the first terminal (710) and the third terminal (730).

[0084] Meanwhile, the first p-type semiconductor layer (270) and the tunnel junction layer (300) may be divided into a first region (A1) in which a V-pit (500) is formed and a second region (A2) excluding the first region (A1). The first region (A1) is the region occupied by the V-pit (500) and refers to the region where the inclined surface of the V-pit (500) is located, and the second region (A2) refers to a flat region in which the V-pit (500) is not formed.

[0085] In the second region (A2), the thickness ratio of the tunnel junction layer (300) and the first p-type semiconductor layer (270) may be 1:4 to 1:5. If the thickness ratio of the first p-type semiconductor layer (270) to the thickness of the tunnel junction layer (300) is less than the above range, the first p-type semiconductor layer (270) becomes excessively thin, making it difficult to supply sufficient holes to the first light-emitting layer (200). Conversely, if it exceeds the above range, the first p-type semiconductor layer (270) becomes unnecessarily thick, increasing the device resistance and making it difficult to control the V-pit (500) formation depth. Therefore, by controlling the thickness ratio of the tunnel junction layer (300) and the first p-type semiconductor layer (270) to a range of 1:4 to 1:5, the operating characteristics of the tunnel junction (300) and the light-emitting efficiency of the first light-emitting layer (200) can be optimized.

[0086] Meanwhile, in the second region (A2), the thickness ratio of the tunnel junction layer (300) and the second n-type semiconductor layer (410) may be 1:25 to 1:30. If the thickness ratio of the second n-type semiconductor layer (410) to the thickness of the tunnel junction layer (300) is less than the above range, the second n-type semiconductor layer (410) becomes excessively thin, making it difficult to completely fill the V-pit (500) and potentially degrading current diffusion characteristics. Conversely, if it exceeds the above range, the second n-type semiconductor layer (410) becomes unnecessarily thick, increasing the total thickness of the device and potentially lowering manufacturing efficiency. Accordingly, by controlling the thickness ratio of the tunnel junction layer (300) and the second n-type semiconductor layer (410) to a range of 1:25 to 1:30, a structure in which the V-pit (500) is completely filled by the second n-type semiconductor layer (410) can be stably formed, and the current dispersion characteristics and light emission efficiency of the second light-emitting layer (400) can be improved.

[0087] Here, thickness may refer to the length in the thickness direction (T) in FIG. 3. The thickness of the tunnel junction layer (300) may be 20 nm to 30 nm. The thickness of the first p-type semiconductor layer (270) may be 100 nm to 120 nm. The thickness of the second n-type semiconductor layer (410) may be 600 nm to 800 nm.

[0088] Meanwhile, the tunnel junction layer (300) may include a p-type junction layer (310) and an n-type junction layer (320).

[0089] The p-type junction layer (310) may be disposed on the first p-type semiconductor layer (270). The p-type junction layer (310) may be provided as a GaN-based semiconductor layer doped with a high concentration of p-type impurities, i.e., a p++-GaN layer. The p-type junction layer (310) serves to supply holes in the tunnel junction layer (300).

[0090] The n-type junction layer (320) can be placed on the p-type junction layer (310). The n-type junction layer (320) can be provided as a GaN-based semiconductor layer doped with a high concentration of n-type impurities, i.e., an n++-GaN layer. The n-type junction layer (320) serves to supply electrons in the tunnel junction layer (300). In the tunnel junction layer (300) where the p-type junction layer (310) and the n-type junction layer (320) are joined, a tunneling phenomenon occurs due to a voltage applied in the reverse direction, allowing current to flow, thereby enabling an electrical connection between the p-type semiconductor of the first light-emitting layer (200) and the n-type semiconductor of the second light-emitting layer (400).

[0091] The thickness ratio of the p-type junction layer (310) and the n-type junction layer (320) may be 1:2 to 1:4. If the thickness ratio of the n-type junction layer (320) to the thickness of the p-type junction layer (310) is less than the above range, the n-type junction layer (320) may become excessively thin, and the formation of the V-pit (500) and electrical connection with the second n-type semiconductor layer (410) may not be smooth. Conversely, if it exceeds the above range, the n-type junction layer (320) may become excessively thick, and the tunneling characteristics may be degraded. Therefore, by controlling the thickness ratio of the p-type junction layer (310) and the n-type junction layer (320) to a range of 1:2 to 1:4, the tunneling characteristics of the tunnel junction layer (300) can be optimized and the light-emitting efficiency of the entire light-emitting diode device (1) can be improved.

[0092] The thickness of the p-type junction layer (310) may be 4 nm to 8 nm. Additionally, the thickness of the n-type junction layer (320) may be 15 nm to 25 nm.

[0093] The thickness of the substrate (100) may be 7,000 nm to 7,500 nm. Meanwhile, the thickness of the base layer (210) may be 1,400 nm to 1,600 nm. The thickness of the first n-type semiconductor layer (220) may be 3,100 nm to 3,700 nm. The thickness of the current diffusion layer (230) may be 850 nm to 950 nm. The thickness of the first strain relief layer (240) and the first active layer (250) may be 75 nm to 95 nm. The thickness of the first blocking layer (260) may be 25 nm to 35 nm.

[0094] Meanwhile, the thickness of the second strain relaxation layer (420) may be 100 nm to 140 nm. The thickness of the second active layer (430) may be 80 nm to 90 nm. The thickness of the second blocking layer (440) may be 15 nm to 25 nm. The thickness of the second p-type semiconductor layer (450) may be 100 nm to 120 nm. In addition, the thickness of the contact layer (460) may be 2 nm to 10 nm.

[0095] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims below, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0096] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below. Explanation of the symbols

[0097] 1: Light-emitting diode element 100: Substrate 200: First light-emitting layer 210: Base layer 220: First n-type semiconductor layer 230: Current diffusion layer 240: First strain relaxation layer 250: First active layer 260: First block layer 270: First p-type semiconductor layer 300: Tunnel Junction Layer 310: p-type junction layer 320: n-type junction layer 400: Second light-emitting layer 410: Second n-type semiconductor layer 420: Second strain relaxation layer 430: Second active layer 440: Secondary fault 450: Second p-type semiconductor layer 460: Contact layer 500: V-pit 610: 1st step 620: Second step 710: First terminal 720: Second terminal 730: Third terminal A1: Area 1 A2: Area 2

Claims

Claim 1 A substrate (100); a first light-emitting layer (200) disposed on the substrate (100); a tunnel junction layer (300) disposed on the first light-emitting layer (200); a second light-emitting layer (400) disposed on the tunnel junction layer (300); and a V-pit (500) formed in a part of the tunnel junction layer (300) and the first light-emitting layer (200); wherein the first light-emitting layer comprises a base layer disposed on the substrate; a first n-type semiconductor layer disposed on the base layer; a current diffusion layer disposed on the first n-type semiconductor layer; a first strain relief layer disposed on the current diffusion layer; a first active layer disposed on the first strain relief layer; and a first blocking layer disposed on the first active layer. and a first p-type semiconductor layer disposed on the first blocking layer; wherein the V-pit is formed on the tunnel junction layer and the first p-type semiconductor layer, and the second light-emitting layer comprises: a second n-type semiconductor layer disposed on the tunnel junction layer; a second strain relaxation layer disposed on the second n-type semiconductor layer; a second active layer disposed on the second strain relaxation layer; a second blocking layer disposed on the second active layer; and a second p-type semiconductor layer disposed on the second blocking layer. and a contact layer disposed on the second p-type semiconductor layer; wherein the second n-type semiconductor layer is provided in a shape that fills the V-pit, and a first step in which a portion of the layers disposed on the upper side of the first n-type semiconductor layer is removed so that the upper side of the first n-type semiconductor layer is exposed; a second step in which a portion of the layers disposed on the upper side of the second n-type semiconductor layer is removed so that the upper side of the second n-type semiconductor layer is exposed; a first terminal disposed on the first n-type semiconductor layer exposed by the first step; a second terminal disposed on the second n-type semiconductor layer exposed by the second step; and a third terminal disposed on the contact layer.A stacked light-emitting diode device comprising: a first p-type semiconductor layer and a tunnel junction layer, wherein the first p-type semiconductor layer and the tunnel junction layer are divided into a first region in which the V-pit is formed and a second region excluding the first region, wherein the thickness ratio of the tunnel junction layer to the first p-type semiconductor layer in the second region is 1:4 to 1:5, and the thickness ratio of the tunnel junction layer to the second n-type semiconductor layer in the second region is 1:25 to 1:30, and wherein the tunnel junction layer includes a p-type junction layer disposed on the first p-type semiconductor layer and an n-type junction layer disposed on the p-type junction layer, and wherein the thickness ratio of the p-type junction layer to the n-type junction layer is 1:2 to 1:

4. Claim 2 A stacked light-emitting diode device according to claim 1, characterized in that the thickness of the tunnel junction layer is 20 nm to 30 nm, the thickness of the first p-type semiconductor layer is 100 nm to 120 nm, and the thickness of the second n-type semiconductor layer is 600 nm to 800 nm. Claim 3 A stacked light-emitting diode device according to claim 1, characterized in that the first light-emitting layer is driven by a voltage applied between the first terminal and the second terminal, and the second light-emitting layer is driven by a voltage applied between the second terminal and the third terminal. Claim 4 A stacked light-emitting diode device according to claim 1, characterized in that the thickness of the p-type junction layer is 4 nm to 8 nm. Claim 5 A stacked light-emitting diode device according to claim 4, characterized in that the thickness of the n-type junction layer is 15 nm to 25 nm.

Images