Image sensor

Abstract

The technical concept of the invention provides an image sensor comprising: a substrate; at least one transfer gate disposed on an upper surface of the substrate; a floating diffusion region disposed within the substrate so as to be spaced apart from the transfer gate in a first direction parallel to the upper surface; an intrinsic semiconductor region disposed between the transfer gate and the floating diffusion region within the substrate; and a photoelectric conversion region disposed within the substrate so as to be spaced apart from the floating diffusion region in a second direction perpendicular to the first direction, wherein the intrinsic semiconductor region is a region not doped with impurities.

Description

Technology Field

[0001] The technical concept of the present invention relates to an image sensor. More specifically, it relates to an image sensor including a photoelectric conversion region. Background Technology

[0002] An image sensor is a device that converts optical images into electrical signals. Commonly used image sensors include Charge Coupled Device (CCD) type image sensors and CMOS type image sensors (CMOS Image Sensor, CIS). These image sensors are equipped with multiple pixels arranged in a two-dimensional matrix, and each pixel outputs an image signal from light energy. Each of the multiple pixels accumulates a photocharge corresponding to the amount of incident light through a photoelectric conversion region and outputs a pixel signal based on the accumulated photocharge. Recently, there has been a trend to include more transfer gates in image sensors to increase the full-well capacity (FWC) of the image sensor. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide an image sensor with improved noise characteristics. means of solving the problem

[0004] To solve the above-mentioned problem, the technical concept of the present invention provides an image sensor comprising: a substrate; at least one transfer gate disposed on an upper surface of the substrate; a floating diffusion region disposed within the substrate so as to be spaced apart from the transfer gate in a first direction parallel to the upper surface; an intrinsic semiconductor region disposed between the transfer gate and the floating diffusion region within the substrate; and a photoelectric conversion region disposed within the substrate so as to be spaced apart from the floating diffusion region in a second direction perpendicular to the first direction, wherein the intrinsic semiconductor region is a region not doped with impurities.

[0005] To solve the above-mentioned problem, the technical concept of the present invention provides an image sensor comprising: a substrate; a floating diffusion region located within the substrate; a plurality of photoelectric conversion regions disposed around the floating diffusion region within the substrate; at least one transfer gate disposed in each of the plurality of photoelectric conversion regions so as to be spaced apart in a first direction parallel to the floating diffusion region and the upper surface of the substrate; and an intrinsic semiconductor region disposed between each of the plurality of transfer gates and the floating diffusion region within the substrate, wherein the intrinsic semiconductor region is a region not doped by impurities.

[0006] To solve the above-mentioned problem, the technical concept of the present invention provides an image sensor comprising: a substrate; two transfer gates disposed on the upper surface of the substrate; a floating diffusion region disposed within the substrate so as to be spaced apart from the transfer gates in a first direction parallel to the upper surface; an intrinsic semiconductor region located between each of the transfer gates and the floating diffusion region within the substrate; an impurity semiconductor region in contact with the floating diffusion region and the intrinsic semiconductor region and doped with a conductive impurity; and a photoelectric conversion region disposed within the substrate so as to be spaced apart from the floating diffusion region in a second direction perpendicular to the first direction; wherein the intrinsic semiconductor region is a region not doped with impurities and extends to the upper surface of the photoelectric conversion region along the second direction perpendicular to the first direction. Effects of the invention

[0007] According to exemplary embodiments of the present invention, the image sensor comprises an intrinsic semiconductor region disposed between a transfer gate and a floating diffusion region, which is not separately doped with impurities. Accordingly, if impurities are doped, Random dopant fluctuation (RDF) that may be caused by the doped impurities can be reduced. Through this, the noise characteristics of the image sensor can be improved, and the Full-well Capacity (FWC) can be enhanced. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram illustrating an image sensor according to an exemplary embodiment of the present invention. FIG. 2 is a circuit diagram of a pixel array of an image sensor according to an exemplary embodiment of the present invention. FIG. 3 is a plan view showing a pixel of an image sensor according to an exemplary embodiment of the present invention. FIGS. 4a to 4d are cross-sectional views showing a cross section cut along the line A1-A1' of FIG. 3. FIG. 5 is a plan view showing the pixels of an image sensor according to an exemplary embodiment of the present invention. FIGS. 6a to 6c are cross-sectional views showing a cross section cut along the line A2-A2' of FIG. 5. FIG. 7 is a plan view showing the pixels of an image sensor according to an exemplary embodiment of the present invention. FIGS. 8a to 8d are cross-sectional views showing a cross section cut along the line A3-A3' of FIG. 7. FIG. 9 is a circuit diagram of a pixel array of an image sensor according to an exemplary embodiment of the present invention. FIG. 10 is a plan view schematically showing a pixel of an image sensor according to an exemplary embodiment of the present invention. FIGS. 11a to 11c are cross-sectional views showing a cross section cut along the line A4-A4' of FIG. 10. FIG. 12 is a plan view schematically showing a pixel of an image sensor according to an exemplary embodiment of the present invention. FIGS. 13a to 13c are cross-sectional views showing a cross section cut along the line A5-A5' of FIG. 12. FIGS. 14a to 14e are cross-sectional views illustrating a method for manufacturing an image sensor according to an exemplary embodiment of the present invention. FIG. 15 is a block diagram showing an electronic system according to an exemplary embodiment of the present invention. FIG. 16 is a detailed block diagram showing a camera module included in the electronic system of FIG. 15. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0010] FIG. 1 is a block diagram illustrating an image sensor (100) according to an exemplary embodiment of the present invention.

[0011] Referring to FIG. 1, an image sensor (100) according to exemplary embodiments of the present invention may include a pixel array (10) and circuits for controlling the pixel array (10). In exemplary embodiments, the circuits for controlling the pixel array (10) may include a column driver (20), a row driver (30), a timing controller (40), and a readout circuit (50).

[0012] The image sensor (100) can operate according to a control command received from the image processor (70) and can convert light transmitted from an external object into an electrical signal and output it to the image processor (70). The image sensor (100) may be a CMOS image sensor.

[0013] The pixel array (10) may include a plurality of unit pixels (PX) having a two-dimensional array structure arranged in a matrix form along a plurality of row lines and a plurality of column lines.

[0014] Each of the multiple unit pixels (PX) may include a photoelectric conversion region. The photoelectric conversion region may receive light transmitted from the object and generate an electric charge. The image sensor (100) may perform an autofocus function by utilizing the phase difference of pixel signals generated from the multiple photoelectric conversion regions included in the multiple unit pixels (PX). Each of the multiple unit pixels (PX) may include a pixel circuit for generating a pixel signal from the electric charge generated in the photoelectric conversion region.

[0015] The column driver (20) may include a Correlated Double Sampler (CDS), an Analog-to-Digital Converter (ADC), etc. The Correlated Double Sampler is connected via column lines to a unit pixel (PX) included in a row selected by a row selection signal supplied by a row driver (30), and can detect a reset voltage and a pixel voltage by performing correlated double sampling. The Analog-to-Digital Converter can convert the reset voltage and pixel voltage detected by the Correlated Double Sampler into a digital signal and transmit it to a readout circuit (50).

[0016] The readout circuit (50) may include a latch or buffer circuit, an amplifier circuit, etc., capable of temporarily storing a digital signal, and may generate image data by temporarily storing or amplifying a digital signal received from the column driver (20). The operation timing of the column driver (20), row driver (30), and readout circuit (50) may be determined by a timing controller (40), and the timing controller (40) may operate by a control command transmitted by the image processor (70).

[0017] The image processor (70) can process the image data output by the readout circuit (50) and output it to a display device or store it in a storage device such as memory. When the image sensor (100) is mounted on an autonomous vehicle, the image processor (70) can process the image data and transmit it to a main controller or the like that controls the autonomous vehicle.

[0018] FIG. 2 is a circuit diagram of a pixel array of an image sensor (100) according to an exemplary embodiment of the present invention.

[0019] Referring to FIG. 2, a unit pixel (PX) including a transfer transistor (TX) and logic transistors (RX, SX, SFX) is shown in an array form.

[0020] Unit pixels (PX) may be arranged in multiple numbers. In exemplary embodiments, multiple unit pixels (PX) may be arranged in a matrix form. Here, the logic transistors may include a reset transistor (RX), a select transistor (SX), and a source follower transistor (SFX). The reset transistor (RX) may include a reset gate (RG), and the select transistor (SX) may include a select gate (SG).

[0021] The above unit pixel (PX) may include a photoelectric conversion region (PD) and a floating diffusion region (FD). The photoelectric conversion region (PD) may generate and accumulate photocharges in proportion to the amount of light incident from the outside, and a photodiode, phototransistor, photogate, pinned photodiode (PPD), or a combination thereof may be used.

[0022] The transfer transistor (TX) can transfer photocharges generated in the photoelectric conversion region (PD) to the floating diffusion region (FD). The floating diffusion region (FD) can receive the photocharges generated in the photoelectric conversion region (PD) and store them cumulatively. The source follower transistor (SFX) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD).

[0023] The reset transistor (RX) can periodically reset the photocharges accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode of the reset transistor (RX) is connected to the power supply voltage (V DD It can be connected to ).

[0024] When the reset transistor (RX) is turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) can be transferred to the floating diffusion region (FD). When the reset transistor (RX) is turned on, photocharges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0025] The source follower transistor (SFX) is connected to a current source (not shown) located outside the unit pixel (PX) and can function as a source follower buffer amplifier, amplifying potential changes in the floating diffusion region (FD) and outputting this to the output line (V OUT It can be output as ).

[0026] The select transistor (SX) can select multiple unit pixels (PX) on a row-by-row basis, and when the select transistor (SX) is turned on, the power supply voltage (V DD This can be transferred to the source electrode of the source follower transistor (SFX).

[0027] FIG. 3 is a plan view showing a pixel of an image sensor (100) according to an exemplary embodiment of the present invention. FIG. 4a is a cross-sectional view showing a cross section cut along the line A1-A1' of FIG. 3.

[0028] Referring to FIGS. 3 and FIGS. 4a, the image sensor (100) may include a substrate (110) having a pixel region (PX1). Although FIG. 3 illustrates one pixel region (PX1), the substrate (110) may include a plurality of pixel regions (PX1). In the substrate (110), the pixel region (PX1) may be defined by a pixel separation film (not shown). The pixel region (PX1) may include a photoelectric conversion region (PD) formed within the substrate (110). In an exemplary embodiment, the photoelectric conversion region (PD) may be a region doped with a first impurity. In an exemplary embodiment, the first impurity may be an n-type impurity. The n-type impurity may be, for example, phosphorus or arsenic. The pixel region (PX1) may be a region that senses light incident from the outside.

[0029] A substrate (110) may include a front surface (110A) and a rear surface (110B) facing the front surface (110A). Here, the front surface (110A) of the substrate (110) may also be referred to as the upper surface of the substrate (110), and the rear surface (110B) of the substrate (110) may also be referred to as the lower surface of the substrate (110). Hereinafter, a direction parallel to the front surface (110A) of the substrate (110) is defined as the first direction, and a direction perpendicular to the first direction is defined as the second direction.

[0030] In exemplary embodiments, the substrate (110) may be composed of a semiconductor layer doped with P-type impurities. For example, the substrate (110) may be composed of a semiconductor layer composed of Si, Ge, SiGe, a group II-VI compound semiconductor, a group III-V compound semiconductor, or a combination thereof, or a Silicon on Insulator (SOI) substrate. In exemplary embodiments, the substrate (110) may be composed of a P-type epitaxial semiconductor layer epitaxially grown from a P-type bulk silicon substrate.

[0031] The pixel isolation film may have a planar structure that surrounds the photoelectric conversion region (PD). The pixel isolation film may include, for example, silicon oxide, silicon nitride, SiCN, SiON, SiOC, polysilicon, metal, metal nitride, metal oxide, BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PE-TEOS (plasma enhanced tetraethyl orthosilicate), FSG (fluoride silicate glass), CDO (carbon-doped silicon oxide), OSG (organosilicate glass), air, or a combination thereof. For example, the metal that may be included in the pixel isolation film may be tungsten (W), copper (Cu), or a combination thereof. The metal nitride that may be included in the pixel isolation film may be TiN, TaN, or a combination thereof. The metal oxide that may be included in the pixel isolation film may be ITO (indium tin oxide), aluminum oxide (Al2O3), or a combination thereof.

[0032] A device isolation film (120) defining a plurality of active regions (ACT1, ACT2, ACT3) may be disposed on the front surface (110A) of the substrate (110). The plurality of active regions (ACT1, ACT2, ACT3) may include a first active region (ACT1), a second active region (ACT2), and a third active region (ACT3). The lower surface of the device isolation film (120) may be vertically spaced apart from the photoelectric conversion region (PD). In exemplary embodiments, the device isolation film (120) may be made of an insulating film comprising a silicon oxide film, a silicon nitride film, or a combination thereof.

[0033] A transfer transistor (TX, see FIG. 2) and a floating diffusion region (FD) may be disposed in the first active region (ACT1). The transfer transistor (TX) may include a transfer gate (130a).

[0034] In an exemplary embodiment, the transfer gate (130a) may be a vertical transfer gate (VTG). Specifically, the transfer gate (130a) may include a horizontal portion (131a1) disposed on the front surface (110A) of the substrate (110), a vertical portion (131b1) connected to the horizontal portion (131a1) and extending into the interior of the substrate (110) from the lower surface of the horizontal portion (131a1), and a gate insulating film (133_1) covering a portion of the lower surface of the horizontal portion (131a1) and the side wall of the vertical portion (131b1).

[0035] A horizontal portion (131a1) may extend along a first direction on the front surface (110A) of the substrate (110). A vertical portion (131b1) may extend from the front surface (110A) of the substrate (110) into the interior of the substrate (110) along a second direction, in contact with a portion of the lower surface of the horizontal portion (131a1). At this time, the vertical portion (131b1) may penetrate a portion of the photoelectric conversion region (PD) formed within the substrate (110). A gate insulating film (133_1) may cover the sidewall of the vertical portion (131b1) and a portion of the lower surface of the horizontal portion (131a) that does not come into contact with the upper surface of the vertical portion (131b1). In an exemplary embodiment, a portion of the gate insulating film (133_1) adjacent to the floating diffusion region (FD) may come into contact with the intrinsic semiconductor region (110_1).

[0036] A floating diffusion region (FD) may be positioned on one side of the transfer gate (130a) so as to be spaced apart from the transfer gate (130a) in a first direction. In an exemplary embodiment, the floating diffusion region (FD) may function as a drain of the transfer gate (130a). In an exemplary embodiment, the floating diffusion region (FD) may be a region doped with a second impurity. In an exemplary embodiment, the second impurity may be an n-type impurity. The n-type impurity may be, for example, phosphorus or arsenic.

[0037] An intrinsic semiconductor region (110_1) may be positioned between a floating diffusion region (FD) and a transfer gate (130a). Here, the intrinsic semiconductor region (110_1) may refer to a region that is not separately doped with p-type impurities or n-type impurities. In an exemplary embodiment, the intrinsic semiconductor region (110_1) may not contain p-type impurities or n-type impurities. In another embodiment, the intrinsic semiconductor region (110_1) may contain impurities at a lower concentration than the floating diffusion region (FD) and the impurity semiconductor region (110_2). In an exemplary embodiment, the intrinsic semiconductor region (110_1) may extend along a second direction to the upper surface of the photoelectric conversion region (PD). Accordingly, the lower surface of the intrinsic semiconductor region (110_1) may be in contact with the upper surface of the photoelectric conversion region (PD). In an exemplary embodiment, a portion of the intrinsic semiconductor region (110_1) located at a vertical level lower than the floating diffusion region (FD) may be extended along a first direction away from the transfer gate (130a). In this case, the portion of the intrinsic semiconductor region (110_1) extended along the first direction is located below the floating diffusion region (FD) and may overlap with the entire floating diffusion region (FD) in a second direction (i.e., vertically).

[0038] An impurity semiconductor region (110_2) may be positioned on one side of a floating diffusion region (FD) that is not adjacent to a transfer gate (130a). A portion of the impurity semiconductor region (110_2) located at a vertical level lower than that of the floating diffusion region (FD) may be in contact with a portion of the intrinsic semiconductor region (110_1) extended along the first direction, and the remaining portion of the impurity semiconductor region (110_2), excluding said portion of the impurity semiconductor region (110_2), may be in contact with the floating diffusion region (FD). In an exemplary embodiment, the impurity semiconductor region (110_2) may be a region doped with a third impurity. In an exemplary embodiment, the third impurity may be a p-type impurity. The p-type impurity may be, for example, boron or indium.

[0039] The first contact plug (141a1) may be in contact with the transfer gate (130a), and the second contact plug (141b) may be in contact with the floating diffusion region (FD). In an exemplary embodiment, the first contact plug (141a1) may penetrate a portion of the horizontal portion (131a1) of the transfer gate (130a), and the second contact plug (141b) may penetrate a portion of the floating diffusion region (FD). In an exemplary embodiment, the first contact plug (141a1) may include a first barrier conductive layer (not shown) and a first contact conductive layer (not shown), and the second contact plug (141b) may include a second barrier conductive layer (not shown) and a second contact conductive layer (not shown). In an exemplary embodiment, the first barrier conductive layer and the second barrier conductive layer may comprise at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), tungsten nitride (WN), and niobium nitride (NbN). In an exemplary embodiment, the first contact conductive layer and the second contact conductive layer may comprise at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tungsten nitride (WN).

[0040] Logic transistors may be placed in the second active region (ACT2). For example, at least one of a reset transistor (RX), a source follower transistor (SFX), and a select transistor (SX) may be placed in the second active region (ACT2). In another example, all three transistors may be placed in the second active region (ACT2). Additionally, according to an embodiment, a source follower transistor (SFX) and a select transistor (SX) may be placed in the second active region (ACT2) of one pixel region (PX1), and a reset transistor (RX) may be placed in the second active region (ACT2) of an adjacent pixel region (PX1). In such a structure, two adjacent pixel regions (PX1) may share logic transistors. A pixel gate (TXG) may be placed in the second active region (ACT2). The pixel gate (TXG) may be, for example, a reset gate (RG, see FIG. 2) or a select gate (SG, see FIG. 2). Contact plugs (143) may be placed in the second active area (ACT2). The contact plugs (143) may be power voltage contact plugs.

[0041] The third active region (ACT3) includes an impurity region (not shown), and a contact plug (145) may be connected to the impurity region of the third active region (ACT3). The impurity region of the third active region (ACT3) is a ground region, and the contact plug (145) connected to the impurity region may be a ground contact plug.

[0042] An interlayer insulating film (147) may be disposed on the front surface (110A) of the substrate (110). The interlayer insulating film (147) may cover a plurality of active regions (ACT1, ACT2, ACT3) and a device isolation film (120).

[0043] In an exemplary embodiment, the interlayer insulating film (147) may include silicon nitride or silicon oxynitride. In an exemplary embodiment, an etch stop layer (not shown) may be interposed between the interlayer insulating film (147) and the front surface (110A) of the substrate.

[0044] A wiring structure (150) may be disposed on an interlayer insulating film (147). The wiring structure (150) may include a plurality of wiring lines (151a), a plurality of wiring vias (151b), and a wiring insulating layer (153). The wiring insulating layer (153) may cover the plurality of wiring lines (151a) and the plurality of wiring vias (151b). The wiring insulating layer (153) may be composed of a single layer or a plurality of layers. In an exemplary embodiment, the wiring insulating layer (153) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The plurality of wiring lines (151a) are disposed on the upper or lower surface of the wiring insulating layer (153) and may extend along the upper or lower surface of the wiring insulating layer (153). Among the plurality of wiring lines (151a), the wiring line (151a) located at the bottom can be connected to contact plugs (141a1, 141b, 143, 145). The plurality of wiring vias (151b) can connect the plurality of wiring lines (151a) located at different vertical levels. In an exemplary embodiment, the plurality of wiring lines (151a) and the plurality of wiring vias (151b) may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, etc.

[0045] On the back surface (110B) of the substrate (110), an anti-reflection film (160), a color filter (CF), and a microlens (ML) can be stacked in sequence.

[0046] The anti-reflection film (160) can serve to prevent incident light passing through the color filter (CF) from being reflected or scattered to the side. The anti-reflection film (160) may include a metal. For example, the anti-reflection film (160) may include tungsten, aluminum, copper, or a combination thereof. Unlike as shown in FIG. 4a, the anti-reflection film (160) may include a plurality of layers. For example, the anti-reflection film (160) may include a first anti-reflection layer (not shown), a second anti-reflection layer (not shown), and a third anti-reflection layer (not shown). Each of the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer may include the same metal. For example, each of the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer may include tungsten. However, it is not limited thereto, and each of the first anti-reflection layer, the second anti-reflection layer, and the third reflective layer may include different metals.

[0047] A color filter (CF) can filter the concentrated light and provide it to a pixel area (PX). In exemplary embodiments, the color filter (CF) may consist of a red color filter, a green color filter, a blue color filter, or a white color filter. The white color filter may be a transparent color filter that transmits light in the visible light wavelength band. In other exemplary embodiments, the color filter (CF) may have other colors such as cyan, magenta, or yellow.

[0048] A microlens (ML) can concentrate incident light. A microlens (ML) can be positioned to correspond to a photoelectric conversion region (PD). A microlens (ML) may have an outwardly convex shape to concentrate light incident on the photoelectric conversion region (PD). A microlens (ML) may be transparent. For example, a microlens (ML) may have a transmittance of 90% or more for light in the visible light region. A microlens (ML) may be formed from a material such as, for example, a styrene-based resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane-based resin.

[0049] An image sensor (100) according to an exemplary embodiment of the present invention includes an intrinsic semiconductor region (110_1) which is disposed between a transfer gate (130a) and a floating diffusion region (FD) and is not separately doped by impurities. Accordingly, when impurities are doped between the transfer gate (130a) and the floating diffusion region (FD), random dopant fluctuation (RDF) that may occur due to the doped impurities can be reduced. Through this, the noise characteristics of the image sensor (100) are improved, and the occurrence of potential hump is prevented, thereby improving the full-well capacity (FWC) of the image sensor (100).

[0050] FIGS. 4b to 4d are cross-sectional views showing cross-sections corresponding to the cross-section cut along the line A1-A1' of FIG. 3. Since the respective configurations of the image sensors (100a1, 100b1, 100c1) shown in FIGS. 4b to 4d are similar to the respective configurations of the image sensor (100) described with reference to FIGS. 3 and FIG. 4a, the following description will focus on the differences.

[0051] Referring to FIG. 4b, the image sensor (100a1) may include an intrinsic semiconductor region (110_1a1) and an impurity semiconductor region (110_2a1). The intrinsic semiconductor region (110_1a1) may be positioned between a floating diffusion region (FD) and a transfer gate (130a). In an exemplary embodiment, a portion of the intrinsic semiconductor region (110_1a1) located at a vertical level lower than the floating diffusion region (FD) may be extended along a first direction away from the transfer gate (130a). In this case, the portion of the intrinsic semiconductor region (110_1a1) extended along the first direction is located below the floating diffusion region (FD) and may overlap with a portion of the floating diffusion region (FD) in a second direction (i.e., vertically).

[0052] The impurity semiconductor region (110_2a1) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130a). In this case, a portion of the impurity semiconductor region (110_2a1) located at a vertical level lower than the floating diffusion region (FD) may be extended in a first direction toward the transfer gate (130a). In this case, the portion of the impurity semiconductor region (110_2a1) extended along the first direction may overlap with the remaining portion of the floating diffusion region (FD) in a second direction (i.e., vertically). Here, the remaining portion of the floating diffusion region (FD) refers to the remaining area excluding the portion of the floating diffusion region (FD) that overlaps in the second direction with the portion of the intrinsic semiconductor region (110_1a1) extended along the first direction. Additionally, a portion of the impurity semiconductor region (110_2a1) extended along the first direction may be in contact with a portion of the intrinsic semiconductor region (110_1a1) extended along the first direction.

[0053] Referring to FIG. 4c, the image sensor (100b1) may include an intrinsic semiconductor region (110_1b1) and an impurity semiconductor region (110_2b1). The intrinsic semiconductor region (110_1b1) may be positioned between the floating diffusion region (FD) and the transfer gate (130a). In an exemplary embodiment, the intrinsic semiconductor region (110_1b1) may not overlap with the floating diffusion region (FD) in a second direction. That is, some regions of the intrinsic semiconductor region (110_1b1) located at a vertical level lower than the floating diffusion region (FD) may not extend along the first direction.

[0054] The impurity semiconductor region (110_2b1) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130a). In this case, a portion of the impurity semiconductor region (110_2b1) located at a vertical level lower than the floating diffusion region (FD) may be extended in a first direction toward the transfer gate (130a). In this case, a portion of the impurity semiconductor region (110_2b1) extended in the first direction may overlap with the entire floating diffusion region (FD) in a second direction. Additionally, a portion of the impurity semiconductor region (110_2b1) extended along the first direction may be in contact with a portion of the intrinsic semiconductor region (110_1b1) located at a vertical level lower than the floating diffusion region (FD).

[0055] Referring to FIG. 4d, the image sensor (100c1) may include an intrinsic semiconductor region (110_1c1) and an impurity semiconductor region (110_2c1).

[0056] An intrinsic semiconductor region (110_1c1) may be positioned between a floating diffusion region (FD) and a transfer gate (130a). In an exemplary embodiment, the intrinsic semiconductor region (110_1c1) may surround the floating diffusion region (FD). Specifically, the intrinsic semiconductor region (110_1c1) may surround the bottom surface and sidewalls of the floating diffusion region (FD).

[0057] The impurity semiconductor region (110_2c1) may be placed on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130a). At this time, the impurity semiconductor region (110_2c1) may be placed so as to be spaced apart from the floating diffusion region (FD). The impurity semiconductor region (110_2c1) may be in contact with the intrinsic semiconductor region (110_1c1).

[0058] FIG. 5 is a plan view showing a pixel of an image sensor (100a2) according to an exemplary embodiment of the present invention. FIG. 6a is a cross-sectional view showing a cross section cut along the line A2-A2' of FIG. 5. Since each component of the image sensor (100a2) illustrated in FIG. 5 and FIG. 6a is similar to each component of the image sensor (100) described with reference to FIG. 3 and FIG. 4a, the following description will focus on the differences.

[0059] Referring to FIGS. 5 and FIGS. 6a, the image sensor (100a2) includes a unit pixel (PX2), and a first active region (ACT1) located at the unit pixel (PX2) may have a transfer transistor (TX, see FIG. 2) and a floating diffusion region (FD) disposed therein. The transfer transistor (TX) may include two transfer gates (130b). Each of the two transfer gates (130b) may be disposed so as to be spaced apart from the floating diffusion region (FD) by the same distance. Specifically, on the XY plane, one of the two transfer gates (130b) may be disposed so as to be spaced apart from the floating diffusion region (FD) in the X direction, and the other of the two transfer gates (130b) may be disposed so as to be spaced apart from the floating diffusion region (FD) in the Y direction. In this case, the distance in the X direction of one of the two transfer gates (130b) may be the same as the distance in the Y direction of the other of the two transfer gates (130b).

[0060] In an exemplary embodiment, each of the two transfer gates (130b) may be a vertical transfer gate (VTG). Specifically, each of the two transfer gates (130b) may include a horizontal portion (131a2), a vertical portion (131b2), and a gate insulating film (133_2). The horizontal portion (131a2), the vertical portion (131b2), and the gate insulating film (133_2) may be similar to the horizontal portion (131a1), the vertical portion (131b1), and the gate insulating film (133_1) described with reference to FIG. 3 and FIG. 4a. In an exemplary embodiment, the gate insulating films (133_2) included in each of the two transfer gates (130b) may be in contact with an intrinsic semiconductor region (110_1a2).

[0061] Each of the two transfer gates (130b) can be connected to the first contact plugs (141a2). The first contact plugs (141a2) can penetrate a portion of the horizontal portion (131a2) of each of the two transfer gates (130b).

[0062] An intrinsic semiconductor region (110_1a2) may be placed between each of the two transfer gates (130b) and a floating diffusion region (FD). The floating diffusion region (FD) may be surrounded by the intrinsic semiconductor region (110_1a2).

[0063] FIGS. 6b and 6c are cross-sectional views showing cross-sections corresponding to the cross-section cut along the line A2-A2' of FIG. 5. Since the respective configurations of the image sensors (100b2, 100c2) shown in FIGS. 6b and 6c are similar to the respective configurations of the image sensor (100a2) described with reference to FIGS. 5 and 6a, the following description will focus on the differences.

[0064] Referring to FIG. 6b, the image sensor (100b2) may include an intrinsic semiconductor region (110_1b2) and an impurity semiconductor region (110_2b2). The intrinsic semiconductor region (110_1b2) may be positioned between each of the two transfer gates (130b) and the floating diffusion region (FD). At this time, the impurity semiconductor region (110_2b2) is interposed in the middle of the intrinsic semiconductor region (110_1b2), and the intrinsic semiconductor region (110_1b2) may be separated by the impurity semiconductor region (110_2b2). Accordingly, one side of the intrinsic semiconductor region (110_1b2) may be in contact with the transfer gate (130b), and the other side of the intrinsic semiconductor region (110_1b2) may be in contact with the impurity semiconductor region (110_2b2) and the floating diffusion region (FD). In an exemplary embodiment, a portion of the intrinsic semiconductor region (110_1b2) located at a vertical level lower than the floating diffusion region (FD) may be extended in a first direction toward the floating diffusion region (FD). In this case, the portion of the intrinsic semiconductor region (110_1b2) extended in the first direction may overlap with a portion of the floating diffusion region (FD) in a second direction.

[0065] Referring to FIG. 6c, the image sensor (100c2) may include an intrinsic semiconductor region (110_1c2) and an impurity semiconductor region (110_2c2). The intrinsic semiconductor region (110_1c2) may be positioned between each of the two transfer gates (130b) and the floating diffusion region (FD). At this time, the impurity semiconductor region (110_2c2) is positioned in the middle of the intrinsic semiconductor region (110_1c2), and the intrinsic semiconductor region (110_1c2) may be separated by the impurity semiconductor region (110_2c2). Accordingly, one side of the intrinsic semiconductor region (110_1c2) may be in contact with the transfer gate (130b), and the other side of the intrinsic semiconductor region (110_1c2) may be in contact with the impurity semiconductor region (110_2c2) and the floating diffusion region (FD). In an exemplary embodiment, the intrinsic semiconductor region (110_1c2) may not overlap with the floating diffusion region (FD) in the second direction. That is, some regions of the intrinsic semiconductor region (110_1c2) located at a vertical level lower than the floating diffusion region (FD) may not extend along the first direction.

[0066] FIG. 7 is a plan view showing a pixel of an image sensor (100a3) according to an exemplary embodiment of the present invention. FIG. 8a is a cross-sectional view showing a cross section cut along the line A3-A3' of FIG. 7. Since each component of the image sensor (100a3) illustrated in FIG. 7 and FIG. 8a is similar to each component of the image sensor (100) described with reference to FIG. 3 and FIG. 4a, the following description will focus on the differences.

[0067] Referring to FIGS. 7 and FIGS. 8a, the image sensor (100a3) includes a unit pixel (PX3), and a first active region (ACT1) located at the unit pixel (PX3) may have a transfer transistor (TX, see FIG. 2) and a floating diffusion region (FD) disposed therein. The transfer transistor (TX) may include a transfer gate (130c).

[0068] In an exemplary embodiment, the transfer gate (130c) may be a planar transfer gate. Specifically, the transfer gate (130c) may include only a horizontal portion disposed on the front surface (110A) of the substrate (110). The transfer gate (130c) may be connected to a first contact plug (141a3). The first contact plug (141a3) may penetrate a portion of the horizontal portion of the transfer gate (130c).

[0069] An intrinsic semiconductor region (110_1a3) can be positioned between a floating diffusion region (FD) and a transfer gate (130c). Since the transfer gate (130c) is a planar transfer gate, the intrinsic semiconductor region (110_1a3) can be located at a lower vertical level than the transfer gate (130c). Accordingly, the intrinsic semiconductor region (110_1a3) and the transfer gate (130c) may not be in contact.

[0070] In an exemplary embodiment, a portion of the intrinsic semiconductor region (110_1a3) located at a vertical level lower than the floating diffusion region (FD) may be extended along a first direction away from the transfer gate (130c). In this case, the portion of the intrinsic semiconductor region (110_1a3) extended along the first direction is located below the floating diffusion region (FD) and may overlap with the entire floating diffusion region (FD) in a second direction (i.e., vertically).

[0071] The impurity semiconductor region (110_2a3) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130c). Some regions of the impurity semiconductor region (110_2a3) located at a vertical level lower than the floating diffusion region (FD) may be in contact with some regions of the intrinsic semiconductor region (110_1a3) extended along the first direction, and the remaining regions of the impurity semiconductor region (110_2a3), excluding the aforementioned regions of the impurity semiconductor region (110_2a3), may be in contact with the floating diffusion region (FD).

[0072] FIGS. 8b to 8d are cross-sectional views showing cross-sections corresponding to the cross-section cut along the line A3-A3' of FIG. 7. Since the respective configurations of the image sensors (100b3, 100c3, 100d3) illustrated in FIGS. 8b to 8d are similar to the respective configurations of the image sensor (100a3) described with reference to FIGS. 7 and FIG. 8a, the following description will focus on the differences.

[0073] Referring to FIG. 8b, the image sensor (100b3) may include an intrinsic semiconductor region (110_1b3) and an impurity semiconductor region (110_2b3). The intrinsic semiconductor region (110_1b3) may be positioned between a floating diffusion region (FD) and a transfer gate (130c). In an exemplary embodiment, a portion of the intrinsic semiconductor region (110_1b3) located at a vertical level lower than the floating diffusion region (FD) may extend in a first direction toward the floating diffusion region (FD). In this case, a portion of the intrinsic semiconductor region (110_1b3) extended in the first direction may overlap with a portion of the floating diffusion region (FD) in a second direction.

[0074] The impurity semiconductor region (110_2b3) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130c). In this case, a portion of the impurity semiconductor region (110_2b3) located at a vertical level lower than the floating diffusion region (FD) may be extended in a first direction along the direction toward the floating diffusion region (FD). In this case, a portion of the impurity semiconductor region (110_2b3) extended in the first direction may overlap with a portion of the remaining portion of the floating diffusion region (FD) in a second direction. Additionally, a portion of the impurity semiconductor region (110_2b3) extended along the first direction may be in contact with a portion of the intrinsic semiconductor region (110_1b3) extended along the first direction.

[0075] Referring to FIG. 8c, the image sensor (100c3) may include an intrinsic semiconductor region (110_1c3) and an impurity semiconductor region (110_2c3). The intrinsic semiconductor region (110_1c3) may be positioned between a floating diffusion region (FD) and a transfer gate (130c). In an exemplary embodiment, the intrinsic semiconductor region (110_1c3) may not overlap with the floating diffusion region (FD) in the second direction. That is, some regions within the intrinsic semiconductor region (110_1c3) located at a vertical level lower than the floating diffusion region (FD) may not extend along the first direction.

[0076] The impurity semiconductor region (110_2c3) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130c). In this case, a portion of the impurity semiconductor region (110_2c3) located at a vertical level lower than the floating diffusion region (FD) may be extended in a first direction toward the transfer gate (130c). In this case, a portion of the impurity semiconductor region (110_2c3) extended along the first direction may overlap with the entire floating diffusion region (FD) in a second direction. Additionally, a portion of the impurity semiconductor region (110_2c3) extended along the first direction may be in contact with a portion of the intrinsic semiconductor region (110_1c3) located at a vertical level lower than the floating diffusion region (FD).

[0077] Referring to FIG. 8d, the image sensor (100d3) may include an intrinsic semiconductor region (110_1d3) and an impurity semiconductor region (110_2d3).

[0078] An intrinsic semiconductor region (110_1d3) may be placed between a floating diffusion region (FD) and a transfer gate (130c). In an exemplary embodiment, the intrinsic semiconductor region (110_1d3) may surround the floating diffusion region (FD).

[0079] The impurity semiconductor region (110_2d3) may be positioned so as to be spaced apart from the floating diffusion region (FD) on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130c). At this time, the impurity semiconductor region (110_2d3) may be in contact with one side of the intrinsic semiconductor region (110_1d3) surrounding the floating diffusion region (FD).

[0080] FIG. 9 is a circuit diagram of a pixel array of an image sensor according to an exemplary embodiment of the present invention.

[0081] Referring to FIG. 9, a unit pixel (PX) may comprise a 4-shared pixel including first to fourth photodiodes (PD1, PD2, PD3, PD4). In this case, the first to fourth photodiodes (PD1, PD2, PD3, PD4) may have a structure that shares one floating diffusion region (FD).

[0082] In a unit pixel (PX), the first to fourth photodiodes (PD1, PD2, PD3, PD4) sharing one floating diffusion region (FD) can be achieved through first to fourth transfer transistors (TX1, TX2, TX3, TX4) corresponding to the first to fourth photodiodes (PD1, PD2, PD3, PD4). That is, the first transfer transistor (TX1) corresponding to the first photodiode (PD1), the second transfer transistor (TX2) corresponding to the second photodiode (PD2), the third transfer transistor (TX3) corresponding to the third photodiode (PD3), and the fourth transfer transistor (TX4) corresponding to the fourth photodiode (PD4) can share one floating diffusion region (FD) as a common drain region.

[0083] As shown in FIG. 9, the first to fourth photodiodes (PD1, PD2, PD3, PD4) in a unit pixel (PX) may share a reset transistor (RX), a source follower transistor (SF), and a select transistor (SX).

[0084] As illustrated in FIG. 9, the first to fourth photodiodes (PD1, PD2, PD3, PD4) can each constitute the source region of the corresponding first to fourth transfer transistors (TX1, TX2, TX3, TX4). The floating diffusion region (FD) can constitute the common drain region of the first to fourth transfer transistors (TX1, TX2, TX3, TX4). The floating diffusion region (FD) can be connected to the source region of the reset transistor (RX) and the gate electrode of the source follower transistor (SF), respectively. The drain region of the reset transistor (RX) and the drain region of the source follower transistor (SF) can be shared and connected to the power supply voltage (Vpix). The source region of the source follower transistor (SF) and the drain region of the select transistor (SX) can be shared with each other. An output line (Vout) can be connected to the source region of the select transistor (SX).

[0085] FIG. 9 illustrates a case where a unit pixel (PX) comprises a 4-shared pixel including first to fourth photodiodes (PD1, PD2, PD3, PD4), but is not limited thereto. For example, a unit pixel (PX) may comprise an N-shared pixel comprising N photodiodes (N is an integer greater than or equal to 2). Specifically, a plurality of pixel units (PX) included in an image sensor may each comprise a 2-shared pixel comprising 2 photodiodes, or an 8-shared pixel comprising 8 photodiodes.

[0086] FIG. 10 is a plan view schematically showing a pixel of an image sensor (100a4) according to an exemplary embodiment of the present invention. FIG. 11a is a cross-sectional view showing a cross section cut along the line A4-A4' of FIG. 10.

[0087] Referring to FIG. 10 and FIG. 11a, the image sensor (100a4) includes a unit pixel (PX4). The unit pixel (PX4) may include four photoelectric conversion regions (PDs) formed on a substrate (110). A floating diffusion region (FD) may be located at the center of the unit pixel (PX4). The four photoelectric conversion regions (PDs) share the floating diffusion region (FD) and may be arranged outwardly around the floating diffusion region (FD) to surround the floating diffusion region (FD).

[0088] Two transfer gates (130d) may be disposed in each of the four photoelectric conversion regions (PD). Each of the two transfer gates (130d) may be disposed at an equal distance from the floating diffusion region (FD). In an exemplary embodiment, each of the two transfer gates (130d) may be a vertical transfer gate (VTG). Specifically, each of the two transfer gates (130d) may include a horizontal portion (131a3) disposed on the front surface (110A) of the substrate (110), a vertical portion (131b3) connected to the horizontal portion (131a3) and extending from the front surface (110A) of the substrate (110) into the interior of the substrate (110), and a gate insulating film (133_3) covering the lower surface of the horizontal portion (131a3) and the side wall of the vertical portion (131b3).

[0089] Each of the two transfer gates (130d) can be connected to the first contact plugs (141a4). The first contact plugs (141a4) can penetrate a portion of the horizontal portion (131a3) of each of the two transfer gates (130d).

[0090] An intrinsic semiconductor region (110_1a4) can be placed between each of the two transfer gates (130d) and the floating diffusion region (FD). The floating diffusion region (FD) can be surrounded by the intrinsic semiconductor region (110_1a4).

[0091] FIGS. 11b and FIG. 11c are cross-sectional views showing cross-sections corresponding to the cross-section cut along the line A4-A4' of FIG. 10. Since the respective configurations of the image sensors (100b4, 100c4) shown in FIGS. 11b and FIG. 11c are similar to the respective configurations of the image sensor (100a4) described with reference to FIGS. 10 and FIG. 11a, the following description will focus on the differences.

[0092] Referring to FIG. 11b, the image sensor (100b4) may include an intrinsic semiconductor region (110_1b4) and an impurity semiconductor region (110_2b4). Since each of the intrinsic semiconductor region (110_1b4) and the impurity semiconductor region (110_2b4) is similar to the intrinsic semiconductor region (110_1b2) and the impurity semiconductor region (110_2b2) described with reference to FIG. 6b, a detailed description is omitted.

[0093] Referring to FIG. 11c, the image sensor (100c4) may include an intrinsic semiconductor region (110_1c4) and an impurity semiconductor region (110_2c4). Since each of the intrinsic semiconductor region (110_1c4) and the impurity semiconductor region (110_2c4) is similar to the intrinsic semiconductor region (110_1c2) and the impurity semiconductor region (110_2c2) described with reference to FIG. 6c, a detailed description is omitted.

[0094] FIG. 12 is a plan view schematically showing a pixel of an image sensor according to an exemplary embodiment of the present invention. FIG. 13a is a cross-sectional view showing a cross section cut along the line A5-A5' of FIG. 12. Since each component of the image sensor (100a5) shown in FIG. 12 and FIG. 13a is similar to each component of the image sensor (100a4) described with reference to FIG. 10 and FIG. 11a, the following description will focus on the differences.

[0095] Referring to FIGS. 12 and FIGS. 13a, the image sensor (100a5) includes a unit pixel (PX5) in which four photoelectric conversion regions (PDs) are arranged. A transfer gate (130e) may be arranged in each of the four photoelectric conversion regions (PDs). In an exemplary embodiment, the transfer gate (130e) may be a vertical transfer gate (VTG). Specifically, the transfer gate (130e) may include a horizontal portion (131a4) arranged on the front surface (110A) of the substrate (110), a vertical portion (131b4) connected to the horizontal portion (131a4) and extending from the front surface (110A) of the substrate (110) into the interior of the substrate (110), and a gate insulating film (133_4) covering the lower surface of the horizontal portion (131a4) and the sidewall of the vertical portion (131b4).

[0096] The transfer gate (130e) can be connected to the first contact plugs (141a5). The first contact plugs (141a5) can penetrate a portion of the horizontal portion (131a4) of the transfer gate (130e).

[0097] The intrinsic semiconductor region (110_1a5) can be placed between the floating diffusion region (FD) and the transfer gate (130e).

[0098] In an exemplary embodiment, some regions of the intrinsic semiconductor region (110_1a5) located at a vertical level lower than the floating diffusion region (FD) may be extended along a first direction away from the transfer gate (130e). In this case, the portion of the intrinsic semiconductor region (110_1a5) extended along the first direction is located below the floating diffusion region (FD) and may overlap with the entire floating diffusion region (FD) in a second direction (i.e., vertically).

[0099] The impurity semiconductor region (110_2a5) may be positioned on one side of the floating diffusion region (FD) that is not adjacent to the transfer gate (130e). Some regions of the impurity semiconductor region (110_2a5) located at a vertical level lower than the floating diffusion region (FD) may be in contact with some regions of the intrinsic semiconductor region (110_1a5) extended along the first direction, and the remaining regions of the impurity semiconductor region (110_2a5), excluding the aforementioned regions of the impurity semiconductor region (110_2a5), may be in contact with the floating diffusion region (FD).

[0100] FIGS. 13b and FIG. 13c are cross-sectional views showing cross-sections corresponding to the cross-section cut along the line A5-A5' of FIG. 12. Since the respective configurations of the image sensors (100b5, 100c5) shown in FIGS. 13b and FIG. 13c are similar to the respective configurations of the image sensor (100a5) described with reference to FIGS. 12 and FIG. 13a, the following description will focus on the differences.

[0101] Referring to FIG. 13b, the image sensor (100b5) may include an intrinsic semiconductor region (110_1b5) and an impurity semiconductor region (110_2b5). Since each of the intrinsic semiconductor region (110_1b5) and the impurity semiconductor region (110_2b5) is similar to the intrinsic semiconductor region (110_1a1) and the impurity semiconductor region (110_2a1) described with reference to FIG. 4b, a detailed description is omitted.

[0102] Referring to FIG. 13c, the image sensor (100c5) may include an intrinsic semiconductor region (110_1c5) and an impurity semiconductor region (110_2c5). Since each of the intrinsic semiconductor region (110_1c5) and the impurity semiconductor region (110_2c5) is similar to the intrinsic semiconductor region (110_1b1) and the impurity semiconductor region (110_2b1) described with reference to FIG. 4c, a detailed description is omitted.

[0103] FIGS. 14a to 14e are cross-sectional views illustrating a method for manufacturing an image sensor (100) according to an exemplary embodiment of the present invention.

[0104] Referring to FIG. 14a, a first mask pattern (M10) is formed on the front surface (110A) of a substrate (110), and the first mask pattern (M10) is used as an etching mask to form a device isolation trench (120T) within the substrate (110).

[0105] Referring to FIG. 14b, in the result of FIG. 14a, a device isolation film (120) can be formed within a device isolation trench (120T). Next, a mask pattern (not shown) can be formed on the front surface (110A) of the substrate (110), and a portion of the substrate (110) can be removed using the mask pattern as an etching mask to form a transfer gate trench (not shown), and a transfer gate (130a) can be formed within the transfer gate trench. Next, a first ion implantation mask (M20) can be formed on the front surface (110A) of the substrate (110), and a first impurity can be implanted into the substrate (110) by an ion implantation process (P10) using the first ion implantation mask (M20) to form an impurity semiconductor region (110_2). The first impurity may be, for example, a p-type impurity.

[0106] Referring to FIG. 14c, a second ion implantation mask (M30) can be formed on the front surface (110A) of the substrate (110) in the result of FIG. 14b. The second ion implantation mask (M30) may include an opening (M30T). Although FIG. 14c is illustrated as not having the opening (M30T) perpendicularly overlapping the impurity semiconductor region (110_2), some or all of the opening (M30T) may overlap with the impurity semiconductor region (110_2). Next, using the second ion implantation mask (M30), a second impurity can be implanted into the substrate (110) by an ion implantation process (P20) to form a floating diffusion region (FD). The second impurity may be, for example, an n-type impurity.

[0107] Referring to FIG. 14d, in the result of 14c, an interlayer insulating film (147) can be formed on the front surface (110A) of the substrate (110). Next, a mask pattern (not shown) can be formed on the interlayer insulating film (147), and a first contact plug (141a1) and a second contact plug (141b) penetrating the interlayer insulating film (147) can be formed using the mask pattern as an etching mask. Next, a conductive layer (not shown) can be formed on the interlayer insulating film (147), the conductive layer can be patterned, and an insulating layer (not shown) covering the patterned conductive layer can be formed by repeatedly performing steps such as forming a wiring line (151a), a wiring via (151b), and a wiring insulating layer (153) to form a wiring structure (150, see FIG. 4a).

[0108] Referring to FIG. 14e, in the result of FIG. 14d, an image sensor (100) can be completed by sequentially forming an anti-reflection film (160), a color filter (CF), and a microlens (ML) on the back surface (110B) of the substrate (110).

[0109] An image sensor (100) according to an exemplary embodiment of the present invention includes an intrinsic semiconductor region (110_1) which is disposed between a transfer gate (130a) and a floating diffusion region (FD) and is not separately doped by impurities. Accordingly, when impurities are doped between the transfer gate (130a) and the floating diffusion region (FD), random dopant fluctuation (RDF) that may occur due to the doped impurities can be reduced. Through this, the noise characteristics of the image sensor (100) are improved, and the occurrence of potential hump is prevented, thereby improving the full-well capacity (FWC) of the image sensor (100).

[0110] FIG. 15 is a block diagram of an electronic device including a multi-camera module. FIG. 16 is a detailed block diagram of the camera module of FIG. 15.

[0111] Referring to FIG. 15, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400).

[0112] The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although the drawing shows an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiments are not limited thereto. In some embodiments, the camera module group (1100) may be modified to include only two camera modules. Also, in some embodiments, the camera module group (1100) may be modified to include n camera modules (n is a natural number greater than or equal to 4).

[0113] Hereinafter, with reference to FIG. 16, the detailed configuration of the camera module (1100b) will be described in more detail, but the following description may be applied equally to other camera modules (1100a, 1100b) according to the embodiment.

[0114] Referring to FIG. 16, the camera module (1100b) may include a prism (1105), an optical path folding element (OPFE, hereinafter referred to as "OPFE") (1110), an actuator (1130), an image sensing device (1140), and a storage unit (1150).

[0115] The prism (1105) can modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material.

[0116] In some embodiments, the prism (1105) can change the path of light (L) incident in a first direction (X) to a second direction (Y) perpendicular to the first direction (X). Additionally, the prism (1105) can change the path of light (L) incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X) by rotating the reflective surface (1107) of the light-reflecting material in direction A around the central axis (1106) or by rotating the central axis (1106) in direction B. At this time, the OPFE (1110) can also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0117] In some embodiments, as illustrated, the maximum rotation angle of the prism (1105) in the A direction may be 15 degrees or less in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, but the embodiments are not limited thereto.

[0118] In some embodiments, the prism (1105) can move in the plus (+) or minus (-) B direction by about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be moved by the same angle in the plus (+) or minus (-) B direction, or by a nearly similar angle within a range of about 1 degree.

[0119] In some embodiments, the prism (1105) can move the reflective surface (1106) of the light-reflecting material in a third direction (e.g., Z direction) parallel to the extension direction of the central axis (1106).

[0120] OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The m lenses can be moved in a second direction (Y) to change the optical zoom ratio of the camera module (1100b). For example, when the basic optical zoom ratio of the camera module (1100b) is Z, moving the m optical lenses included in the OPFE (1110) may change the optical zoom ratio of the camera module (1100b) to an optical zoom ratio of 3Z or 5Z or more.

[0121] The actuator (1130) can move the OPFE (1110) or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator (1130) can adjust the position of the optical lens so that the image sensor (1142) is positioned at the focal length of the optical lens for accurate sensing.

[0122] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) can sense an image of a sensing target using light (L) provided through an optical lens. The control logic (1144) can control the overall operation of the camera module (1100b). For example, the control logic (1144) can control the operation of the camera module (1100b) according to a control signal provided through a control signal line (CSLb).

[0123] The memory (1146) can store information necessary for the operation of the camera module (1100b), such as calibration data (1147). The calibration data (1147) may include information necessary for the camera module (1100b) to generate image data using light (L) provided from the outside. The calibration data (1147) may include, for example, information regarding the degree of rotation described above, information regarding the focal length, information regarding the optical axis, etc. If the camera module (1100b) is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data (1147) may include focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing.

[0124] The storage unit (1150) can store image data sensed through the image sensor (1142). The storage unit (1150) may be placed outside the image sensing device (1140) and may be implemented in a stacked form with the sensor chip constituting the image sensing device (1140). In some embodiments, the storage unit (1150) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto.

[0125] Referring to FIG. 15 and FIG. 16 together, in some embodiments, each of a plurality of camera modules (1100a, 1100b, 1100c) may include an actuator (1130). Accordingly, each of the plurality of camera modules (1100a, 1100b, 1100c) may include identical or different calibration data (1147) according to the operation of the actuator (1130) included therein.

[0126] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100b) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but the embodiments are not limited thereto.

[0127] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data provided from this depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0128] In some embodiments, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0129] Additionally, in some embodiments, the field of view of each of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also be different from each other, but are not limited thereto.

[0130] In some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0131] Referring again to FIG. 15, the application processor (1200) may include an image processing device (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separately from a plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor (1200) and the plurality of camera modules (1100a, 1100b, 1100c) may be implemented separately from each other as separate semiconductor chips.

[0132] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216).

[0133] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0134] Image data generated from each camera module (1100a, 1100b, 1100c) can be provided to corresponding sub-image processors (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module (1100a) can be provided to sub-image processor (1212a) via image signal line (ISLa), image data generated from camera module (1100b) can be provided to sub-image processor (1212b) via image signal line (ISLb), and image data generated from camera module (1100c) can be provided to sub-image processor (1212c) via image signal line (ISLc). Such image data transmission can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0135] Meanwhile, in some embodiments, a single sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor (1212a) and the sub-image processor (1212c) are not implemented separately as illustrated, but are integrated into a single sub-image processor, and image data provided from the camera module (1100a) and the camera module (1100c) may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0136] Image data provided to each sub-image processor (1212a, 1212b, 1212c) may be provided to an image generator (1214). The image generator (1214) may generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0137] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal.

[0138] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based, for example, on a mode selected by a user.

[0139] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different viewing angle (angle of view), the image generator (1214) can perform different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image data output from the camera module (1100a) and the image data output from the camera module (1100c) can be merged, and then an output image can be generated using the merged image signal and the image data output from the camera module (1100b) that was not used for merging. If the zoom signal is a second signal different from the first signal, the image generator (1214) can generate an output image by selecting one of the image data output from each camera module (1100a, 1100b, 1100c) without performing such image data merging. However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0140] In some embodiments, the image generator (1214) receives multiple image data with different exposure times from at least one of a plurality of sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0141] The camera module controller (1216) can provide control signals to each camera module (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0142] One of the plurality of camera modules (1100a, 1100b, 1100c) may be designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a, 1100c) may be designated as slave cameras. This information may be included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0143] The camera module operating as a master and slave may be changed according to the zoom factor or operation mode signal. For example, if the field of view of the camera module (1100a) is wider than the field of view of the camera module (1100b) and the zoom factor indicates a low zoom magnification, the camera module (1100b) may operate as a master and the camera module (1100a) may operate as a slave. Conversely, if the zoom factor indicates a high zoom magnification, the camera module (1100a) may operate as a master and the camera module (1100b) may operate as a slave.

[0144] In some embodiments, the control signal provided from the camera module controller (1216) to each camera module (1100a, 1100b, 1100c) may include a sync enable signal. For example, if the camera module (1100b) is a master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller (1216) may transmit a sync enable signal to the camera module (1100b). The camera module (1100b) that receives this sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules (1100a, 1100c) through a sync signal line (SSL). The camera module (1100b) and camera modules (1100a, 1100c) can be synchronized with this sync signal to transmit image data to the application processor (1200).

[0145] In some embodiments, a control signal provided from a camera module controller (1216) to a plurality of camera modules (1100a, 1100b, 1100c) may include mode information according to a mode signal. Based on this mode information, the plurality of camera modules (1100a, 1100b, 1100c) may operate in a first operation mode and a second operation mode with respect to the sensing speed.

[0146] A plurality of camera modules (1100a, 1100b, 1100c) can, in a first operating mode, generate an image signal at a first speed (e.g., generate an image signal at a first frame rate) and encode it at a second speed higher than the first speed (e.g., encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to an application processor (1200). At this time, the second speed may be 30 times or less of the first speed.

[0147] The application processor (1200) stores the received image signal, that is, the encoded image signal, in a memory (1230) provided internally or in a storage (1400) outside the application processor (1200), and subsequently reads the encoded image signal from the memory (1230) or the storage (1400) to decode it, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device (1210) can perform decoding, and can also perform image processing on the decoded image signal.

[0148] A plurality of camera modules (1100a, 1100b, 1100c) can generate an image signal at a third speed lower than a first speed in a second operation mode (e.g., generate an image signal at a third frame rate lower than a first frame rate) and transmit the image signal to an application processor (1200). The image signal provided to the application processor (1200) may be an unencoded signal. The application processor (1200) may perform image processing on the received image signal or store the image signal in memory (1230) or storage (1400).

[0149] The PMIC (1300) can supply power, such as power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0150] The PMIC (1300) can generate power corresponding to each of the plurality of camera modules (1100a, 1100b, 1100c) and adjust the power level in response to a power control signal (PCON) from the application processor (1200). The power control signal (PCON) may include power adjustment signals for each operating mode of the plurality of camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the power level being set. The power levels provided to each of the plurality of camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Additionally, the power level may be changed dynamically.

[0151] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0152] 100: Image sensor, FD: Floating diffusion region, PD: Photoelectric conversion region, 110_1: Intrinsic semiconductor region, 110_2: Impurity semiconductor region, 110: Substrate, 120: Device isolation layer, 130: Transfer gate

Claims

Claim 1 An image sensor comprising: a substrate; at least one transfer gate disposed on an upper surface of the substrate; a floating diffusion region disposed within the substrate so as to be spaced apart from the transfer gate in a first direction parallel to the upper surface; an intrinsic semiconductor region disposed between the transfer gate and the floating diffusion region within the substrate; and a photoelectric conversion region disposed within the substrate so as to be spaced apart from the floating diffusion region in a second direction perpendicular to the first direction, wherein the intrinsic semiconductor region is a region not doped with impurities. Claim 2 In claim 1, the intrinsic semiconductor region is an image sensor that extends to the upper surface of the photoelectric conversion region along the second direction. Claim 3 An image sensor according to claim 1, wherein a portion of the intrinsic semiconductor region located at a vertical level lower than the floating diffusion region extends along the first direction and overlaps with the entire floating diffusion region in the second direction. Claim 4 An image sensor according to claim 1, wherein a portion of the intrinsic semiconductor region located at a vertical level lower than the floating diffusion region extends along the first direction and overlaps with a portion of the floating diffusion region in the second direction. Claim 5 In claim 1, the intrinsic semiconductor region is an image sensor that does not overlap with the floating diffusion region in the second direction. Claim 6 An image sensor according to claim 1, wherein the transfer gate comprises a horizontal portion disposed on the upper surface of the substrate, a vertical portion extending from the lower surface of the horizontal portion into the interior of the substrate, and a gate insulating film covering the horizontal portion and the vertical portion. Claim 7 An image sensor according to claim 1, comprising a plurality of transfer gates disposed on the upper surface of the substrate, wherein each of the plurality of transfer gates comprises a horizontal portion disposed on the upper surface of the substrate, a vertical portion extending from the lower surface of the horizontal portion into the interior of the substrate, and a gate insulating film covering the horizontal portion and the vertical portion. Claim 8 In claim 1, the transfer gate is a planar transfer gate, an image sensor. Claim 9 An image sensor comprising: a substrate; a floating diffusion region located within the substrate; a plurality of photoelectric conversion regions disposed around the floating diffusion region within the substrate; at least one transfer gate disposed in each of the plurality of photoelectric conversion regions so as to be spaced apart in a first direction parallel to the floating diffusion region and the upper surface of the substrate; and an intrinsic semiconductor region disposed between each of the plurality of transfer gates and the floating diffusion region within the substrate, wherein the intrinsic semiconductor region is a region not doped by impurities. Claim 10 An image sensor according to claim 9, wherein at least two transfer gates are disposed in each of the plurality of photoelectric conversion regions, and the at least two transfer gates comprise a horizontal portion disposed on the upper surface of the substrate, a vertical portion extending from the lower surface of the horizontal portion into the interior of the substrate, and a gate insulating film covering the horizontal portion and the vertical portion.

Images