Digital-to-analog converter including current cell arrary

Abstract

A digital-to-analog converter configured to generate an analog output from a digital input may include a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude, a first pattern connecting first current cells arranged along a diagonal of the current cell array among the plurality of current cells, a second pattern connecting second current cells arranged along a first diagonal parallel to the diagonal among the plurality of current cells, and a third pattern connecting third current cells arranged along a second diagonal parallel to the diagonal among the plurality of current cells and electrically connected to the second pattern, wherein the diagonal may be between the first diagonal and the second diagonal.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a digital-to-analog converter, and specifically to a digital-to-analog converter comprising a current cell array. Background Technology

[0002] A digital-to-analog converter can convert a digital input into an analog output. As one of the various structures of a digital-to-analog converter, a current-steering digital-to-analog converter can generate a current with a magnitude corresponding to the value of the digital input and produce an analog output from the generated current. A current-steering digital-to-analog converter may include multiple current sources that generate currents according to the digital input, and a mismatch among the multiple current sources can degrade the linearity of the current-steering digital-to-analog converter. The problem to be solved

[0003] The technical concept of the present disclosure provides a digital-to-analog converter that provides high linearity and a method of operation of the digital-to-analog converter. means of solving the problem

[0004] To achieve the above objectives, according to one aspect of the technical concept of the present disclosure, a digital-to-analog converter configured to generate an analog output from a digital input may include a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude, a first pattern connecting first current cells arranged along a diagonal of the current cell array among the plurality of current cells, a second pattern connecting second current cells arranged along a first diagonal parallel to the diagonal among the plurality of current cells, and a third pattern connecting third current cells arranged along a second diagonal parallel to the diagonal among the plurality of current cells and electrically connected to the second pattern, wherein the diagonal may be between the first diagonal and the second diagonal.

[0005] According to one aspect of the technical concept of the present disclosure, a digital-to-analog converter configured to generate an analog output from a digital input may include a decoder configured to generate a thermometer code from an upper bit group including the MSB (most significant bit) of the digital input, a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude, and a switch circuit configured to select at least some of the currents generated by the current cell array, wherein the plurality of current cells may include first current cells arranged along a diagonal of the current cell array and corresponding to a first bit of the thermometer code, second current cells arranged along a first diagonal parallel to the diagonal and corresponding to a second bit of the thermometer code, and third current cells arranged along a second diagonal parallel to the diagonal and corresponding to a second bit of the thermometer code, and the diagonal may be between the first diagonal and the second diagonal.

[0006] According to one aspect of the technical concept of the present disclosure, a method for converting a digital input into an analog output may include: generating a thermometer code from an upper bit group including the MSB (most significant bit) of the digital input; generating a reference current by a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude; selecting at least a portion of the reference current based on the thermometer code and a lower bit group including the LSB (least significant bit) of the digital input; and generating an analog output by summing the selected currents. The step of selecting at least a portion of the generated currents may include selecting currents generated by first current cells that are mutually exclusively arranged in the rows of the current cell array and mutually exclusively arranged in the columns of the current cell array among the plurality of current cells, based on one bit of the thermometer code. Effects of the invention

[0007] According to the digital-to-analog converter according to the exemplary embodiment of the present disclosure, degradation of linearity can be minimized despite the occurrence of various variations.

[0008] In addition, according to the digital-to-analog converter according to the exemplary embodiment of the present disclosure, the linearity of the digital-to-analog converter can be improved without additional area or power, and accordingly, the performance and efficiency of an application including the digital-to-analog converter can be simultaneously increased.

[0009] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the description below. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram showing a digital-to-analog converter according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing a digital-to-analog converter according to an exemplary embodiment of the present disclosure. FIGS. 3a and 3b are drawings illustrating examples of current cell arrays according to exemplary embodiments of the present disclosure. FIGS. 4a and FIGS. 4b are drawings showing examples of current cells selected according to input in accordance with exemplary embodiments of the present disclosure. FIG. 5 is a plan view showing the layout of a digital-to-analog converter according to an exemplary embodiment of the present disclosure. FIGS. 6a and FIGS. 6b are circuit diagrams showing examples of current cells according to exemplary embodiments of the present disclosure. FIG. 7 is a plan view showing the layout of a digital-to-analog converter according to an exemplary embodiment of the present disclosure. FIG. 8 is a flowchart illustrating a method for converting a digital input into an analog output according to an exemplary embodiment of the present disclosure. FIG. 9 is a flowchart illustrating a method for converting a digital input into an analog output according to an exemplary embodiment of the present disclosure. FIG. 10 is a block diagram showing a signal processing system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0011] FIG. 1 is a block diagram illustrating a digital-to-analog converter (10) according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 1, the digital-to-analog converter (10) may include a current cell array (11), a bias generator (12), a decoder (13), a delay circuit (14), a switch circuit (15), and a summing circuit (16). In some embodiments, the digital-to-analog converter (10) may further include a latch circuit that latches an input (IN), and the latch circuit may provide an upper bit group (IN[N:M+1]) and a lower bit group (IN[M:1]) of the latched input (IN) to the decoder (13) and the delay circuit (14), respectively.

[0012] A digital-to-analog converter (10) can receive a digital input and generate an analog output having a magnitude corresponding to the value of the digital input. For example, as illustrated in FIG. 1, the digital-to-analog converter (10) can generate an output (OUT) from an input (IN) of N bits (N is an integer greater than 1). In some embodiments, the digital-to-analog converter (10) can be manufactured by a semiconductor process. In some embodiments, the components of the digital-to-analog converter (10) can be contained in a single die or package. In some embodiments, the components of the digital-to-analog converter (10) can each be contained in two or more packages, and the digital-to-analog converter (10) can include a printed circuit board (PCB) on which two or more packages are mounted.

[0013] The current cell array (11) may include a plurality of current cells, each designed to generate a current of the same magnitude. For example, as shown in FIG. 1, the current cell array (11) may include a current cell (CC), and the current cell (CC) generates an LSB current (I) based on a bias signal (BS) provided from a bias generator (12). LSB It can be designed to generate a reference current (I) comprising LSB currents generated by each of the plurality of current cells. REF It can generate ) and reference current (I REF ) can be provided to the switch circuit (15) through a plurality of wires. In some embodiments, unlike as shown in FIG. 1, the current cell array (11) has a reference current (I REF ) can also be drained from the switch circuit (15). As described below, the reference current (I REF At least a portion of ) can be selected by the switch circuit (15), and the selected current (I SEL ) can have a size corresponding to the value of the input (IN).

[0014] The bias generator (12) can provide a bias signal (BS) to the current cell array (11). For example, the bias generator (12) can generate at least one bias voltage, and a plurality of current cells included in the current cell array (11) can receive the at least one bias voltage provided from the bias generator (12) in common. In some embodiments, the bias generator (12) can adjust the bias signal (BS) based on external control, and accordingly, the LSB current (I) generated by each of the plurality of current cells LSB The magnitude of ) can be adjusted, and consequently, the reference current (I REF The size of ) can be adjusted.

[0015] The decoder (13) can receive an upper bit group containing the MSB (most significant bit) of an input (IN) and can decode the upper bit group into a thermometer code (TMP). The thermometer code (TMP) may refer to a code containing a number of 1s (or 0s) proportional to the value and may also refer to a unary code. For example, as illustrated in FIG. 1, the decoder (13) can receive an upper bit group (IN[N:M+1]) of (NM) bits containing the MSB (i.e., IN[N]) of an N-bit input (IN) (where M is an integer greater than 1 and less than N), (2 N-M -1) A bit thermometer code (TMP) can be generated. In this specification, the thermometer code (TMP) is assumed to contain a number of 1s proportional to the value of the upper bit group of the input (IN).

[0016] The delay circuit (14) can receive and delay a lower bit group containing the least significant bit (LSB) of the input (IN) and output the delayed lower bit group. For example, as shown in FIG. 1, the delay circuit (14) can receive an M-bit lower bit group (IN[M:1]) containing the LSB (i.e., IN[1]) of an N-bit input (IN) and output a delayed lower bit group (IN'[M:1]). In order for the thermometer code (TMP) generated from the same value of the input (IN) and the delayed lower bit group (IN'[M:1]) to be provided to the switch circuit (15) simultaneously, the delay circuit (14) can delay the lower bit group (IN[M:1]) of the input (IN) by an amount corresponding to the time it takes for the temperature code (TMP) to be generated from the upper bit group (IN[N:M+1]) of the input (IN) at the decoder (13). In some embodiments, the delay circuit (14) may include at least one logic gate, and the delay circuit (14) may delay a lower bit group (IN[M:1]) of an input (IN) based on the gate delay of at least one logic gate.

[0017] The switch circuit (15) can receive a thermometer code (TMP) from the decoder (13) and a delayed lower bit group (IN'[M:1]) from the delay circuit (14). Additionally, the switch circuit (15) can receive a reference current (I) from the current cell array (11). REF Can receive ), and based on the thermometer code (TMP) and the delayed lower bit group (IN'[M:1]), the reference current (I REF By selecting at least a portion of ), the selected current (I SEL) can be output. For example, as described below with reference to FIG. 2, each of the bits of the thermometer code (TMP) and the delayed lower bit group (IN'[M:1]) can correspond to one group of at least one current cell included in the current cell array (11), and the switch circuit (15) can output a reference current (I REF The currents generated by the group of current cells corresponding to the bit whose value is 1 can be selected. In this specification, the selection of the current generated by the current cells included in the current cell array (11) by the switch circuit (15) may simply be referred to as the selection of the corresponding current cells by the switch circuit (15).

[0018] The switch circuit (15) may include a plurality of switches controlled by a thermometer code (TMP) and a delayed lower bit group (IN'[M:1]), and each of the plurality of switches has a reference current (I REF The current generated by the corresponding group of current cells among ) is the selected current (I SEL It can be optionally included in ). For example, the switch circuit (15) receives a reference current (I) from the current cell array (11). REF It may include switches respectively connected to the wires provided with ), and a selected current (I SEL ) can be provided to the summing circuit (16) through wires connected to each switch.

[0019] The summing circuit (16) is a current (I) selected from the switch circuit (15). SEL Can receive ) and selected current (I SEL The output (OUT) can be generated by summing the currents included in ). For example, the selected current (I SELAs described above, the current may be provided from the switch circuit (15) through a plurality of wires, and the summing circuit (16) may generate an output (OUT) from the current received through the plurality of wires, and accordingly, the output (OUT) may have a magnitude corresponding to the value of the input (IN). In some embodiments, as described below with reference to FIG. 2, the summing circuit (16) may convert the summed current into a voltage and generate an output (OUT) having a voltage of a magnitude corresponding to the value of the input (IN).

[0020] In some embodiments, the current cell array (11) may include a number of current cells corresponding to a range of inputs (IN), and accordingly 2 N-1 It may include 2 current cells. In some embodiments, the current cell array (11) is 2 as described below with reference to FIG. 3a, etc. N It may include current cells, and 2 N One of the current cells may not be used or may always be summed by the summing circuit (16) regardless of the input (IN). As the number of bits of the input (IN), i.e., N, increases, the number of current cells included in the current cell array (11) may increase, and the area of ​​the current cell array (11) may increase. When the area of ​​the current cell array (11) increases, the effects on each of the multiple current cells included in the current cell array (11), such as process, voltage, temperature, etc., may differ. Accordingly, each of the multiple current cells may generate currents of different magnitudes, and as a result, the linearity of the digital-to-analog converter (10), such as differential nonlinearity (DNL) and integral nonlinearity (INL), may be degraded.

[0021] As described below, even if variations exist in the current cell array (11), the influence of the variations can be evenly distributed to the current cells selected by the switch circuit (15) according to the value of the input (IN). Accordingly, the degradation of the linearity of the digital-analog converter (10) can be minimized, and the linearity of the digital-analog converter (10) can be improved without additional costs, such as area or power, and accordingly, the performance and efficiency of the application including the digital-analog converter (10) can be increased simultaneously.

[0022] FIG. 2 is a block diagram illustrating a digital-to-analog converter (20) according to an exemplary embodiment of the present disclosure. Specifically, the block diagram of FIG. 2 schematically illustrates the operation of a current-steering digital-to-analog converter that generates an output (OUT) from an 8-bit input (IN) (N=8). In the example of FIG. 2, the lower bit group (IN[4:1]) of the input (IN) may include 4 bits (M=4), and the upper bit group (IN[8:4]) of the input (IN) may include 4 bits (NM=4). As illustrated in FIG. 2, the digital-to-analog converter (20) may include first to ninth current sources (CS1 to CS19), a switch circuit (21), a decoder (22), a delay circuit (23), and a summing circuit (24).

[0023] Each of the first to ninth current sources (CS1 to CS19) may include at least one current cell included in the current cell array (11) of FIG. 1. For example, an LSB current (I LSB The first current source (CS1) generating ) may include one current cell, and the LSB current (I LSB A second current source (CS2) that generates twice the amount of ) may include two current cells, and the LSB current (I LSB A third current source (CS3) generating four times ) may include four current cells, and the LSB current (I LSBThe fourth current source (CS4) generating eight times ) may include eight current cells. In addition, the LSB current (I LSB Each of the 5th to 19th current cells (CS5 to CS19), which each generate 16 times the value of ), may include 16 current cells. In this specification, the current cells included in the 1st to 4th current sources (CS1 to CS4) corresponding to the lower bit group of the input (IN) may be referred to as LSB current cells or LSB cells, and the current cells included in the 5th to 15th current sources (CS5 to CS19) corresponding to the upper bit group of the input (IN) may be referred to as MSB current cells or MSB cells.

[0024] The switch circuit (21) may include 19 switches corresponding to each of the first to 19th current sources (CS1 to CS19), and the 19 switches may each receive currents generated by the first to 19th current sources (CS1 to CS19). The switches of the switch circuit (21) may each be controlled by bits output by the decoder (22) and the delay circuit (23). For example, as shown in FIG. 2, the first to 4th current sources (CS1 to CS4) may each be controlled by 4 bits (IN'[1], IN'[2], IN'[3], IN'[4]) of the delayed lower bit group (IN'[4:1]). Additionally, the fifth to 19th current sources (CS5 to CS19) may each be controlled by 15 bits (TMP[1] to TMP

[15] ) of the thermometer code (TMP). Each of the switches of the switch circuit (21) may have any structure and may include at least one transistor in some embodiments.

[0025] The summing circuit (24) is the current that passed through the switch circuit (21) (i.e., I of FIG. 1). SELIt can receive ) and generate an output (OUT). For example, as shown in FIG. 2, the summing circuit (24) may include an amplifier (A) and a resistor (R), and can convert the summing currents that have passed through the switches of the switching circuit (21) into a voltage.

[0026] The linearity of the digital-analog converter (20) may depend on the accuracy of the currents generated by each of the first to ninth current sources (CS1 to CS19) shown in FIG. 2. For example, if the influence caused by variations in current cells affects the first to ninth current sources (CS1 to CS19), each containing at least one current cell, differently, the currents generated by each of the first to ninth current sources (CS1 to CS19) may vary differently, and the linearity of the digital-analog converter (20) may deteriorate. On the other hand, if the influence caused by variations in current cells affects the first to ninth current sources (CS1 to CS19), each containing at least one current cell, commonly, the currents generated by each of the first to ninth current sources (CS1 to CS19) may vary commonly, and the linearity of the digital-analog converter (20) may be maintained or improved. Accordingly, the grouping of at least one current cell included in each of the first to ninth current sources (CS1 to CS19) in the current cell array (11) of FIG. 1 may be important. Various groupings of current cells that provide high linearity of the digital-to-analog converter (20) will be described below with reference to the drawings. A digital-to-analog converter receiving an 8-bit input (IN) including a 4-bit upper bit group and a 4-bit lower bit group, such as the digital-to-analog converter (20) of FIG. 2, will be mainly described below. However, it should be noted that exemplary embodiments of the present disclosure are not limited thereto.

[0027] FIGS. 3a and 3b are drawings illustrating examples of current cell arrays according to exemplary embodiments of the present disclosure. Specifically, FIGS. 3a and 3b illustrate current cell arrays (30a, 30b) comprising 256 current cells and included in a digital-to-analog converter receiving an 8-bit input, in a plane formed by the X-axis and Y-axis. Hereinafter, FIGS. 3a and 3b will be described with reference to FIGS. 2, and any redundant descriptions of FIGS. 3a and 3b will be omitted.

[0028] Referring to FIGS. 3a and 3b, each of the current cell arrays (30a, 30b) may contain 256 current cells according to 16 rows extending parallel to the X-axis and 16 columns extending parallel to the Y-axis. In FIGS. 3a and 3b, MSB current cells having the same reference numeral may be included in the same current source, namely one of the 5th to 19th current sources (CS5 to CS19). For example, 16 current cells labeled 'M1' may be included in the 5th current source (CS5) corresponding to the LSB (TMP[1]) of the thermometer code (TMP), and 16 current cells labeled 'M15' may be included in the 19th current source (CS19) corresponding to the MSB (TMP

[15] ) of the thermometer code (TMP). MSB current cells having the same reference numeral can be interconnected through a pattern, and the current generated by the MSB current cells can be output to the outside of the current cell array (30a) through the pattern. The pattern connecting the current cell array will be described later with reference to FIG. 5, which shows an enlarged view of the area (R3) in FIG. 3a. Additionally, 15 of the 16 current cells marked 'L' in FIG. 3a and 3b may be included in one of the first to fourth current sources (CS1 to CS4), and the remaining 1 current cell may not be used or may be the selected current (I) in FIG. 1 regardless of the value of the input (IN). SEL It can be included in ).

[0029] MSB current cells included in a single current source can be arranged along the diagonal (Da) of the current cell array (30a). For example, as indicated by 'M8' in FIG. 3a, 16 MSB current cells included in the 12th current source (CS12) corresponding to one bit (TMP[8]) of the thermometer code (TMP) can be arranged along the diagonal (Da) of the current cell array (30a). Additionally, MSB current cells included in a single current source can be arranged along two diagonal lines parallel to the diagonal (Da) of the current cell array (30a). For example, as indicated by 'M4' in FIG. 3a, 16 MSB current cells included in the 8th current source (CS8) corresponding to one bit (TMP[4]) of the thermometer code (TMP) can be arranged along the first diagonal (L1a) and the second diagonal (L2a) of the current cell array (30a), and the first diagonal (L1a) and the second diagonal (L2a) can be parallel to the diagonal (Da). As shown in FIG. 3a, for the 16 MSB current cells corresponding to one current source, the first diagonal (L1a) and the second diagonal (L2a) can have the diagonal (Da) in between. Consequently, the MSB current source cells included in one current source can be arranged mutually exclusively in the rows of the current cell array (30a) and mutually exclusively in the columns of the current cell array (30a).

[0030] When MSB current cells are grouped as illustrated in FIG. 3a, the effects caused by a variation may be common to the groups of MSB current cells. For example, if a variation occurs on one side of the current cell array (30a), the current cells included in each of the 5th to 19th current sources (CS5 to CS19) may all be commonly affected by the variation. Accordingly, the currents generated by the 5th to 19th current sources (CS5 to CS19) may increase or decrease equally, and thus the linearity of the digital-to-analog converter may be maintained. Furthermore, as described later with reference to FIG. 5, etc., for grouping the current cells, only patterns for connecting the current cells on the current cell array (30a) may be added, and thus the linearity of the digital-to-analog converter may be improved without additional costs, such as area or power, and consequently, the performance and efficiency of the application including the digital-to-analog converter may be simultaneously increased.

[0031] LSB current cells can be arranged along two diagonal lines parallel to the diagonal (Da) of the current cell array (30a). For example, as indicated by 'L' in FIG. 3a, 16 LSB current cells can be arranged along the third diagonal line (L3a) and the fourth diagonal line (L4a) of the current cell array (30a), and the third diagonal line (L3a) and the fourth diagonal line (L4a) can be parallel to the diagonal (Da). As shown in FIG. 3a, for the 16 LSB current cells, the third diagonal line (L3a) and the fourth diagonal line (L4a) can be placed with the diagonal (Da) in between. In some embodiments, the number of LSB current cells arranged along the third diagonal (L3a) may be equal to the number of LSB current cells arranged along the fourth diagonal (L4a), and the distance between the third diagonal (L3a) and the diagonal (Da) may be equal to the distance between the fourth diagonal (L4a) and the diagonal (Da). Accordingly, the third diagonal (L3a) and the fourth diagonal (L4a) may correspond to the diagonals of the quadrants of the current cell array (30a), respectively.

[0032] Referring to FIG. 3b, MSB current cells included in a single current source can be arranged along the diagonal (Db) of the current cell array (30b). While the diagonal (Da) of FIG. 3a has a negative slope in a Cartesian coordinate system consisting of the X-axis and Y-axis, the diagonal (Db) of FIG. 3b can have a positive slope. As indicated by 'M8' in FIG. 3b, 16 MSB current cells included in the 12th current source (CS12) corresponding to one bit (TMP[8]) of the thermometer code (TMP) can be arranged along the diagonal (Db) of the current cell array (30b). Additionally, MSB current cells included in a single current source can be arranged along two diagonal lines parallel to the diagonal (Db) of the current cell array (30b). For example, as indicated by 'M4' in FIG. 3b, 16 MSB current cells included in the 8th current source (CS8) corresponding to one bit (TMP[4]) of the thermometer code (TMP) can be arranged along the first diagonal line (L1b) and the second diagonal line (L2b) of the current cell array (30b), and the first diagonal line (L1b) and the second diagonal line (L2b) can be parallel to the diagonal (Db). As shown in FIG. 3b, for 16 MSB current cells corresponding to one current source, the first diagonal line (L1b) and the second diagonal line (L2b) can have the diagonal (Db) in between.

[0033] LSB current cells can be arranged along two diagonal lines parallel to the diagonal (Db) of the current cell array (30b). For example, as indicated by 'L' in FIG. 3b, 16 LSB current cells can be arranged along the third diagonal line (L3b) and the fourth diagonal line (L4b) of the current cell array (30b), and the third diagonal line (L3b) and the fourth diagonal line (L4b) can be parallel to the diagonal (Db). As shown in FIG. 3b, for the 16 LSB current cells, the third diagonal line (L3b) and the fourth diagonal line (L4b) can be placed with the diagonal (Db) in between. In some embodiments, the number of LSB current cells arranged along the third diagonal line (L3b) may be the same as the number of LSB current cells arranged along the fourth diagonal line (L4b), and the distance between the third diagonal line (L3b) and the diagonal line (Db) may be the same as the distance between the fourth diagonal line (L4b) and the diagonal line (Db).

[0034] FIGS. 4a and 4b are drawings illustrating examples of current cells selected according to an input in accordance with an exemplary embodiment of the present disclosure. Specifically, FIG. 4a shows a current cell array (40) comprising current cells grouped in the same way as FIG. 3a, where the value of the input (IN) is 2 N-1 Figure 4b shows the current cells selected when -1, and in the current cell array (40) including current cells grouped in the same way as Figure 3a, the value of the input (IN) is 2 N-1 In the case of, it indicates the current cells selected. The hatched current cells in FIGS. 4a and 4b may represent the selected current cells. Below, FIGS. 4a and 4b will be described with reference to FIGS. 2.

[0035] In some embodiments, MSB current cells corresponding to the center code of the digital-to-analog converter may be arranged along the diagonal of the current cell array (40). For example, as shown in FIGS. 4a and 4b, 16 MSB current cells labeled 'M8' correspond to the center code of the N-bit input (IN) (i.e., 2 N-1 In response to an input (IN) of ) or more, it can be selected by the switch circuit (21), and the current generated by 16 MSB current cells can be used to generate the output (OUT).

[0036] Referring to Fig. 4a, the value of the input (IN) is 2 N-1 In the case of -1, LSB current cells can be selected, and MSB current cells included in the 5th to 11th current sources (CS5 to CS11) can be selected. Additionally, referring to FIG. 4b, the value of the input (IN) is the center code, i.e., 2 N-1 In this case, LSB current cells may not be selected, and MSB current cells included in the 5th to 11th current sources (CS5 to CS11) as well as the 12th current source (CS12) may be selected. As illustrated in FIGS. 4a and 4b, the MSB current cells selected as the value of the input (IN) varies may be in contact with all four sides of the current cell array (40), and consequently, the influence caused by the locally occurring variation may be common to the current sources.

[0037] FIG. 5 is a plan view showing the layout of a digital-to-analog converter according to an exemplary embodiment of the present disclosure. Specifically, the plan view of FIG. 5 shows the region (R3) of the current cell array (30a) of FIG. 3a. In FIG. 5, the plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, a component positioned in the +Z direction relative to another component may be referred to as being above another component, and a component positioned in the -Z direction relative to another component may be referred to as being below another component. Also, in FIG. 5, for convenience of illustration, only some layers may be shown, and a pattern composed of a conductive material, such as a pattern of wiring layers, may be referred to as a conductive pattern or simply a pattern. Hereinafter, FIG. 5 will be described with reference to FIG. 2.

[0038] Referring to FIG. 5, a pattern connecting current cells can be formed on the current cells. As described above with reference to the drawings, current cells included in a current source can be interconnected to generate current from the current source. For example, as shown in FIG. 5, a first pattern (W11) of the lower wiring layer can connect MSB current cells labeled 'M8', a second pattern (W12) of the lower wiring layer can connect MSB current cells labeled 'M6', and a third pattern (W13) of the lower wiring layer can connect MSB current cells labeled 'M10'. Additionally, as illustrated in FIG. 5, the first pattern (W21) of the upper wiring layer can connect MSB current cells labeled 'M7', the second pattern (W22) of the upper wiring layer can connect MSB current cells labeled 'M5', the third pattern (W23) of the upper wiring layer can connect MSB current cells labeled 'M11', and the fourth pattern (W24) of the upper wiring layer can connect MSB current cells labeled 'M9'. The first to third patterns (W11 to W13) of the lower wiring layer can be connected to the switch circuit (21), and the first to fourth patterns (W21 to W24) of the upper wiring layer can also be connected to the switch circuit (21). It should be noted that the shape of the patterns connecting the current cells can vary, and the exemplary embodiments of the present disclosure are not limited to the patterns illustrated in FIG. 5.

[0039] FIGS. 6a and 6b are circuit diagrams illustrating examples of current cells according to exemplary embodiments of the present disclosure. Specifically, the circuit diagram of FIG. 6a shows an LSB current (I LSB ) shows a current cell (60a) outputting ), and the circuit of FIG. 6b shows an LSB current (I LSBIt shows a current cell (60b) that draws out ). In some embodiments, the current cell may have a cascode structure as shown in FIG. 6a and FIG. 6b, but it should be noted that exemplary embodiments of the present disclosure are not limited thereto.

[0040] Referring to FIG. 6a, the current cell (60a) may include a first p-channel field effect transistor (PFET) (P1) and a second PFET (P2) connected in series. The gate of the first PFET (P1) may receive a first voltage (V1), and the gate of the second PFET (P2) may receive a second voltage (V2). The first voltage (V1) and the second voltage (V2) may be included in the bias signal (BS) of FIG. 1, and the bias generator (12) of FIG. 1 may generate the first voltage (V1) and the second voltage (V2). The first PFET (P1) and the second PFET (P2) receive an LSB current (I) from a node to which a positive supply voltage (VDD) is applied according to the first voltage (V1) and the second voltage (V2). LSB It can generate ) and LSB current (I) to the outside of the current cell (60a). LSB It can output ). In some embodiments, the first voltage (V1) and the second voltage (V2) may be the same, and the gates of the first PFET (P1) and the second PFET (P2) may be interconnected.

[0041] Referring to FIG. 6b, the current cell (60b) may include a first n-channel field effect transistor (NFET) (N1) and a second NFET (N2) connected in series. The gate of the first NFET (N1) may receive a first voltage (V1), and the gate of the second NFET (N2) may receive a second voltage (V2). The first voltage (V1) and the second voltage (V2) may be included in the bias signal (BS) of FIG. 1, and the bias generator (12) of FIG. 1 may generate the first voltage (V1) and the second voltage (V2). The first NFET (N1) and the second NFET (N2) have an LSB current (I) drawn out to a node to which a ground potential (or a negative supply voltage) is applied according to the first voltage (V1) and the second voltage (V2). LSB It can generate ) and LSB current (I) from outside the current cell (60b). LSB ) can be drawn. In some embodiments, the first voltage (V1) and the second voltage (V2) may be the same, and the gates of the first NFET (N1) and the second NFET (N2) may be interconnected.

[0042] FIG. 7 is a plan view showing the layout of a digital-to-analog converter according to an exemplary embodiment of the present disclosure. Specifically, the plan view of FIG. 7 shows one MSB current cell (M8') included in a current cell array and some patterns placed above the MSB current cell (M8'). In FIG. 7, a plane formed by the X-axis and Y-axis may be referred to as a horizontal plane, a component placed in the +Z direction relative to another component may be referred to as being above another component, and a component placed in the -Z direction relative to another component may be referred to as being below another component. Also, in FIG. 7, only some layers may be shown for convenience of illustration.

[0043] Referring to FIG. 7, an active region can be extended parallel to the X-axis in the MSB current cell (M8'). The active region can be referred to as a device region, and a transistor can be formed therein. For example, if the MSB current cell (M8') corresponds to the current cell (60a) of FIG. 6a, a PFET can be formed in the active region, whereas if the MSB current cell (M8') corresponds to the current cell (60b) of FIG. 6b, an NFET can be formed in the active region.

[0044] In the active region, at least one active pattern may be extended parallel to the X-axis. For example, as shown in FIG. 7, three active patterns may be extended parallel to the X-axis in the active region. The active patterns may intersect with a gate electrode that is extended parallel to the Y-axis to form a transistor. For example, as shown in FIG. 7, the first gate electrode (G1) and the second gate electrode (G2) may be extended parallel to the Y-axis, and the active patterns may form transistors with the first gate electrode (G1) and the second gate electrode (G2), respectively.

[0045] The current cell may include a transistor of any structure. In some embodiments, a fin-shaped active pattern may extend parallel to the X-axis, and the active pattern and the gate electrode may form a FinFET (fin field effect transistor). In some embodiments, the active pattern may include a plurality of nanowires extending parallel to the X-axis while being spaced apart from each other in the Y-axis direction and / or the Z-axis direction, and may form a GAAFET (gate all around field effect transistor) with the gate electrode. In some embodiments, the active pattern may include a plurality of nanosheets extending parallel to the X-axis while being spaced apart from each other in the Y-axis direction and / or the Z-axis direction, and may form a multi-bridge channel field effect transistor (MBCFET) with the gate electrode. In some embodiments, the current cell may include a ForkFET having a structure in which the N-type transistor and the P-type transistor are closer together by separating the nanosheets for the P-type transistor and the nanosheets for the N-type transistor by a dielectric wall. In some embodiments, the current cell may include a vertical field effect transistor (VFET) having a structure in which source / drain regions are spaced apart from each other in the Z-axis direction with a channel region in between, and a gate electrode surrounds the channel region. Additionally, the current cell may include transistors with structures different from those described above, such as field effect transistors (FETs) like complementary field effect transistors (CFETs), negative field effect transistors (NCFETs), carbon nanotube (CNT) FETs, bipolar junction transistors, or other three-dimensional transistors.

[0046] When the MSB current cell (M8') corresponds to the current cell (60a) of FIG. 6a, the first gate electrode (G1) may correspond to the gate of the first PFET (P1), and the second gate electrode (G2) may correspond to the gate of the second PFET (P2). The first pattern (W11) may be connected to the drain of the second PFET (P2) and may be connected to the drain of the second PFET (P2) included in another MSB current cell included in the same current source as the MSB current cell (M8'), that is, in an MSB current cell arranged diagonally opposite to the MSB current cell (M8'). The second pattern (W12) may be connected to the source of the first PFET (P1), and a positive supply voltage (VDD) may be applied to the second pattern (W12).

[0047] When the MSB current cell (M8') corresponds to the current cell (60b) of FIG. 6b, the first gate electrode (G1) may correspond to the gate of the first NFET (N1), and the second gate electrode (G2) may correspond to the gate of the second NFET (N2). The first pattern (W11) may be connected to the drain of the second NFET (N2) and may be connected to the drain of the second NFET (N2) included in another MSB current cell included in the same current source as the MSB current cell (M8'), that is, in an MSB current cell arranged diagonally opposite to the MSB current cell (M8'). The second pattern (W12) may be connected to the source of the first NFET (N1), and a ground potential (or negative supply voltage) may be applied to the second pattern (W12).

[0048] FIG. 8 is a flowchart illustrating a method for converting a digital input into an analog output according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 8, the method for converting a digital input into an analog output may include a plurality of steps (S10, S30, S50, S70, S90). In some embodiments, the method of FIG. 8 may be performed by the digital-to-analog converter (10) of FIG. 1 and may be referred to as the method of operation of the digital-to-analog converter (10). Hereinafter, FIG. 8 will be described with reference to FIG. 1.

[0049] Referring to FIG. 8, a digital input may be received in step S10. For example, the digital-to-analog converter (10) may receive an N-bit input (IN). Based on the value of the input (IN), the digital-to-analog converter (10) 2 N It is possible to generate an output (OUT) having one of several different sizes.

[0050] In step S30, a thermometer code (TMP) can be generated. For example, the decoder (13) can generate the thermometer code (TMP) by decoding the upper bit group (IN[N:M+1]) of the input (IN). The upper bit group (IN[N:M+1]) of the input (IN) may have (NM) bits, and accordingly, the decoder (13) 2 N-M- A 1-bit thermometer code (TMP) can be generated. The thermometer code (TMP) may contain a number of 1s proportional to the value of the upper bit group (IN[N:M+1]) of the input (IN).

[0051] In step S50, the reference current (I REF ) can be generated. For example, the current cell array (11) can generate the same current, i.e., the LSB current (I LSB 2 designed to generate ) respectively N It may include current cells, and a reference current (I REF ) is 2 NIt may include currents generated by current cells. As the number of bits N of the input (IN) increases, the number of current cells included in the current cell array (11) and the area of ​​the current cell array (11) may increase, and accordingly, local variation may occur in the current cells included in the current cell array (11). As described above with reference to the drawings, the current cells in the current cell array (11) may be grouped so that the influence of local variation is common, and accordingly, the linearity of the digital-to-analog converter (10) may be maintained despite the local variation.

[0052] In step S70, the reference current (I REF At least some of ) may be selected. For example, the switch circuit (15) receives a reference current (I) from the current cell array (11) through a plurality of wires. REF ) can be received. The delay circuit (14) can delay the lower bit group (IN[M:1]) of the input (IN), and the switch circuit (15) can receive the delayed lower bit group (IN'[M:1]) from the delay circuit (14). The switch circuit (15) may include switches corresponding to the bits of the thermometer code (TMP) and the delayed lower bit group (IN'[M:1]), respectively, and a reference current (I) according to the thermometer code (TMP) and the delayed lower bit group (IN'[M:1]). REF Current (I) selected as at least a part of ) SEL ) can be output. As described above with reference to the drawings, a plurality of current cells in the current cell array (11) can be grouped so that the influence of local variation is common. Accordingly, despite the local variation occurring in the current cell array (11), the selected current (I SEL ) can increase or decrease in common across various values ​​of the input (IN). An example of step S70 will be described later with reference to FIG. 9.

[0053] In step S90, the selected current (I SEL ) can be summed. For example, the summing circuit (16) selects the current (I SEL ) can be received from the switch circuit (15) through multiple wires. The summing circuit (16) can sum the currents received through each of the multiple wires and can generate an output (OUT) having a magnitude corresponding to the summed current. In some embodiments, as described above with reference to FIG. 2, the summing circuit (16) can generate an output (OUT) by converting the summed current into a voltage.

[0054] FIG. 9 is a flowchart illustrating a method for converting a digital input into an analog output according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 9 illustrates an example of step S70 of FIG. 8. As described above with reference to FIG. 8, in step S70' of FIG. 9, the reference current (I REF At least some of ) may be selected. As illustrated in FIG. 9, step S70' may include steps S71 and S72. In some embodiments, step S70' may be performed by the digital-to-analog converter (20) of FIG. 2, and FIG. 9 will be described below with reference to FIG. 2.

[0055] Referring to FIG. 9, currents can be selected based on a thermometer code (TMP) in step S71. For example, the decoder (22) can generate a 15-bit thermometer code (TMP) from the upper bit group (IN[8:5]) of the input (IN). The switch circuit (21) may include 15 switches that are each turned on or off according to the bits of the thermometer code (TMP), and the 15 switches can select some of the currents provided from the 5th to 19th current sources (CS5 to CS19), respectively.

[0056] In step S72, currents may be selected based on the lower bit group of the input (IN). For example, the delay circuit (23) may delay the lower bit group (IN[4:1]) of the input (IN) and output the delayed lower bit group (IN'[4:1]). The switch circuit (21) may include four switches that are each turned on or off according to the bits of the delayed lower bit group (IN'[4:1]), and the four switches may select some of the currents provided from the first to fourth current sources (CS1 to CS4), respectively.

[0057] FIG. 10 is a block diagram showing a signal processing system (100) according to an exemplary embodiment of the present disclosure. A digital-to-analog converter described above with reference to the drawings may be included in the signal processing system (100).

[0058] A signal processing system (100) may refer to a system that performs operations by processing any signal. In some embodiments, the signal processing system (100) may be a stationary computing system, such as a desktop PC or server, or a mobile computing system, such as a laptop PC, mobile phone, or wearable device. Additionally, the signal processing system (100) may be a single chip manufactured by a semiconductor process, such as a system-on-chip (SoC), or a module in which two or more chips are mounted on a printed circuit board (PCB). As illustrated in FIG. 10, the signal processing system (100) may include an analog signal processing circuit (110), a digital signal processing circuit (120), and a mixed signal processing circuit (130). In some embodiments, the analog signal processing circuit (110) and / or the digital signal processing circuit (120) may be omitted.

[0059] The analog signal processing circuit (110) can process analog signals. For example, the analog signal processing circuit (110) may include components for processing analog signals, such as amplifiers, filters, mixers, etc. Additionally, the analog signal processing circuit (110) may include passive components, such as resistors, capacitors, inductors, etc.

[0060] The digital signal processing circuit (120) can process digital signals. For example, the digital signal processing circuit (120) may include components that store data, such as memory, registers, etc. Additionally, the digital signal processing circuit (120) may include programmable components such as a CPU (central processing unit) or DSP (digital signal processing unit), reconfigurable components such as a field programmable gate array (FPGA), and / or components that provide fixed functions such as an IP (intellectual property) core.

[0061] The mixed signal processing circuit (130) may include at least one analog-to-digital converter (ADC) (131) and at least one digital-to-analog converter (132). The at least one analog-to-digital converter (131) can convert an analog signal provided from the analog signal processing circuit (110) into a digital signal and provide the converted digital signal to the digital signal processing circuit (120). Additionally, the at least one digital-to-analog converter (132) can convert a digital signal provided from the digital signal processing circuit (120) into an analog signal and provide the converted analog signal to the analog signal processing circuit (110). The at least one digital-to-analog converter (132) can maintain linearity despite the occurrence of local variations as described above with reference to the drawings, and accordingly, the performance and efficiency of the signal processing system (100) can be increased.

[0062] Although the present disclosure has been described with reference to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims

Claim 1 A digital-to-analog converter configured to generate an analog output from a digital input, comprising: a current cell array including a plurality of current cells each designed to generate a current of the same magnitude; a first pattern connecting first current cells arranged along a diagonal of the current cell array among the plurality of current cells; a second pattern connecting second current cells arranged along a first diagonal parallel to the diagonal among the plurality of current cells; and a third pattern connecting third current cells arranged along a second diagonal parallel to the diagonal among the plurality of current cells and electrically connected to the second pattern, wherein the diagonal is between the first diagonal and the second diagonal, and the second current cells and the third current cells are mutually exclusively arranged in the rows of the current cell array and mutually exclusively arranged in the columns of the current cell array. Claim 2 delete Claim 3 In claim 1, the digital input is N bits when N is an integer greater than 1, and the currents generated by the first current cells are such that the value of the digital input is 2 N-1 A digital-to-analog converter characterized by being used to generate the above analog output in the case of an abnormal case. Claim 4 The digital-to-analog converter according to claim 1 further comprises a decoder configured to generate a thermometer code from an upper bit group including the MSB (most significant bit) of the digital input, wherein the first current cells correspond to the first bit of the thermometer code, and the second current cells and the third current cells correspond in common to the second bit of the thermometer code. Claim 5 A digital-to-analog converter according to claim 4, wherein the plurality of current cells includes fourth current cells and fifth current cells corresponding to a lower bit group including the least significant bit (LSB) of the digital input, the fourth current cells are arranged along a third diagonal line parallel to the diagonal, the fifth current cells are arranged along a fourth diagonal line parallel to the diagonal, and the diagonal is located between the third diagonal line and the fourth diagonal line. Claim 6 A digital-to-analog converter according to claim 5, wherein the fourth current cells and the fifth current cells are mutually exclusively arranged in the rows of the current cell array and mutually exclusively arranged in the columns of the current cell array. Claim 7 A digital-to-analog converter according to claim 5, wherein the third diagonal line and the fourth diagonal line correspond respectively to the diagonals of the quadrants of the cell array. Claim 8 A digital-to-analog converter configured to generate an analog output from a digital input, comprising: a decoder configured to generate a thermometer code from an upper bit group including the MSB (most significant bit) of the digital input; a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude; and a switch circuit configured to select at least some of the currents generated by the current cell array, wherein the plurality of current cells include: first current cells arranged along a diagonal of the current cell array and corresponding to a first bit of the thermometer code; second current cells arranged along a first diagonal parallel to the diagonal and corresponding to a second bit of the thermometer code; and third current cells arranged along a second diagonal parallel to the diagonal and corresponding to the second bit of the thermometer code, wherein the diagonal is located between the first diagonal and the second diagonal. Claim 9 A method for converting a digital input into an analog output, comprising: generating a thermometer code from an upper bit group including the MSB (most significant bit) of the digital input; generating a reference current by a current cell array comprising a plurality of current cells each designed to generate a current of the same magnitude; selecting at least a portion of the reference current based on the thermometer code and a lower bit group including the LSB (least significant bit) of the digital input; and generating the analog output by summing the selected currents, wherein the step of selecting at least a portion of the generated currents includes selecting currents generated by first current cells among the plurality of current cells that are mutually exclusively arranged in the rows of the current cell array and mutually exclusively arranged in the columns of the current cell array, based on one bit of the thermometer code. Claim 10 A method according to claim 9, wherein the first current cells are arranged along the diagonal of the cell array or along a first diagonal and a second diagonal parallel to the diagonal.

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